TW202345216A - Semiconductor structure and method of forming the same - Google Patents

Abstract

A method of forming a semiconductor structure is provided. The method includes providing a substrate. An epitaxial layer is formed on the substrate. A first etching process is performed to form a first trench in the epitaxial layer. A first doping process is performed to form a channel doped region in a portion of the epitaxial layer adjacent to a sidewall and a bottom surface of the first trench. A second etching process is performed to remove a portion of the channel doped region and another portion of the epitaxial layer from the bottom surface of the first trench to form a second trench through the channel doped region. A gate structure is formed in the second trench.

Description

Semiconductor structures and methods of forming them

The present invention relates to semiconductor structures and methods of forming the same, and in particular to vertical transistor devices and methods of forming the same, which have channel doping regions with uniform dopant concentration distribution in the channel direction.

For horizontal transistors, the current technology forms a channel doping region through ion implantation, so that the dopant profile of the channel doping region in the horizontal channel direction is well controlled and has a uniform dopant concentration ( dopant concentration) to further control the electrical characteristics and reliability of the horizontal transistor.

However, for vertical transistors, the dopant concentration distribution of the channel doping region formed by ion implantation will change drastically in the vertical channel direction due to the intrinsic dopant profile of the ion implantation. Uneven channel dopant concentration distribution can lead to unstable electrical characteristics, including critical voltage fluctuation (Vth fluctuation), breakdown lowering, and leakage.

Therefore, it is necessary to seek a novel semiconductor structure and its formation method to solve or improve the above problems.

In view of the above problems, the present disclosure uses a double trench process and a diffusion process to form a channel doping region with a uniform dopant concentration distribution in the vertical channel direction to improve problems such as critical voltage disturbance, breakdown voltage drop, and leakage. , thereby improving the electrical characteristics and reliability of the vertical transistor device.

According to some embodiments, a method for forming a semiconductor structure is provided. The method for forming a semiconductor structure includes providing a substrate; forming an epitaxial layer on the substrate; performing a first etching process to form a first trench in the epitaxial layer; and performing a first doping process. A doping process is performed to form a channel doped region in part of the epitaxial layer on the sidewall and bottom of the adjacent first trench; a second etching process is performed to remove part of the channel doped region and part of the epitaxial layer from the bottom of the first trench. crystal layer to form a second trench penetrating the channel doping region in the epitaxial layer; and forming a gate structure in the second trench.

According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate; an epitaxial layer disposed on the substrate; a first trench disposed in the epitaxial layer; a first gate structure disposed in the first trench; and a first channel doping region disposed in In the epitaxial layer and adjacent to the upper part of the first gate structure, the first channel doping region has a doping profile that is wide at the top and narrow at the bottom.

The following disclosure provides many different embodiments or examples for implementing various features of the invention. The following disclosure is a specific example describing each component and its arrangement in order to simplify the disclosure. Of course, these are only examples and are not intended to limit the present invention. In addition, this disclosure may repeat reference numerals and/or text in different examples. Repetition is provided for purposes of simplicity and clarity and does not inherently specify the relationship between the various embodiments and/or configurations discussed.

Figure 1 is a flowchart of a method 100 of forming a semiconductor structure according to some embodiments of the present disclosure. The operations shown in Figure 1 will be illustrated with an example process for the semiconductor structures shown in Figures 2-10. 2 to 10 are schematic cross-sectional views of a semiconductor structure 250 at various manufacturing stages according to some embodiments of the present disclosure. In some embodiments, semiconductor structure 250 may include a trench gate semiconductor device (eg, a vertical transistor device). It should be noted that the method 100 may not produce the complete semiconductor structure 250 . Therefore, it is understood that additional processes may be provided before, during, and after the method 100 , and some of the additional processes may only be briefly described in the following disclosure.

Referring to FIG. 1 , in operation 102 , a substrate of a semiconductor structure is provided. For example, as shown in FIG. 2 , a substrate 200 of a semiconductor structure is provided, which has a top surface 201 and a bottom surface 203 . The substrate 200 may be a part of a semiconductor wafer, such as a silicon wafer. The substrate 200 may be a bulk semiconductor or a semiconductor-on-insulation (SOI) substrate. Generally speaking, an insulator-on-semiconductor substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar material that provides an insulating layer on a silicon or glass substrate. The substrate 200 can also be other types of substrates, such as a multi-layer substrate or a gradient substrate. In other embodiments, the substrate 200 may be an elemental semiconductor (eg, silicon, germanium), a compound semiconductor (eg, silicon carbide, gallium arsenide, gallium phosphide, phosphide). Indium (indium phosphide), indium arsenide (indium arsenide) and/or indium antimonide (indium antimonide), alloy semiconductors (for example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP or combinations thereof).

Next, referring to Figure 1, in operation 104, an epitaxial layer is formed on the substrate. For example, please refer to FIG. 2 , the epitaxial layer 204 is disposed on the top surface 201 of the substrate 200 . In some embodiments, the epitaxial layer 204 may include silicon, germanium, silicon germanium, III-V compounds, or combinations thereof. Furthermore, the epitaxial layer 204 can be formed by an epitaxial growth process, such as a molecular beam epitaxy (MBE) process or a metal organic chemical vapor deposition (MOCVD) process. , vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (ultra-high vacuum, CVD UHV-CVD)) and/or other suitable epitaxial growth processes.

In some embodiments, substrate 200 and epitaxial layer 204 have the same conductivity type. For example, if the finally formed semiconductor structure (eg, a trench gate semiconductor device) is an N-type transistor device, the conductivity type of the substrate 200 and the epitaxial layer 204 is N-type. On the contrary, if the semiconductor structure (eg, trench gate semiconductor device) is a P-type transistor device, the conductivity type of the substrate 200 and the epitaxial layer 204 is P-type. In some embodiments, the conductivity type of the substrate 200 and the epitaxial layer 204 is N-type. Furthermore, the substrate 200 and a portion of the epitaxial layer 204 can serve as a drain region of a semiconductor structure (eg, a trench gate semiconductor device). In this case, the doping concentration of the substrate 200 may be greater than the epitaxial layer 204 in the drain region. Furthermore, a metal layer may be disposed on the bottom surface 203 of the substrate 200 relative to the epitaxial layer 204, which may be called a backside metal layer or a drain electrode, as will be described below.

Next, please refer to FIG. 1. In operation 106, a first etching process is performed to form a first trench in the epitaxial layer. For example, please refer to FIG. 3 to perform a first etching process 1000 to form adjacent first trenches 208A and 208B in the epitaxial layer 204 . In some embodiments, before performing the first etching process 1000, a hard mask pattern 206 may be formed on the epitaxial layer 204. The hard mask pattern 206 covers a portion of the epitaxial layer 204 to define the formation locations of the first trenches 208A, 208B that are subsequently formed in the epitaxial layer 204 . Hard mask pattern 206 may include nitride, oxide, or a combination thereof. In some embodiments, the nitride may include silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), or other suitable nitrides. The oxide layer may include an oxide having tetraethyl orthosilicate (TEOS) as a precursor or other suitable oxides. In this embodiment, the hard mask pattern 206 may include silicon nitride (SiN). It can be understood that suitable hard mask pattern materials can be matched according to process conditions, and therefore the embodiments of the present disclosure are not limited thereto. In some embodiments, a deposition process (eg, chemical vapor deposition (CVD)) may be used to deposit a hard mask material layer (not shown), and then the hard mask material layer may be patterned (eg, , lithography and etching processes) to form a hard mask pattern 206. In some other embodiments, after depositing the hard mask material layer, a photolithography process can be performed to define the formation positions of the subsequent first trenches 208A and 208B with patterned photoresist (not shown), and then the first etching process can be performed. During 1000 a hard mask pattern 206 is formed.

Referring to FIG. 3 , the hard mask pattern 206 is used as an etching mask. During the first etching process 1000 , a portion of the epitaxial layer 204 exposed from the hard mask pattern 206 is removed to form the first trench 208A. ,208B. In some embodiments, the first trenches 208A, 208B are disposed in the epitaxial layer 204, and the bottom surfaces 212A, 212B of the first trenches 208A, 208B stop within the epitaxial layer 204 (that is, the first trenches 208A, 208B At least part of the epitaxial layer 204) remains below the bottom surfaces 212A and 212B of the first trench 208B, and the two opposite side walls 210A and 210B of the first trench 208A and 208B each have a linear profile. In other embodiments, the first trenches 208A and 208B may penetrate the epitaxial layer 204 so that their bottom surfaces 212A and 212B are exposed to the top surface 201 of the substrate 200 . Alternatively, the first trenches 208A and 208B can further extend downward so that their bottom surfaces 212A and 212B stop within the substrate 200 . In some embodiments, the number of first grooves, as well as the shape, depth, and width of each first groove are determined according to different needs of users. For ease of understanding, in the following embodiments, the first trenches 208A, 208B may have the same depth D1. In some embodiments, the first etching process 1000 may include dry etching or other suitable etching methods. Dry etching may include, but is not limited to, plasma etching, plasma-less gas etching, sputter etching, ion milling, and reactive ion etching (RIE).

Next, referring to FIG. 1 , in operation 108 , a first doping process is performed to form a channel doping region in a portion of the epitaxial layer adjacent to the sidewalls and bottom surface of the first trench. For example, please refer to FIG. 4 to perform a first doping process 1005 to form channel doping in part of the epitaxial layer 204 on the sidewalls 210A and 210B of the adjacent first trenches 208A and 208B and the bottom surfaces 212A and 212B respectively. Miscellaneous areas 214A and 214B. The channel doping region 214A is disposed in the epitaxial layer 204 along the sidewall 210A and the bottom surface 212A of the first trench 208A. The channel doping region 214B is disposed in the epitaxial layer 204 along the sidewall 210A and the bottom surface 212B of the first trench 208B. middle. In some embodiments, the conductivity type of the channel doped regions 214A, 214B is opposite to the conductivity type of the substrate 200 and the epitaxial layer 204 . For example, when the conductivity type of the substrate 200 and the epitaxial layer 204 is N-type, the conductivity type of the channel doped regions 214A and 214B is P-type.

In some embodiments, the first doping process 1005 may be a diffusion process, such as solid state diffusion, gaseous diffusion, or other suitable diffusion processes. In some embodiments, the first doping process 1005 may be implemented as a solid-state source diffusion process, which includes a predeposition step and a drive-in step. As shown in FIG. 4 , the preparatory steps of the first doping process 1005 can be performed, and the doped silicon oxide material layers 216A and 216B are filled in the first trenches 208A and 208B respectively. In some embodiments, the doped silicon oxide material layers 216A and 216B include a silicon oxide material layer containing an impurity, such as borophosphosilicate glass (BPSG), and the conductivity type of the impurity is the same as The conductivity type of the epitaxial layer 204 is opposite (for example, if the conductivity type of the epitaxial layer 204 is N-type, then the conductivity type of the dopant is P-type). In some embodiments, spin-on, chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), plasma enhanced CVD may be utilized. , PECVD), physical vapor deposition (PVD), or any appropriate deposition technology, fill the first trenches 208A and 208B with a doped silicon oxide material layer (not shown in the figure). Then, a reflow process is performed to planarize the surface of the doped silicon oxide material layer. Then, an etching process (such as a dry etching process) is performed on the silicon oxide material layer to remove the doped silicon oxide material layer above the hard mask pattern 206 and outside the first trenches 208A and 208B, so as to separate the first trenches 208A and 208B. Doped silicon oxide material layers 216A and 216B are formed in 208A and 208B. The top surfaces of the doped silicon oxide material layers 216A, 216B may be flush with the top surface of the hard mask pattern 206 .

Then, as shown in FIG. 4 , the driving step of the first doping process 1005 is performed to diffuse the dopants in the doped silicon oxide material layers 216A and 216B to the sidewalls 210A and 210B of the first trenches 208A and 208B. Channel doping regions 214A and 214B are formed in the portion of the epitaxial layer 204 other than the bottom surfaces 212A and 212B. In some embodiments, the drive-in step is performed at a process temperature between 800°C and 1000°C (eg, 900°C) to form the channel doping regions 214A and 214B. During the drive-in step of the first doping process 1005, the dopants in the doped silicon oxide material layers 216A and 216B will diffuse isotropically and uniformly into the portion of the epitaxial layer 204 outside the first trenches 208A and 208B. Therefore, the channel doped regions 214A and 214B respectively surround the sidewalls 210A and 210B and the bottom surfaces 212A and 212B of the first trenches 208A and 208B. In the cross-sectional view shown in FIG. 4 , the channel doping regions 214A and 214B have isotropic doping profiles, and the channel doping regions 214A and 214B have uniform doping concentrations. Therefore, the boundary 214A1 of the channel doped region 214A and the first trench 208A have corresponding and similar profiles (for example, a U-shaped profile), and the distance S between the boundary 214A1 of the channel doped region 214A and the first trench 208A Essentially uniform. Similarly, the boundary 214B1 of the channel doping region 214B and the first trench 208B have a similar profile (for example, a U-shaped profile), and the distance S between the boundary 214B1 of the channel doping region 214B and the first trench 208B is substantially Above is uniformity.

Then, as shown in FIG. 5 , after the channel doping regions 214A and 214B are formed, the doped silicon oxide material layers 216A and 216B are removed from the first trenches 208A and 208B. In some embodiments, wet etching may be used to remove the doped silicon oxide material layers 216A, 216B, and simultaneously clean the sidewalls 210A, 210B and bottom surfaces 212A, 212B of the first trenches 208A, 208B. In some embodiments, the aforementioned wet etching has an etch selectivity for the hard mask pattern 206 , such as silicon nitride, and therefore the hard mask pattern 206 is not removed during removal of the doped silicon oxide material layers 216A, 216B.

Next, please refer to Figure 1. In operation 110, a second etching process is performed to remove part of the channel doping region and part of the epitaxial layer from the bottom surface of the first trench to form a through channel doping in the epitaxial layer. The second trench of the area. For example, please refer to FIG. 6 , using the hard mask pattern 206 as an etching mask, a second etching process 1010 is performed on the epitaxial layer 204 to remove portions from the bottom surfaces 212A and 212B of the first trenches 208A and 208B respectively. The channel doped regions 214A and 214B and part of the epitaxial layer 204 form second trenches 218A and 218B respectively in the epitaxial layer 204 that penetrate the channel doped regions 214A and 214B. In some embodiments, the second trenches 218A, 218B are disposed in the epitaxial layer 204, and the bottom surfaces 222A, 222B of the second trenches 218A, 218B stop within the epitaxial layer 204 (that is, the second trenches 218A, 218B At least part of the epitaxial layer 204) remains below the bottom surfaces 222A and 222B of the second trench 218B, and the two opposite side walls 220A and 220B of the second trench 218A and 218B each have a linear profile. In other embodiments, the second trenches 218A and 218B may penetrate the epitaxial layer 204 so that their bottom surfaces 222A and 222B are exposed to the top surface 201 of the substrate 200 . Alternatively, the second trenches 218A and 218B can further extend downward so that their bottom surfaces 222A and 222B stop within the substrate 200 . In some embodiments, the number of second grooves, as well as the shape, depth, and width of each second groove are determined according to different needs of users. For ease of understanding, in the following embodiments, the second trenches 218A and 218B may have the same depth D2, which is greater than the depth D1 of the first trenches 208A and 208B (FIG. 3). In some embodiments, the second etching process 1010 and the first etching process 1000 are the same or similar etching process, such as a dry etching process.

In some embodiments, the sidewall 220A of the second trench 218A has an upper sidewall portion 220A1 proximate the top surface of the epitaxial layer 204 to adjoin a lower sidewall portion 220A2 of the bottom surface 222A. Similarly, sidewall 220B of second trench 218B has an upper sidewall portion 220B1 proximate the top surface of epitaxial layer 204 to abut lower sidewall portion 220B2 of bottom surface 222B. During the second etching process 1010, part of the channel doped regions 214A and 214B located below the bottom surfaces 212A and 212B of the first trenches 208A and 208B (FIG. 5) will be removed, and the remaining parts of the channel doped regions will be removed respectively. Upper sidewall portions 220A1 and 220B1 surrounding and adjacent to the second trenches 218A and 218B are respectively labeled channel doped regions 254A and 254B. In the cross-sectional view shown in FIG. 6 , the channel doping regions 254A and 254B have a doping profile that is wide at the top and narrow at the bottom (tapered), and has the same depth D3. The lower sidewall portions 220A2 and 220B2 and the bottom surfaces 222A and 222B of the second trenches 218A and 218B are respectively located outside the boundaries 254A1 and 254B1 of the channel doped regions 254A and 254B. In some embodiments, the depth D3 of the channel doped regions 254A, 254B is less than the depth D2 of the second trenches 218A, 218B.

Next, referring to FIG. 1 , in operation 112 , a gate structure is formed in the second trench. For example, please refer to Figures 7-8 to form gate structures 230A and 230B in the second trenches 218A and 218B. Please refer to Figure 7. A growth process (for example, a thermal oxidation process) can be performed to selectively form a gate dielectric on the sidewalls 220A, 220B and bottom surfaces 222A, 222B of the second trenches 218A, 218B respectively (Figure 6). Layers 226A, 226B (which are also called gate oxide layers). In some embodiments, gate dielectric layers 226A, 226B are conformally formed along sidewalls 220A, 220B and bottom surfaces 222A, 222B of second trenches 218A, 218B. In some embodiments, gate dielectric layers 226A, 226B may be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or any other suitable dielectric material, or A combination of the above. The materials of high dielectric constant dielectric materials can be metal oxides, metal nitrides, metal silicides, transition metal oxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, zirconium Silicates, zircoaluminates. In some embodiments, the process temperature of the above-mentioned growth process may be approximately in the range of 800°C to 1100°C, and the process time may be approximately in the range of 5 minutes to 100 minutes. In other embodiments, the gate dielectric layers 226A, 226B may be formed by a chemical vapor deposition (CVD) deposition process, an atomic layer deposition (ALD) process, or other suitable processes.

Next, please refer to Figure 8. A deposition process can be performed to form a conductive material layer (not shown) in the second trenches 218A and 218B (Figure 7) and cover the gate dielectric layers 226A and 226B. In some embodiments, the layer of conductive material fills the second trenches 218A, 218B and extends to cover the hard mask pattern 206 outside the second trenches 218A, 218B. The conductive material layer may include polycrystalline silicon, metal, metal nitride, conductive metal oxide, or other suitable materials. In some embodiments, the conductive material layer may be polycrystalline silicon and may be formed by a chemical vapor deposition (CVD) process, a sputtering process, an electron beam evaporation process, an atomic layer deposition (ALD) process, or any other suitable deposition process. layer of conductive material.

Next, please refer to Figure 8. An etch-back process can be performed to remove the conductive material layer outside the second trenches 218A and 218B (Figure 7) until the gate dielectric layers 226A and 226B are exposed, respectively. Gate electrodes 228A and 228B are formed in trenches 218A and 218B. In some embodiments, the top surfaces of gate electrodes 228A, 228B may be flush with, or slightly lower than (having recessed portions) the top surfaces of gate dielectric layers 226A, 226B. ). In some embodiments, the etch back process is a dry etching process or other suitable etching process, and the hard mask pattern 206 and the gate dielectric layers 226A, 226B serve as etch masks for the etch back process. As shown in FIG. 8 , the gate dielectric layer 226A in the second trench 218A and the gate electrode 228A located on the gate dielectric layer 226A can be regarded as the gate structure 230A. The gate electrode in the second trench 218B The dielectric layer 226B and the gate electrode 228B located on the gate dielectric layer 226B can be regarded as the gate structure 230B. As shown in the cross-sectional view of Figure 8, the gate structures 230A and 230B are respectively disposed in the second trenches 218A and 218B. The channel doping regions 254A and 254B respectively surround and are adjacent to the upper portions 230A1 and 230B1 of the gate structures 230A and 230B. , and has a doping profile that is wide at the top and narrow at the bottom (taper).

In other embodiments, hard mask pattern 206 may be removed before forming gate dielectric layers 226A, 226B. Then, a growth process (eg, a thermal oxidation process) can be performed on the sidewalls 220A, 220B and bottom surfaces 222A, 222B (FIG. 6) of the second trenches 218A, 218B, respectively, and on the top surface of the epitaxial layer 204. A layer of gate dielectric material is selectively formed (not shown). Then, a deposition process (such as a chemical vapor deposition (CVD) process, a sputtering process, an electron beam evaporation process, an atomic layer deposition (ALD) or any other suitable deposition process) can be performed, in the second trench 218A, A conductive material layer (not shown) is formed in 218B and covers the gate dielectric material layer. Then, an etch-back process (for example, a chemical mechanical polishing (CMP) process) can be performed to sequentially remove the conductive material layer and the gate dielectric material layer outside the second trenches 218A and 218B until the epitaxial layer 204 is exposed. On the top surface, a gate dielectric layer 226A and a gate electrode 228A located on the gate dielectric layer 226A are respectively formed in the second trench 218A, and a gate dielectric layer 226B and a gate electrode 226B are formed in the second trench 218B. Gate electrode 228B located on gate dielectric layer 226B.

Next, the formation method of the body doped region 236 is explained with reference to FIG. 9 . Since the channel doping regions 254A and 254B surrounding the gate structures 230A and 230B have a wide top and narrow (tapered) doping profile, when the distance L1 between adjacent channel doping regions 254A and 254B is 0, The upper portions 254A2 and 254B2 of the channel doped regions 254A and 254B will be connected to each other, while the lower portions 254A3 and 254B3 of the channel doped regions 254A and 254B will still be separated and not connected to each other. When the distance L1 between adjacent channel doping regions 254A and 254B is greater than 0 (that is, the upper parts 254A2 and 254B2 of the channel doping regions 254A and 254B are separated from each other and not interconnected), body doping can be selectively formed according to design requirements. doped regions to laterally connect the channel doped regions 254A and 254B. In addition, FIG. 9 also illustrates the formation method of the source doped region 232 and the channel pickup doped region 234.

Referring to FIG. 9 , after the gate structures 230A and 230B are formed, the hard mask pattern 206 is removed from the epitaxial layer 204 . After the hard mask pattern 206 is removed, a thermal oxidation process may be performed to form an oxide layer 231 on the top surfaces of the gate structures 230A, 230B and the epitaxial layer 204 . In some embodiments, the oxide layer 231 is a thin layer that serves as a scattering layer for subsequent doping processes (used to form similar doping regions such as body doping regions, source doping regions, and channel contact doping regions), The epitaxial layer 204 can be protected from channeling effects caused by, for example, the second doping process of ion implantation, causing the implanted ions to pass through the lattice gap, resulting in an over-deep implantation effect.

As shown in Figure 9, when the channel doping regions 254A and 254B are not connected to each other, a second doping process 1015 can be selectively performed according to design requirements to implant dopant into the second trench 218A. , 218B (Fig. 6), and in part of the epitaxial layer 204 between the gate structures 230A and 230B, a body doped region 236 is formed on the channel doped regions 254A and 254B. (along the X-axis direction) connects the upper portion 254A2 of the channel doping region 254A and the upper portion 254B2 of the channel doping region 254B. In some embodiments, since the channel doping regions 254A and 254B have a wide upper and narrow doping profile (the width of the upper portions 254A2 and 254B2 along the X-axis direction is greater than the width of the lower portions 254A3 and 254B3), the body doping can be controlled. The depth D5 of the impurity region 236 is such that it connects the upper part 254A2 of the channel doping region 254A and the upper part 254B2 of the channel doping region 254B laterally (substantially along the X-axis direction). Therefore, the lower portion 254A3 of the channel doped region 254A and the lower portion 254B3 of the channel doped region 254B protrude from the bottom surface 236B of the body doped region 236 and are spaced apart from each other. In some embodiments, the depth D5 of the body doped region 236 is less than the depth D3 of the channel doped regions 254A, 254B.

In some embodiments, the second doping process 1015 and the first doping process 1005 are different types of doping processes, and the doping regions formed by the two have completely different dopant distribution patterns. For example, the first doping process 1005 is a solid-state source diffusion process, and the channel doped regions 214A and 214B formed by it have isotropic dopant concentration distributions corresponding to the first trenches 208A and 208B; the second doping process 1015 is Through the ion implantation process, the body doped region 236 thus formed has an anisotropic dopant concentration distribution (for example, a uniform distribution in the horizontal direction along the X-axis and a Gaussian distribution in the vertical direction along the Y-axis). In some embodiments, the body doped region 236 and the channel doped regions 254A, 254B have the same conductivity type (eg, P-type) and are opposite to the conductivity type of the epitaxial layer 204 (eg, N-type). After the body doped region 236 is formed, an annealing process (eg, rapid thermal annealing (RTA) and/or laser annealing) may be performed to activate the dopants in the body doped region 236 and repair possible problems caused by the second doping process 1015 Lattice damage to the epitaxial layer 204 .

As shown in Figure 9, after the oxide layer 231 is formed, a third doping process 1120 is performed to implant dopants into part of the epitaxial layer 204 outside the second trenches 218A and 218B (Figure 6) to form the channels. A source doped region 232 and a channel contact doped region 234 are formed on the doped regions 254A and 254B. The source doped region 232 is located in the epitaxial layer 204 on the channel doped regions 254A and 254B, and is close to the top surface of the epitaxial layer 204 (the interface between the epitaxial layer 204 and the oxide layer 231). Source doped region 232 may surround and adjoin gate structures 230A, 230B, while channel contact doped region 234 may adjoin source doped region 232 and channel doped regions 254A, 254B (and body doped region 236). In some embodiments, the third doping process 1120 and the first doping process 1005 are different types of doping processes. For example, the first doping process 1005 is a solid-state source diffusion process, and the third doping process 1120 is an ion implantation process. In some embodiments, the third doping process 1120 may include multiple doping steps to form the source doping region 232 and the channel contact doping region 234 respectively. In some embodiments, the source doped region 232 has the same conductivity type (eg, N-type) as the substrate 200 and the epitaxial layer 204 and is opposite to the conductivity type of the channel doped regions 254A and 254B. Furthermore, the dopant concentration of the source doped region 232 is greater than the dopant concentration of the epitaxial layer 204 . In some embodiments, channel contact doped region 234 and channel doped regions 254A, 254B have the same conductivity type (eg, P-type). Furthermore, the dopant concentration of the channel contact doped region 234 is greater than the dopant concentration of the channel doped regions 254A and 254B (and the body doped region 236). After the source doped region 232 and the channel contact doped region 234 are formed, an annealing process (eg, rapid thermal annealing (RTA) and/or laser annealing) may be performed to activate the source doped region 232 and the channel contact doped region. The doping and repair third doping process 1120 in region 234 may cause lattice damage to the epitaxial layer 204 . After the source doped region 232 and the channel contact doped region 234 are formed, an etching process (including wet etching or dry etching) can be used to remove the oxide layer 231 from the top surfaces of the gate structures 230A, 230B and the top surface of the epitaxial layer 204 .

Next, the formation method of the interlayer dielectric (ILD) 238A and 238B, the source electrode 240 and the drain electrode 242 is explained with reference to FIG. 10 . After forming the source doped region 232 and the channel contact doped region 234, a deposition process and a patterning process can be performed sequentially to form interlayer dielectrics 238A and 238B on the epitaxial layer 204. As shown in Figure 10, the interlayer dielectrics 238A and 238B are located directly above the gate structures 230A and 230B respectively, and cover the top surfaces of the gate structures 230A and 230B, so that the gate electrodes 228A and 228B are respectively covered by the interlayer dielectric. The materials 238A and 238B are completely covered with the corresponding gate dielectric layers 226A and 226B. Therefore, the gate electrodes 228A, 228B can be electrically isolated from the subsequently formed source electrode 240. In some embodiments, interlayer dielectrics 238A, 238B include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some embodiments, the deposition process includes spin-on, chemical vapor deposition (CVD), flow chemical vapor deposition (FCVD), plasma assisted chemical vapor deposition (PECVD), physical vapor deposition (PVD), or any appropriate deposition technology. In some embodiments, the patterning process includes lithography and etching processes.

As shown in FIG. 10 , after the interlayer dielectrics 238A and 238B are formed, the source electrode 240 is formed above the top surface 201 of the substrate 200 and on the top surface of the epitaxial layer 204 . In addition, a drain electrode 242 is formed on the bottom surface 203 of the substrate 200 . The source electrode 240 covers the source doped region 232 , the channel contact doped region 234 , the gate electrodes 228A and 228B and the interlayer dielectrics 238A and 238B, and is electrically connected to the source doped region 232 . The drain electrode 242 covers the bottom surface 203 of the substrate 200 and is electrically connected to the substrate 200 and the epitaxial layer 204, where the substrate 200 and the epitaxial layer 204 can together serve as the drain doping region of the finally formed semiconductor structure 250. In some embodiments, source electrode 240 and drain electrode 242 include polycrystalline silicon, metal, metal nitride, conductive metal oxide, or other suitable conductive materials. In some embodiments, the source electrode 240 and the drain electrode 242 may be formed using chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process. After the foregoing process, the semiconductor structure 250 of some embodiments of the present disclosure is formed.

As shown in FIG. 10 , the semiconductor structure 250 includes semiconductor structural units 250A and 250B that are adjacent to each other and have the same structure, and are disposed in the epitaxial layer 204 on the substrate 200 . The semiconductor structural unit 250A includes a gate structure 230A disposed in the second trench 218A (FIG. 6), a channel doping region disposed in the epitaxial layer 204 and adjacent to the upper portion 230A1 (FIG. 8) of the gate structure 230A. 254A, and the channel doping region 254A has a doping profile that is wide at the top and narrow at the bottom (taper). The semiconductor structural unit 250B includes a gate structure 230B disposed in the second trench 218B (FIG. 6), a channel doping region disposed in the epitaxial layer 204 and adjacent to the upper portion 230B1 (FIG. 8) of the gate structure 230B. 254B, and the channel doping region 254B has a doping profile that is wide at the top and narrow at the bottom (taper). Furthermore, the source electrode 240 and the drain electrode 242 of the semiconductor structural units 250A and 250B are respectively provided on the top surface 201 and the bottom surface 203 of the substrate 200.

The semiconductor structure forming method (method 100) of some embodiments of the present disclosure is used to form a trench gate semiconductor device, such as a vertical transistor device, through a dual trench process (first etching process 1000, second etching process 1000). The etching process 1010) and the diffusion process (first doping process 1005) form a channel doping region that is self-aligned and has a uniform dopant concentration distribution. Specifically, a substrate 200 is provided; and then an epitaxial layer 204 is formed on the substrate 200. ; Then, a first trench process (first etching process 1000) is performed to form first trenches 208A and 208B in the epitaxial layer 204; and then a first doping process 1005 (such as a solid-state source diffusion process) is performed. Channel doping regions 214A and 214B with isotropic dopant concentration distribution are formed on the sidewalls and bottom surfaces of trenches 208A and 208B; then a second trench process (second etching process 1010) is performed, from the first trench 208A , remove part of the channel doped regions 214A, 214B and part of the epitaxial layer 204 from the bottom surface of 208B to form second trenches 218A, 218B penetrating the channel doped regions in the epitaxial layer. At this time, the remaining portions of the channel doping regions (channel doping regions 254A and 254B) will be self-aligned and formed on the upper sidewall portions 220A1 and 220B1 of the second trenches 218A and 218B; and then formed in the second trenches 218A and 218B. Gate structures 230A, 230B are provided. Compared with the channel doped regions formed using ion implantation, the channel doped regions 254A and 254B formed through the double trench process and the diffusion process have more uniform doping in the vertical channel direction (substantially along the Y-axis direction). The dopant concentration distribution can avoid the problems such as critical voltage fluctuation (Vth fluctuation), breakdown lowering, and leakage caused by the uneven channel dopant concentration distribution of conventional vertical transistor devices, and thus Improve the electrical characteristics and reliability of vertical transistor devices.

Although the embodiments and advantages of the present disclosure have been disclosed above, it should be understood that any modification, substitution, modification, and combination can be made by anyone with ordinary knowledge in the art without departing from the spirit and scope of the disclosure. Various embodiments described above.

100:Method 102,104,106,108,110,112: Operation 200:Substrate 201:Top surface 203,212A,212B,222A,222B,236B: Bottom 204: Epitaxial layer 208A, 208B: first groove 206: Hard mask pattern 210A, 210B, 220A, 220B: side wall 214A, 214B, 254A, 254B: Channel doping area 216A, 216B: Doped silicon oxide material layer 214A1,214B1,254A1,254B1:Border 218A, 218B: Second groove 220A1, 220B1: Upper side wall part 220A2, 220B2: Lower side wall part 226A, 226B: Gate dielectric layer 228A, 228B: Gate electrode 230A, 230B: Gate structure 230A1, 230B1, 254A2, 254B2: upper part 230A2, 230B2, 254A3, 254B3: lower part 231:Oxide layer 232: Source doped region 234: Channel contact doping area 236: Body doped region 238A, 238B: Interlayer dielectric 240: Source electrode 242: Drain electrode 250:Semiconductor Structure 250A, 250B: Semiconductor structural unit 1000: First etching process 1005: The first doping process 1010: Second etching process 1015: Second doping process 1120: The third doping process D1,D2,D3,D4,D5: Depth L1,S: distance

The embodiments of the disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced in order to clearly illustrate the features of the embodiments of the invention. FIG. 1 is a flowchart of a method of forming a semiconductor structure according to some embodiments of the present disclosure. 2 to 10 are schematic cross-sectional views of semiconductor structures at various manufacturing stages according to some embodiments of the present disclosure.

100:Method

102,104,106,108,110,112: Operation

Claims (11)

A method for forming a semiconductor structure, including: providing a substrate; forming an epitaxial layer on the substrate; Perform a first etching process to form a first trench in the epitaxial layer; Performing a first doping process to form a channel doping region in the epitaxial layer adjacent to a side wall and a bottom surface of the first trench; Perform a second etching process to remove part of the channel doping region and part of the epitaxial layer from the bottom surface of the first trench to form a second trench penetrating the channel doping region in the epitaxial layer slot; and A gate structure is formed in the second trench. The method for forming a semiconductor structure as claimed in claim 1, wherein performing the first doping process includes: Perform a preset step to fill the first trench with a doped silicon oxide material layer, the conductivity type of the dopant in the doped silicon oxide material layer being opposite to the conductivity type of the epitaxial layer; Performing a driving step to diffuse the dopants in the doped silicon oxide material layer into the epitaxial layer beyond the sidewalls and the bottom surface of the first trench; and After forming the channel doped region, the doped silicon oxide material layer is removed. The method for forming the semiconductor structure of claim 1 further includes: After forming the second trench, a second doping process is performed to implant dopants into the epitaxial layer outside the second trench to form an integrated doping region on the channel doping region, where The first doping process and the second doping process are different types of doping processes. The method of forming a semiconductor structure according to claim 3, wherein the first doping process is a solid-state source diffusion process, and the second doping process is an ion implantation process. The method of forming a semiconductor structure as claimed in claim 1, wherein before performing the first etching process, a hard mask pattern is formed on the epitaxial layer, and during the first etching process, the hard mask pattern is removed from the epitaxial layer. The exposed portion of the epitaxial layer forms the first trench. A semiconductor structure including: a substrate; and A first semiconductor structural unit is provided on the substrate. The first semiconductor structural unit includes: An epitaxial layer is provided on the substrate; A trench is provided in the epitaxial layer; a gate structure disposed in the trench; and A channel doping region is disposed in the epitaxial layer and adjacent to an upper part of the gate structure, wherein the channel doping region has a doping profile that is wide at the top and narrow at the bottom. The semiconductor structure of claim 6, further comprising a second semiconductor structure unit disposed on the substrate, the second semiconductor structure unit and the first semiconductor structure unit being adjacent to each other and having the same properties as the first semiconductor structure unit. structure. The semiconductor structure of claim 7, wherein the lower part of the channel doping region of the first semiconductor structural unit and the lower part of the channel doping region of the second semiconductor structural unit are separated from each other. For example, the semiconductor structure of claim 7 further includes: A body doped region located in the epitaxial layer between the gate structure of the first semiconductor structural unit and a gate structure of the second semiconductor structural unit, wherein the body doped region is laterally connected to the first semiconductor An upper part of the channel doping region of the structural unit and an upper part of a channel doping region of the second semiconductor structural unit. The semiconductor structure of claim 9, wherein the channel doping region of the first semiconductor structural unit, the channel doping region and the body doping region of the second semiconductor structural unit have the same conductivity type, and are of the same conductivity type as the Lei The conductivity types of the crystal layers are opposite. For example, the semiconductor structure of claim 6 further includes: a source doping region located in the epitaxial layer on the channel doping region of the first semiconductor structural unit; A source electrode is disposed above a top surface of the substrate and on the epitaxial layer; and A drain electrode is provided on a bottom surface of the substrate.

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