TW202341662A - Oscillating signal generating circuit and a semiconductor apparatus using the same - Google Patents

Abstract

An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

Description

Oscillation signal generating circuit and semiconductor device using same

Various embodiments relate generally to integrated circuit technology, and more specifically to oscillation signal generating circuits and semiconductor devices using the same.

Electronic equipment includes many electronic components, and a computer system as the electronic equipment includes many semiconductor devices, each of which is configured by a semiconductor. Semiconductor devices that configure computer systems communicate with each other by sending and receiving clock signals and data. Semiconductor devices can operate in synchronization with clock signals. The clock signal may be generated by one of an oscillator, a phase locked loop circuit, etc.

Semiconductor devices can perform various operations by receiving system clock signals. In order to use the system clock signal internally, the semiconductor device can generate multiple internal clock signals from the system clock signal. Multiple internal clock signals may be generated by dividing the system clock signal or by frequency increasing the system clock signal. Multiple internal clock signals can be generated through multiple clock paths. Often, multiple clock paths can be designed with the same components and the same structure. However, multiple clock paths may have different amounts of delay due to process variations or degradation. These different amounts of delay can result in phase deviations between the multiple internal clock signals, which can reduce the effective window or duration of signals transmitted synchronously with the multiple internal clock signals. Accordingly, each semiconductor device may have a configuration for correcting phase deviations between a plurality of internal clock signals.

This application claims priority from Korean Application No. 10-2022-0045797 filed with the Korean Intellectual Property Office on April 13, 2022, the entire content of which is incorporated herein by reference in its entirety.

In one embodiment, an oscillation signal generating circuit may include a first clock delay circuit, a timing control circuit and an oscillation driver. The first clock delay circuit may be configured to delay the oscillation signal to generate the first control signal. The timing control circuit may be configured to delay the oscillation signal by a fixed delay amount to generate a second control signal. The oscillation driver may be configured to drive the oscillation signal to a first logic level based on the first control signal and to drive the oscillation signal to a second logic level based on the second control signal. Accurate.

In one embodiment, an oscillation signal generating circuit may include a first clock delay circuit, a first timing control circuit, a second timing control circuit and an oscillation driver. The first clock delay circuit may be configured to delay the oscillation signal. The first timing control circuit may be configured to receive an output signal from the first clock delay circuit to generate a first control signal. The second timing control circuit may be configured to delay the oscillation signal by a fixed delay amount to generate a second control signal. The oscillation driver may be configured to drive the oscillation signal to a first logic level based on the first control signal and to drive the oscillation signal to a second logic level based on the second control signal. Accurate.

In one embodiment, an oscillation signal generating circuit may include a first clock delay circuit, a second clock delay circuit, a selection circuit, a timing control circuit and an oscillation driver. The first clock delay circuit may be configured to delay the oscillation signal. The second clock delay circuit may be configured to delay the oscillation signal. The selection circuit may be configured to output one of an output signal from the first clock delay circuit and an output signal from the second clock delay circuit as a first control signal based on a selection signal. The timing control circuit may be configured to delay the oscillation signal by a fixed delay amount to generate a second control signal. The oscillation driver may be configured to generate the oscillation signal based on the first control signal and the second control signal.

In one embodiment, an oscillation signal generating circuit may include a first clock delay circuit, a set pulse generating circuit, a reset pulse generating circuit and an oscillation driver. The first clock delay circuit may be configured to delay the oscillation signal. The set pulse generator may be configured to generate a set pulse signal synchronized with one of a rising edge and a falling edge of the oscillation signal based on the output from the first clock delay circuit. The reset pulse generator may be configured to receive the set pulse signal and to generate a reset pulse signal. The oscillation driver may be configured to drive the oscillation signal to a first logic level based on the set pulse signal and to drive the oscillation signal to a second logic level based on the reset pulse signal. .

In one embodiment, an oscillation signal generating circuit may include a first clock delay circuit, a second clock delay circuit, a selection circuit, a setting pulse generator, a reset pulse generating circuit and an oscillation driver. The first clock delay circuit may be configured to delay the oscillation signal. The second clock delay circuit may be configured to delay the oscillation signal. The selection circuit may be configured to output one of an output signal from the first clock delay circuit and an output signal from the second clock delay circuit based on a selection signal. The set pulse generator may be configured to receive an output signal from the selection circuit and to generate a set pulse signal synchronized with one of a rising edge and a falling edge of the oscillation signal. The reset pulse generator may be configured to generate a reset pulse signal based on the set pulse signal. The oscillation driver may be configured to generate the oscillation signal based on the set pulse signal and the reset pulse signal.

In one embodiment, a semiconductor device may include a first clock delay circuit, a second clock delay circuit, an oscillation control circuit and a delay message generating circuit. The first clock delay circuit may be configured to delay the oscillation signal to generate a first output clock signal. The second clock delay circuit may be configured to delay the oscillation signal based on a delay control signal to generate a second output clock signal. The oscillation control circuit may be configured to control the oscillation signal to transition from a second logic level to a first logic level based on one of the first output clock signal and the second output clock signal, and be Configured to control the transition of the oscillation signal from the first logic level to the second logic level based on a signal generated by delaying the oscillation signal by a fixed delay amount. The delay message generation circuit may be configured to generate the delay control signal based on the oscillation signal generated by the first clock delay circuit and the oscillation signal generated by the second clock delay circuit.

In one embodiment, a semiconductor device may include a first clock delay circuit, a second clock delay circuit, an oscillation control circuit and a delay message generating circuit. The first clock delay circuit may be configured to delay the oscillation signal to generate a first output clock signal. The second clock delay circuit may be configured to delay the oscillation signal based on a delay control signal to generate a second output clock signal. The oscillation control circuit may be configured to generate a setting pulse signal based on one of the first output clock signal and the second output clock signal to control the transition of the oscillation signal from the second logic level to the first logic level. level, and is configured to generate a reset pulse signal based on the set pulse signal to control the transition of the oscillation signal from the first logic level to the second logic level. The delay message generation circuit may be configured to generate the delay control signal based on the oscillation signal generated by the first clock delay circuit and the oscillation signal generated by the second clock delay circuit.

FIG. 1 is a diagram illustrating the configuration of an oscillation signal generating circuit 100 according to one embodiment. In order to monitor the delay amount of the clock delay circuit through which the clock signal propagates, the oscillation signal generation circuit 100 can generate the oscillation signal ROD through the clock delay circuit. The oscillation signal generation circuit 100 can generate the oscillation signal ROD such that one of the rising edge and the falling edge of the oscillation signal ROD meets consistent timing. On the other hand, the oscillation signal generation circuit 100 may generate the oscillation signal ROD such that the other one of the rising edge and the falling edge of the oscillation signal ROD meets the timing that changes according to the delay amount of the clock delay circuit. The rising edge of the oscillation signal ROD may be the part where the oscillation signal ROD transitions from a low logic level to a high logic level. The falling edge of the oscillation signal ROD may be the portion where the oscillation signal ROD transitions from a high logic level to a low logic level. For example, the oscillation signal generation circuit 100 can generate the falling edge of the oscillation signal ROD according to the delay amount of the clock delay circuit, and can generate the rising edge of the oscillation signal ROD when a fixed period elapses after generating the falling edge. In one embodiment, the oscillation signal generation circuit 100 can generate the rising edge of the oscillation signal ROD according to the delay amount of the clock delay circuit, and can generate the falling edge of the oscillation signal ROD when a fixed period elapses after generating the rising edge. The oscillation signal generation circuit 100 may be coupled to a plurality of clock delay circuits in sequence, and may be configured to generate the oscillation signal ROD. The oscillation signal generation circuit 100 can generate the rising edge of the oscillation signal ROD after a fixed period has elapsed after generating the falling edge of the oscillation signal ROD. Therefore, the period of the oscillation signal ROD can accurately include the delay amount deviation among the plurality of clock delay circuits. ,The delay deviation is the difference between the actual delay ,and the expected delay of the clock delay circuit.

Referring to FIG. 1 , the oscillation signal generation circuit 100 may include a first clock delay circuit 111 , a timing control circuit 120 and an oscillation driver 130 . The first clock delay circuit 111 can receive the oscillation signal ROD to delay the oscillation signal ROD. The first clock delay circuit 111 may provide a delayed oscillation signal as the first control signal RCS. In the normal mode, the first clock delay circuit 111 may receive the first input clock signal CLKI1 and may delay the first input clock signal CLKI1 to generate the first output clock signal CLKO1. In the compensation mode, the first clock delay circuit 111 can receive the oscillation signal ROD, and can delay the oscillation signal ROD to generate the first output clock signal CLKO1, and provide the first output clock signal CLKO1 as the first control signal RCS. . The first control signal RCS may be generated based on an edge of the oscillation signal ROD transitioning from the first logic level to the second logic level. The first control signal RCS may be generated when a period corresponding to the delay amount of the first clock delay circuit 111 passes after the oscillation signal ROD transitions from the first logic level to the second logic level. The first logic level may be a low logic level and the second logic level may be a high logic level. In one embodiment, the first logic level may be a high logic level and the second logic level may be a low logic level. The normal mode may be a mode in which the first clock delay circuit 111 operates as a clock buffer. The compensation mode may be a mode in which the amount of delay caused by the first clock delay circuit 111 is monitored. The normal mode and the compensation mode can be determined based on the enable signal OSCEN. When the enable signal OSCEN is disabled, the oscillation signal generation circuit 100 can operate in the normal mode, and the first clock delay circuit 111 can delay the first input clock signal CLKI1 to generate the first output clock signal CLKO1 . When the enable signal OSCEN is enabled, the oscillation signal generation circuit 100 may operate in the compensation mode, and the first clock delay circuit 111 may delay the oscillation signal ROD to generate the first output clock signal CLKO1. The first clock delay circuit 111 may be configured by a plurality of inverters or a plurality of logic gates coupled in series.

The timing control circuit 120 can receive the oscillation signal ROD. The timing control circuit 120 may delay the oscillation signal ROD by a fixed delay amount to generate the second control signal FCS. The timing control circuit 120 may generate the second control signal FCS based on the edge of the oscillation signal ROD transitioning from the second logic level to the first logic level. The timing control circuit 120 may generate the second control signal FCS when a period corresponding to the fixed delay amount elapses after generating an edge in which the oscillation signal ROD transitions from the second logic level to the first logic level. The timing control circuit 120 may include a delay replica unit 121 and a pulse generator 122 . The delay replica unit 121 can receive the oscillation signal ROD, and can delay the oscillation signal ROD by a fixed delay amount. The delay replica unit 121 can be implemented by modeling the first clock delay circuit 111 . Therefore, in an ideal case, the delay replica unit 121 may have the same delay amount as the first clock delay circuit 111 . The pulse generator 122 may be coupled to the delay replica unit 121 and may receive an output signal from the delay replica unit 121 . The pulse generator 122 may generate the second control signal FCS based on the output signal from the delay replica unit 121 .

The oscillation driver 130 may receive the first control signal RCS and the second control signal FCS, and may generate the oscillation signal ROD based on the first control signal RCS and the second control signal FCS. The oscillation driver 130 may drive the oscillation signal ROD to a first logic level based on the first control signal RCS, and may drive the oscillation signal ROD to a second logic level based on the second control signal FCS. The oscillation driver 130 can control the oscillation signal ROD to transition from the second logic level to the first logic level when the first control signal RCS is enabled, and can control the oscillation signal ROD to transition from the second logic level to the first logic level when the second control signal FCS is enabled. One logic level transitions to a second logic level. The oscillation driver 130 may receive the first power supply voltage VH and the second power supply voltage VL, and may generate the oscillation signal ROD based on the first power supply voltage VH and the second power voltage VL. The first power supply voltage VH may have a higher voltage level than the second power supply voltage VL. The first power supply voltage VH may have a high enough voltage level to be considered a high logic level. The second supply voltage VL may have a low enough voltage level to be considered a low logic level. The oscillation driver 130 may drive the oscillation signal ROD to a voltage level of the second power supply voltage VL based on the first control signal RCS, and may drive the oscillation signal ROD to a voltage level of the first power supply voltage VH based on the second control signal FCS. The oscillation driver 130 can also receive the enable signal OSCEN. When the enable signal OSCEN is enabled, the oscillation driver 130 may be activated and may generate the oscillation signal ROD based on the first control signal RCS and the second control signal FCS. When the enable signal OSCEN is disabled, the oscillation driver 130 can be deactivated, and the oscillation signal ROD can be fixed to a predetermined logic level regardless of the first control signal RCS and the second control signal FCS. For example, the oscillation driver 130 may disable the oscillation signal ROD.

The oscillation signal generating circuit 100 may further include a second clock delay circuit 112 and a selection circuit 140. The second clock delay circuit 112 can receive the oscillation signal ROD to delay the oscillation signal ROD. In the normal mode, the second clock delay circuit 112 may receive the second input clock signal CLKI2 and may delay the second input clock signal CLKI2 to generate the second output clock signal CLKO2. In the compensation mode, the second clock delay circuit 112 may receive the oscillation signal ROD, delay the oscillation signal ROD to generate the second output clock signal CLKO2, and provide the second output clock signal CLKO2 to the selection circuit 140. When the enable signal OSCEN is disabled, the oscillation signal generation circuit 100 can operate in the normal mode, and the second clock delay circuit 112 can delay the second input clock signal CLKI2 to generate the second output clock signal CLKO2 . When the enable signal OSCEN is enabled, the oscillation signal generation circuit 100 may operate in the compensation mode, and the second clock delay circuit 112 may delay the oscillation signal ROD to generate the second output clock signal CLKO2. The second clock delay circuit 112 may be configured through a plurality of inverters or a plurality of logic gates coupled in series. The second clock delay circuit 112 may have substantially the same configuration as the first clock delay circuit 111 . The delay replica unit 121 may be implemented by modeling at least one of the first clock delay circuit 111 and the second clock delay circuit 112 .

The selection circuit 140 may be coupled to the first and second clock delay circuits 111 and 112 . The selection circuit 140 may receive the first output clock signal CLKO1 and the second output clock signal CLKO2 from the first clock delay circuit 111 and the second clock delay circuit 112 respectively as output signals. The selection circuit 140 can also receive the selection signal SEL. Based on the selection signal SEL, the selection circuit 140 may output one of the output signals from the first clock delay circuit 111 and the second clock delay circuit 112 as the first control signal RCS. In the compensation mode, the selection signal SEL may be a control signal for sequentially monitoring the delay amounts of the first clock delay circuit 111 and the second clock delay circuit 112 . For example, when the selection signal SEL has a first logic level, the selection circuit 140 may output the first output clock signal CLKO1 as the first control signal RCS. When the selection signal SEL has the second logic level, the selection circuit 140 may output the second output clock signal CLKO2 as the first control signal RCS. When the first output clock signal CLKO1 is selected by the selection circuit 140, the oscillation signal generation circuit 100 can generate the oscillation signal ROD that reflects the delay amount of the first clock delay circuit 111. When the second output clock signal CLKO2 is selected by the selection circuit 140, the oscillation signal generation circuit 100 can generate the oscillation signal ROD that reflects the delay amount of the second clock delay circuit 112. The selection signal SEL can be realized by any control signal. For example, when the enable signal OSCEN is enabled and the oscillation signal generation circuit 100 operates in the compensation mode, the initial level of the selection signal SEL may be at the first logic level. When the monitoring of the oscillation signal ROD generated by being coupled to the first clock delay circuit 111 is completed, the logic level of the selection signal SEL may transition to the second logic level. The selection signal SEL can be initialized when the enable signal OSCEN is disabled.

FIG. 2 is a diagram explaining the pulse generator 122 shown in FIG. 1 . Referring to FIG. 2 , the pulse generator 122 may include a first inverter 122-1, a delay 122-2, a second inverter 122-3, and an NAND gate 122-4. The first inverter 122 - 1 may receive an output signal from the delay replica unit 121 (see FIG. 1 ) to invert and drive the output signal from the delay replica unit 121 . Delayer 122-2 may receive the output from first inverter 122-1 to delay the output from first inverter 122-1. Second inverter 122-3 may receive the output from delayer 122-2 to invert and drive the output from delayer 122-2. The NAND gate 122-4 may receive the output from the first inverter 122-1 and the output from the second inverter 122-3 to output the second control signal FCS. When the output from the delay replica unit 121 transitions from a high logic level to a low logic level, the pulse generator 122 may generate a low logic level pulse signal having a pulse width corresponding to the delay amount of the delay device 122-2 as The second control signal FCS.

FIG. 3 is a diagram explaining the oscillation driver 130 shown in FIG. 1 . Referring to FIG. 3 , the oscillation driver 130 may include a pull-up transistor 131 , a pull-down transistor 132 , an NAND gate 133 , a first inverter 134 and a second inverter 135 . Based on the second control signal FCS, the pull-up transistor 131 can drive the driving node DN to the first power voltage VH. The pull-up transistor 131 may be a P-channel MOS transistor. In one embodiment, the pull-up transistor 131 may be implemented by an N-channel MOS transistor. The pull-up transistor 131 may receive the first supply voltage VH at its source and may be coupled to the drive node DN at its drain. The pull-up transistor 131 can receive the second control signal FCS at its gate. When the second control signal FCS is enabled to a low logic level, the pull-up transistor 131 can drive the driving node DN to the first power voltage VH. Based on the first control signal RCS, the pull-down transistor 132 can drive the driving node DN to the second power voltage VL. Pull-down transistor 132 may be an N-channel MOS transistor. Pull-down transistor 132 may be coupled to the drive node DN at its drain and may receive the second supply voltage VL at its source. The pull-down transistor 132 can receive the first control signal RCS at its gate. When the first control signal RCS is enabled to a high logic level, the pull-down transistor 132 can drive the driving node DN to the second power voltage VL. NAND gate 133 may be coupled to the driving node DN and may receive a signal from the driving node DN. The NAND gate 133 can receive the signal from the driving node DN and the enabling signal OSCEN. When the enable signal OSCEN is enabled to a high logic level, the NAND gate 133 can invert and drive the signal from the drive node DN. The output of NAND gate 133 may be coupled to latch node LN. In one embodiment, the oscillation driver 130 may not receive the enable signal OSCEN, and the NAND gate 133 may be replaced with an inverter. The first inverter 134 may be coupled between the latch node LN and the drive node DN. The first inverter 134 may invert and drive the signal from the latch node LN, and may output the inverted and driven signal to the driving node DN. The first inverter 134 may form an inversion latch together with the NAND gate 133 and may maintain the logic levels of the drive node DN and the latch node LN. The second inverter 135 may receive the signal from the latch node LN, and may invert and drive the signal from the latch node LN to output the oscillation signal ROD.

4A and 4B are timing diagrams illustrating the operation of the oscillation signal generation circuit 100 according to one embodiment. The operation of the oscillation signal generating circuit 100 will be described below with reference to FIGS. 1 to 4B. Referring to FIG. 4A , when the enable signal OSCEN is enabled, the selection signal SEL may have a first logic level, and the oscillation signal generation circuit 100 may generate the oscillation signal ROD through the first clock delay circuit 111 . For convenience of description, the oscillation signal ROD generated by being connected to the first clock delay circuit 111 may be called the first oscillation signal ROD1. The first clock delay circuit 111 may delay the first oscillation signal ROD1 to generate the first output clock signal CLKO1. The selection circuit 140 may provide the first output clock signal CLKO1 as the first control signal RCS. After the first oscillation signal ROD1 transitions from a low logic level to a high logic level, the first control signal RCS may be delayed by a period corresponding to the delay amount TD1 of the first clock delay circuit 111 to be enabled to a high logic level. Accurate. The first control signal RCS may remain enabled during a period corresponding to the high-level pulse portion of the first oscillation signal ROD1. Based on the first control signal RCS, the oscillation driver 130 can drive the driving node DN to the second power supply voltage VL to control the first oscillation signal ROD1 to change from a high logic level to a low logic level. The NAND gate 133 and the first inverter 134 can maintain the logic level of the first oscillation signal ROD1 at a low logic level. In the timing control circuit 120, the delay replica unit 121 may delay the first oscillation signal ROD1, and the pulse generator 122 may generate a second control signal FCS that transitions to a low logic level based on the output from the delay replica unit 121. . After the first oscillation signal ROD1 transitions from a high logic level to a low logic level, the second control signal FCS may be delayed by a period corresponding to the delay amount TDR of the delay replica unit 121 and the delay amount α of the pulse generator 122 corresponding period to be enabled to a low logic level. Based on the second control signal FCS, the oscillation driver 130 can drive the driving node DN to the first power supply voltage VH to control the first oscillation signal ROD1 to transition from a low logic level to a high logic level. The NAND gate 133 and the first inverter 134 can maintain the logic level of the first oscillation signal ROD1 at a high logic level. Therefore, the high-level pulse part of the first oscillation signal ROD1 may correspond to the delay amount TD1 of the first clock delay circuit 111 , and the low-level pulse part of the first oscillation signal ROD1 may correspond to the delay amount TDR of the delay replica unit 121 and The sum of the delay amounts α of the pulse generator 122 is TDR+α.

After the oscillation signal ROD is generated by being connected to the first clock delay circuit 111 , the selection signal SEL may be changed to have a second logic level, and the oscillation signal generation circuit 100 may generate an oscillation signal through the second clock delay circuit 112 ROD. For convenience of description, the oscillation signal ROD generated by being connected to the second clock delay circuit 112 may be referred to as the second oscillation signal ROD2. The second clock delay circuit 112 may delay the second oscillation signal ROD2 to generate the second output clock signal CLKO2. The selection circuit 140 may provide the second output clock signal CLKO2 as the first control signal RCS. After the second oscillation signal ROD2 transitions from a low logic level to a high logic level, the first control signal RCS may be delayed for a period corresponding to the delay amount TD2 of the second clock delay circuit 112 to be enabled to a high logic level. Accurate. The first control signal RCS may remain enabled during a period corresponding to the high-level pulse portion of the second oscillation signal ROD2. Based on the first control signal RCS, the oscillation driver 130 can drive the driving node DN to the second power supply voltage VL to control the second oscillation signal ROD2 to transition from a high logic level to a low logic level. The NAND gate 133 and the first inverter 134 can maintain the logic level of the second oscillation signal ROD2 at a low logic level. In the timing control circuit 120, the delay replica unit 121 may delay the second oscillation signal ROD2, and the pulse generator 122 may generate the second control signal FCS that transitions to a low logic level based on the output from the delay replica unit 121. . After the second oscillation signal ROD2 transitions from a high logic level to a low logic level, the second control signal FCS may be delayed by a period corresponding to the delay amount TDR of the delay replica unit 121 and the delay amount α of the pulse generator 122 corresponding period to be enabled to a low logic level. Based on the second control signal FCS, the oscillation driver 130 can drive the driving node DN to the first power supply voltage VH to control the second oscillation signal ROD2 to transition from a low logic level to a high logic level. The NAND gate 133 and the first inverter 134 can maintain the logic level of the second oscillation signal ROD2 at a high logic level. Therefore, the high-level pulse part of the second oscillation signal ROD2 may correspond to the delay amount TD2 of the second clock delay circuit 112 , and the low-level pulse part of the second oscillation signal ROD2 may correspond to the delay amount TDR of the delay replica unit 121 and The sum of the delay amounts α of the pulse generator 122 is TDR+α.

When the first oscillation signal ROD1 and the second oscillation signal ROD2 are compared with each other, the high-level pulse parts of the first oscillation signal ROD1 and the second oscillation signal ROD2 may be based on the delay amount TD1 and the second clock delay circuit 111 respectively. The delay amount TD2 of the two clock delay circuit 112 changes, and each of the low-level pulse parts of the first oscillation signal ROD1 and the second oscillation signal ROD2 can be equal to the sum of the delay amounts of the delay replica unit 121 and the pulse generator 122 TDR+α is the same. Therefore, the period between each of the first oscillation signal ROD1 and the second oscillation signal ROD2 transitioning to a low logic level and each of the first oscillation signal ROD1 and the second oscillation signal ROD2 transitioning to a high logic level It may be consistent regardless of the delay amount deviation between the first clock delay circuit 111 and the second clock delay circuit 112 . Typically, a semiconductor device can be synchronized to at least one of a rising edge and a falling edge of a clock signal. For example, when a semiconductor device is synchronized to the rising edge of a clock signal, the timing of the falling edge may be less important than the timing of the rising edge. The oscillation signal generation circuit 100 can be used for the oscillation signal ROD, and the period between the oscillation signal ROD that transitions to a low logic level and the oscillation signal ROD that transitions to a high logic level is set to be consistent, excluding the first output clock. The timing deviation between the falling edge of signal CLKO1 and the second output clock signal CLKO2. On the other hand, the oscillation signal generation circuit 100 can be used for the oscillation signal ROD, and the period between the oscillation signal ROD that transitions to a high logic level and the oscillation signal ROD that transitions to a low logic level is set according to the first clock delay circuit The delay amount of 111 and the second clock delay circuit 112 is variable to include only the timing deviation between the rising edges of the first output clock signal CLKO1 and the second output clock signal CLKO2.

Referring to FIG. 4B , when the first clock delay circuit 111 is implemented through multiple inverters, path A (illustrated with dotted lines) may be used to generate the falling edge of the first output clock signal CLKO1 and the oscillation signal ROD. path B (illustrated by alternating long and dash lines) may be a path for generating the rising edge of the first output clock signal CLKO1 and the falling edge of the oscillation signal ROD. It may happen that the transistor in path A is damaged but no transistor in path B is damaged. In this case, as shown in FIG. 4B , the first oscillation signal ROD1' generated according to the prior art may have a relatively short high level part and a relatively long low level part. On the other hand, according to one embodiment, the oscillation signal generation circuit 100 may generate the rising edge of the first oscillation signal ROD1 through the timing control circuit 120 including the delay replica unit 121 . The second clock delay circuit 112 may not be damaged, so the second oscillation signal ROD2' generated according to the prior art may have a high level part and a low level part of substantially the same duration. On the other hand, according to one embodiment, the oscillation signal generation circuit 100 may generate the rising edge of the second oscillation signal ROD2 through the timing control circuit 120 including the delay replica unit 121 . Therefore, according to one embodiment, even when the first clock delay circuit 111 is damaged, the periods of the first oscillation signal ROD1 and the second oscillation signal ROD2 may be substantially the same as each other. That is, even when a timing deviation occurs between falling edges due to the first clock delay circuit 111 and the second clock delay circuit 112, the oscillation signal generation circuit 100 may not include the timing deviation between the falling edges of the oscillation signal ROD. , and only includes the timing deviation between the rising edges of the oscillation signal ROD. Therefore, the oscillation signal generating circuit 100 can accurately detect the timing deviation between the rising edges of the first clock delay circuit 111 and the second clock delay circuit 112 to effectively correct the first clock delay circuit 111 and the second clock delay circuit 112 . Phase deviation of clock delay circuit 112.

FIG. 5 is a diagram illustrating the configuration of the oscillation signal generating circuit 200 according to one embodiment. Referring to FIG. 5 , the oscillation signal generation circuit 200 may include a first clock delay circuit 211 , a first timing control circuit 250 , a second timing control circuit 220 and an oscillation driver 230 . The second timing control circuit 220 may include a delay replica unit 221 and a first pulse generator 222. The first clock delay circuit 211, the second timing control circuit 220 and the oscillation driver 230 may be substantially the same components as the first clock delay circuit 111, the timing control circuit 120 and the oscillation driver 130 shown in FIG. 1, respectively, and therefore will Description of the same elements is omitted. The first timing control circuit 250 may receive the output signal from the first clock delay circuit 211 to generate the first control signal RCS based on the output signal from the first clock delay circuit 211 . The first timing control circuit 250 may generate the first control signal RCS based on an edge of the oscillation signal ROD transitioning from the second logic level to the first logic level. The first timing control circuit 250 may include a second pulse generator 251. The second pulse generator 251 may receive the first output clock signal CLKO1 to generate the first control signal RCS based on the first output clock signal CLKO1. The oscillation signal generating circuit 200 may also include a second clock delay circuit 212 and a selection circuit 240. The second clock delay circuit 212 and the selection circuit 240 may be substantially the same components as the second clock delay circuit 112 and the selection circuit 140 shown in FIG. 1 , respectively. The first timing control circuit 250 may generate the first control signal RCS based on the output signal 241 from the selection circuit 240 . The oscillation signal generation circuit 100 (see FIG. 1 ) may provide the oscillation signal ROD delayed through one of the first clock delay circuit 111 and the second clock delay circuit 112 as the first control signal RCS. The oscillation signal generation circuit 200 of FIG. 5 can generate a pulse-type first control signal RCS from the oscillation signal ROD delayed through one of the first clock delay circuit 211 and the second clock delay circuit 212. The first control signal RCS Similar to the second control signal FCS.

FIG. 6 is a diagram explaining the second pulse generator 251 shown in FIG. 5 . Referring to FIG. 6 , the second pulse generator 251 may include a first inverter 251-1, a delayer 251-2, a second inverter 251-3, and an inverse-OR gate 251-4. The first inverter 251-1 can receive the output signal 241 from the selection circuit 240 to invert and drive the output signal 241 from the selection circuit 240. The delayer 251-2 may receive the output from the first inverter 251-1 to delay the output from the first inverter 251-1. The second inverter 251-3 may receive the output from the delayer 251-2 to invert and drive the output from the delayer 251-2. The NOR gate 251-4 may receive the output from the first inverter 251-1 and the output from the second inverter 251-3 to output the first control signal RCS. When the output signal 241 from the selection circuit 240 transitions from a low logic level to a high logic level, the second pulse generator 251 may generate a high logic level pulse having a pulse width corresponding to the delay amount of the delay device 251-2 signal as the first control signal RCS.

FIG. 7 is a timing diagram illustrating the operation of the oscillation signal generating circuit 200 shown in FIG. 6 according to one embodiment. The operation of the oscillation signal generating circuit 200 will be described below with reference to FIGS. 6 and 7 . When the enable signal OSCEN is enabled, the selection signal SEL may have a first logic level, and the oscillation signal generation circuit 200 may generate the oscillation signal ROD through the first clock delay circuit 211 . The first clock delay circuit 211 may delay the oscillation signal ROD to generate the first output clock signal CLKO1. The selection circuit 240 may provide the first output clock signal CLKO1 as the output signal 241 to the first timing control circuit 250 . The first timing control circuit 250 may generate a third signal that is enabled to a high logic level after a period corresponding to the delay amount TD1 of the first clock delay circuit 211 after the oscillation signal ROD transitions from a low logic level to a high logic level. A control signal RCS. The first control signal RCS can be generated in the form of pulses through the second pulse generator 251 . Based on the first control signal RCS, the oscillation driver 230 can control the oscillation signal ROD to change from a high logic level to a low logic level. In the second timing control circuit 220 , the delay replica unit 221 may delay the oscillation signal ROD, and the first pulse generator 222 may generate a second control signal that transitions to a low logic level based on the output from the delay replica unit 221 FCS. After the oscillation signal ROD transitions from a high logic level to a low logic level, the second control signal FCS may be delayed by a period corresponding to the delay amount TDR of the delay replica unit 221 and the delay amount α of the first pulse generator 222 corresponding period to be enabled to a low logic level. Based on the second control signal FCS, the oscillation driver 230 can control the oscillation signal ROD to change from a low logic level to a high logic level. Therefore, the high-level pulse part of the oscillation signal ROD may correspond to the delay amount TD1 of the first clock delay circuit 211 , and the low-level pulse part of the oscillation signal ROD may correspond to the delay amount TDR of the delay replica unit 221 and the first pulse generation The sum of the delay amounts α of the device 222 is TDR+α. As shown in FIG. 1 , when the output signals from the first clock delay circuit 111 and the second clock delay circuit 112 are directly provided as the first control signal RCS, it is possible to set the delay amount TDR of the delay replica unit 121 There are limitations. When the delay amount TDR of the delay replica unit 121 is smaller than the delay amount of the first clock delay circuit 111 or the second clock delay circuit 112, the second control signal FCS may be enabled before the first control signal RCS is disabled. situation. When the enabling portions of the first control signal RCS and the second control signal FCS overlap each other, it may be difficult for the oscillation driver 130 to drive the oscillation signal ROD normally. However, the first timing control circuit 250 (see FIG. 5 ) may generate the oscillation signal ROD having the same pulse form as the second control signal FCS, so the delay amount TDR of the delay replica unit 221 may be removed or reduced based on the set limit.

FIG. 8 is a diagram illustrating the configuration of the oscillation signal generation circuit 300 according to one embodiment. Referring to FIG. 8 , the oscillation signal generation circuit 300 may include a first clock delay circuit 311 , a set pulse generator 320 , a reset pulse generator 330 and an oscillation driver 340 . The first clock delay circuit 311 may be substantially the same element as the first clock delay circuit 111 shown in FIG. 1 , and therefore the description of the first clock delay circuit 311 will be omitted. The setting pulse generator 320 may receive the output signal from the first clock delay circuit 311 and may generate the setting pulse signal SET based on the output signal from the first clock delay circuit 311 . The set pulse generator 320 may generate the set pulse signal SET synchronized with one of the rising edge and the falling edge of the oscillation signal ROD based on the output signal from the first clock delay circuit 311. For example, the setting pulse generator 320 may receive the output signal from the first clock delay circuit 311 to generate the setting pulse signal SET based on the edge of the oscillation signal ROD transitioning from the first logic level to the second logic level. The setting pulse generator 320 may generate the setting pulse signal SET when a period corresponding to the delay amount of the first clock delay circuit 311 elapses after generating the edge of the oscillation signal ROD. The reset pulse generator 330 may receive the set pulse signal SET from the set pulse generator 320. The reset pulse generator 330 may generate the reset pulse signal RST based on the set pulse signal SET. The reset pulse generator 330 can enable the reset pulse signal RST when the setting pulse signal SET is disabled.

The oscillation driver 340 may receive the set pulse signal SET and the reset pulse signal RST, and may generate the oscillation signal ROD based on the set pulse signal SET and the reset pulse signal RST. The oscillation driver 340 may drive the oscillation signal ROD to a first logic level based on the set pulse signal SET, and may drive the oscillation signal ROD to a second logic level based on the reset pulse signal RST. The oscillation driver 340 can control the oscillation signal ROD to change from the second logic level to the first logic level when the set pulse signal SET is enabled, and control the oscillation signal ROD to change from the first logic level to the first logic level when the reset pulse signal RST is enabled. level transition to the second logic level. The oscillation driver 340 may receive the first power supply voltage VH and the second power supply voltage VL, and may generate the oscillation signal ROD based on the first power supply voltage VH and the second power voltage VL. The oscillation driver 340 may drive the oscillation signal ROD to the voltage level of the second power supply voltage VL based on the set pulse signal SET, and may drive the oscillation signal ROD to the voltage level of the first power supply voltage VH based on the reset pulse signal RST. The oscillation driver 340 can also receive the enable signal OSCEN. When the enable signal OSCEN is enabled, the oscillation driver 340 may be activated to generate the oscillation signal ROD based on the set pulse signal SET and the reset pulse signal RST. When the enable signal OSCEN is disabled, the oscillation driver 340 can be deactivated to fix the oscillation signal ROD to a predetermined logic level regardless of the set pulse signal SET and the reset pulse signal RST. The oscillation driver 340 may have substantially the same configuration as the oscillation driver 130 shown in FIG. 3 except that the oscillation driver 340 receives the set pulse signal SET instead of the first control signal RCS and the reset pulse signal RST instead of the second control signal FCS. .

The oscillation signal generating circuit 300 may also include a second clock delay circuit 312 and a selection circuit 350. The second clock delay circuit 312 and the selection circuit 350 may be substantially the same elements as the second clock delay circuit 112 and the selection circuit 140 shown in FIG. 1 , respectively, and therefore descriptions of the same elements will be omitted. When the oscillation signal generation circuit 300 includes the selection circuit 350 , the setting pulse generator 320 may receive the output signal 351 from the selection circuit 350 , and may generate the setting pulse signal SET based on the output signal 351 from the selection circuit 350 . According to the oscillation signal generation circuit 300, the timing for generating the set pulse signal SET may depend on the delay amount of the first clock delay circuit 311 and the second clock delay circuit 312, and the timing for enabling the reset pulse signal RST The timing for the disabling setting pulse signal SET may be consistent. Therefore, the oscillation signal generation circuit 300 can generate the oscillation signal ROD, which only includes the timing deviation between the rising edges of the first clock delay circuit 311 and the second clock delay circuit 312, and does not include the timing deviation due to the first clock delay. Timing offset between the falling edges of circuit 311 and second clock delay circuit 312.

FIG. 9 is a diagram illustrating the installation pulse generator 320 shown in FIG. 8 . Referring to FIG. 9 , the set pulse generator 320 may include a first inverter 321 , a delay 322 , a second inverter 323 and an inverse-OR gate 324 . The first inverter 321 may receive the output signal 351 from the selection circuit 350 to invert and drive the output signal 351 from the selection circuit 350 . The delayer 322 may receive the output from the first inverter 321 to delay the output from the first inverter 321 . The second inverter 323 may receive the output from the delayer 322 to invert and drive the output from the delayer 322 . The NOR gate 324 may receive the output from the first inverter 321 and the output from the second inverter 323 to output the setting pulse signal SET. When the output signal 351 from the selection circuit 350 transitions from a high logic level to a low logic level, the pulse generator 320 is set to generate a high logic level pulse signal with a pulse width corresponding to the delay amount of the delayer 322 as Set the pulse signal SET.

FIG. 10 is a diagram illustrating the reset pulse generator 330 shown in FIG. 8 . Referring to FIG. 10 , the reset pulse generator 330 may include a first inverter 331 , a delay 332 , a second inverter 333 and an NAND gate 334 . The first inverter 331 may receive the setting pulse signal SET to invert and drive the setting pulse signal SET. The delayer 332 may receive the output from the first inverter 331 to delay the output from the first inverter 331 . The second inverter 333 may receive the output from the delayer 332 to invert and drive the output from the delayer 332 . The NAND gate 334 may receive the output from the first inverter 331 and the output from the second inverter 333 to output the reset pulse signal RST. When the set pulse signal SET transitions from a high logic level to a low logic level, the reset pulse generator 330 may generate a low logic level pulse signal having a pulse width corresponding to the delay amount of the delay 332 as a reset pulse. Signal RST.

FIG. 11 is a timing diagram illustrating the operation of the oscillation signal generation circuit 300 according to one embodiment. Referring to FIGS. 8 to 11 , when the enable signal OSCEN is enabled, the selection signal SEL may have a first logic level, and the oscillation signal generation circuit 300 may generate the oscillation signal ROD through the first clock delay circuit 311 . The first clock delay circuit 311 may delay the oscillation signal ROD to generate the first output clock signal CLKO1. The selection circuit 350 may provide the first output clock signal CLKO1 to the setting pulse generator 320 . The setting pulse generator 320 may generate a setting pulse enabled to a high logic level when a period corresponding to the delay amount TD1 of the first clock delay circuit 311 passes after the oscillation signal ROD transitions from a low logic level to a high logic level. Signal SET. Based on the setting pulse signal SET, the oscillation driver 340 can control the oscillation signal ROD to change from a high logic level to a low logic level. The reset pulse generator 330 may generate the reset pulse signal RST that is enabled to a low logic level when the setting pulse signal SET is disabled. Based on the reset pulse signal RST, the oscillation driver 340 can control the oscillation signal ROD to change from a low logic level to a high logic level. Therefore, the high-level pulse part of the oscillation signal ROD may correspond to the delay amount TD1 of the first clock delay circuit 311 , and the low-level pulse part of the oscillation signal ROD may correspond to the pulse width of the setting pulse signal SET.

FIG. 12 is a diagram illustrating the configuration of a semiconductor device 400 according to one embodiment. Referring to FIG. 12 , the semiconductor device 400 may include at least two clock delay circuits, an oscillation control circuit 430 and a delay message generation circuit 440 . FIG. 12 illustrates four clock delay circuits, but the number of clock delay circuits is not limited thereto. The semiconductor device 400 may include first to fourth clock delay circuits 411, 412, 413, and 414. The first clock delay circuit 411 may receive the first phase clock signal ICLK and the oscillation signal ROD to generate the first output clock signal ICLKO. The first clock delay circuit 411 may delay the first phase clock signal ICLK to generate the first output clock signal ICLKO in the normal mode, and may delay the oscillation signal ROD in the compensation mode to generate the first output clock signal. Pulse signal ICLKO. The first clock delay circuit 411 may have a fixed delay amount. In one embodiment, the first clock delay circuit 411 may have a variable delay amount. The first clock delay circuit 411 can also receive the enable signal OSCEN. When the enable signal OSCEN is disabled, the first clock delay circuit 411 may delay the first phase clock signal ICLK to generate the first output clock signal ICLKO. When the enable signal OSCEN is enabled, the first clock delay circuit 411 may delay the oscillation signal ROD to generate the first output clock signal ICLKO.

The second clock delay circuit 412 may receive the second phase clock signal QCLK and the oscillation signal ROD to generate the second output clock signal QCLKO. The second clock delay circuit 412 may delay the second phase clock signal QCLK in the normal mode to generate the second output clock signal QCLKO, and may delay the oscillation signal ROD in the compensation mode to generate the second output clock signal. Pulse signal QCLKO. The second clock delay circuit 412 may receive the first delay control signal DQC. The delay amount of the second clock delay circuit 412 may be changed based on the first delay control signal DQC. The second clock delay circuit 412 can also receive the enable signal OSCEN. When the enable signal OSCEN is disabled, the second clock delay circuit 412 may delay the second phase clock signal QCLK to generate the second output clock signal QCLKO. When the enable signal OSCEN is enabled, the second clock delay circuit 412 may delay the oscillation signal ROD to generate the second output clock signal QCLKO.

The third clock delay circuit 413 may receive the third phase clock signal IBCLK and the oscillation signal ROD to generate the third output clock signal IBCLKO. The third clock delay circuit 413 may delay the third phase clock signal IBCLK to generate the third output clock signal IBCLKO in the normal mode, and may delay the oscillation signal ROD in the compensation mode to generate the third output clock signal. Pulse signal IBCLKO. The third clock delay circuit 413 may receive the second delay control signal DIBC. The delay amount of the third clock delay circuit 413 may be changed based on the second delay control signal DIBC. The third clock delay circuit 413 can also receive the enable signal OSCEN. When the enable signal OSCEN is disabled, the third clock delay circuit 413 may delay the third phase clock signal IBCLK to generate the third output clock signal IBCLKO. When the enable signal OSCEN is enabled, the third clock delay circuit 413 may delay the oscillation signal ROD to generate the third output clock signal IBCLKO.

The fourth clock delay circuit 414 may receive the fourth phase clock signal QBCLK and the oscillation signal ROD to generate the fourth output clock signal QBCLKO. The fourth clock delay circuit 414 may delay the fourth phase clock signal QBCLK in the normal mode to generate the fourth output clock signal QBCLKO, and may delay the oscillation signal ROD in the compensation mode to generate the fourth output clock signal. Pulse signal QBCLKO. The fourth clock delay circuit 414 may receive the third delay control signal DQBC. The delay amount of the fourth clock delay circuit 414 may be changed based on the third delay control signal DQBC. The fourth clock delay circuit 414 can also receive the enable signal OSCEN. When the enable signal OSCEN is disabled, the fourth clock delay circuit 414 may delay the fourth phase clock signal QBCLK to generate the fourth output clock signal QBCLKO. When the enable signal OSCEN is enabled, the fourth clock delay circuit 414 may delay the oscillation signal ROD to generate the fourth output clock signal QBCLKO.

The first to fourth phase clock signals ICLK, QCLK, IBCLK and QBCLK may have a predetermined phase difference among each other in sequence. For example, the first phase clock signal ICLK may have a leading phase of 90° relative to the second phase clock signal QCLK, and the second phase clock signal QCLK may have a leading phase of 90° relative to the third phase clock signal IBCLK. . The third phase clock signal IBCLK may have a leading phase of 90° relative to the fourth phase clock signal QBCLK, and the fourth phase clock signal QBCLK may have a leading phase of 90° relative to the first phase clock signal ICLK. The semiconductor device 400 may further include a multi-phase clock signal generating circuit 420 . Based on the pair of clock signals CLK and CLKB, the multi-phase clock signal generating circuit 420 can generate the first to fourth phase clock signals ICLK, QCLK, IBCLK and QBCLK. The multi-phase clock signal generation circuit 420 may include: any clock generation circuit configured to correct the phases of CLK and CLKB by correcting the clock signal or by dividing the clock signal by frequency dividing CLK and CLKB to generate a phase with Different phase clock signals. For example, the multi-phase clock signal generating circuit 420 may include at least one of a delay locked loop circuit, a phase locked loop circuit, a phase interpolation circuit and a frequency dividing circuit.

The first to fourth clock delay circuits 411, 412, 413, and 414 may have substantially the same configuration, and may ideally have the same delay amount. However, due to local process variations and degradations, the actual delay amounts of the first to fourth clock delay circuits 411, 412, 413, and 414 may differ from each other. When the delay amounts of the first to fourth clock delay circuits 411, 412, 413 and 414 are different from each other, it is difficult to obtain the first to fourth phase clock signals ICLK, QCLK, IBCLK and The phase difference between the first output clock signal to the fourth output clock signal ICLKO, QCLKO, IBCLKO and QBCLKO generated by QBCLK is maintained at 90°, so the phase difference between the first output clock signal to the fourth output clock signal will be reduced. The valid window or duration of the signal synchronized by signals ICLKO, QCLKO, IBCLKO and QBCLKO. In order to compensate for the delay amount deviation among the first to fourth clock delay circuits 411, 412, 413, and 414, the semiconductor device 400 may operate in a compensation mode. In the compensation mode, the semiconductor device 400 may monitor delay amounts of the first to fourth clock delay circuits 411 , 412 , 413 and 414 to change at least the second to fourth clock delay circuits 412 , 413 and 414 delay amount. For example, the first clock delay circuit 411 may be a reference delay circuit, and the delay amount of the first clock delay circuit 411 may be the reference delay amount. The semiconductor device 400 may compare each of the delay amounts of the second to fourth clock delay circuits 412, 413, and 414 with the delay amount of the first clock delay circuit 411 to compare the second to fourth clock delay circuits 412, 413, and 414. Each delay amount of the delay circuit to the fourth clock delay circuit 412, 413 and 414 is set to be the same as the delay amount of the first clock delay circuit 411, thereby correcting the first to fourth clock delay circuit 411 Delay deviation among , 412, 413 and 414. In order to correct the delay amount deviation among the first to fourth clock delay circuits 411, 412, 413, and 414, the semiconductor device 400 may include an oscillation control circuit 430 and a delay message generation circuit 440.

The oscillation control circuit 430 may receive the first to fourth output clock signals ICLKO, QCLKO, IBCLKO and QBCLKO from the first to fourth clock delay circuits 411, 412, 413 and 414 respectively. The oscillation control circuit 430 may be coupled to the first to fourth clock delay circuits 411, 412, 413, and 414 in sequence, and may be configured according to the first to fourth clock delay circuits 411, 411, 412, and 414. The delay amounts of 412, 413 and 414 generate the oscillation signal ROD. The oscillation control circuit 430 may select one of the first to fourth output clock signals ICLKO, QCLKO, IBCLKO, and QBCLKO, and may generate the oscillation signal ROD based on the selected output clock signal. In one embodiment, based on one of the first to fourth output clock signals ICLKO, QCLKO, IBCLKO and QBCLKO, the oscillation control circuit 430 may control the oscillation signal ROD to transition from the second logic level to the first Logic level. Based on the signal generated by delaying the oscillation signal ROD by a fixed delay amount, the oscillation control circuit 430 can control the oscillation signal ROD to change from the first logic level to the second logic level. In one embodiment, the oscillation control circuit 430 may generate the setting pulse signal SET based on one of the first to fourth output clock signals ICLKO, QCLKO, IBCLKO and QBCLKO to control the oscillation signal ROD from the second logic level transition to the first logic level. The oscillation control circuit 430 may generate the reset pulse signal RST based on the set pulse signal SET to control the oscillation signal ROD to change from the first logic level to the second logic level. The oscillation control circuit 430 can receive the enable signal OSCEN. The oscillation control circuit 430 may be activated based on the enable signal OSCEN. When the enable signal OSCEN is enabled, the oscillation control circuit 430 may be coupled to one of the first to fourth clock delay circuits 411, 412, 413 and 414 to generate the oscillation signal ROD. At least part of the components in the oscillation signal generation circuit 100 , the oscillation signal generation circuit 200 and the oscillation signal generation circuit 300 respectively shown in FIGS. 1 , 5 and 8 may be used as the oscillation control circuit 430 . When the oscillation signal generation circuit 100 (see FIG. 1 ) is used as the oscillation control circuit 430, the oscillation control circuit 430 may include a selection circuit 140, a timing control circuit 120 and an oscillation driver 130. When the oscillation signal generation circuit 200 (see FIG. 5 ) is used as the oscillation control circuit 430 , the oscillation control circuit 430 may include a selection circuit 240 , a first timing control circuit 250 , a second timing control circuit 220 and an oscillation driver 230 . When the oscillation signal generation circuit 300 (see FIG. 8 ) is used as the oscillation control circuit 430 , the oscillation control circuit 430 may include a selection circuit 350 , a set pulse generator 320 , a reset pulse generator 330 and an oscillation driver 340 . However, the selection signal SEL provided for controlling the selection circuit 140, the selection circuit 240 and the selection circuit 350 may be modified to include selection of the first to fourth output clock signals ICLKO, QCLKO, IBCLKO and Multiple bits of one of the QBCLKOs.

The delay message generation circuit 440 may be coupled to the oscillation control circuit 430 and may be configured to receive the oscillation signal ROD. Based on the oscillation signal ROD, the delay message generation circuit 440 can generate the first delay control signal DQC, the second delay control signal DIBC and the third delay control signal DQBC. The delay message generation circuit 440 may generate a delay message for each of the first to fourth clock delay circuits 411, 412, 413 and 414. For example, the delay message generation circuit 440 may be coupled to the first clock delay circuit 411 and may be configured to generate the first delay message based on the oscillation signal ROD generated from the first output clock signal ICLKO. The delay message generation circuit 440 may be coupled to the second clock delay circuit 412 and may be configured to generate the second delay message based on the oscillation signal ROD generated from the second output clock signal QCLKO. The delay message generation circuit 440 may be coupled to the third clock delay circuit 413, and may be configured to generate the third delay message based on the oscillation signal ROD generated from the third output clock signal IBCLKO. The delay message generation circuit 440 may be coupled to the fourth clock delay circuit 414 and may be configured to generate the fourth delay message based on the oscillation signal ROD generated from the fourth output clock signal QBCLK. The delay message generation circuit 440 can compare and operate the first delay message and the second delay message to the fourth delay message, and can generate the first delay control signal to the third delay control signal DQC respectively according to the results of the comparison and operation operation. , DIBC and DQBC. The delay message generation circuit 440 can compare and operate the second delay message and the first delay message to generate the first delay control signal DQC, and can provide the first delay control signal DQC to the second clock delay circuit 412 . The first delay control signal DQC may be generated based on the difference between the second delay information and the first delay information, and the delay amount of the second clock delay circuit 412 may become the same as the first clock based on the first delay control signal DQC. The delay amount of the pulse delay circuit 411 is basically the same. The delay message generation circuit 440 can compare and operate the third delay message and the first delay message to generate the second delay control signal DIBC, and can provide the second delay control signal DIBC to the third clock delay circuit 413 . The second delay control signal DIBC may be generated based on the difference between the third delay information and the first delay information, and the delay amount of the third clock delay circuit 413 may become the same as the first clock based on the second delay control signal DIBC. The delay amount of the pulse delay circuit 411 is basically the same. The delay message generation circuit 440 may compare and operate the fourth delay message and the first delay message to generate a third delay control signal DQBC, and may provide the third delay control signal DQBC to the fourth clock delay circuit 414 . The third delay control signal DQBC may be generated based on the difference between the fourth delay message and the first delay message, and the delay amount of the fourth clock delay circuit 414 may become the same as the first clock based on the third delay control signal DQBC. The delay amount of the pulse delay circuit 411 is basically the same. The first to third delay control signals DQC, DIBC and DQBC may be digital signals each having multiple bits, and may be analog signals having multiple voltage levels.

FIG. 13 is a diagram illustrating the connection relationship between each of the first to fourth clock delay circuits 411, 412, 413, and 414 shown in FIG. 12 and the oscillation control circuit 430. Referring to FIG. 13, the first clock delay circuit 411 may include a first switch 411-1 and a fixed delay line 411-2. Based on the enable signal OSCEN, the first switch 411-1 can provide one of the first phase clock signal ICLK and the oscillation signal ROD to the fixed delay line 411-2. The first switch 411-1 can provide the first phase clock signal ICLK to the fixed delay line 411-2 when the enable signal OSCEN is disabled, and can provide the first phase clock signal ICLK to the fixed delay line 411-2 when the enable signal OSCEN is enabled. Provide oscillation signal ROD. The fixed delay line 411-2 may have a fixed delay amount. The fixed delay line 411-2 can delay the output signal from the first switch 411-1 to output the first output clock signal ICLKO. In one embodiment, fixed delay line 411-2 may be replaced by a variable delay line.

The second clock delay circuit 412 may include a second switch 412-1 and a variable delay line 412-2. Based on the enable signal OSCEN, the second switch 412-1 can provide one of the second phase clock signal QCLK and the oscillation signal ROD to the variable delay line 412-2. The second switch 412-1 can provide the second phase clock signal QCLK to the variable delay line 412-2 when the enable signal OSCEN is disabled, and can provide the second phase clock signal QCLK to the variable delay line 412 when the enable signal OSCEN is enabled. -2 provides the oscillation signal ROD. The variable delay line 412-2 can receive the first delay control signal DQC. The delay amount of the variable delay line 412-2 may vary based on the first delay control signal DQC. The variable delay line 412-2 can variably delay the output signal from the second switch 412-1 to output the second output clock signal QCLKO.

The third clock delay circuit 413 may include a third switch 413-1 and a variable delay line 413-2. Based on the enable signal OSCEN, the third switch 413-1 can provide one of the third phase clock signal IBCLK and the oscillation signal ROD to the variable delay line 413-2. The third switch 413-1 can provide the third phase clock signal IBCLK to the variable delay line 413-2 when the enable signal OSCEN is disabled, and can provide the third phase clock signal IBCLK to the variable delay line 413 when the enable signal OSCEN is enabled. -2 provides the oscillation signal ROD. The variable delay line 413-2 can receive the second delay control signal DIBC. The delay amount of the variable delay line 413-2 may vary based on the second delay control signal DIBC. The variable delay line 413-2 can variably delay the output signal from the third switch 413-1 to output the third output clock signal IBCLKO.

The fourth clock delay circuit 414 may include a fourth switch 414-1 and a variable delay line 414-2. Based on the enable signal OSCEN, the fourth switch 414-1 can provide one of the fourth phase clock signal QBCLK and the oscillation signal ROD to the variable delay line 414-2. The fourth switch 414-1 can provide the fourth phase clock signal QBCLK to the variable delay line 414-2 when the enable signal OSCEN is disabled, and can provide the fourth phase clock signal QBCLK to the variable delay line 414 when the enable signal OSCEN is enabled. -2 provides the oscillation signal ROD. The variable delay line 414-2 can receive the third delay control signal DQBC. The delay amount of the variable delay line 414-2 may vary based on the third delay control signal DQBC. The variable delay line 414-2 can variably delay the output signal from the fourth switch 414-1 to output the fourth output clock signal QBCLKO.

The oscillation control circuit 430 may include at least a part of elements included in each of the oscillation signal generation circuit 100 and the oscillation signal generation circuit 200 shown in FIGS. 1 and 5 . The oscillation control circuit 430 may include a selection circuit 510, a second timing control circuit 520, and an oscillation driver 530. The selection circuit 510 may receive the first to fourth output clock signals ICLKO, QCLKO, IBCLKO and QBCLKO to output the first to fourth output clock signals ICLKO, QCLKO, IBCLKO based on the selection signal SEL. and one of QBCLKO. The selection circuit 510 may provide one of the first to fourth output clock signals ICLKO, QCLKO, IBCLKO and QBCLKO as the first control signal RCS. The oscillation control circuit 430 may also include a first timing control circuit 540. Based on the output signal from the selection circuit 510, the first timing control circuit 540 may generate the first control signal RCS in the form of an enabled pulse. The first timing control circuit 540 may generate the first control signal RCS based on the edge of the oscillation signal ROD transitioning from the second logic level to the first logic level. The first timing control circuit 540 may pass through one of the first to fourth clock delay circuits 411, 412, 413 and 414 after the oscillation signal ROD transitions from the second logic level to the first logic level. The first control signal RCS is enabled during a period corresponding to the delay amount. The first timing control circuit 540 may include a pulse generator 541 configured to generate the first control signal RCS based on the output signal from the selection circuit 510 . The second timing control circuit 520 may receive the oscillation signal ROD, and may delay the oscillation signal ROD by a fixed delay amount to generate the second control signal FCS. Based on the oscillation signal ROD, the second timing control circuit 520 may generate the second control signal FCS in the form of an enabled pulse. The second timing control circuit 520 may generate the second control signal FCS based on the edge of the oscillation signal ROD transitioning from the first logic level to the second logic level. The second timing control circuit 520 may enable the second control signal FCS when a period corresponding to the fixed delay amount passes after the oscillation signal ROD transitions from the first logic level to the second logic level. The second timing control circuit 520 may include a delay replica unit 521 and a pulse generator 522. The delay replica unit 521 can receive the oscillation signal ROD, and can delay the oscillation signal ROD by a fixed delay amount. The pulse generator 522 may generate the second control signal FCS based on the output signal from the delay copy unit 521 . The oscillation driver 530 may receive the first control signal RCS and the second control signal FCS, and may generate the oscillation signal ROD based on the first control signal RCS and the second control signal FCS. Based on the first control signal RCS, the oscillation driver 530 can control the oscillation signal ROD to change from the second logic level to the first logic level. Based on the second control signal FCS, the oscillation driver 530 can control the oscillation signal ROD to change from the first logic level to the second logic level. The oscillation signal ROD may be fed back to the first to fourth clock delay circuits 411, 412, 413, and 414, and may be provided to the second timing control circuit 520 and the delay message generation circuit 440.

FIG. 14 is a diagram illustrating the connection relationship between each of the first to fourth clock delay circuits 411, 412, 413, and 414 shown in FIG. 12 and the oscillation control circuit 430. Referring to FIG. 14 , the oscillation control circuit 430 may include a selection circuit 610 , a set pulse generator 620 , a reset pulse generator 630 and an oscillation driver 640 . The selection circuit 610 may receive the first to fourth output clock signals ICLKO, QCLKO, IBCLKO and QBCLKO, and may output the first to fourth output clock signals ICLKO, QCLKO, based on the selection signal SEL. One of IBCLKO and QBCLKO. The pulse generator 620 is configured to receive an output signal from the selection circuit 610 . The set pulse generator 620 may generate the set pulse signal SET based on the output signal from the selection circuit 610 . The setting pulse generator 620 may generate the setting pulse signal SET synchronized with one of the rising edge and the falling edge of the oscillation signal ROD. For example, the set pulse generator 620 may generate the set pulse signal SET synchronized with the rising edge of the oscillation signal ROD. The pulse generator 620 is configured to undergo a delay amount equal to one of the first to fourth clock delay circuits 411, 412, 413 and 414 after the oscillation signal ROD transitions from a low logic level to a high logic level. The setting pulse signal SET is enabled during the corresponding period. The reset pulse generator 630 may receive the set pulse signal SET, and may generate the reset pulse signal RST based on the set pulse signal SET. The reset pulse generator 630 can enable the reset pulse signal RST when the setting pulse signal SET is disabled. The oscillation driver 640 may receive the set pulse signal SET and the reset pulse signal RST, and may generate the oscillation signal ROD based on the set pulse signal SET and the reset pulse signal RST. Based on the setting pulse signal SET, the oscillation driver 640 can control the oscillation signal ROD to change from the second logic level to the first logic level. Based on the reset pulse signal RST, the oscillation driver 640 can control the oscillation signal ROD to change from the first logic level to the second logic level. The oscillation signal ROD may be fed back to the first to fourth clock delay circuits 411, 412, 413, and 414, and may be provided to the delay message generation circuit 440.

Although specific embodiments have been described above, those of ordinary skill in the art to which this invention pertains will understand that the described embodiments are only examples. Therefore, the oscillation signal generating circuit and the semiconductor device using the same should not be limited based on the described embodiments. On the contrary, the oscillation signal generating circuit and the semiconductor device using the same described herein, when combined with the above description and drawings, should be limited only by the scope of the accompanying claims.

100: Oscillation signal generation circuit 111: First clock delay circuit 112: Second clock delay circuit 120: Timing control circuit 121: Delayed replication unit 122:Pulse generator 122-1: First inverter 122-2: Delay 122-3: Second inverter 122-4:Reverse gate 130: Oscillation driver 131:Pull-up transistor 132: Pull-down transistor 133: Anti-and gate 134: First inverter 135: Second inverter 140:Select circuit 200: Oscillation signal generation circuit 211: First clock delay circuit 212: Second clock delay circuit 220: Second timing control circuit 221: Delayed replication unit 222: First pulse generator 230: Oscillation driver 240: Select circuit 241:Output signal 250: First timing control circuit 251: Second pulse generator 251-1: First inverter 251-2: Delay 251-3: Second inverter 251-4:Reverse OR gate 300: Oscillation signal generation circuit 311: First clock delay circuit 312: Second clock delay circuit 320: Set pulse generator 321: First inverter 322:Delayer 323: Second inverter 324:Reverse OR gate 330:Reset pulse generator 331: First inverter 332:Delayer 333: Second inverter 334: Anti-and gate 340: Oscillation driver 350:Select circuit 351:Output signal 400:Semiconductor device 411: First clock delay circuit 411-1: First switch 411-2: Fixed delay line 412: Second clock delay circuit 412-1: Second switch 412-2: Variable delay line 413: Third clock delay circuit 413-1:Third switch 413-2: Variable delay line 414: Fourth clock delay circuit 414-1: The fourth switch 414-2: Variable delay line 420: Polyphase clock signal generation circuit 430: Oscillation control circuit 440: Delayed message generation circuit 510: Select circuit 520: Second timing control circuit 521: Delayed replication unit 522: Pulse generator 530: Oscillation driver 540: First timing control circuit 541:Pulse generator 610: Select circuit 620: Set pulse generator 630:Reset pulse generator 640: Oscillation driver A:Path B:Path CLK: clock signal pair CLKB: clock signal pair CLKI1: first input clock signal CLKI2: second input clock signal CLKO1: The first output clock signal CLKO2: The second output clock signal DIBC: second delay control signal DN: driver node DQBC: third delay control signal DQC: first delay control signal FCS: second control signal IBCLK: third phase clock signal IBCLKO: The third output clock signal ICLK: first phase clock signal ICLKO: first output clock signal LN: latch node OSCEN: Empowerment Signal QBCLK: fourth phase clock signal QBCLKO: The fourth output clock signal QCLK: second phase clock signal QCLKO: second output clock signal RCS: first control signal ROD: oscillation signal ROD1: the first oscillation signal ROD1’: the first oscillation signal ROD2: The second oscillation signal ROD2’: the second oscillation signal RST: reset pulse signal SEL: select signal SET: Set pulse signal TD1: Delay amount TD2: Delay amount TDR: amount of delay TDR+α:sum VH: first power supply voltage VL: second power supply voltage α: delay amount

FIG. 1 is a diagram illustrating the configuration of an oscillation signal generating circuit according to one embodiment. FIG. 2 is a diagram explaining the pulse generator shown in FIG. 1 . FIG. 3 is a diagram explaining the oscillation driver shown in FIG. 1 . 4A and 4B are timing diagrams illustrating the operation of the oscillation signal generating circuit according to one embodiment. FIG. 5 is a diagram illustrating the configuration of an oscillation signal generating circuit according to one embodiment. FIG. 6 is a diagram explaining the pulse generator shown in FIG. 5 . FIG. 7 is a timing diagram illustrating the operation of the oscillation signal generating circuit according to one embodiment. FIG. 8 is a diagram illustrating the configuration of an oscillation signal generating circuit according to one embodiment. FIG. 9 is a diagram illustrating the installation of the pulse generator shown in FIG. 8 . FIG. 10 is a diagram explaining the reset pulse generator shown in FIG. 8 . FIG. 11 is a timing diagram illustrating the operation of the oscillation signal generating circuit according to one embodiment. FIG. 12 is a diagram illustrating the configuration of a semiconductor device according to one embodiment. FIG. 13 is a diagram explaining the connection relationship between the clock delay circuit and the oscillation control circuit shown in FIG. 12 . FIG. 14 is a diagram explaining the connection relationship between the clock delay circuit and the oscillation control circuit shown in FIG. 12 .

100: Oscillation signal generation circuit

111: First clock delay circuit

112: Second clock delay circuit

120: Timing control circuit

121: Delayed replication unit

122:Pulse generator

130: Oscillation driver

140:Select circuit

CLKI1: first input clock signal

CLKI2: second input clock signal

CLKO1: The first output clock signal

CLKO2: The second output clock signal

FCS: second control signal

OSCEN: Empowerment Signal

RCS: first control signal

ROD: oscillation signal

SEL: select signal

VH: first power supply voltage

VL: second power supply voltage

Claims (39)

An oscillation signal generating circuit includes: a first clock delay circuit configured to delay an oscillation signal to generate a first control signal; a timing control circuit configured to delay the oscillation signal by a fixed delay amount to generate a second control signal; and An oscillation driver configured to: drive the oscillation signal to a first logic level based on the first control signal, and drive the oscillation signal to a second logic level based on the second control signal. The oscillation signal generation circuit as claimed in claim 1, wherein the timing control circuit includes: a delay replica unit configured to delay the oscillation signal by the fixed delay amount; and A first pulse generator is configured to receive an output signal from the delay replica unit and generate the second control signal based on an edge of the oscillation signal transitioning from the second logic level to the first logic level. The oscillation signal generating circuit of claim 2, wherein the delay replicating unit is designed by modeling the first clock delay circuit. The oscillation signal generation circuit of claim 1, further comprising a second pulse generator configured to receive an output signal from the first clock delay circuit to change the oscillation signal from the first logic level based on The edge to the second logic level generates the first control signal. The oscillation signal generating circuit as described in claim 1 also includes: a second clock delay circuit configured to delay the oscillation signal; and A selection circuit is configured to output one of the output signal from the first clock delay circuit and the output signal from the second clock delay circuit as the first control signal based on a selection signal. The oscillation signal generating circuit of claim 5, further comprising a second pulse generator configured to receive an output signal from the selection circuit to change from the first logic level to the second based on the oscillation signal. The edge of the logic level generates the first control signal. An oscillation signal generating circuit includes: a first clock delay circuit configured to delay an oscillation signal; a first timing control circuit configured to receive an output signal from the first clock delay circuit to generate a first control signal; a second timing control circuit configured to delay the oscillation signal by a fixed delay amount to generate a second control signal; and An oscillation driver configured to: drive the oscillation signal to a first logic level based on the first control signal, and drive the oscillation signal to a second logic level based on the second control signal. The oscillation signal generation circuit of claim 7, wherein the first timing control circuit includes a first pulse generator configured to receive an output signal from the first clock delay circuit, and based on the oscillation signal from The edge of the first logic level transitioning to the second logic level generates the first control signal. The oscillation signal generating circuit of claim 7, wherein the second timing control circuit includes: a delay replica unit configured to delay the oscillation signal by the fixed delay amount; and A second pulse generator is configured to receive an output signal from the delay replica unit and generate the second control signal based on an edge of the oscillation signal transitioning from the second logic level to the first logic level. The oscillation signal generating circuit of claim 9, wherein the delay replicating unit is designed by modeling the first clock delay circuit. The oscillation signal generating circuit as described in claim 7 also includes: a second clock delay circuit configured to delay the oscillation signal; and a selection circuit configured to selectively output one of the output signal from the first clock delay circuit and the output signal from the second clock delay circuit based on a selection signal, Wherein, the first timing control circuit is configured to generate the first control signal based on the output signal from the selection circuit. An oscillation signal generating circuit includes: a first clock delay circuit configured to delay an oscillation signal; a second clock delay circuit configured to delay the oscillation signal; a selection circuit configured to: output one of the output signal from the first clock delay circuit and the output signal from the second clock delay circuit as a first control signal based on a selection signal; a timing control circuit configured to delay the oscillation signal by a fixed delay amount to generate a second control signal; and An oscillation driver is configured to generate the oscillation signal based on the first control signal and the second control signal. The oscillation signal generation circuit as claimed in claim 12, wherein the timing control circuit includes: a delay replica unit configured to delay the oscillation signal by the fixed delay amount; and A first pulse generator is configured to receive an output signal from the delay replica unit and generate the second control signal based on an edge of the oscillation signal transitioning from a second logic level to a first logic level. The oscillation signal generation circuit of claim 13, wherein the delay replica unit is designed by modeling at least one of the first clock delay circuit and the second clock delay circuit. The oscillation signal generating circuit of claim 13, further comprising a second pulse generator configured to receive an output signal from the selection circuit to change the oscillation signal from the first logic level to the second The edge of the logic level generates the first control signal. The oscillation signal generation circuit of claim 12, wherein the oscillation driver is configured to: drive the oscillation signal to a first logic level based on the first control signal, and drive the oscillation signal based on the second control signal. The signal is driven to a second logic level. An oscillation signal generating circuit includes: a first clock delay circuit configured to delay an oscillation signal; a setting pulse generator configured to: generate a setting pulse signal synchronized with one of the rising edge and the falling edge of the oscillation signal based on the output from the first clock delay circuit; a reset pulse generator configured to: receive the set pulse signal and generate a reset pulse signal; and An oscillation driver is configured to: drive the oscillation signal to a first logic level based on the set pulse signal, and drive the oscillation signal to a second logic level based on the reset pulse signal. The oscillation signal generating circuit of claim 17, wherein when the setting pulse signal is disabled, the reset pulse signal is enabled. The oscillation signal generating circuit as described in claim 17 also includes: a second clock delay circuit configured to delay the oscillation signal; and a selection circuit configured to selectively output one of the output signal from the first clock delay circuit and the output signal from the second clock delay circuit based on a selection signal, Wherein, the setting pulse generator is configured to generate the setting pulse signal based on the output signal from the selection circuit. An oscillation signal generating circuit includes: a first clock delay circuit configured to delay an oscillation signal; a second clock delay circuit configured to delay the oscillation signal; a selection circuit configured to: output one of an output signal from the first clock delay circuit and an output signal from the second clock delay circuit based on a selection signal; a setting pulse generator configured to: receive the output signal from the selection circuit and generate a setting pulse signal synchronized with one of the rising edge and falling edge of the oscillation signal; a reset pulse generator configured to generate a reset pulse signal based on the setting pulse signal; and An oscillation driver is configured to generate the oscillation signal based on the set pulse signal and the reset pulse signal. The oscillation signal generating circuit of claim 20, wherein when the setting pulse signal is disabled, the reset pulse signal is enabled. The oscillation signal generation circuit of claim 20, wherein the oscillation driver is configured to drive the oscillation signal to a first logic level based on the set pulse signal, and drive the oscillation signal based on the reset pulse signal to a second logic level. A semiconductor device including: a first clock delay circuit configured to delay an oscillation signal to generate a first output clock signal; a second clock delay circuit configured to delay the oscillation signal based on a delay control signal to generate a second output clock signal; An oscillation control circuit configured to: control the oscillation signal to transition from a second logic level to a first logic level based on one of the first output clock signal and the second output clock signal, and based on Control the transition of the oscillation signal from the first logic level to the second logic level by delaying the oscillation signal by a signal generated by a fixed delay amount; and A delay message generating circuit is configured to generate the delay control signal based on the oscillation signal generated by the first clock delay circuit and the oscillation signal generated by the second clock delay circuit. The semiconductor device of claim 23, wherein the first clock delay circuit is configured to delay a first phase clock signal to generate the first output clock signal in the normal mode, and in the compensation mode The oscillation signal is delayed to generate the first output clock signal. The semiconductor device of claim 24, wherein the second clock delay circuit is configured to delay a second phase clock signal to generate the second output clock signal in the normal mode, and in the normal mode In the compensation mode, the oscillation signal is delayed to generate the second output clock signal. The semiconductor device according to claim 23, wherein the oscillation control circuit includes: a selection circuit configured to output one of the first output clock signal and the second output clock signal as a first control signal based on a selection signal; a timing control circuit configured to delay the oscillation signal by the fixed delay amount to generate a second control signal; and An oscillation driver configured to: control the oscillation signal to transition from the second logic level to the first logic level based on the first control signal, and control the oscillation signal to transition from the first logic level to the first logic level based on the second control signal. level transition to the second logic level. The semiconductor device of claim 26, wherein the timing control circuit includes: a delay replica unit configured to delay the oscillation signal by the fixed delay amount; and A first pulse generator is configured to receive an output signal from the delay replica unit and generate the second control signal based on an edge of the oscillation signal transitioning from the second logic level to the first logic level. The semiconductor device of claim 27, wherein the delay replication unit is designed by modeling at least one of the first clock delay circuit and the second clock delay circuit. The semiconductor device of claim 26, further comprising a second pulse generator configured to transition from the first logic level to the second logic level based on the oscillation signal based on the output signal from the selection circuit. The edge of generates the first control signal. The semiconductor device according to claim 23, wherein the oscillation control circuit includes: a selection circuit configured to output one of the first output clock signal and the second output clock signal based on a selection signal; a first timing control circuit configured to generate a first control signal based on the output signal from the selection circuit; a second timing control circuit configured to delay the oscillation signal by the fixed delay amount to generate a second control signal; and An oscillation driver configured to: control the oscillation signal to transition from the second logic level to the first logic level based on the first control signal, and control the oscillation signal to transition from the first logic level to the first logic level based on the second control signal. level transition to the second logic level. The semiconductor device of claim 30, wherein the first timing control circuit includes a first pulse generator configured to receive an output signal from the first clock delay circuit, and to receive an output signal from the first clock delay circuit based on the oscillation signal. An edge that transitions from a logic level to the second logic level generates the first control signal. The semiconductor device of claim 30, wherein the second timing control circuit includes: a delay replica unit configured to delay the oscillation signal by the fixed delay amount; and A second pulse generator is configured to receive an output signal from the delay replica unit and generate the second control signal based on an edge of the oscillation signal transitioning from the second logic level to the first logic level. The semiconductor device of claim 32, wherein the delay replication unit is designed by modeling at least one of the first clock delay circuit and the second clock delay circuit. A semiconductor device including: a first clock delay circuit configured to delay an oscillation signal to generate a first output clock signal; a second clock delay circuit configured to delay the oscillation signal based on a delay control signal to generate a second output clock signal; An oscillation control circuit configured to: generate a setting pulse signal based on one of the first output clock signal and the second output clock signal to control the oscillation signal to change from a second logic level to a first logic level level, and generate a reset pulse signal based on the set pulse signal to control the oscillation signal to change from the first logic level to the second logic level; and A delay message generating circuit is configured to generate the delay control signal based on the oscillation signal generated by the first clock delay circuit and the oscillation signal generated by the second clock delay circuit. The semiconductor device of claim 34, wherein the first clock delay circuit is configured to delay a first phase clock signal and generate the first output clock signal in the normal mode, and in the compensation mode The oscillation signal is delayed and the first output clock signal is generated. The semiconductor device of claim 35, wherein the second clock delay circuit is configured to delay the second phase clock signal to generate the second output clock signal in the normal mode, and in the normal mode In the compensation mode, the oscillation signal is delayed to generate the second output clock signal. The semiconductor device according to claim 34, wherein the oscillation control circuit includes: a selection circuit configured to output one of the first output clock signal and the second output clock signal based on a selection signal; a setting pulse generator configured to: receive an output signal from the selection circuit and generate a setting pulse signal synchronized with one of the rising edge and the falling edge of the oscillation signal; a reset pulse generator configured to generate a reset pulse signal based on the setting pulse signal; and An oscillation driver is configured to generate the oscillation signal based on the set pulse signal and the reset pulse signal. The semiconductor device of claim 37, wherein when the setting pulse signal is disabled, the reset pulse signal is enabled. The semiconductor device of claim 37, wherein the oscillation driver is configured to drive the oscillation signal to the first logic level based on the set pulse signal, and drive the oscillation signal to the first logic level based on the reset pulse signal. Second logic level.

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