TW202341594A - Surface emitting laser, method for fabricating surface emitting laser - Google Patents

Abstract

A vertical cavity surface emitting laser (VCSEL) includes a distributed Bragg reflector (DBR) including a first dielectric layer and a second dielectric layer alternately arranged in a first axial direction; and a semiconductor section including a p-type III nitride region, a III nitride region, and a III nitride active region between the p-type III nitride region and the III nitride region, the p-type III nitride region, the III nitride active region, and the III nitride region being arranged in the first axial direction, the III nitride region including an n-type III nitride region. The semiconductor section includes a monolithic grating having a periodic one-dimensional pattern. The monolithic grating, the III nitride active region, and the distributed Bragg reflector are arranged in the first axial direction to form an optical cavity. The periodic one-dimensional pattern extends in a second axial direction that intersects the first axial direction.

Description

Surface emitting laser and method of manufacturing surface emitting laser

The present disclosure relates to a surface-emitting laser and a method of manufacturing the surface-emitting laser.

Surface emitting laser is also called vertical cavity surface emitting laser (VCSEL). The VCSEL includes a semiconductor active region disposed between the n-side semiconductor region and the p-side semiconductor region, and two distributed Bragg reflectors (DBR) that function as high-reflection mirrors. The semiconductor active region is disposed between the two DBRs to form an optical cavity. The n-side and p-side regions inject carriers, namely electrons and holes, into the active region respectively, and these carriers recombine in the active region to generate light. Therefore, the generated light will be reflected by these DBRs many times to travel in the optical cavity, thereby generating coherent rays (lasing). One of the DBRs in a VCSEL is a lower reflectivity mirror used to emit laser light. [citation list] [Non-patent literature]

[Non-patent document 1] 1. Appl. Phys. Lett. 92, 141102 (2008) [Non-patent document 2] 2. Apply. Phys. Express, 12, 036504 (2019) [Non-patent document 3] 3. Appl. Phys. Lett. 105, 031111 (2014) [Non-patent document 4] 4. J. Vac. Sci. Technol. B 33, 050603 (2015) [Non-patent document 5] 5. Appl. Phys. Express 12, 044004 (2019) [Non-patent document 6] 6. Sci. Rep. 8, 10350 (2018) [Non-patent document 7] 7. Semicond. Sci. Technol. 26, 014017 (2010) [Non-patent document 8] 8. IEEE Signal Process. Mag. 37, 50-61 (2020) [Non-patent document 9] 9. IEICE Trans. Electron. E92-C, 194 (2009) [Non-patent document 10] 10. Phys. Stat. Soli, 215, 1700513 (2018) [Non-patent document 11] 11. Appl. Phys. Lett. 75, 1515 (1999) [Non-patent document 12] 12. Soc. Inf. Disp. Int. Symp. Dig. Tech. 44, 832 (2013) [Non-patent document 13] 13. AIP Adv.3, 072107 (2013) [Non-patent document 14] 14. Optics Letters, 41, 2608-2611 (2016) [Non-patent document 15] 15. Phys. Status Solidi A. 215, 1700513 (2018) [Non-patent document 16] 16. Opt. Express, 27,24717 (2019) [Non-patent document 17] 17. Appl. Phys. Express, 13, 041003 (2020) [Non-patent document 18] 18. Appl. Phys. Express,14,031002 (2021) [Non-patent document 19] 19. Applied Phys. Lett.119, 142103 (2021) [Non-patent document 20] 20. Crystals, 11 (12) 1563, (2021)

[Technical Issue] For decades, the fabrication of VCSEL mid-reflectors, known as dispersed Bragg reflectors, has been challenging within the scientific community, especially for III-nitride material systems. Group III nitride VCSEL has an upper mirror surface and a lower mirror surface. Group III nitride device layers are deposited on a substrate to form a semiconductor stack of n-side regions, active regions, and p-side regions. The upper mirror can then be formed as a p-side mirror on the semiconductor stack with different features disposed on the device layer. Alternating layers of dielectric material. The lower mirror surface must be positioned to form a cavity. The formation of the optical cavity is achieved by placing the upper mirror surface and the lower mirror surface close to each other, which results in the removal of the substrate. Another way to form a lower mirror surface without removing the substrate is to use the epitaxial DBR in Non-Patent Document 1 or the nanoporous DBR in Non-Patent Document 2. Another way to form the lower mirror surface is to use the dielectric DBR of Non-Patent Document 3 or the high-contrast index grating of Non-Patent Document 4, by grinding the substrate until the device layer or using laser lift-off to separate the substrate. to form. However, these methods show that the manufacturing of lower mirrors is still a bottleneck challenge, and each method still has certain technical difficulties relative to its advantages.

For example, the formation of epitaxial DBR is complex and requires time-consuming semiconductor deposition and crystal quality that may be prone to degradation. The formation of dielectric DBR requires the use of complex chemical mechanical polishing (CMP) to remove the substrate. The use of CMP in the removal process remains challenging, lengthy, difficult to control, and wastes expensive III-nitride substrates.

On the other hand, the curved mirror method in Non-Patent Document 5 and Patent Document 6 utilizes most of the substrate and involves grinding and etching the semiconductor substrate to produce an n-side DBR mirror. The curved DBR mirror is formed on the back side of the substrate, so this structure of the VCSEL does not require the removal of the substrate, which causes some disadvantages. Curved mirrors are utilized to provide grease VCSELs with long optical cavities.

Specifically, the substrate is first thinned in thickness to reduce the absorption loss in the cavity. Thinning the substrate is a difficult-to-control process, and may be because the substrate must be thinned from an initial thickness of 300 to 400 microns to a target thickness of 10 to 30 microns. microns to provide VCSELs with cavities without damaging the wafer.

Furthermore, another approach is to provide a III-nitride based VCSEL with a single crystal high contrast index grating as the reflector. The fabrication of gratings for use at visible wavelengths involves complex, etching of semiconductor materials. Under prolonged operation, device performance may deteriorate and shorten device life.

In addition, current methods of manufacturing high contrast index gratings utilize electron beam (e-beam) lithography and etching, which may damage device layers. Therefore, this fabrication requires additional protective layers to avoid damage to the active area and subsequent device layers.

Considering these shortcomings, the purpose of the present disclosure is to provide a structure of a III-nitride-based VCSEL and a method of manufacturing a III-nitride-based VCSEL. Another object of the present disclosure is to provide a single crystal high contrast index grating and a method for manufacturing a single crystal high contrast index grating using epitaxial lateral overgrowth (ELO). The ELO process and ELO structure can make the semiconductor device layer have high crystal quality and prevent the device layer from directly facing the etching environment during the formation of the grating.

[Solution] The present disclosure provides a VCSEL, which includes: a first distributed Bragg reflector (DBR) including first dielectric layers and second dielectric layers alternately arranged in a first axial direction; and a semiconductor portion including p A type III nitride region, a group III nitride region, and a group III nitride active region between the p-type III nitride region and the group III nitride region, the p-type III nitride region, The Group III nitride active region and the Group III nitride region are arranged in the first axial direction, and the Group III nitride region includes an n-type Group III nitride region, wherein the semiconductor portion includes a periodic one-dimensional pattern. Single crystal grating, the single crystal grating, the Group III nitride active region and the first dispersed Bragg reflector are arranged in the first axis to form an optical cavity, and the periodic one-dimensional pattern extends to the first axis to the second axis of intersection.

The present disclosure also provides a method for manufacturing a VCSEL. The method includes: forming a patterned epitaxial lateral elongation growth (ELO) mask on one side of a substrate, wherein the substrate includes a Group III nitride substrate, a silicon substrate, a sapphire substrate, and a sapphire substrate. One of the GaN-on-Sapphire template or the GaN-on-Silicon template, the patterned epitaxial lateral extension growth mask includes the grating pattern and up to the The opening on the surface of the substrate; the patterned epitaxial lateral extension growth mask is used to grow Group III nitride on the substrate to form a Group III nitride area covering the grating pattern, and the grating pattern is transferred to the III Group III nitride region; growing a semiconductor stack including an n-type Group III nitride region, a Group III nitride active region, and a p-type Group III nitride region; after growing the semiconductor stack, a conductive layer is grown; forming a first dispersed Bragg reflection disposed on the conductive layer to produce a product, wherein the first distributed Bragg reflector includes alternately arranged first dielectric layers and second dielectric layers; and removing the substrate from the product to expose the patterned epitaxial Laterally elongated growth masks are formed, wherein the grating pattern includes a periodic one-dimensional pattern extending along the surface of the substrate. [Efficacy of this disclosure]

The above invention can provide a structure of a Group III nitride-based VCSEL and a method of manufacturing a Group III nitride-based VCSEL.

As used herein, terms such as “first”, “second”, “third”, “fourth” and “fifth” describe various elements, components, regions, layers and/or sections. Elements, components, regions, layers and/or sections shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Terms such as "first," "second," "third," "fourth" and "fifth" used herein do not imply a sequence or order unless otherwise clearly indicated by the context.

Other features, aspects, and advantages of the subject matter herein will be apparent from the description, drawings, and claims. Referring to the drawings, the disclosed vertical resonant cavity surface emitting laser, the method of manufacturing the vertical resonant cavity surface emitting laser, the single crystal high contrast index grating and the use of epitaxial lateral extension to grow the single crystal to produce the high contrast index are shown. A schematic diagram of the grating method is detailed below. For ease of understanding, the same components are represented by the same symbols in the drawings.

FIG. 1 is a schematic diagram showing a vertical cavity surface emitting laser (VCSEL) according to an embodiment of the present disclosure. The VCSEL 11 includes a distributed Bragg reflector (DBR) 13 and a semiconductor portion 15 with a single crystal grating 17 . The DBR 13 includes first dielectric layers 19 and second dielectric layers 21 alternately arranged in the first axial direction Ax1, and the materials of the first dielectric layer 19 and the second dielectric layer 21 are different. Semiconductor portion 15 excludes the substrate on which it is grown. The VCSEL 11 may further include a dielectric layer 18 covering part or all of the single crystal grating 17. The dielectric layer 18 may extend along the surface structure of the single crystal grating 17 as it comes from the patterned ELO mask used in the growth process. Details Instructions are as follows.

The semiconductor portion 15 includes a p-type Group III nitride region 23, a Group III nitride region 25 having an n-type Group III nitride region, and an n-type Group III nitride region 23 between the p-type Group III nitride region 23 and the Group III nitride region 25. Group III nitride active region 27 between Group III nitride regions. The p-type Group III nitride region 23, the Group III nitride active region 27, and the n-type Group III nitride region 25 are arranged in the first axial direction Ax1. The single crystal grating 17 has a periodic one-dimensional pattern 17a. The single crystal grating 17, the semiconductor part 15, and the DBR 13 are arranged in the first axis Ax1 to form an optical cavity 29. The single crystal grating 17 is arranged along the surface of the group III nitride region 25, and the periodic one-dimensional pattern 17a extends in the second axial direction Ax2 that intersects the first axial direction Ax1.

The VCSEL 11 further includes an anode electrode 31 and a conductive layer 35 . The conductive layer 35 has an inner portion 35a and an outer portion 35b surrounding the inner portion 35a, and is disposed in the p-type Group III nitride region 23. The inner portion 35a is transparent to light from the III-nitride active region 27 and may be disposed between the semiconductor portion 15 and the DBR 13. The outer portion 35b does not cover the DBR 13, allowing the anode electrode 31 to be in contact with the outer portion 35b. The conductive layer 35 connects the anode electrode 31 and the p-type Group III nitride region 23 . The conductive layer 35 may include either a Group III nitride semiconductor (such as p-type gallium nitride (GaN)) or a conductive inorganic material (such as indium tin oxide (ITO)), or both. In some embodiments, DBR 13 may be disposed in contact with conductive layer 35 . If necessary, the semiconductor portion 15 may further include a tunnel junction disposed between the p-type Group III nitride region 23 and the conductive layer 35 and have n-type conductivity.

VCSEL 11 includes cathode electrode 33 . The cathode electrode 33 is electrically connected to the n-type Group III nitride region of the Group III nitride region 25 . As shown in FIG. 1 , the cathode electrode 33 ( 33 a and 33 b ) is provided in contact with either the front surface or the back surface of the n-type Group III nitride region of the Group III nitride region 25 , or in contact with both.

Specifically, the cathode electrode 33 (33a and 33b) may be provided in contact with either the front surface or the back surface of the n-type Group III nitride region of the Group III nitride region 25.

In a VCSEL 11 provided with a semiconductor portion 15 having a mesa 37 , the mesa 37 includes a p-type III-nitride region 23 , a III-nitride active region 27 , and an n-type III-nitride region 25 part of it. Mesa 37 is located in the remainder of the n-type III-nitride region of III-nitride region 25 and at the bottom of mesa 37, mesa 37 is surrounded by n-type III-nitride front face 25a of III-nitride region 25. The cathode electrode 33a may be disposed on the n-type Group III nitride front face 25a of the Group III nitride region 25.

In the VCSEL 11 provided with the single crystal grating 17 having a surrounding portion not covered by the dielectric layer 18 to expose a portion of the n-type III-nitride backside 25b of the III-nitride region 25, the cathode electrode 33b may be disposed at n The type III nitride backside 25b is located outside the single crystal grating 17 and the dielectric layer 18 .

Dielectric layer 18 may include unpatterned portions 18b and patterned portions 18c. The patterned portion 18c may cover the backside 25b of the Group III nitride region 25 so that the patterned portion 18c has a periodic one-dimensional pattern 18a relative to the periodic one-dimensional pattern 17a. The unpatterned portion 18b can be replaced by another dielectric DBR buildup 18d, whereby the single crystal grating 17 not only includes the periodic one-dimensional pattern 17a extending in the second axis Ax2, but also includes other dielectric DBR buildup 18d, that is, two The dielectric layers are alternately arranged in the first axial direction Ax1.

The cavity 29 has a total cavity length Lcav, which can be defined as the distance between the single crystal grating 17 and the DBR 13 of the current VCSEL 11, and is more than 1 micron. The total cavity length Lcav is not greater than 30 microns, since the VCSEL 11 does not include any part of the substrate for growing the semiconductor portion 15 .

The semiconductor portion 15 has a conductive window portion 39a and a low conductive portion 39b surrounding the conductive window portion 39a. Conductive window portion 39a provides VCSEL 11 with an electrical path from anode electrode 31 to cathode electrode 33. Carriers, such as electrons or holes, flow through the electrical path and recombine in the III-nitride active region 27 to produce light, which is emitted from either the DBR 13 or the single crystal grating 17 .

FIG. 2 is a flowchart showing the main steps of a method of manufacturing a VCSEL according to an embodiment of the present disclosure. As shown in Figure 2, which provides a schematic description of an example manufacturing process in accordance with this embodiment. First, in S101, a substrate is prepared. In S102, an epitaxial lateral elongation growth (ELO) mask is formed on the substrate and has a surface patterned for the periodic one-dimensional pattern 18b to produce a patterned ELO mask from the ELO mask. In S103, Group III nitride is deposited on the substrate and patterned ELO mask. Deposition on the patterned ELO mask transfers the patterned surface of the patterned ELO mask to the deposited III-nitride. In S104, the deposited Group III nitride is polished to obtain a flatter surface, and the cavity length of the VCSEL is adjusted. In S105, a Group III nitride semiconductor stack is grown on the planarized surface, and then a front-end process is performed to form the window structure, DBR and electrodes, thereby manufacturing the product. In S106, the product is connected to the support tool, and then the substrate is separated from the product, such as by cryogenic treatment or laser lift-off, to obtain the device buildup connected to the support tool. The separated substrates can be recycled. In S107, the back-end process is applied to the device stack-up, and then in S108, the device stack-up is separated into semiconductor device wafers.

An embodiment of the VCSEL of the present disclosure is described in detail below. In the following description, the Group III nitride may be deposited, for example, by metal organic chemical vapor deposition (MOCVD).

3A, 3B, 3C and 3D illustrate the steps of manufacturing the single crystal grating 17. As shown in Figures 3A and 3B, a substrate 101 is prepared. The substrate 101 may include a Group III nitride substrate, a GaN-on-Sapphire template, or a GaN-on-Silicon template. ), silicon substrate, sapphire substrate, or one of other foreign substrates. The Group III nitride substrate may include gallium nitride-based materials, such as gallium nitride (GaN). Before performing epitaxial lateral extension (ELO), the ELO mask 103 is formed on one side of the substrate 101 by photolithography and etching. ELO mask 103 includes an inorganic dielectric material, such as silicon dioxide. Specifically, a layer of inorganic dielectric material is deposited on the substrate 101 and then patterned twice not only for the ELO but also for the single crystal grating 17 .

Specifically, as shown in FIGS. 3A to 3C , a photolithographic mask 105 (such as a photoresist) is first formed on the inorganic dielectric layer 103 , and the inorganic dielectric layer 103 is formed by etching the photoresist mask 105 ELO mask 107 with ELO pattern. The ELO pattern includes an opening 107a up to the substrate 101. After the photolithography mask 105 is removed, another photolithography mask 109 (eg, photoresist) is formed on the ELO mask 107, and then the dielectric layer 110 is deposited on the photomask 109. To provide an ELO mask 107 with a one-dimensional pattern, the dielectric layer 110 is etched without any mask 1 to expose the top of the mask 109, and the photoresist mask 109 is then removed to create a patterned ELO mask 111. Patterned ELO mask 111 includes pattern 18a for single crystal grating 17.

In the present disclosure, the first patterning forms the ELO pattern, and the second patterning forms the pattern 18a for the single crystal grating 17. Depending on the requirements, the second patterning can also be performed before the first patterning.

FIG. 4 is a plan view of a patterned ELO mask formed by secondary patterning according to an embodiment of the present disclosure. As shown in FIG. 4 , the patterned ELO mask 111 has a plurality of patterned areas 111 a that are separated from each other. Each patterned area 111a is prepared for the single crystal grating 17 of the VCSEL 11 and is located away from the opening 107a.

As shown in FIG. 3C , III-nitride is grown or deposited on the substrate 101 with the patterned ELO mask 111 by MOCVD to form a thick III-nitride region 113 . At least a portion of the III-nitride region 113 may be doped with an n-type dopant, such as silicon. In this embodiment, the III-nitride region 113 may completely cover the grating 17 . The thickness of Group III nitride region 113 may be greater than the thickness of nitride region 25 . The ELO region of the Group III nitride may include defects with a density less than 10 ⁵ /cm ² , 10 ⁴ /cm ² or 10 ³ /cm ² .

As shown in FIG. 3D , III-nitride region 113 may be processed to obtain the desired length of optical cavity 29 prior to subsequent semiconductor deposition. For example, the III-nitride region 113 may be ground or etched to form a planarized III-nitride region 115, and the polished or etched surface of the III-nitride region 115 may be planarized in preparation for subsequent epitaxial growth.

5A, 5B and 5C illustrate the steps of manufacturing VCSEL 11. After the group III nitride region 113 is planarized, as shown in FIG. 5A , the semiconductor layer 117 including the group III nitride region 25 , the group III nitride active region 27 , and the p-type group III nitride region 23 is grown. The Group III nitride region 25 may include GaN-based or AlN-based materials doped with n-type dopants to provide electrons to the Group III nitride active region 27 , and the p-type Group III nitride region 23 may include GaN-based or AlN-based materials. The material is doped with p-type dopants to provide holes to the III-nitride active region 27 . Group III nitride active region 27 may include GaN-based or AlN-based materials, such as GaN, InGaN, AIN, or AlGaN. III-nitride active region 27 may have a single layer or quantum well structure, such as single quantum wells (SQWs) or multiple quantum wells (MQWs). If required, a buried tunnel junction can be grown after depositing the p-type Group III nitride region 23 .

As shown in FIG. 5B , in order to create a semiconductor window region from the semiconductor stack 117 and the polished Group III nitride region 115 , a photomask 119 (such as a photoresist) is formed on the semiconductor stack 117 . Implantation of ions (such as hydrogen atoms, n-type dopant atoms, and/or p-type dopant atoms) into the semiconductor stack 117 with the photomask 119 can produce the window structure 117a for the semiconductor portion 15 from the semiconductor stack 115 . The window structure 117a has a semiconductor window area 121 and an isolation area 123 surrounding the semiconductor window area 121.

The first half of the method of manufacturing the VCSEL of this embodiment has been described above. The second half of the method of this embodiment is described in detail below.

After the photomask 119 is removed, as shown in FIG. 5C , the conductive layer 125 is deposited on the window structure 117a, which covers the semiconductor window area 121 and the isolation area 123. The conductive layer 125 may include a heavily doped III-nitride semiconducting layer (such as GaN or AlGaN) and/or an inorganic layer (such as indium tin oxide (ITO)), and is sensitive to light from the III-nitride active region 27 transparent.

6A, 6B and 6C illustrate the steps of manufacturing VCSEL 11. As shown in FIG. 6A , a u(DBR) stack 127 is formed on the conductive layer 125 , and specifically, the first dielectric layer 127 a and the second dielectric layer 127 b are alternately deposited to form the dielectric layers. configuration.

As shown in FIG. 6B , a photomask 129 (eg, photoresist) is formed on the DBR buildup 127 . The DBR buildup 127 is etched through the photomask 129 to expose a portion of the conductive layer 125 , thereby forming a patterned DBR buildup 131 , ie, DBR 131 . DBR 131 is aligned with single crystal grating 17 associated with patterned ELO mask 111 (17), thereby providing VCSEL 11 with a substantial portion of optical cavity 29.

As shown in FIG. 6C , a first electrode 133 , such as an anode metal electrode, is formed over the DBR 127 to provide a product 135 . The first electrode 133 is deposited in contact with the exposed surface of the conductive layer 125 .

7A, 7B and 7C illustrate the steps of manufacturing VCSEL 11. As shown in FIG. 7A , the product 135 is connected to the support tool ST located on the first electrode 133 .

The VCSEL buildup 137 is produced by removing the substrate 101 from the product 135 by cryogenic processing or laser lift-off to expose the patterned ELO mask 111 associated with the single crystal grating 17 . VCSEL buildup 137 already has a first electrode 133 on its front side.

As shown in FIG. 7B , to form a second electrode, such as a cathode metal electrode, in the VCSEL buildup 137 , a patterned ELO mask 111 is processed through a mask 139 (eg, photoresist) to allow photolithography and etching therein. An opening 111b is formed.

As shown in FIG. 7C , after the photomask 139 is removed, the second electrode 141 is formed on the back side of the VCSEL build-up layer 137 to manufacture a VCSEL, which has a first electrode 133 and a second electrode 141 respectively on opposite sides of the VCSEL 11 . A second electrode 141 is deposited in rear-side contact with the III-nitride region 115 .

The above process completes the manufacturing of a VCSEL 11.

Embodiments of VCSELs according to the present disclosure are described in detail below. 8A, 8B and 8C illustrate the steps of manufacturing VCSEL 11.

After forming the semiconductor build-up layer 117 as shown in FIG. 5A , as shown in FIGS. 8A and 8B , a semiconductor mesa 143 and a window structure 117 a are formed from the semiconductor build-up layer 117 to expose the n-type Group III nitride region 115 . In this embodiment, as shown in FIG. 8A , the semiconductor mesa 143 is first formed through a photomask 145 (such as photoresist) by photolithography and etching, and then the window structure 117a is formed as shown in FIG. 5B . As shown in FIG. 8B , the window structure 117a has a semiconductor window region 121 and an isolation region 123 surrounding the semiconductor window region 121 . If required, the window structure 117a may be formed first and then the semiconductor mesa 143 is formed.

As shown in FIG. 8C , the conductive layer 125 is grown on the window structure 117 a, and the conductive layer 125 covers the semiconductor window region 121 and the isolation region 123 and is not grown on the n-type Group III nitride region 115 . Conductive layer 125 is transparent to light coming from III-nitride active region 27 . The conductive layer 125 may also include a heavily doped Group III nitride semiconducting layer, such as GaN or AlGaN, and/or an inorganic layer, such as indium tin oxide (ITO). The conductive layer 125 of the Group III nitride semiconductor may be formed on the semiconductor mesa 143 , for example, by selective growth using an inorganic photomask or a dielectric photomask 147 .

9A and 9B illustrate the steps of manufacturing VCSEL 11. As shown in FIG. 9A , a DBR buildup layer 127 is formed on the conductive layer 125 . A portion of the DBR build-up layer 127 is removed through etching to expose a portion of the conductive layer 125 , thereby forming a patterned DBR build-up layer 131 , ie, DBR 131 . DBR 131 is aligned with single crystal grating 17 associated with patterned ELO mask 111 (17), thereby providing VCSEL 11 with a substantial portion of optical cavity 29.

As shown in FIG. 9B, a first electrode 133, such as an anode metal electrode, and a second electrode 141, such as a cathode metal electrode, are formed on the exposed conductive layer 125 and the exposed n-type Group III nitride region 115, respectively. This manufactured product 149. The first electrode 133 and the second electrode 141 are both located on the front side of the semiconductor region (125 and 115). Specifically, the first electrode 133 is deposited on the mesa 143 in contact with the conductive layer 125 , and the second electrode 141 is deposited in contact with the n-type Group III nitride region 115 .

10A, 10B and 10C illustrate the steps of manufacturing VCSEL 11. Product 149 is linked to the support tool in the same manner as in Figure 6C, which is omitted in Figures 9B-10C to simplify the drawing.

As shown in FIG. 10A , substrate 101 is removed from product 149 to expose patterned ELO mask 111 associated with single crystal grating 17 , thereby fabricating VCSEL buildup 151 . The VCSEL stack 151 already has the first electrode 133 and the second electrode 141 on the same side.

As shown in FIG. 10B , in a VCSEL with the first electrode 133 and the second electrode 141 on the same side, the patterned ELO mask 111 is retained behind the Group III nitride region 115 . The above process completes the manufacturing of a VCSEL 11.

If desired, as shown in FIG. 10C , the dielectric material of the patterned ELO mask 111 can be removed to expose the periodic one-dimensional pattern 17 a transferred from the patterned ELO mask 111 to the III-nitride region 115 . Thereby, the single crystal grating 17 is formed on the rear side of the group III nitride region 115 .

The above process completes the manufacturing of a VCSEL 11.

Multiple embodiments of VCSELs according to the present disclosure are described with reference to FIGS. 11 to 15 . The DBR mirror 13 can also serve as a passivation/isolation layer between p-type electrodes and n-type electrodes.

FIG. 11A is a plan view of a VCSEL 11a according to an embodiment of the present disclosure, and FIG. 11B is a cross-sectional view along line I-I of FIG. 11A.

A process of one embodiment includes the following steps. 1. Deposit the ELO dielectric mask layer on the host substrate, such as GaN substrate, GaN-on-Sapphire template, GaN-on-Silicon template; 2. Pattern the grating in the ELO mask; 3. In the ELO A growth auxiliary part, that is, an opening is formed in the mask layer to expose the surface of the main substrate 101, thereby forming a patterned ELO mask 111; 4. Grow the GaN layer on the mask through the epitaxial lateral extension growth process to Make the lateral growth layer at least cover the grating pattern of the patterned ELO mask, thereby forming an epitaxial lateral extension growth (ELO) nitride layer; 5. Planarize the extension growth nitride layer by grinding or etching. Control the length of the optical cavity; 6. Form a semiconductor stack by continuing to grow the following layers: n-GaN layer for coating (for example, about 1000 nanometers (nm) thick) and a plurality of n-type contact layers; active region (e.g., complex InGaN/GaN quantum wells); AlGaN electron blocking layer (e.g., approximately 30 nm thick); p-GaN layer (e.g., approximately 200 nm thick); and p ⁺ -GaN layer (e.g., approximately 10 nm thick) ; 7. Perform ion implantation to define electrical and optical windows in the semiconductor buildup; 8. Form transparent conductive layers for p-type contacts; 9. Deposit dielectric DBR mirror area layers; 10. Deposit contact metal electrodes and cover The die is bonded to a supporting tool (not shown in the figure); 11. When using a template substrate, the substrate is removed by cryogenic treatment as described in Non-Patent Documents 16 to 20, or laser lift-off, and the substrate is removed to make The same substrate can be reused, thereby significantly reducing costs; 12. Finally deposit the metal contact electrode on the n-type side; and 13. Remove the patterned ELO mask 111.

A single crystal grating 17, such as n-GaN or unintentionally doped (UID)-GaN, is disposed on the surface of the III-nitride region 25, which covers the patterned ELO mask 111 by epitaxial lateral extension growth technology. . Therefore, the III-nitride has a GaN grating, which is transferred from the patterned ELO mask 111 . After the III-nitride region 25 is formed by grinding (which can be used to adjust the cavity length and/or planarize the III-nitride region), the III-nitride regions 23 and 27 can be grown by MOCVD. Group III nitride regions 23 and 27, which are continuous device layers, include undoped active regions and p-type layers, each having an alloy of indium (In), gallium (Ga), and/or aluminum (Al), and Nitrogen (N).

FIG. 12A is a plan view of a VCSEL 11b according to an embodiment of the present disclosure, and FIG. 12B is a cross-sectional view along line II-II of FIG. 12A.

A process of one embodiment includes the following steps. 1. Form the DBR mirror area layer (18d) of the periodically configured dielectric layer on the motherboard (101), such as GaN substrate, GaN-on-Sapphire template, GaN-on-Silicon template; 2. Deposit the separated dielectric Layer (18c) on the DBR mirror surface layer (18d); 3. Form the grating pattern for the single crystal grating pattern in the separate dielectric layer (18c); 4. Form the grating pattern on the separate dielectric layer (18c) and the DBR mirror surface A growth auxiliary part, that is, an opening is formed in the build-up layer (18d) to expose the surface of the main substrate 101, thereby forming a patterned ELO mask 111; 5. Grow the GaN layer on the mask through the epitaxial lateral extension growth process. So that the lateral growth layer at least covers the grating pattern, thereby forming the ELO nitride layer; 6. Planarize the ELO nitride layer (113) by grinding or etching to control the length of the optical cavity; 7. By continuing The following layers are grown to form a semiconductor stack: an n-GaN layer for cladding (e.g., about 1000 nm thick) and a plurality of n-type contact layers; an active region (e.g., a plurality of InGaN/GaN quantum wells); an AlGaN electron blocking layer (e.g., a plurality of InGaN/GaN quantum wells) , approximately 30 nm); p-GaN layer (e.g., approximately 200 nm thick); and p ⁺ -GaN layer (e.g., approximately 10 nm thick); 8. Perform ion implantation to define electrical, optical properties in the semiconductor stack Window; 9. Deposit a transparent conductive layer for p-type contact (35); 10. Deposit a dielectric DBR mirror area layer (13); 11. Deposit a contact metal electrode (31) and flip-chip bond it to a supporting tool (not shown) in the figure); 12. When a template substrate is used, the substrate (101) is removed by cryogenic treatment or laser lift-off as described in Non-Patent Documents 16 to 20, and the substrate is removed so that the same substrate can be reused. , thereby significantly reducing costs; and 13. Finally deposit a metal contact electrode (33b) on the n-type side.

A single crystal grating 17, such as n-GaN or UID-GaN, is disposed on the surface of the Group III nitride region 25, which covers the patterned ELO mask 111 through epitaxial lateral extension growth technology. Therefore, the III-nitride has a GaN grating that is transferred from the patterned ELO mask 111 with an additional DBR mirror (18d). The additional DBR mirror (18d) is located adjacent to the GaN grating (17a) to connect with the grating (17a), thereby forming a single mirror. After the III-nitride region 25 is formed by grinding (which can be used to adjust the cavity length and/or planarize the III-nitride region), the III-nitride regions 23 and 27 can be grown by MOCVD. Group III nitride regions 23 and 27, which are continuous device layers, respectively include an undoped active region and a p-type layer, each having an alloy of indium (In), gallium (Ga) and/or aluminum (Al), and nitrogen (N).

Periodic one-dimensional patterns 17a and additional DBR mirrors (18d) are connected to enhance reflectivity without complexity. An additional DBR mirror (18d) is placed in contact with the periodic one-dimensional pattern 17a, and the dielectric layer has the periodic one-dimensional pattern 18a.

FIG. 13A is a plan view of a VCSEL 11c according to an embodiment of the present disclosure. Fig. 13B is a cross-sectional view taken along line III-III of Fig. 13A.

A process of one embodiment includes the following steps. 1. Deposit the ELO dielectric mask layer on the main substrate, such as GaN substrate, GaN-on-Sapphire template, GaN-on-Silicon template; 2. Pattern the grating on the ELO mask layer; 3. Pattern the ELO mask layer A growth auxiliary part, that is, an opening is formed in the main substrate 101 to expose the surface of the main substrate 101, thereby forming a patterned ELO mask 111; 4. Grow the GaN layer on the ELO mask through the epitaxial lateral extension growth process, so that the side Cover at least the grating pattern to the growing layer, whereby the ELO nitride layer; 5. Planarize the ELO nitride layer by grinding or etching to control the length of the optical cavity; 6. Form the semiconductor stack by continuing to grow the following layers : n-GaN layer (e.g., approximately 1000 nm thick) and multiple n-type contact layers for coating; active region (e.g., multiple InGaN/GaN quantum wells); AlGaN electron blocking layer (e.g., approximately 30 nm); p-GaN layer (e.g., about 200 nm thick); and p ⁺ -GaN layer (e.g., about 10 nm thick); 7. Make a mesa from the semiconductor build-up to form an n-GaN contact region in the semiconductor build-up; 8. Execute Ion implantation to define electrical and optical windows in the semiconductor buildup; 9. Deposition of a transparent conductive layer for p-type contact (35); 10. Deposition of a dielectric DBR mirror area layer (13) (can be used as a p-type side pad and Isolation between n-type side pads); 11. Deposit contact metal electrodes (31 and 33a) and flip-chip bond them to the supporting tool (not shown in the figure); 12. When using a template substrate, use non-patent document 16 To remove the substrate 101 by cryogenic treatment or laser lift-off as described in Non-Patent Document 20, the substrate is removed so that the same substrate can be reused, thereby significantly reducing costs; and 13. Remove the patterned ELO mask 111 to expose III The group nitride region 25 has a periodic one-dimensional pattern 17a of the single crystal grating 17 on its rear side.

The dielectric DBR mirror 13 is located on the conductive layer 35 , is disposed on the top of the mesa 37 , and extends from the anode electrode 31 to the cathode electrode 33 a to cover the top and side surfaces of the mesa 37 . Another dielectric material film 45 may be located on the dielectric DBR mirror 13 and extend from the anode electrode 31 to the cathode electrode 33a. The dielectric DBR mirror 13 and another dielectric material film 45 (if any) serve as passivation films. The mesa 37 can position the anode electrode 31 and the cathode electrode 33a on the same side of the VCSEL 11c, and the VCSEL 11c can be disposed in a flip-chip bonding manner.

A single crystal grating 17, such as n-GaN or UID-GaN, is disposed on the surface of the Group III nitride region 25, which covers the patterned ELO mask 111 through epitaxial lateral extension growth technology. The grown III-nitride has a GaN grating, which is transferred from the patterned ELO mask 111 . After the III-nitride region 25 is formed by grinding (which can be used to adjust the cavity length and/or planarize the III-nitride region), the III-nitride regions 23 and 27 can be grown by MOCVD. Group III nitride regions 23 and 27, which are continuous device layers, respectively include an undoped active region and a p-type layer, each having an alloy of indium (In), gallium (Ga) and/or aluminum (Al), and nitrogen (N).

FIG. 14A is a plan view of the VCSEL 11d according to an embodiment of the present disclosure, and FIG. 14B is a cross-sectional view along line IV-IV of FIG. 14A.

A process of one embodiment includes the following steps. 1. Form the DBR mirror area layer (18d) of the periodically configured dielectric layer on the motherboard (101), such as GaN substrate, GaN-on-Sapphire template, GaN-on-Silicon template; 2. Deposit the separated dielectric Layer (18c) on the DBR mirror area layer (18d); 3. Forming a single crystal grating pattern in the separated dielectric layer (18c); 4. In the separated dielectric layer (18c) and the DBR mirror area layer (18d) Form the growth auxiliary part, that is, the opening to expose the surface of the main substrate 101, thereby forming the patterned ELO mask 111; 5. Grow the GaN layer on the mask through the epitaxial lateral extension growth process to allow lateral growth. The layer at least covers the grating pattern, thereby forming the ELO nitride layer; 6. Planarize the ELO nitride layer (113) by grinding or etching to control the length of the optical cavity; 7. Form by continuing to grow the following layers Semiconductor build-up: n-GaN layer for coating (for example, about 1000nm thick) and a plurality of n-type contact layers; active region (for example, a plurality of InGaN/GaN quantum wells); AlGaN electron blocking layer (for example, about 30 nm) ; p-GaN layer (e.g., about 200 nm thick); and p ⁺ -GaN layer (e.g., about 10 nm thick); 8. Making a mesa from the semiconductor build-up to form a contact n-GaN region in the semiconductor build-up; 9. Perform ion implantation to define electrical and optical windows in the semiconductor buildup; 10. Deposit transparent conductive layer for p-type contact (35); 11. Deposit dielectric DBR mirror area layer (13) (can be used as p-type side pad and isolation between n-type side pads); 12. Deposit contact metal electrodes (31 and 33a) and flip-chip bond them to the support tool (not shown in the figure); 13. When using a template substrate, use non-patent literature 16 to non-patent document 20 to remove the substrate (101) by cryogenic treatment or laser lift-off. The substrate is removed so that the same substrate can be reused, thereby significantly reducing costs.

The dielectric DBR mirror 13 is located on the conductive layer 35 , is disposed on the top of the mesa 37 , and extends from the anode electrode 31 to the cathode electrode 33 a to cover the top and side surfaces of the mesa 37 . Another dielectric material film 45 may be located on the dielectric DBR mirror 13 and extend from the anode electrode 31 to the cathode electrode 33a. The dielectric DBR mirror 13 and another dielectric material film 45 (if any) serve as passivation films. The mesa 37 can position the anode electrode 31 and the cathode electrode 33a on the same side of the VCSEL 11d, and the VCSEL 11d can be disposed in a flip-chip bonding manner.

A single crystal grating 17, such as n-GaN or UID-GaN, is disposed on the surface of the Group III nitride region 25, which covers the patterned ELO mask 111 through epitaxial lateral extension growth technology. The grown III-nitride has a GaN grating that is transferred from the patterned ELO mask 111 with an additional DBR mirror (18d). The additional DBR mirror (18d) is located adjacent to the GaN grating (17a) to connect with the grating (17a), thereby forming a single mirror. Periodic one-dimensional patterns 17a and additional DBR mirrors (18d) are connected to enhance reflectivity without complexity. An additional DBR mirror (18d) is placed in contact with the periodic one-dimensional pattern 17a, and the dielectric layer has the periodic one-dimensional pattern 18a. After the III-nitride region 25 is formed by grinding (which can be used to adjust the cavity length and/or planarize the III-nitride region), the III-nitride regions 23 and 27 can be grown by MOCVD. Group III nitride regions 23 and 27, which are continuous device layers, respectively include an undoped active region and a p-type layer, each having an alloy of indium (In), gallium (Ga) and/or aluminum (Al), and nitrogen (N).

FIG. 15A is a plan view of a VCSEL 11e according to an embodiment of the present disclosure. Fig. 15B is a cross-sectional view taken along line V-V in Fig. 15A.

A process of one embodiment includes the following steps. 1. Deposit the ELO dielectric mask layer on the main substrate, such as GaN substrate, GaN-on-Sapphire template, GaN-on-Silicon template; 2. Pattern the grating on the ELO mask; 3. Form growth auxiliary on the main substrate Part; 4. Grow the GaN layer on the mask through the epitaxial lateral extension growth process, so that the lateral growth layer at least covers the grating pattern, thereby ELO nitride layer; 5. Planarize by grinding or etching ELO nitride layer to control the length of the optical cavity; 6. Form a semiconductor stack by continuing to grow the following layers: an n-GaN layer for capping (for example, about 1000 nm thick) and a plurality of n-type contact layers; active region (e.g., complex InGaN/GaN or InGaN/InGaN quantum wells); AlGaN electron blocking layer (e.g., approximately 30 nm); p-GaN layer (e.g., approximately 200 nm thick); and includes a p ⁺⁺ -GaN layer ( For example, about 10 nm thick) and a buried tunnel junction (51) of the n ⁺⁺ -GaN layer (for example, about 10 nm thick); 7. Fabricating a mesa from the semiconductor build-up to form a contact n- in the semiconductor build-up GaN area; 8. Perform ion implantation to define electrical and optical windows in the semiconductor buildup; 9. Deposit transparent conductive layer for p-type contact (35); 10. Deposit dielectric DBR mirror area layer (13) and passivation Layer 45; 11. Deposit the contact metal electrode (31) and flip-chip bond it to the supporting tool (not shown in the figure); 12. When using a template substrate, use the methods described in Non-Patent Documents 16 to 20 Cryogenic treatment, or laser lift-off to remove the substrate (101), removes the substrate so that the same substrate can be reused, thereby significantly reducing costs.

The VCSEL 11e further includes a buried tunnel junction 51 disposed between the p-type Group III nitride region 23 and the DBR 13 . Buried tunnel junction 51 includes heavily doped p-type Group III nitride, such as p ⁺⁺ -GaN, and heavily doped n-type Group III nitride, such as n ⁺⁺ -GaN. In certain embodiments, a p ⁺⁺ -GaN layer is deposited on p-type Group III nitride region 23, followed by an n ⁺⁺ -GaN layer being deposited on the p ⁺⁺ -GaN layer to form a tunnel junction. n ⁺⁺ -GaN layer is deposited with n-type conductive layer 35. At the tunnel junction, the conductivity type of the III-nitride is changed to another conductivity type. Reverse bias is applied to the tunnel junction, so carriers tunnel across the junction.

The tunnel junction 51 of this embodiment can be applied to any of the VCSELs 11a to 11d of the above embodiments. Including tunnel junctions improves VCSEL performance and slows down ITO absorption.

The dielectric DBR mirror 13 is located on the conductive layer 35 provided on the top of the mesa 37 . The dielectric material film 45 or the dielectric DBR mirror 13 extends from the anode electrode 31 to the cathode electrode 33a to cover the top and side surfaces of the mesa 37 and serves as a passivation film. The mesa 37 can position the anode electrode 31 and the cathode electrode 33a on the same side of the VCSEL 11e, and the VCSEL 11e can be disposed in a flip-chip bonding manner.

A single crystal grating 17, such as n-GaN or UID-GaN, is disposed on the surface of the Group III nitride region 25, which covers the patterned ELO mask 111 through epitaxial lateral extension growth technology. The grown III-nitride has a GaN grating, which is transferred from the patterned ELO mask 111 . After the III-nitride region 25 is formed by grinding (which can be used to adjust the cavity length and/or planarize the III-nitride region), the III-nitride regions 23 and 27 can be grown by MOCVD. Group III nitride regions 23 and 27, which are continuous device layers, respectively include an undoped active region and a p-type layer, each having an alloy of indium (In), gallium (Ga) and/or aluminum (Al), and nitrogen (N).

The following describes technical explanations of certain technical terms regarding the VCSEL of the present disclosure.

Main substrate and ELO mask

In some embodiments, the GaN base layer 113 is grown by ELO on the main substrate 101 having a patterned ELO mask 111 composed of silicon dioxide (SiO ₂ ), and the GaN base layer 113 does not coalesce with the silicon dioxide. . The patterned ELO mask 111 can be composed of strip-shaped openings 107a. The silicon dioxide stripes of the patterned ELO mask 111 define the distance between the openings 107a, so that a high-quality Group III nitride semiconductor layer can be grown and can avoid The coalescence between adjacent semiconductor layers can prevent the substrate 101 from twisting or bending during epitaxial growth. Thereby, a VCSEL with reduced defect density (such as dislocation and stacking faults) can be provided. Furthermore, these techniques can be used with heterogeneous substrates (such as sapphire, SiC, LiAlO ₂ , Si, etc.) as long as they can grow ELO GaN base layers.

Patterned grating on top of ELO mask

Gratings can be formed on patterned ELO masks. For example, nano-imprinting is a commercially acceptable technology compared to other technologies, such as E-beam lithography or holography.

The grating can be formed by first depositing a photosensitive material on the ELO mask and then applying the desired grating pattern to the photosensitive material. On the other hand, nanoimprinting, electron beam or holography can also be used to print the desired grating pattern. Next, the grating pattern to be used is transferred to the photoresist material. For example, grating pattern coefficients, such as height (H), period (P) and width (W), can be defined using elements H/P and W/P as shown in Figure 3D. When it has a period P of about 375 nm, its H/P is about 0.27 and W/P is about 0.35, the transverse electric field (TE) mode mapping of the n-GaN grating reflectance mapping can be greater than 99 at the optical wavelength of 405 nm. %. After transferring the grating pattern to the photoresist, a dielectric material, such as silicon dioxide, is deposited to completely bury the photoresist, and an etching, such as reactive ion etching, is performed to expose the underlying photoresist. Next, the photoresist is chemically stripped to retain the grating pattern on the ELO mask, thereby forming a patterned ELO mask.

Form grating on ELO mask with DBR mirror structure

The grating can be formed by first depositing the photosensitive material on the ELO mask (in some embodiments, the DBR mirror can be used as the ELO mask), and then applying the desired grating pattern to the photosensitive material. On the other hand, nanoimprinting, electron beam or holography can also be used to print the desired grating pattern. Next, the grating pattern to be used is transferred to the photoresist material. For example, grating pattern coefficients such as height (H), period (P), and width (W) can be defined using the elements H/P and W/P.

When the grating pattern is transferred to the photoresist, an interface material, such as silicon dioxide, is deposited over the pattern to completely bury it, and an etch, such as reactive ion etching, is performed to expose the underlying photoresist. Next, chemical lift-off of the photoresist leaves the grating pattern in the silicon dioxide layer on top of the DBR structure.

Growth of Group III Nitride Layer

Next, the Group III nitride region 113 is grown by MOCVD. The III-nitride region has a grating shape at the bottom of the grown III-nitride, as shown in FIG. 3C. Group III nitride region 113 is ground or etched to a desired thickness to form planarized Group III nitride region 115 . After adjusting the thickness of the III-nitride region 113 by grinding or etching, the III-nitride stack 117 is grown thereon.

Trimethylgallium (TMGa), trimethylindium (TMIn), and triethylaluminum (TMAl) are used as Group III element sources, and ammonia gas (NH ₃ ) is used as a raw material gas to supply nitrogen. Hydrogen (H ₂ ) and/or nitrogen (N ₂ ) are used as carrier gases. SiH ₄ and Bis (cyclopentadienyl) magnesium (Cp ₂ Mg) are used as n-type and p-type dopants respectively.

Pressure can typically be set from 50 to 760 Torr. Group III nitride-based semiconductor layers generally grow in the temperature range of 700 to 1250°C.

Exemplary growth coefficients include the following: TMG can be about 12 sccm; _NH3 can be about 8 slm; carrier gas can be about 3 slm; _SiH4 can be about 1.0 sccm; and the Group V/III ratio can be about 7700.

In some embodiments, the growth pressure can be in the range of 50 to 760 Torr, and the growth pressure is preferably in the range of 100 to 300 Torr to obtain a large width of island-shaped Group III nitride-based semiconductor region; the growth temperature can be in Within the temperature range of 900 to 1200 ℃; the Group V/III ratio can be in the range of 50 to 30000, and preferably 3000 to 10000; TMG can be in the range of 2 to 20 sccm; _NH3 can be in the range of 3 to 10 within the range of slm; and the carrier gas can be hydrogen only, or both hydrogen and nitrogen. After about 2 to 8 hours of growth, the ELG GaN base layer has a thickness of about 8 to 50 microns and a width of about 20 to 150 microns, and the grown ELG GaN base layer extends laterally in both directions along the ELO mask to provide epitaxial lateral extension. Grow low-defect crystal regions (wings).

ion implantation

Ion implantation forms electrical and optical windows in the GaN base layer by damaging the GaN base layer outside the window, and the damaged GaN base material is no longer conductive. This method keeps the surface flat and provides slight index guiding between the window area and the damaged area. However, damaged areas may increase optical losses within the cavity and tend to have higher absorption values than unimplanted material in the window areas. Heavy ions, such as aluminum (Al), boron (B), etc., can be used in ion implantation procedures.

Transparent conductive layer

ITO can be used as a commonly used transparent current spreading layer. VCSEL containing ITO may cause additional absorption, but the additional absorption can be reduced by making the intensity of electromagnetic waves lower near the ITO layer. Alternative approaches, such as tunnel junctions, can also be used to distribute current and achieve lower optical absorption.

tunnel junction

Tunnel junctions provide an alternative to using ITO. The tunnel junction allows holes to be injected into the p-type side of the device through the n-type semiconductor. It can be achieved by utilizing the junction between the highly doped n-type region and the highly doped p-type region under reverse bias, allowing electrons to tunnel from the depletion band of the p-type region to the conduction band of the n-type region. .

Distributed Bragg Reflector (DBR)

Traditionally, VCSELs use epitaxial DBR, with either an AlN/GaN double layer or an AlInN/GaN double layer, or a dielectric DBR mirror. The primary consideration in choosing a DBR design involves ease of fabrication. A DBR mirror consists of alternating dielectric layers joined together to form a reflective mirror on top of the VCSEL's resonant cavity. For example, a combination of SiO ₂ /Ta ₂ O ₅ dielectric layers can be used as a dielectric DBR mirror.

Single crystal epitaxial GaN grating

The important part of VCSEL is the reflector. Typically, dielectric DBR is used as a mirror. However, in terms of electrical injection or thermal management considerations, at least one side of the mirror used in the resonant cavity of the VCSEL should be replaced with other better solutions. In the VCSEL of the present disclosure, a single crystal grating system is used, which is formed on the epitaxial lateral extension of GaN as an alternative to one of the many DBR mirrors.

Single crystal epitaxial GaN gratings have a periodic structure, such as GaN concave parts or GaN convex parts arranged on the GaN surface. The height (H), width (W) and period (P) of their arrangement are equivalent to the wavelength of the VCSEL. When light hits the grating vertically, it is diffracted in different directions depending on the wavelength and the period of the grating. By appropriately choosing the grating period and fill factors such as W/P and H/P, all light energy can be reflected.

There are many options for exemplifying gratings, but this disclosure provides a unique way to exemplify subwavelength gratings on a device that avoids exposure of device layers to any etching environment during fabrication.

metal pad

Metals, such as gold (Au), aluminum (Al), nickel (Ni), platinum (Pd), titanium (Ti), etc., can be used as the material of the metal pad. The metal layer can be formed by sputtering, evaporation or electroplating.

The present disclosure illustrates an improved fabrication method for single crystal gratings for III-nitride VCSELs. Specifically, the present disclosure includes a VCSEL having a single crystal GaN grating as one of the mirrors of the VCSEL operating at visible or ultraviolet wavelengths. A novel and progressive feature of the present disclosure is the integration of gratings through epitaxial lateral extension growth. The disclosure prevents device layers from being exposed to physical etching during the manufacturing process. In physical etching, semiconductor device layers are bombarded with heavy ions (such as aluminum or boron) to form the desired grating shape. This process ultimately increases the resistance of these layers due to ion bombardment and may introduce leakage current paths. In addition, this approach may damage the active area of the device or adjacent epitaxial layers. The process detailed in this disclosure is expected to provide significant improvements in device performance and reduce manufacturing costs by eliminating complex processes. The present disclosure simplifies the fabrication of gratings operating at many wavelengths of VCSELs. The present disclosure can be applied to non-patent documents 7 to 15, such as visible light emitted by lasers for data communication, laser imaging detection and ranging (LiDar), biochemical and environmental sensing, scientific instruments, comprehensive Like data storage, and extended/virtual display and lighting. Since cleaved facets or etched facets are not necessary for laser operation, the present disclosure is beneficial for hybrid integration with other optoelectronic devices, such as silicon photonics.

Using single crystal epitaxial gratings has the following advantages.

Use a sufficiently long cavity without excessive diffraction losses. Defining the VCSEL cavity through two mirrors, this disclosure proposes to use n-GaN as the grating layout, and design the grating pattern adjacent to the active area, that is, it will be more complicated on the p-type side and may damage the device layer.

Better thermal management due to sufficiently long cavities and/or contact layout on the nitride layer.

The grating is usually placed on the p-GaN side of the device, which makes the process simpler without the risk of possible damage. On the other hand, the formation of the grating on the n-type side requires removal of the substrate, which is more complex, lengthy, and cannot be used for all III groups. Nitride crystal planes.

The N-side grating is usually formed after removing the device layer from the substrate, but in this disclosure, the grating is formed before forming the device layer.

In the present disclosure, the grating is designed to be formed on either the main substrate or a material disposed over the substrate, so damage to the device layer during laser lift-off can be avoided.

A dielectric DBR can be formed above the top plane to improve its reflectivity.

Template substrates, called heterogeneous substrates such as GaN/Sapphire or GaN/Si, can be used to instantiate gratings.

When the template substrate is used, laser lift-off can be used. In the conventional technology, the use of a template substrate may damage the device layer, but in the present disclosure, the ELO method is used to reduce the damage, that is, the ELO mask can act as a protective layer for the device layer.

In the present disclosure, the grating on the n-type side can be realized with the help of designing an ELO mask. Furthermore, for almost all crystallographic directions of GaN substrates, the removal of the substrate has been verified in Non-Patent Document 16 to Non-Patent Document 20, and laser lift-off can be easily applied to foreign substrates. High-quality and large-size GaN substrates are very expensive. Using ELO technology can unlock the use of heterogeneous substrates in the production of VCSELs.

Designing gratings that operate at visible wavelengths is tedious, complex, and requires caution. Electron beam lithography and holography are generally preferred over nanoimprinting. In nanoimprinting, applying additional force to the device layer to imprint the pattern may cause damage or breakage of the device layer. In the present disclosure, nanoimprinting to form grating patterns is performed on either a thick motherboard or an ELO mask, so any existing technology can be used to print gratings.

Formation of grating

The grating surface on the n-type side can be formed using a number of methods, including, but not limited to, forming a grating pattern on a master substrate with an ELO mask. The master substrate may include a GaN substrate, a GaN/Sapphire template, or a GaN/Si template. The procedure for obtaining the raster is detailed below.

Set a thin dielectric film, such as about 100 nm, on the main substrate; Coating photoresist (PR) material or nanoimprint auxiliary material on the thin dielectric film; Transfer raster patterns to materials; Use dielectric materials to bury patterns; Expose PR material or nanoimprint auxiliary material by etching; Retain the desired grating pattern on the ELO mask by removing the PR material or nanoimprint auxiliary material.

The procedure for obtaining an ELO mask with a grating pattern has been described with reference to the drawings.

To assist lateral semiconductor growth, the III-nitride material beneath the ELO mask is exposed through openings such as stripes or other shapes.

The process begins by providing a master substrate, preferably a GaN substrate. GaN substrates have less dislocation density (10 ⁵ to 10 ⁶ defects per cm ^-2 ). Alternatives can utilize template substrates such as GaN-on-Silicon and GaN-on-Sapphire. The main substrate, such as GaN substrate, GaN-on-Sapphire template or GaN-on-Silicon template, is used as the ELO seed layer. Utilizing these template substrates can improve the yield of Group III nitride devices, thereby reducing manufacturing costs. Non-patent literature 15 to non-patent literature 20 propose using the ELO method to form low-defect epitaxial layers for optical devices such as edge-emitting lasers, micro-LEDs and VCSELs.

In a first aspect of the above embodiment, a vertical resonant cavity surface-emitting laser (VCSEL) includes: a first distributed Bragg reflector (DBR), which includes first distributed Bragg reflectors alternately arranged in a first axis direction. a dielectric layer and a second dielectric layer; and a semiconductor portion including a p-type Group III nitride region, a Group III nitride region, and between the p-type Group III nitride region and the Group III nitride region The Group III nitride active region, the p-type Group III nitride region, the Group III nitride active region and the Group III nitride region are arranged in the first axial direction, and the Group III nitride region includes an n-type Group III nitride The nitride region, wherein the semiconductor part includes a single crystal grating with a periodic one-dimensional pattern, the single crystal grating, the III nitride active region and the first distributed Bragg reflector are arranged in the first axis direction and An optical cavity is formed, and the periodic one-dimensional pattern extends in a second axis intersecting the first axis.

In a second aspect of the above embodiment, the VCSEL as described in the first aspect further includes a dielectric layer disposed on the semiconductor part, and the dielectric layer extends on the single crystal grating to cover the periodic one-dimensional pattern. .

In a third aspect of the above embodiment, the VCSEL as described in the second aspect further includes a second distributed Bragg reflector, wherein the dielectric layer is disposed between the second distributed Bragg reflector and the semiconductor part. time, wherein the second distributed Bragg reflector includes third dielectric layers and fourth dielectric layers alternately arranged in the first axial direction, and wherein the second distributed Bragg reflector and the periodic one-dimensional The patterns are connected to each other to form a single reflector.

In a fourth aspect of the above embodiment, the VCSEL as described in any one of the first to third aspects further includes: a conductive layer disposed on the semiconductor part, and a part of the conductive layer is disposed on the third between a distributed Bragg reflector and the semiconductor part; and a first electrode disposed on the conductive layer and located outside the first distributed Bragg reflector, the first electrode being disposed in contact with the conductive layer.

In a fifth aspect of the above embodiment, the VCSEL of the fourth aspect further includes a second electrode, wherein the group III nitride region has a first surface, and a third electrode located on an opposite side of the first surface. Two sides, wherein the single crystal grating is formed on the first side, and the second electrode is disposed on the second side.

In a sixth aspect of the above embodiment, the VCSEL of the fourth aspect further includes a second electrode, wherein the group III nitride region has a first surface and a third electrode located on an opposite side of the first surface. Two sides, wherein the single crystal grating is formed on the first side, and the second electrode is disposed on the first side.

In a seventh aspect of the above embodiment, the VCSEL as described in any one of the first to sixth aspects, wherein the total cavity length of the optical cavity is more than 1 micron.

In an eighth aspect of the above embodiment, the VCSEL as described in any one of the first to seventh aspects, wherein the distance between the single crystal grating and the first distributed Bragg reflector is no more than 30 microns.

In a ninth aspect of the above embodiment, a method of manufacturing a vertical cavity surface emitting laser (VCSEL) includes: forming a patterned epitaxial lateral elongation growth (ELO) mask on one side of a substrate, wherein The substrate includes one of a Group III nitride substrate, a silicon substrate, a sapphire substrate, a sapphire-based gallium nitride template, or a silicon-based gallium nitride template. The patterned epitaxial lateral extension growth mask includes a grating pattern and up to the The opening on the surface of the substrate; the patterned epitaxial lateral extension growth mask is used to grow Group III nitride on the substrate to form a Group III nitride area covering the grating pattern, and the grating pattern is transferred to the III Group III nitride region; growing a semiconductor stack including an n-type Group III nitride region, a Group III nitride active region, and a p-type Group III nitride region; after growing the semiconductor stack, a conductive layer is grown; forming a first dispersed Bragg reflection (DBR) on the conductive layer to produce a product, wherein the first distributed Bragg reflector includes alternately configured first dielectric layers and second dielectric layers; and removing the substrate from the product to expose the pattern The epitaxial wafer is laterally extended into a growth mask, wherein the grating pattern includes a periodic one-dimensional pattern extending along the surface of the substrate.

In a tenth aspect of the above-mentioned embodiment, the method described in the ninth aspect further includes forming a first metal electrode on the conductive layer after forming the first distributed Bragg reflector and before removing the substrate.

In an eleventh aspect of the above embodiment, the method as described in the ninth or tenth aspect further includes planarizing the group III nitride region by at least one of grinding or etching before growing the semiconductor layer. .

In a twelfth aspect of the above embodiment, the method as described in any one of the ninth to eleventh aspects further includes: before growing the conductive layer, making a mesa from the semiconductor layer by etching to form The etched surface of the semiconductor stack, wherein the mesa includes the Group III nitride active region; and a second electrode is formed on the etched surface of the semiconductor stack.

In a thirteenth aspect of the above embodiment, the method described in any one of the ninth to eleventh aspects further includes: after removing the substrate, removing the patterned epitaxial lateral extension growth mask A portion is used to expose the Group III nitride region; and a second metal electrode is formed on the exposed surface of the Group III nitride region.

In a fourteenth aspect of the above embodiment, the method described in any one of the ninth to twelfth aspects further includes removing the patterned epitaxial lateral extension growth mask after removing the substrate.

In a fifteenth aspect of the above embodiment, the method as described in any one of the ninth to thirteenth aspects, wherein the patterned epitaxial lateral extension growth mask further includes a second dispersed Bragg reflector, The second distributed Bragg reflector has third dielectric layers and fourth dielectric layers alternately arranged on the surface of the substrate.

As used herein and not otherwise defined, the terms "substantially" and "approximately" are used to describe and describe small changes. When used in connection with an event or situation, the term may include the precise moment at which the event or situation occurs, as well as the event or situation occurring to a close approximation. For example, when combined with a numerical value, the term may include a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

The components of several embodiments are summarized above so that those with ordinary skill in the technical field to which this disclosure belongs can better understand the concepts of the embodiments of this disclosure. It should be understood by those of ordinary skill in the art that the embodiments of the present disclosure can be used as a basis to design or modify other processes and structures to achieve the same purposes and/or achieve the same results as the embodiments introduced herein. benefits. Those of ordinary skill in the technical field to which the present disclosure belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure, and that various modifications can be made herein without departing from the spirit and scope of the present disclosure. Changes, Substitutions and Alternatives. Therefore, the protection scope of the present disclosure shall be determined by the appended patent application scope.

11. 11a~11e: VCSEL 13: Distributed Bragg reflector (DBR) 15: Semiconductor part 17: Single crystal grating 17a, 18a: Periodic one-dimensional pattern 17b, 18b: Unpatterned part 17c, 18c: Patterned part 18d: Dielectric DBR buildup 19: First dielectric layer 21: Second dielectric layer 23: p-type Group III nitride region 25: n-type Group III nitride region 25a: front side 25b: back side 27: Group III nitride Active area 29: Optical cavity 31: Anode electrodes 33, 33a, 33b: Cathode electrode 35: Conductive layer 35a: Inner part 35b: Outer part 37: Mesa 39a: Conductive window part 39b: Low conductive part L _CAV : Total cavity Length Ax1, Ax2: Axial S101~S108: Steps

[Fig. 1] is a schematic diagram showing a vertical cavity surface emitting laser (VCSEL) according to an embodiment of the present disclosure. [Fig. 2] is a flow chart showing the main steps of a method of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 3A] is a diagram showing the steps of manufacturing a single crystal grating according to an embodiment of the present disclosure. [Fig. 3B] is a diagram illustrating the steps of manufacturing a single crystal grating according to an embodiment of the present disclosure. [Fig. 3C] is a diagram showing the steps of manufacturing a single crystal grating according to an embodiment of the present disclosure. [Fig. 3D] is a diagram showing the steps of manufacturing a single crystal grating according to an embodiment of the present disclosure. [Fig. 4] is a plan view of a patterned ELO mask formed by secondary patterning according to an embodiment of the present disclosure. [Fig. 5A] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 5B] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 5C] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 6A] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 6B] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 6C] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 7A] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 7B] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 7C] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 8A] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 8B] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 8C] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 9A] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 9B] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 10A] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 10B] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 10C] is a diagram showing the main steps of manufacturing a VCSEL according to an embodiment of the present disclosure. [Fig. 11A] is a plan view showing a VCSEL according to an embodiment of the present disclosure. [Fig. 11B] is a cross-sectional view taken along line I-I in Fig. 11A. [Fig. 12A] is a plan view showing a VCSEL according to an embodiment of the present disclosure. [Fig. 12B] is a cross-sectional view taken along line II-II in Fig. 12A. [Fig. 13A] is a plan view showing a VCSEL according to an embodiment of the present disclosure. [Fig. 13B] is a cross-sectional view taken along line III-III in Fig. 13A. [Fig. 14A] is a plan view showing a VCSEL according to an embodiment of the present disclosure. [Fig. 14B] is a cross-sectional view taken along line IV-IV in Fig. 14A. [Fig. 15A] is a plan view showing a VCSEL according to an embodiment of the present disclosure. [Fig. 15B] is a cross-sectional view taken along line V-V in Fig. 15A.

11:VCSEL

13: Distributed Bragg Reflector (DBR)

15:Semiconductor part

17:Single crystal grating

17a, 18a: Periodic one-dimensional pattern

17b, 18b: Unpatterned part

17c, 18c: Patterned part

18d: Dielectric DBR laminate

19: First dielectric layer

21: Second dielectric layer

23: p-type III nitride region

25: n-type III nitride region

25a: front

25b: Back

27: Group III nitride active region

29: Optical cavity

31: Anode electrode

33, 33a, 33b: cathode electrode

35: Conductive layer

35a: Internal part

35b:External part

37: Countertop

39a: Conductive window part

39b: Low conductive part

L _CAV : total cavity length

Ax1, Ax2: axial direction

Claims (15)

A vertical resonant cavity surface-emitting laser, which includes: A first distributed Bragg reflector including first dielectric layers and second dielectric layers alternately arranged in the first axis; and A semiconductor part including a p-type Group III nitride region, a Group III nitride region, and a Group III nitride active region between the p-type Group III nitride region and the Group III nitride region, the p-type Group III nitride region The Group III nitride region, the Group III nitride active region and the Group III nitride region are arranged in the first axial direction, and the Group III nitride region includes an n-type Group III nitride region, Wherein, the semiconductor part includes a single crystal grating with a periodic one-dimensional pattern, and the single crystal grating, the III-nitride active region and the first distributed Bragg reflector are arranged in the first axis to form an optical cavity. , the periodic one-dimensional pattern extends in the second axial direction that intersects the first axial direction. The vertical resonant cavity surface-emitting laser according to claim 1 further includes a dielectric layer disposed on the semiconductor part, and the dielectric layer extends on the single crystal grating to cover the periodic one-dimensional pattern. The vertical resonant cavity surface-emitting laser as described in claim 2 further includes a second dispersed Bragg reflector, wherein: the dielectric layer is disposed between the second distributed Bragg reflector and the semiconductor portion, The second distributed Bragg reflector includes third dielectric layers and fourth dielectric layers alternately arranged in the first axis direction, and The second dispersed Bragg reflector and the periodic one-dimensional pattern are connected to each other to form a single reflector. The vertical resonant cavity surface-emitting laser as described in any one of claims 1 to 3, further includes: A conductive layer is provided on the semiconductor part, a part of the conductive layer is provided between the first distributed Bragg reflector and the semiconductor part; and A first electrode is disposed on the conductive layer and located outside the first distributed Bragg reflector. The first electrode is disposed in contact with the conductive layer. The vertical resonant cavity surface-emitting laser as described in claim 4 further includes a second electrode, wherein: The Group III nitride region has a first side and a second side opposite the first side, and The single crystal grating is formed on the first surface, and the second electrode is disposed on the second surface. The vertical resonant cavity surface-emitting laser as described in claim 4 further includes a second electrode, wherein: The Group III nitride region has a first side and a second side opposite the first side, and The single crystal grating is formed on the first surface, and the second electrode is disposed on the first surface. The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the total cavity length of the optical cavity is more than 1 micron. The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the distance between the single crystal grating and the first dispersed Bragg reflector is no more than 30 microns. A method of manufacturing a vertical resonant cavity surface-emitting laser, which method includes: Forming a patterned epitaxial lateral extension growth mask on one side of the substrate, wherein the substrate includes one of a Group III nitride substrate, a silicon substrate, a sapphire substrate, a sapphire-based gallium nitride template, or a silicon-based gallium nitride template, The patterned epitaxial lateral extension growth mask includes a grating pattern and an opening up to the surface of the substrate; Using the patterned epitaxial lateral extension growth mask to grow Group III nitride on the substrate to form a Group III nitride region covering the grating pattern, and the grating pattern is transferred to the Group III nitride region; Growth of semiconductor stacks including n-type Group III nitride region, Group III nitride active region, and p-type Group III nitride region; After growing the semiconductor layer, a conductive layer is grown; Forming a first distributed Bragg reflector on the conductive layer to produce a product, wherein the first distributed Bragg reflector includes first dielectric layers and second dielectric layers that are alternately arranged; and Remove the substrate from the product to expose the patterned epitaxial lateral extension growth mask, Wherein, the grating pattern includes a periodic one-dimensional pattern extending along the surface of the substrate. The method of claim 9, further comprising: forming a first metal electrode on the conductive layer after forming the first distributed Bragg reflector and before removing the substrate. The method of claim 9 or 10, further comprising: planarizing the Group III nitride region by at least one of grinding or etching before growing the semiconductor stack. The method described in request item 9 or 10 further includes: Before growing the conductive layer, creating a mesa from the semiconductor buildup by etching to form an etched surface of the semiconductor buildup, wherein the mesa includes the Group III nitride active region; and A second electrode is formed on the etched surface of the semiconductor stack. The method described in request item 9 or 10 further includes: After removing the substrate, removing a portion of the patterned epitaxial lateral extension growth mask to expose the III-nitride region; and A second metal electrode is formed on the exposed surface of the Group III nitride region. The method of claim 9 or 10 further includes: after removing the substrate, removing the patterned epitaxial lateral extension growth mask. The method of claim 9 or 10, wherein the patterned epitaxial lateral extension growth mask further includes a second dispersed Bragg reflector, the second dispersed Bragg reflector having alternating The third dielectric layer and the fourth dielectric layer are configured.