TW202341283A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a silicon carbide circuit board, a gallium nitride device and a silicon integrated circuit device. The silicon carbide circuit board includes a silicon carbide substrate and a circuit structure located above the silicon carbide substrate. The gallium nitride device includes a sapphire substrate, a gallium nitride component on the sapphire substrate, and a first redistribution structure on the gallium nitride component. The silicon integrated circuit device includes a silicon substrate, a field-effect transistor on the silicon substrate, and a second redistribution structure on the field-effect transistor.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

In the field of integrated circuits, III-V compound semiconductors are often used to form a variety of semiconductor components, such as high power field-effect transistors, high efficiency transistors or high electron migration High electron mobility transistors (HEMT), etc. High electron mobility transistor is a field effect transistor, which can use one interface between two materials with different energy gaps as a channel, so that the channel has a two-dimensional electron gas with high electron mobility (2 -dimensional electron gas, 2DEG). In recent years, high electron mobility transistors have gradually attracted attention due to their high power efficiency.

Generally speaking, when manufacturing semiconductor devices, the performance of the semiconductor device will be affected by the material of the semiconductor substrate. For example, silicon semiconductor material has the advantage of mature manufacturing processes. However, when III-V compound semiconductor devices (such as gallium nitride semiconductor devices) are formed on a silicon substrate, parasitic channels may be formed in the silicon substrate, thereby reducing the risk of III-V compound semiconductor devices (such as gallium nitride semiconductor devices). -Performance of Group V compound semiconductor devices. In addition, gallium nitride semiconductor devices formed on a sapphire substrate can have better performance. However, if the gallium nitride semiconductor device is formed on a sapphire substrate, the gallium nitride semiconductor device may be damaged in the long run due to the poor heat dissipation ability of the sapphire substrate. The problem of characteristic drift occurs after time is used.

The present invention provides a semiconductor device that can improve the problem of parasitic resistance in circuits in the semiconductor device, and the semiconductor device has the advantage of good heat dissipation effect.

The present invention provides a manufacturing method of a semiconductor device, which can improve the problem of parasitic resistance in circuits in the semiconductor device, and the semiconductor device has the advantage of good heat dissipation effect.

At least one embodiment of the present invention provides a semiconductor device, including a silicon carbide circuit board, a gallium nitride device, and a silicon integrated circuit device. A silicon carbide circuit board includes a silicon carbide substrate and a circuit structure located above the silicon carbide substrate. The circuit structure includes a plurality of first internal connection terminals, a plurality of second internal connection terminals and a plurality of external connection terminals. The external connection terminal is configured to connect external signals. The gallium nitride device includes a sapphire substrate, a gallium nitride element located on the sapphire substrate, and a first redistribution structure located on the gallium nitride element. The first rewiring structure is electrically connected to the first internal connection terminal. The silicon integrated circuit device includes a silicon substrate, a field effect transistor element located on the silicon substrate, and a second rewiring structure located on the field effect transistor element. The second rewiring structure is electrically connected to the second internal connection terminal.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a circuit structure on a silicon carbide substrate, wherein the circuit structure includes a plurality of first internal connection terminals, a plurality of second internal connection terminals and a plurality of external connections. Terminals, wherein the external connection terminals are configured for connecting external signals; forming a gallium nitride device layer on the sapphire wafer; forming a first rewiring layer on the gallium nitride device layer; cutting the sapphire wafer to form a plurality of nitrogen Gallium nitride devices, each gallium nitride device including a sapphire substrate, a first redistribution structure and a gallium nitride element; electrically connecting at least one gallium nitride device to a first internal connection terminal; forming a field effect transistor element layer on on the silicon wafer; forming a second rewiring layer on the field effect transistor element layer; cutting the silicon wafer to form a plurality of silicon integrated circuit devices, each silicon integrated circuit device including a silicon substrate and a second rewiring structure and a field effect transistor element; and electrically connecting at least one silicon integrated circuit device to the second internal connection terminal.

1A to 2A are schematic top views of a method for manufacturing a silicon carbide circuit board according to an embodiment of the present invention. 1B to 2B are schematic cross-sectional views along line a-a’ of FIGS. 1A to 2A respectively.

Referring to FIGS. 1A and 1B , a silicon carbide substrate 100 is provided. In this embodiment, the silicon carbide substrate 100 is a cut substrate. For example, a circular silicon carbide wafer is cut into a rectangular silicon carbide substrate 100, but the invention is not limited thereto. In other embodiments, the silicon carbide substrate 100 includes other shapes, such as triangular, pentagonal, circular, elliptical, or other shapes. In addition, in other embodiments, the silicon carbide substrate 100 may also be an uncut silicon carbide wafer. In some embodiments, the silicon carbide substrate 100 has a thickness 100t of 200 microns to 700 microns.

Compared with polymer base materials used in general printed circuit boards, the silicon carbide base 100 has the advantage of high heat dissipation coefficient. Specifically, in some embodiments, the heat dissipation coefficient of the silicon carbide substrate 100 ranges from 3.3 W/cmK to 4.9 W/cmK at room temperature (25 degrees Celsius). In this embodiment, since the silicon carbide substrate 100 is not used in the epitaxial process, the quality of the silicon carbide substrate 100 may be lower than the quality of silicon carbide wafers generally used in the epitaxial process. In other words, the production cost of the silicon carbide substrate 100 can be lower than the production cost of silicon carbide wafers generally used in the epitaxial process. For example, the defect density in the silicon carbide substrate 100 is greater than 9000 cm ^-2 , the bow is less than ±800µm (preferably less than ±350µm, most preferably less than ±100µm), and the warp (Warp) is less than ± 900µm (preferably less than ±450µm, most preferably less than ±100µm), but the present invention is not limited to this.

Next, please refer to FIG. 2A and FIG. 2B to form the circuit structure CS on the silicon carbide substrate 100 to form the silicon carbide circuit board 10 .

The circuit structure CS includes a plurality of first internal connection terminals (111, 112), a plurality of second internal connection terminals (113, 114), and a plurality of external connection terminals (115, 116). A plurality of first internal connection terminals (111, 112) and a plurality of second internal connection terminals (113, 114) are configured to connect internal components in wafers, passive components or other semiconductor devices, while external connection terminals (115 , 116) is configured for connecting external signals. In other words, the external connection terminals (115, 116) are the input/output (Input/Output) terminals of the silicon carbide circuit board 10. In some embodiments, the external connection terminals (115, 116) are larger in size than the first internal connection terminals (111, 112) and the second internal connection terminals (113, 114).

In this embodiment, the first internal connection terminals (111, 112), the plurality of second internal connection terminals (113, 114) and the plurality of external connection terminals (115, 116) are connected to each other through corresponding wirings 117 And electrical connection. For example, the first internal connection terminal 111 is electrically connected to the external connection terminal 115, the first internal connection terminal 112 is electrically connected to the second internal connection terminal 113, and the second internal connection terminal 114 is electrically connected to the external connection terminal. 116. In this embodiment, the first internal connection terminals (111, 112), the second internal connection terminals (113, 114), the external connection terminals (115, 116) and the traces 117 belong to the same layer. Specifically, the method of forming the first internal connection terminals (111, 112), the second internal connection terminals (113, 114), the external connection terminals (115, 116) and the traces 117 includes depositing on the silicon carbide circuit board 10 The first metal layer is then patterned to form a first metal circuit layer, where the first metal circuit layer includes first internal connection terminals (111, 112), second internal connection terminals (113, 114), External connection terminals (115, 116) and wiring 117. However, in other embodiments, the circuit structure CS may include more than one metal circuit layer, and different metal circuit layers are separated from each other by insulating layers.

In this embodiment, the circuit structure CS also includes a protective layer 120 (not shown in FIG. 2A ). The protective layer 120 is, for example, a primer layer, and is used to protect the traces 117 in the circuit structure CS. The protective layer 120 exposes the first internal connection terminals (111, 112), the second internal connection terminals (113, 114), and the external connection terminals (115, 116).

It should be noted that in FIGS. 2A and 2B , the circuit layout in the circuit structure CS is only for illustration, and the circuit layout in the circuit structure CS can be adjusted according to actual needs. In other words, the number and position of the first internal connection terminals (111, 112), the second internal connection terminals (113, 114), the external connection terminals (115, 116) and the traces 117 can be adjusted according to actual needs.

3A to 3C are schematic cross-sectional views of a method for manufacturing a gallium nitride device according to an embodiment of the present invention.

Referring to Figure 3A, a sapphire wafer 200 is provided.

Referring to FIG. 3B , a gallium nitride device layer 210 is formed on the sapphire wafer 200 . For example, the gallium nitride device layer 210 includes a channel layer 211, a first semiconductor layer 212, a passivation layer 213, a plurality of gate electrodes 214 and a plurality of source/drain electrodes 215.

In this embodiment, the channel layer 211 directly contacts the sapphire wafer 200, but the invention is not limited thereto. In other embodiments, other intermediate layers are sandwiched between the channel layer 211 and the sapphire wafer 200 . In one embodiment, the material of the channel layer 211 includes a III-V semiconductor material, which may be, for example, doped or non-doped GaN.

The first semiconductor layer 212 is located on the channel layer 211. The material of the first semiconductor layer 212 may be, for example, doped or non-doped AlGaN. For example, the material of the first semiconductor layer 212 includes n-AlGaN. The channel layer 211 may form a heterojunction with the first semiconductor layer 212 , so that a two-dimensional electron gas (2DEG) with high electron mobility is formed in a region of the channel layer 211 close to the first semiconductor layer 212 .

A plurality of gates 214 are located above the first semiconductor layer 212 . In this embodiment, the gate 214 directly contacts the first semiconductor layer 212, but the invention is not limited thereto. In other embodiments, p-GaN (not shown) is sandwiched between the gate 214 and the first semiconductor layer 212 .

The passivation layer 213 is located above the gate 214 and the first semiconductor layer 212 . The plurality of source/drain electrodes 215 penetrates the passivation layer 213 and contacts the first semiconductor layer 212 . The source/drain 215 selectively penetrates the first semiconductor layer 212 and contacts the two-dimensional electron gas in the channel layer 211 .

In this embodiment, the gallium nitride element layer 210 has multiple gallium nitride elements 2101 , and each gallium nitride element 2101 includes a corresponding channel layer 2111 , a corresponding first semiconductor layer 2121 , and a corresponding passivation layer 2131 , the corresponding gate 214 and the corresponding source/drain 215.

A first redistribution layer 220 is formed on the gallium nitride device layer 210 . The first redistribution layer 220 includes a dielectric structure 222 and a circuit structure 221 embedded in the dielectric structure 222 . In this embodiment, each of the circuit structure 221 and the dielectric structure 222 may include a single-layer or multi-layer structure. When the circuit structure 221 includes a multi-layer structure, the circuit structures 221 between different layers are electrically connected through conductive holes.

Please continue to refer to FIG. 3B , a plurality of connection terminals 230 are selectively formed on the first redistribution layer 220 . The connection terminal 230 is electrically connected to the gate 214 and the source/drain 215 in the gallium nitride device layer 210 through the first redistribution layer 220 . The connection terminals 230 include, for example, tin, conductive glue, or other similar structures.

Referring to FIG. 3C , the sapphire wafer 200 is cut to form a plurality of gallium nitride devices 20 . Each GaN device 20 includes a sapphire substrate 2001, a first redistribution structure 2201, and a GaN element 2101. In some embodiments, each gallium nitride device 20 optionally further includes connection terminals 230 on the first redistribution structure 2201 .

In this embodiment, the lattice matching between the gallium nitride and the sapphire substrate 2001 is good, and the sapphire substrate 2001 is not easy to generate parasitic channels during the manufacturing process. Therefore, the gallium nitride device 20 with better performance can be obtained.

4A to 4C are schematic cross-sectional views of a manufacturing method of a silicon integrated circuit device according to an embodiment of the present invention.

Referring to Figure 4A, a silicon wafer 300 is provided. The silicon wafer 300 includes, for example, doped or undoped bulk silicon or semiconductor on insulator (SOI), where the semiconductor on insulator includes an insulating layer and a silicon layer formed on the insulating layer.

Referring to FIG. 4B , a field effect transistor element layer 310 is formed on the silicon wafer 300 . In FIG. 4B , the field effect transistor element 311 in the field effect transistor element layer 310 is illustrated by a dotted box, and the specific structure of the field effect transistor element 311 is omitted. The field effect transistor element layer 310 may include multiple layers of semiconductor elements and multiple layers of interconnect layers. For example, the field effect transistor element layer 310 may include semiconductor elements manufactured in a front-end-of-line (FEOL) process and semiconductor elements manufactured in a back-end-of-line (BEOL) process. Semiconductor components. Semiconductor components can be electrically connected to each other through interconnect layers.

A second redistribution layer 320 is formed on the field effect transistor element layer 310 . The second redistribution layer 320 includes a dielectric structure 322 and a circuit structure 321 embedded in the dielectric structure 322 . In this embodiment, each of the circuit structure 321 and the dielectric structure 322 may include a single-layer or multi-layer structure. When the circuit structure 321 includes a multi-layer structure, the circuit structures 321 between different layers are electrically connected through conductive holes.

Please continue to refer to FIG. 4B , a plurality of connection terminals 330 are selectively formed on the second redistribution layer 320 . The connection terminal 330 is electrically connected to the field effect transistor element 311 in the field effect transistor element layer 310 through the second redistribution layer 320 . The connection terminal 330 includes, for example, tin, conductive glue, or other similar structures.

Referring to FIG. 4C , the silicon wafer 300 is cut to form a plurality of silicon integrated circuit devices 30 . Each silicon integrated circuit device 30 includes a silicon substrate 3001, a second rewiring structure 3201 and a field effect transistor element 311. In this embodiment, the cut field effect transistor element layer 3101 includes a plurality of field effect transistor elements 311 , and each silicon integrated circuit device 30 includes a plurality of field effect transistor elements 311 . In some embodiments, each silicon semiconductor circuit device 30 optionally further includes connection terminals 330 on the second redistribution structure 3201 .

In this embodiment, the silicon wafer is used to manufacture the field effect transistor element, which has the advantages of mature yellow light process technology, high production yield, and low cost.

5A to 7A are schematic top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 5B to 7B are schematic cross-sectional views along line a-a’ of FIGS. 7A to 7A respectively.

Referring to FIGS. 5A and 5B , at least one gallium nitride device 20 is electrically connected to the first internal connection terminals ( 111 , 112 ) of the silicon carbide circuit board 10 . Specifically, the gallium nitride device 20 is connected to the first internal connection terminals (111, 112) of the silicon carbide circuit board 10 through the connection terminals 230. In this embodiment, the manufacturing method of the gallium nitride device 20 is as shown in FIGS. 3A to 3C , but the invention is not limited thereto. In other embodiments, other methods may be used to fabricate the gallium nitride device 20 .

At least one silicon integrated circuit device 30 is electrically connected to the second internal connection terminals (113, 114) of the silicon carbide circuit board 10. Specifically, the silicon integrated circuit device 30 is connected to the second internal connection terminals (113, 114) of the silicon carbide circuit board 10 through the connection terminals 330. In this embodiment, the manufacturing method of the silicon integrated circuit device 30 is as shown in FIGS. 4A to 4C , but the invention is not limited thereto. In other embodiments, other methods may be used to manufacture the silicon semiconductor circuit device 30 .

In this embodiment, the gallium nitride device 20 and the silicon integrated circuit device 30 are bonded (eg, welded or eutectic bonded) to the silicon carbide circuit board 10 in an inverted manner. The gallium nitride element 2101 is located between the sapphire substrate 2001 and the silicon carbide substrate 100 , and the field effect transistor element 311 is located between the silicon substrate 3001 and the silicon carbide substrate 100 . The gallium nitride device 20 and the silicon integrated circuit device 30 can be electrically connected to each other through the circuit structure CS on the silicon carbide circuit board 10 . In this embodiment, the gallium nitride element 2101 in the gallium nitride device 20 includes a high electron mobility crystal transistor, and the high electron mobility crystal transistor passes through the first rewiring structure 2201, the circuit structure CS and the third The double wiring structure 3201 is electrically connected to the field effect transistor element 311 of the silicon integrated circuit device 30 . In some embodiments, the silicon semiconductor circuit device 30 is a driving component, such as a power chip.

In this embodiment, since the circuit structure CS that electrically connects the gallium nitride device 20 and the silicon integrated circuit device 30 is directly formed on the silicon carbide substrate 100 with a high resistance value (for example, greater than 5000 ohm-cm), therefore Compared with using jumpers to connect the gallium nitride device 20 and the silicon integrated circuit device 30, this embodiment can improve the metal trace breakage and parasitic generation between the gallium nitride device 20 and the silicon integrated circuit device 30. Problems with resistance and parasitic inductance.

Referring to FIGS. 6A and 6B , a packaging material 400 is formed above the silicon carbide substrate 100 to cover the sapphire substrate 2001 and the silicon substrate 3001 . In this embodiment, the packaging material 400 laterally covers the gallium nitride device 20 and the silicon integrated circuit device 30 . In this embodiment, the packaging material 400 covers the top surface of the sapphire substrate 2001 and the top surface of the silicon substrate 3001 .

In this embodiment, the packaging material 400 is filled between the gallium nitride device 20 and the silicon carbide circuit board 10 and between the silicon integrated circuit device 30 and the silicon carbide circuit board 10 , and laterally covers the connection terminals 230 and the connections. Terminal 330, but the present invention is not limited to this. In other embodiments, other underfill materials (Underfill) are first formed to cover the connection terminals 230 and 330 , and then the packaging material 400 is formed above the silicon carbide circuit board 10 .

Referring to FIGS. 7A and 7B , the packaging material 400 , the sapphire substrate 2001 of the gallium nitride device 20 and the silicon substrate 3001 of the silicon integrated circuit device 30 are simultaneously ground to reduce the thickness of the gallium nitride device 20 and the silicon integrated circuit. The thickness of the device 30 is improved, and the heat dissipation problem of the gallium nitride device 20 and the silicon integrated circuit device 30 is improved. In this embodiment, the top surface 2001t of the sapphire substrate 2001 is coplanar with the top surface 3001t of the silicon substrate 3001.

8A to 9A are schematic top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8B to 9B are schematic cross-sectional views along line a-a' of FIGS. 8A to 9A respectively. It must be noted here that the embodiment of FIGS. 8A to 9A follows the component numbers and part of the content of the embodiment of FIGS. 5A to 7A , where the same or similar numbers are used to represent the same or similar elements, and the same or similar elements are omitted. Description of technical content. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIGS. 8A and 8B . In this embodiment, before electrically connecting the gallium nitride device 20 to the first internal connection terminals ( 111 , 112 ) of the silicon carbide circuit board 10 , the gallium nitride device 20 is ground. The sapphire substrate 2001 may be a sapphire wafer used to prepare the gallium nitride device 20 . In other words, the ground and thinned gallium nitride device 20 is directly connected to the first internal connection terminals (111, 112) of the silicon carbide circuit board 10 through the connection terminals 230.

In this embodiment, before electrically connecting the silicon integrated circuit device 30 to the second internal connection terminals (113, 114) of the silicon carbide circuit board 10, the silicon substrate 3001 of the silicon integrated circuit device 30 is ground or used. A silicon wafer for the silicon integrated circuit device 30 is prepared. In other words, the ground and thinned silicon integrated circuit device 30 is directly connected to the second internal connection terminals (113, 114) of the silicon carbide circuit board 10 through the connection terminals 330.

In this embodiment, since the grinding process is performed first, and then the gallium nitride device 20 and the silicon integrated circuit device 30 are electrically connected to the silicon carbide circuit board 10, the impact of the stress generated by the grinding process on the nitride circuit board 10 can be improved. The negative impact caused by the contact between the gallium device 20 and the silicon carbide circuit board 10 or the contact between the silicon integrated circuit device 30 and the silicon carbide circuit board 10 . In this embodiment, the top surface 2001t of the sapphire substrate 2001 and the top surface 3001t of the silicon substrate 3001 may or may not be coplanar.

Referring to FIGS. 9A and 9B , a packaging material 400 is formed above the silicon carbide substrate 100 to cover the sapphire substrate 2001 and the silicon substrate 3001 . In this embodiment, the packaging material 400 laterally covers the gallium nitride device 20 and the silicon integrated circuit device 30 . In this embodiment, the packaging material 400 covers the top surface 2001t of the sapphire substrate 2001 and the top surface 3001t of the silicon substrate 3001.

In this embodiment, the packaging material 400 is filled between the gallium nitride device 20 and the silicon carbide circuit board 10 and between the silicon integrated circuit device 30 and the silicon carbide circuit board 10 , and laterally covers the connection terminals 230 and the connections. Terminal 330, but the present invention is not limited to this. In other embodiments, other underfill materials are first formed to cover the connection terminals 230 and 330 , and then the encapsulation material 400 is formed above the silicon carbide circuit board 10 .

10 to 11 are schematic top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Please refer to FIG. 10. In this embodiment, multiple circuit structures are formed above the silicon carbide substrate 100a, where the silicon carbide substrate 100a is a silicon carbide wafer. In this embodiment, the specific structure and description of each circuit structure can be referred to the embodiments of FIG. 1A to FIG. 2A , and will not be described again.

Then, the plurality of gallium nitride devices 20 are electrically connected to the first internal connection terminals of the circuit structure, and the plurality of silicon integrated circuit devices 30 are electrically connected to the second internal connection terminals of the circuit structure. In this embodiment, the gallium nitride device 20 and the silicon integrated circuit device 30 are transferred to the silicon carbide substrate 100 a by, for example, mass transfer technology.

Next, referring to FIG. 11 , a cutting process is performed on the silicon carbide substrate 100 a to form a plurality of silicon carbide circuit boards 10 . Each silicon carbide circuit board 10 is provided with a corresponding gallium nitride device 20 and a corresponding silicon integrated circuit device 30 .

In some embodiments, before performing the cutting process, the gallium nitride device 20 and the silicon integrated circuit device 30 are packaged on the silicon carbide substrate 100a with a packaging material (not shown in FIGS. 10 and 11 ), thereby avoiding The cutting process causes damage to the gallium nitride device 20 and the silicon integrated circuit device 30 . In addition, in some embodiments, before performing the cutting process, a grinding process is performed on the gallium nitride device 20 and the silicon integrated circuit device 30 to reduce the thickness of the gallium nitride device 20 and the silicon integrated circuit device 30 .

FIG. 12 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. FIG. 12 is, for example, a circuit diagram of a semiconductor device according to any of the aforementioned embodiments.

Referring to FIG. 12 , the semiconductor device includes a silicon integrated circuit device 30 and a gallium nitride device 20 . The external connection terminals (115a, 115b) of the semiconductor device are input terminals and are connected to the silicon integrated circuit device 30. The external connection terminals (116a, 116b) of the semiconductor device are output terminals and are connected to the gallium nitride device 20. The gallium nitride device 20 is a high electron mobility transistor, and the silicon integrated circuit device 30 can be used as a driving device to control the potential of the gate of the gallium nitride device 20 .

If the silicon integrated circuit device 30 and the gallium nitride device 20 are fabricated on the same wafer, the production cost will be high and the production yield will be poor due to the complicated manufacturing process. The silicon integrated circuit device 30 and the gallium nitride device 20 in this embodiment are manufactured separately on different wafers, and are electrically connected to each other through the silicon carbide circuit board and the circuit above it, thereby reducing production costs and and improve production yield.

10: Silicon carbide circuit board 20:GaN device 30:Silicon integrated circuit device 100,100a: Silicon carbide substrate 111,112: First internal connection terminal 113,114: Second internal connection terminal 115,116: External connection terminals 117: Routing 120:Protective layer 200: Sapphire wafer 2001: Sapphire substrate 2001t, 3001t: top surface 210:GaN component layer 2101:GaN components 211,2111: Channel layer 212,2121: first semiconductor layer 213,2131: Passivation layer 214: Gate 215: Source/Drain 220: First rewiring layer 2201: First rewiring structure 221: Line structure 222:Dielectric structure 230:Connection terminal 300:Silicon wafer 3001:Silicon substrate 310: Field effect transistor element layer 3101: Cut field effect transistor element layer 311: Field effect transistor element 320: Second rewiring layer 3201: Second rewiring structure 321: Line structure 322:Dielectric structure 330:Connection terminal 400:Packaging materials CS:Circuit structure

1A to 2A are schematic top views of a method for manufacturing a silicon carbide circuit board according to an embodiment of the present invention. 1B to 2B are schematic cross-sectional views along line a-a’ of FIGS. 1A to 2A respectively. 3A to 3C are schematic cross-sectional views of a method for manufacturing a gallium nitride device according to an embodiment of the present invention. 4A to 4C are schematic cross-sectional views of a manufacturing method of a silicon integrated circuit device according to an embodiment of the present invention. 5A to 7A are schematic top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 5B to 7B are schematic cross-sectional views along line a-a’ of FIGS. 7A to 7A respectively. 8A to 9A are schematic top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8B to 9B are schematic cross-sectional views along line a-a' of FIGS. 8A to 9A respectively. 10 to 11 are schematic top views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 12 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

10: Silicon carbide circuit board

20:GaN device

30:Silicon integrated circuit device

100: Silicon carbide substrate

2001: Sapphire substrate

2001t, 3001t: top surface

2101:GaN components

2201: First rewiring structure

230:Connection terminal

3001:Silicon substrate

3101: Cut field effect transistor element layer

311: Field effect transistor element

3201: Second rewiring structure

330:Connection terminal

400:Packaging materials

Claims (11)

A semiconductor device including: Silicon carbide circuit boards, including: Silicon carbide substrate; and a circuit structure located above the silicon carbide substrate and including a plurality of first internal connection terminals, a plurality of second internal connection terminals and a plurality of external connection terminals, wherein the external connection terminals are configured to connect external signals; Gallium nitride devices, including: sapphire base; a gallium nitride component located on the sapphire substrate; and A first redistribution structure is located on the gallium nitride component and is electrically connected to the first internal connection terminal; and Silicon integrated circuit devices, including: silicon substrate; A field effect transistor element located on the silicon substrate; and A second rewiring structure is located on the field effect transistor element and is electrically connected to the second internal connection terminal. The semiconductor device of claim 1, wherein the gallium nitride element includes a high electron mobility crystal transistor, and the high electron mobility crystal transistor passes through the first rewiring structure, the circuit structure and The second redistribution structure is electrically connected to the field effect transistor element. The semiconductor device according to claim 1, wherein the gallium nitride element is located between the sapphire substrate and the silicon carbide substrate, and the field effect transistor element is located between the silicon substrate and the silicon carbide substrate. wherein the top surface of the sapphire substrate is coplanar with the top surface of the silicon substrate. The semiconductor device according to claim 1, wherein the silicon carbide substrate has a thickness of 200 microns to 700 microns. The semiconductor device according to claim 1, wherein the size of the external connection terminal is larger than the size of the first internal connection terminal and the size of the second internal connection terminal. A method of manufacturing a semiconductor device, including: A circuit structure is formed above the silicon carbide substrate, wherein the circuit structure includes a plurality of first internal connection terminals, a plurality of second internal connection terminals and a plurality of external connection terminals, wherein the external connection terminals are configured to connect external signal; Forming a gallium nitride device layer on the sapphire wafer; Forming a first redistribution layer on the gallium nitride component layer; cutting the sapphire wafer to form a plurality of gallium nitride devices, each of the gallium nitride devices including a sapphire substrate, a first redistribution structure, and a gallium nitride element; electrically connecting at least one of the gallium nitride devices to the first internal connection terminal; Forming a field effect transistor element layer on the silicon wafer; Forming a second rewiring layer on the field effect transistor element layer; dicing the silicon wafer to form a plurality of silicon integrated circuit devices, each of the silicon integrated circuit devices including a silicon substrate, a second redistribution structure, and a field effect transistor element; and At least one of the silicon integrated circuit devices is electrically connected to the second internal connection terminal. The manufacturing method of a semiconductor device as claimed in claim 6, further comprising: After electrically connecting at least one of the gallium nitride devices to the first internal connection terminals and after electrically connecting at least one of the silicon integrated circuit devices to the second internal connection terminals, grinding the The sapphire substrate and the silicon substrate. The manufacturing method of a semiconductor device as claimed in claim 6, further comprising: grinding the sapphire substrate or the sapphire wafer before electrically connecting at least one of the gallium nitride devices to the first internal connection terminal; and Before electrically connecting at least one of the silicon integrated circuit devices to the second internal connection terminal, the silicon substrate or the silicon wafer is ground. The manufacturing method of a semiconductor device as claimed in claim 6, further comprising: A packaging material is formed above the silicon carbide substrate to cover the sapphire substrate and the silicon substrate. The manufacturing method of a semiconductor device as claimed in claim 6, further comprising: Before forming a circuit structure on the silicon carbide substrate, the silicon carbide wafer is cut to form the silicon carbide substrate. The manufacturing method of a semiconductor device as claimed in claim 6, further comprising: After electrically connecting at least one of the gallium nitride devices to the first internal connection terminals and after electrically connecting at least one of the silicon semiconductor circuit devices to the second internal connection terminals, the The silicon carbide substrate performs a cutting process, wherein the silicon carbide substrate is a silicon carbide wafer.

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