TW202336751A - Memory device and method for manufacturing memory device - Google Patents

Abstract

According to one embodiment, a memory device includes a memory element provided above a substrate in a first direction perpendicular to a first surface of the substrate; a switching element provided between the substrate and the memory element; and a first layer provided between the memory element and the switching element. The first layer includes at least one selected from the group including boron, carbon, silicon, magnesium, aluminum, scandium, titanium, vanadium, gallium, germanium, yttrium, zirconium, niobium, molybdenum, palladium, silver, hafnium, tantalum, tungsten, iridium, and platinum. The first layer includes an air gap.

Description

Memory device and method of manufacturing memory device

Embodiments of the present invention relate to a memory device and a manufacturing method of the memory device.

There are known memory devices using variable resistance elements (such as magnetoresistance effect elements) as memory elements. In order to improve the characteristics of memory devices, research and development of various technologies related to memory devices are being promoted.

The problem to be solved by the present invention is to provide a memory device and a manufacturing method of the memory device that reduce defects of the memory device.

The memory device of the embodiment includes: a memory element disposed above the substrate in a first direction perpendicular to the first surface of the substrate; a switching element disposed between the substrate and the memory element; and 1 layer, which is disposed between the above-mentioned memory element and the above-mentioned switching element; and the above-mentioned first layer includes boron, carbon, silicon, magnesium, aluminum, scandium, titanium, vanadium, gallium, germanium, yttrium, zirconium, niobium , molybdenum, palladium, silver, hafnium, tantalum, tungsten, iridium and platinum, and the first layer includes an air gap.

Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, elements with the same function and composition are designated by the same symbols.

In the following embodiments, the same plural components (such as circuits, wirings, various voltages and signals, etc.) may be distinguished by numbers/English characters at the end of the reference symbols. When there is no need to distinguish the constituent elements that are marked with numbers/English reference symbols at the end for differentiation, the description (reference symbol) with the numbers/English reference symbols at the end omitted can be used.

[Embodiment] The memory device according to the embodiment will be described with reference to FIGS. 1 to 16 .

(1)Configuration example A structural example of the memory device according to the embodiment will be described with reference to FIGS. 1 to 7 .

(1-a) Overall composition FIG. 1 is a block diagram showing a structural example of the memory device 100 according to this embodiment.

As shown in FIG. 1 , the memory device 100 of this embodiment is connected to a device 900 external to the memory device 100 (hereinafter referred to as an external device).

The external device 900 sends the command CMD, the address ADR and the control signal CNT to the memory device 100 . Data DT is transmitted between the memory device 100 and the external device 900 . During the writing operation, the external device 900 sends the data written in the storage device 100 (hereinafter referred to as the writing data) to the storage device 100 . During the reading operation, the external device 900 receives the data read from the memory device 100 (hereinafter referred to as read data) from the memory device 100 .

The memory device 100 of this embodiment includes: a memory cell array 110, a column control circuit 120, a row control circuit 130, a writing circuit 140, a reading circuit 150, a voltage generating circuit 160, an input/output circuit 170 and a control circuit 180.

The memory cell array 110 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

Each of the plurality of memory cells MC is respectively paired with a plurality of columns and a plurality of rows in the memory cell array 110 . Each memory cell MC is connected to a corresponding one of the plurality of word lines WL. Each memory cell MC is connected to a corresponding one of the plurality of bit lines BL.

The column control circuit 120 is connected to the memory cell array 110 via the word line WL. The column control circuit 120 receives the column address (or the decoding result of the column address) of the memory cell array 110 in the address ADR. The column control circuit 120 controls a plurality of word lines WL based on the decoding result of the column address. Thereby, the column control circuit 120 sets each of the plurality of word lines WL (plural columns) to the selected state or the non-selected state. Hereinafter, the word lines WL set to the selected state are called selected word lines WL, and the word lines WL other than the selected word lines WL are called unselected word lines WL.

The row control circuit 130 is connected to the memory cell array 110 via the bit line BL. The row control circuit 130 receives the row address (or the decoding result of the row address) of the memory cell array 110 in the address ADR. The row control circuit 130 controls a plurality of bit lines BL based on the decoding result of the row address. Thereby, the row control circuit 130 sets each of the plurality of bit lines BL (plurality of rows) to the selected state or the non-selected state. Hereinafter, the bit lines BL set to the selected state are called selected bit lines BL, and the bit lines BL other than the selected bit lines BL are called non-selected bit lines BL.

The writing circuit 140 writes data into the memory cell MC. The write circuit 140 supplies voltage (or current) for writing data to each of the selected word line WL and the selected bit line BL. Thereby, a certain writing voltage (or writing current) is supplied to the selected memory cell MC. The writing circuit 140 may supply any one of the plurality of writing voltages corresponding to the writing data to the selected memory cell MC. For example, each of the plurality of write voltages (or write currents) has a polarity (bias direction) corresponding to the write data. For example, the write circuit 140 includes a write driver (not shown), a write slot (not shown), and the like.

The readout circuit 150 reads data from the memory cell MC. The readout circuit 150 amplifies the signal output from the selected memory cell MC to the selected bit line BL. The readout circuit 150 determines the data in the selected memory cell MC based on the amplified signal. For example, the readout circuit 150 includes a preamplifier (not shown), a sense amplifier (not shown), a readout driver (not shown), a readout slot (not shown), and the like.

The voltage generating circuit 160 uses the power supply voltage supplied from the external device 900 to generate voltages for various operations of the memory cell array 110 . For example, the voltage generation circuit 160 generates various voltages used in writing operations. The voltage generating circuit 160 outputs the generated voltage to the writing circuit 140 . For example, the voltage generation circuit 160 generates various voltages used in the readout operation. The voltage generation circuit 160 outputs the generated voltage to the readout circuit 150 .

The input/output circuit 170 functions as an interface circuit related to various signals between the memory device 100 and the external device 900, such as address ADR, command CMD, control signal CNT, and data DT. The input-output circuit 170 transmits the address ADR from the external device 900 to the control circuit 180 . The input/output circuit 170 transmits the command CMD from the external device 900 to the control circuit 180 . The input/output circuit 170 transmits various control signals CNT between the external device 900 and the control circuit 180 . The input/output circuit 170 transmits the write data DT from the external device 900 to the write circuit 140 . The input/output circuit 170 transmits the data from the readout circuit 150 to the external device 900 as readout data DT.

Control circuitry (also called a sequencer, state machine, or internal controller) 180 decodes the command CMD. The control circuit 180 controls the column control circuit 120 , the row control circuit 130 , the writing circuit 140 , the reading circuit 150 , the voltage generating circuit 160 and the input/output circuit 170 in the memory device 100 based on the decoding result of the command CMD and the control signal CNT. to control the action. For example, control circuit 180 may decode the address ADR. The control circuit 180 sends the decoding result of the address ADR to the column control circuit 120 and the row control circuit 130 and so on. For example, the control circuit 180 includes a register circuit (not shown) that temporarily stores the command CMD and the address ADR. Furthermore, the register circuit, the circuit for decoding the command CMD (command decoder), and the circuit for decoding the address ADR (address decoder) can also be provided in an external memory device of the control circuit 180 Within 100.

(1-b) Memory cell array Referring to FIGS. 2 to 5 , a structural example of the memory cell array 110 in the memory device 100 of this embodiment will be described.

FIG. 2 is an equivalent circuit diagram showing a structural example of the memory cell array 110 of the memory device 100 of this embodiment.

As shown in FIG. 2 , a plurality of memory cells MC are arranged in a matrix in the memory cell array 110 . Each memory cell MC corresponds to one of the plurality of bit lines BL (BL<0>, BL<1>,..., BL<i-1>), and the plurality of word lines WL (WL<0>, One connection corresponding to WL＜1＞,..., WL＜j-1＞). i and j are integers above 2.

Each memory cell MC includes a memory element 1 and a selector 2 .

The memory element 1 is, for example, a variable resistance element. The resistance state of the memory element 1 changes to any one of a plurality of resistance states (such as a low resistance state and a high resistance state) according to the supplied voltage (or current). The memory element 1 can store data by associating the resistance state of the element 1 with data (such as "0" data and "1" data).

The selector 2 functions as the selecting element of the memory cell MC. The selector 2 has the following function: when writing data into the corresponding memory element 1 and when reading data from the corresponding memory element 1, it controls the supply of voltage (or current) to the memory element 1.

For example, the selector 2 is a two-terminal switching element. Hereinafter, the selector 2 is referred to as the switching element 2 . When the voltage applied between the two terminals of the switching element 2 does not reach the threshold voltage of the switching element 2 , the switching element 2 changes to the off state (high resistance state, non-electrical conduction state). When the voltage applied between the two terminals of the switching element 2 is equal to or higher than the threshold voltage of the switching element 2 , the switching element 2 changes to the conductive state (low resistance state, electrical conduction state). Regardless of the polarity of the applied voltage (such as positive polarity and negative polarity), the two-terminal switching element 2 can have the above functions.

The switching element 2 can switch whether to flow current in the memory cell MC according to the magnitude of the voltage applied to the memory cell MC, regardless of the polarity of the voltage applied to the memory cell MC (the direction of the current flowing in the memory cell MC).

FIGS. 3 to 5 are diagrams for explaining a structural example of the memory cell array 110 of the memory device 100 according to this embodiment. FIG. 3 is a bird's-eye view illustrating a configuration example of the memory cell array 110. FIG. 4 is a schematic cross-sectional view showing the cross-sectional structure of the memory cell array 110 along the Y direction (Y-axis). FIG. 5 is a schematic cross-sectional view showing the cross-sectional structure of the memory cell array 110 along the X direction (X-axis).

As shown in FIGS. 3 to 5 , the memory cell array 110 is disposed above the upper surface of the substrate 80 .

The X direction is parallel to the upper surface of the substrate 80 . The Y direction is parallel to the upper surface of the substrate 80 and crosses the X direction. Hereinafter, the plane parallel to the upper surface of the substrate 80 will be referred to as the X-Y plane. Set the direction (axis) perpendicular to the X-Y plane as the Z direction (Z-axis). The plane parallel to the plane including the X direction and the Z direction is called the X-Z plane. The plane parallel to the plane including the Y direction and the Z direction is called the Y-Z plane.

A plurality of wirings (conductive layers) 50 are arranged above the upper surface of the substrate 80 through the insulating layer 81 on the substrate 80 in the Z direction. A plurality of wirings 50 are arranged in the X direction. Each wiring 50 extends in the Y direction. Each of the plurality of wirings 50 functions as a bit line BL, for example.

A plurality of wirings (conductive layers) 51 are provided above the plurality of wirings 50 in the Z direction. A plurality of wirings 51 are arranged in the Y direction. Each wiring 51 extends in the X direction. Each of the plurality of wirings 51 functions as a word line WL, for example.

A plurality of memory cells MC are disposed between a plurality of wirings 50 and a plurality of wirings 51 . A plurality of memory cells MC are arranged in a matrix in the X-Y plane.

A plurality of memory cells MC arranged in the Y direction are provided on one wiring 50 in the Z direction. A plurality of memory cells MC arranged in the Y direction are connected to a common bit line BL.

A plurality of memory cells MC arranged in the X direction are provided under one wiring 51 in the Z direction. A plurality of memory cells MC arranged in the X direction are connected to a common word line WL.

A space having a certain size (interval) in the Y direction is provided between the two memory cells MC arranged in the Y direction. A space having a certain size (interval) in the X direction is provided between the two memory cells MC arranged in the X direction. The distance between two memory cells MC in the Y direction is substantially the same as the distance between two memory cells MC in the X direction. However, the distance between the memory cells MC in the Y direction may also be different from the distance between the memory cells MC in the X direction.

An insulating layer (not shown) is disposed between the memory cells MC.

For example, when the memory cell array 110 has the circuit configuration of FIG. 2 , the switching element 2 (selector 2 ) is disposed below the memory element 1 in the Z direction. The switching element 2 is provided between the memory element 1 and the wiring 50 . The memory element 1 is provided between the wiring 51 and the switching element 2 .

In this way, each memory cell MC is a laminate of the memory element 1 and the switching element 2 . According to the memory cell MC, the memory cell array 110 has the structure of a stacked memory cell array.

Depending on the process (eg, etching method) used to form the memory cell array 110, the memory cell MC may have a tapered cross-sectional shape.

In FIGS. 4 and 5 , an example in which the insulating layer 81 is provided between a plurality of wirings 50 and the substrate 80 is shown. When the substrate 80 is a semiconductor substrate, one or more field effect transistors (not shown) may also be disposed on the semiconductor region on the upper surface of the substrate 80 . The field effect transistor is covered by an insulating layer 81 . The field effect transistor on the substrate 80 is a component of the column control circuit 120 and other circuits. The field effect transistor is connected to the memory cell array 110 through contact plugs (not shown) and wiring (not shown) in the insulating layer 81 . In this way, a circuit for controlling the operation of the memory cell array 110 may also be provided below the memory cell array 110 in the Z direction. Furthermore, if the substrate 80 is an insulating substrate, the plurality of wirings 50 can also be directly disposed on the upper surface of the substrate 80 without the insulating layer 81 .

The circuit structure and structure of the stacked memory cell array 110 are not limited to the examples shown in FIGS. 2 to 5 . The circuit structure and structure of the memory cell array 110 can be appropriately changed according to the connection relationship between the memory element 1 and the switching element 2 relative to the bit line BL and the word line WL. For example, the structure of the memory cell array 110 having the circuit structure of FIG. 2 is not limited to the examples of FIGS. 3 to 5 . For example, the switching element 2 can also be disposed above the memory element 1 in the Z direction. In this case, the wiring 51 can be used as the bit line BL, and the wiring 50 can be used as the word line WL.

Furthermore, in FIGS. 3 to 5 , an example in which the memory cell MC has a angular prism structure is shown, but the memory cell MC may also have a cylindrical (or elliptical cylindrical) structure.

(1-c) Memory cell FIG. 6 is a cross-sectional view schematically showing a structural example of memory cells MC in the memory device 100 according to this embodiment.

As shown in FIG. 6 , in the memory cell MC of the laminated body 90 , the memory element 1 and the switching element 2 are arranged in the Z direction. As described above, the memory element 1 is provided on the switching element 2 in the Z direction.

For example, the variable resistance element as the memory element 1 is a magnetoresistance effect element. In this case, the memory device 100 of this embodiment is a magnetic memory such as MRAM (Magnetoresistive random access memory).

＜Configuration example of switching element＞ As shown in FIG. 6 , the switching element 2 includes at least a variable resistance layer (also called a selector layer or a switching layer) 20 and two electrodes (conductive layers) 21A and 21B. The variable resistance layer 20 is provided between the two electrodes 21A and 21B in the Z direction. The resistance state (resistance value) of the variable resistance layer 20 changes. The variable resistance layer 20 may have a plurality of resistance states.

In the example of FIG. 6 , electrode (hereinafter, also referred to as lower electrode) 21A is provided below the variable resistance layer 20 in the Z direction, and electrode (hereinafter, also referred to as upper electrode) 21B is provided below the variable resistance layer 20 in the Z direction. above the variable resistance layer 20 . For example, electrode 21A is provided between wiring 50 and variable resistance layer 20 . The electrode 21B is provided between the variable resistance layer 20 and the magnetoresistive effect element 1 .

The switching element 2 is connected to the wiring 50 via the electrode 21A. The switching element 2 is connected to the magnetoresistive effect element 1 via the electrode 21B.

The switching element 2 has a dimension T2 in a direction perpendicular to the surface of the substrate 80 (for example, the Z direction). The switching element 2 has a dimension D2 in a direction parallel to the surface of the substrate 80 (for example, the X direction or the Y direction).

Depending on the voltage applied to the switching element 2 (memory cell MC), the resistance state of the variable resistance layer 20 becomes a high resistance state (non-conducting state) or a low resistance state (conducting state). When the resistance state of the variable resistance layer 20 is a high resistance state, the switching element 2 is turned off. When the resistance state of the variable resistance layer 20 is a low resistance state, the switching element 2 is turned on.

When the memory cell MC is set to the selected state, the switching element 2 is turned on, so the resistance state of the variable resistance layer 20 becomes a low resistance state. In this case, the switching element 2 supplies voltage (or current) to the memory element 1 . When the memory cell MC is set to the non-selected state, the switching element 2 is turned off, so the resistance state of the variable resistance layer 20 becomes a high resistance state. In this case, the switching element 2 cuts off the voltage (or current) supply to the memory element 1 .

Furthermore, depending on the material of the variable resistance layer 20, the change in the resistance state of the variable resistance layer 20 may also depend on the current flowing in the switching element 2 (memory cell MC) (eg, the magnitude of the current).

The variable resistance layer 20 of the switching element 2 includes a material selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), and tin (Sn). ), at least one element from the group consisting of arsenic (As), phosphorus (P) and antimony (Sb).

For example, the switching element 2 may include an insulator containing a dopant (impurity) in the variable resistance layer 20 . Dopants added to insulators are impurities that help conduct electricity within the insulator. An example of the insulator used in the variable resistance layer 20 of the switching element 2 is silicon oxide. When the material of the variable resistance layer 20 is silicon oxide, the dopant added to the silicon oxide is phosphorus or arsenic. Furthermore, the type of dopant added to the silicon oxide of the variable resistance layer 20 is not limited to the above example.

<Configuration example of magnetoresistance effect element> As shown in FIG. 6 , the magnetoresistive effect element 1 includes two magnetic layers 11 and 13 and a nonmagnetic layer 12 . The nonmagnetic layer 12 is provided between the two magnetic layers 11 and 13 in the Z direction. In the example of FIG. 6 , the plurality of layers 11 , 12 , and 13 are arranged from the wiring (eg, bit line BL) 50 side toward the wiring (eg, word line WL) 51 side according to the order of the magnetic layer 11 , the nonmagnetic layer 12 and the magnetic layer 13 . Arranged in order in the Z direction.

The two magnetic layers 11 and 13 and the non-magnetic layer 12 form a magnetic tunnel junction. Hereinafter, the magnetoresistance effect element 1 including the magnetic tunnel junction will be referred to as the MTJ element 1 . The non-magnetic layer 12 in the MTJ element 1 is called a tunnel barrier layer.

The magnetic layers 11 and 13 are, for example, ferromagnetic layers containing at least one element among cobalt (Co), iron (Fe), and nickel (Ni). Moreover, the magnetic layers 11 and 13 may further contain boron (B). More specifically, for example, the magnetic layers 11 and 13 contain cobalt iron boron (CoFeB) or iron boride (FeB). The magnetic layers 11 and 13 may be single-layer films (such as alloy films) or multi-layer films (such as artificial lattice films). The tunnel barrier layer 12 is, for example, an insulating layer (such as a magnesium oxide layer) containing oxygen (O) and magnesium (Mg). The tunnel barrier layer 12 may be a single-layer film or a multi-layer film. Furthermore, the tunnel barrier layer 12 may further include elements other than oxygen and magnesium.

In this embodiment, the MTJ element 1 is a perpendicular magnetization type magnetoresistance effect element.

For example, each of the magnetic layers 11 and 13 has perpendicular magnetic anisotropy. The direction of the easy magnetization axis of each magnetic layer 11, 13 is perpendicular to the layer (film surface) of the magnetic layer 11, 13. Each magnetic layer 11, 13 has magnetization perpendicular to the plane of the magnetic layer 11, 13. The direction of magnetization of each magnetic layer 11 and 13 is parallel to the arrangement direction (Z direction) of the magnetic layers 11 and 13 .

Among the two magnetic layers 11 and 13, the magnetization direction of one magnetic layer is variable, and the magnetization direction of the other magnetic layer is constant. According to the relative relationship between the magnetization direction of one magnetic layer and the magnetization direction of another magnetic layer (magnetization arrangement), the MTJ element 1 can have a plurality of resistance states (resistance values).

In the example of FIG. 6 , the magnetization direction of the magnetic layer 13 is variable. The magnetization direction of the magnetic layer 11 does not change (fixed state). Hereinafter, the magnetic layer 13 with variable magnetization direction is called a memory layer. Hereinafter, the magnetic layer 11 with a constant magnetization direction is called a reference layer. Furthermore, the memory layer 13 is sometimes also called a free layer, a magnetization free layer, or a magnetization variable layer. The reference layer 11 is sometimes also called a plug layer, a pinned layer, a magnetization-invariant layer, or a magnetization-pinned layer.

In this embodiment, "the magnetization direction of the reference layer (magnetic layer) remains unchanged" or "the magnetization direction of the reference layer (magnetic layer) is in a fixed state" means: when supplying the memory layer 13 to the MTJ element 1 In the case of current or voltage in the magnetization direction, before and after supplying current or voltage, the magnetization direction of the reference layer 11 will not change due to the supplied current or voltage.

When the magnetization direction of the memory layer 13 is the same as the magnetization direction of the reference layer 11 (when the magnetization arrangement state of the MTJ element 1 is a parallel arrangement state), the resistance state of the MTJ element 1 is the first resistance state. When the magnetization direction of the memory layer 13 is different from the magnetization direction of the reference layer 11 (when the magnetization arrangement state of the MTJ element 1 is an anti-parallel arrangement state), the resistance state of the MTJ element 1 is different from the first resistance state. 2nd resistance state. For example, the resistance value of the MTJ element 1 in the second resistance state (anti-parallel arrangement state) is higher than the resistance value of the MTJ element 1 in the first resistance state (parallel arrangement state).

Hereinafter, regarding the magnetization arrangement state of the MTJ element 1, the parallel arrangement state is also referred to as the P (Parallel, parallel) state, and the anti-parallel arrangement state is also referred to as AP (Anti-Parallel, anti-parallel).

Furthermore, depending on the circuit structure of the memory cell array 110, there are also situations where the reference layer is disposed above the tunnel barrier layer 12 in the Z direction, and the memory layer is disposed below the tunnel barrier layer 12 in the Z direction.

For example, the MTJ element 1 includes conductive layers (electrodes) 18A and 18B. The magnetic layers 11 and 13 and the tunnel barrier layer 12 are provided between the two conductive layers 18A and 18B in the Z direction. The reference layer 11 is provided between the conductive layer 18A and the tunnel barrier layer 12 . The memory layer 13 is disposed between the conductive layer 18B and the tunnel barrier layer 12 .

For example, the offset elimination layer 14 can also be disposed in the MTJ element 1 . In this case, the offset cancellation layer 14 is disposed between the reference layer 11 and the conductive layer 18A. The offset elimination layer 14 is a magnetic layer used to reduce the influence of the leakage magnetic field of the reference layer 11 . When the MTJ element 1 includes the offset cancellation layer 14 , the nonmagnetic layer 15 is disposed between the offset cancellation layer 14 and the reference layer 11 . The nonmagnetic layer 15 is, for example, a metal layer such as a ruthenium layer. The offset cancellation layer 14 is antiferromagnetically coupled to the reference layer 11 via the non-magnetic layer 15 . Thereby, the laminate including the reference layer 11 and the offset cancellation layer 14 forms a SAF (Synthetic antiferromagnetic, synthetic antiferromagnetic) structure. In the SAF structure, the magnetization direction of the offset cancellation layer 14 is opposite to the magnetization direction of the reference layer 11 . Through the SAF structure, the magnetization direction of the reference layer 11 can be fixed in a more stable state. Furthermore, the set of the two magnetic layers 11 and 14 and the non-magnetic layer 15 forming the SAF structure is sometimes called a reference layer.

For example, a non-magnetic layer (not shown) called a base layer may also be provided between the offset elimination layer 14 and the conductive layer 18A. The base layer is a layer used to improve the characteristics (such as crystallinity and magnetic characteristics) of the magnetic layer (here, the offset elimination layer 14) connected to the base layer.

For example, a non-magnetic layer (not shown) called a cap layer may also be disposed between the memory layer 13 and the conductive layer 18B. The cap layer is a layer used to improve the characteristics (such as crystallinity and magnetic properties) of the magnetic layer (here, the memory layer 13) connected to the cap layer.

The MTJ element 1 has a dimension T1 in the Z direction. For example, size T1 is larger than size T2. However, depending on the structure of the memory element 1, the size T1 may be smaller than the size T2.

The MTJ element 1 has a tapered cross-sectional structure. Regarding the dimensions D1a and D1b of the tapered MTJ element 1 in the direction parallel to the surface of the substrate 80 (X direction or Y direction), the dimension D1b of the lower side (wiring 50 side) of the MTJ element 1 is larger than that of the MTJ element 1 Dimension D1a on the upper side (wiring 51 side).

The taper angle of the upper side of the MTJ element 1 may also be different from the taper angle of the lower side of the MTJ element 1 . For example, the taper angle on the upper side of the MTJ element 1 (eg, the portion above the tunnel barrier layer 12 ) is greater than the taper angle on the lower side of the MTJ element 1 (eg, the portion below the tunnel barrier layer 12 ). Furthermore, in this embodiment, the taper angle of the MTJ element 1 is the angle formed by the side surface of a certain part of the MTJ element 1 and a direction parallel to the upper surface of the substrate 80 .

The conductive layer 19 is provided between the MTJ element 1 and the wiring 51 . The wiring 51 is electrically connected to the electrode 18B of the MTJ element 1 via the conductive layer 19 . The conductive layer 19 is, for example, a tungsten layer or a molybdenum layer. The conductive layer 19 is used, for example, as a mask layer (hard mask) for etching when forming the memory cell MC. Hereinafter, the conductive layer 19 may also be referred to as the mask layer 19 .

Furthermore, when the conductive layer 19 is used as an electrode of the MTJ element 1, the conductive layer 18B does not need to be provided.

The conductive layer 19 has a dimension Tx in a direction perpendicular to the surface of the substrate 80 (here, the Z direction). Dimension Tx is smaller than dimension T1. The size of a certain part of the conductive layer 19 (for example, the bottom of the conductive layer 19) in a direction parallel to the surface of the substrate 80 (X direction or Y direction) is, for example, substantially the same size as the size D1a.

In the memory device 100 of this embodiment, the memory cell MC includes an intermediate layer 30 between the MTJ element 1 and the switching element 2 .

The intermediate layer 30 contains a material selected from the group consisting of boron (B), carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), and gallium (Ga). , germanium (Ge), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), hafnium (Hf), tantalum (Ta), tungsten (W) , at least 1 component of iridium (Ir) and platinum (Pt).

The middle layer 30 is, for example, a layer including components selected from the above-mentioned groups. The intermediate layer 30 may also be a compound layer of a selected component. Specific examples of the intermediate layer 30 are a silicon oxide layer or a silicon carbide layer. Furthermore, the intermediate layer 30 may also be a layer formed by adding at least one selected from the above groups to a certain base material. In this case, the intermediate layer 30 includes a plurality of granular portions in the base material, and the plurality of granular portions include components selected from the above group. For example, the middle layer 30 may also be an organic layer including components selected from the above groups.

The middle layer 30 includes a plurality of air gaps 39 inside the layer. As a more specific example, the intermediate layer 30 is a porous layer (also called a nanoporous layer).

The intermediate layer 30 has a dimension T3 in a direction perpendicular to the surface of the substrate 80 (herein, the Z direction). Size T3 is above size T1. Dimension T3 is larger than dimension Tx.

For example, the side surface of the intermediate layer 30 is substantially parallel to the Z direction, and is substantially perpendicular to the upper surface of the substrate 80 . In this case, the size of the lower part of the intermediate layer 30 (on the wiring 50 side) is substantially the same as the size of the upper part of the intermediate layer 30 (on the wiring 51 side). The intermediate layer 30 has a dimension D3 in a direction parallel to the upper surface of the substrate 80 (herein, the X direction or the Y direction). The size D3 of the intermediate layer 30 is smaller than the size D2 of the switching element 2 .

FIG. 7 is a schematic diagram showing an example of the structure of the intermediate layer 30 in the memory device 100 of this embodiment.

As shown in FIG. 7 , the intermediate layer 30 includes a plurality of granular portions 310 . The granular portion 310 includes the above-described B, C, Si, Mg, Al, Sc, Ti, V, Ga, Ge, Y, Zr, Nb, Mo, Pd, Ag, Hf, Ta, W, Ir, and Pt components. The granular portions 310 are irregularly arranged in the middle layer 30 .

The air gap 39 is provided in the space between the granular portions 310 . The air gap 39 may have a tunnel-like structure extending from one end of the middle layer 30 to the other end, or may have a structure of a closed space surrounded by a plurality of granular parts 310 inside the middle layer 30 .

The intermediate layer 30 may also include a granular portion 311 that includes components other than the components of the granular portion 310 . The granular portions 311 are irregularly provided in the intermediate layer 30 . The granular portion 311 is an insulator (such as silicon oxide or silicon nitride), a conductor, or an organic substance.

With the structure of FIG. 7 , the etching rate of the intermediate layer 30 is higher than the etching rate of the conductive layer 19 .

Furthermore, in FIG. 7 , in order to simplify the drawing, circular (spherical) granular portions 310 and 311 are shown, but the shapes of the granular portions 310 and 311 may also be other shapes (eg, polygonal).

Returning to FIG. 6 , the insulating layer 40 is continuously provided on the side of the conductive layer 19 , the side of the MTJ element 1 and the side of the intermediate layer 30 . The insulating layer 40 continuously covers the side surfaces of the conductive layer 19 , the side surfaces of the MTJ element 1 and the side surfaces of the intermediate layer 30 . The side surfaces of the conductive layer 19 , the side surfaces of the MTJ element 1 and the side surfaces of the intermediate layer 30 are surfaces intersecting with a direction parallel to the upper surface of the substrate 80 .

The insulating layer 40 contains oxide, nitride, oxynitride, or the like. The insulating layer 40 may be a single-layer film or a laminated film. For example, the insulating layer 40 is a silicon nitride film.

The insulating layer 40 has a film thickness Tq. The film thickness Tq of the insulating layer 40 is the size of the insulating layer 40 in a direction parallel to the upper surface of the substrate 80 (for example, the X direction or the Y direction). In this embodiment, the film thickness Tq of the insulating layer 40 is set to the thickness of the portion provided on the side surface of the intermediate layer 30 . For example, the value of twice the dimension D2 and the film thickness Tq is substantially equal to the total of the dimensions D3 (D3+2×Tq).

For example, the plug 55 is provided between the switching element 2 and the wiring 50 . The plug 55 is disposed in the insulating layer 60 . The insulating layer 60 is provided between the switching element 2 and the wiring 50 . The wiring 50 is electrically connected to the lower electrode 21A of the switching element 2 via the plug 55 . Furthermore, the plug 55 may not be provided, and the lower electrode 21A of the switching element 2 may be directly provided on the wiring 50 . In this case, the insulating layer 60 is not provided between the switching element 2 and the wiring 50 .

The insulating layer 61 covers the side surfaces of the memory cells MC. The insulating layer 61 is disposed between the memory cells MC.

In this embodiment, the etching rate of the intermediate layer 30 in the formation step of the memory cell MC is higher than the etching rate of other components of the memory cell MC (such as the magnetic layers 11 and 13 or the conductive layer 19 ). For example, in the formation step of the memory cell MC, the Z-direction dimension (>Tx) of the conductive layer 19 when deposited is larger than the Z-direction dimension (eg, dimension T3) of the intermediate layer 30 when deposited.

(2) Manufacturing method Referring to FIGS. 8 to 13 , a method of manufacturing the memory device 100 of this embodiment will be described.

8 to 13 are schematic cross-sectional step views showing the manufacturing steps of the manufacturing method of the memory device 100 according to this embodiment.

As shown in FIG. 8 , after circuits (not shown) of the memory device 100 such as column control circuits are formed on a substrate (semiconductor substrate) 80 , an insulating layer 81 is formed on the substrate 80 . The insulating layer 81 covers the circuit on the substrate 80 .

A plurality of conductive layers 50 are formed on the insulating layer 81 . The conductive layer 50 is a layer used to form wirings (eg, bit lines BL) of the memory cell array 110 . An insulating layer 60 is formed on the conductive layer 50 . A plurality of contact holes are formed in the insulating layer 60 at specific positions where the memory cells are arranged. A plurality of plugs 55 are formed in a plurality of contact holes in contact with the conductive layer 50 .

A laminated body 90Z is formed on the insulating layer 60 and the plug 55 . The laminated body 90Z includes a plurality of components of the memory cell MC.

For example, the member 2Z that is a component of the switching element 2 is formed on the insulating layer 60 and the plug 55 . The member 2Z includes at least a conductive layer as the lower electrode 21A, a layer as the variable resistance layer 20, a conductive layer as the upper electrode 21B, and the like that are laminated in the Z direction. The member 2Z has a dimension (thickness) T2 in the Z direction.

In this embodiment, the intermediate layer 30Z is formed on the member 2Z. The intermediate layer 30Z has a dimension (thickness) T3 in the Z direction.

The intermediate layer 30Z contains a material selected from the group consisting of boron (B), carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), and gallium (Ga). , germanium (Ge), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), hafnium (Hf), tantalum (Ta), tungsten (W) , iridium (Ir), platinum (Pt), etc.

The middle layer 30Z is a porous layer. That is, a plurality of air gaps 39 and a plurality of granular portions (not shown) are formed in the intermediate layer 30Z. For example, the air gap 39 in the intermediate layer 30Z is formed using known techniques that utilize corrosion or etching of a certain component.

The component 1Z of the memory element 1 is formed on the intermediate layer 30Z. When the memory element 1 is an MTJ element, the component 1Z at least includes: a magnetic layer as the reference layer 11 , a non-magnetic layer as the tunnel barrier layer 12 , a magnetic layer as the memory layer 13 , and Conductive layers of electrodes 18A and 18B, etc. The member 1Z may further include a magnetic layer as the offset cancellation layer 14, a non-magnetic layer between the reference layer 11 and the offset cancellation layer 14, or a base layer. The member 1Z has a dimension (thickness) T1 in the Z direction. For example, dimension T1 of member 1Z is substantially the same as dimension T3 of intermediate layer 30Z. However, the dimension T3 of the intermediate layer 30Z may also be larger than the dimension T1 of the component 1Z.

A plurality of mask layers 19Z are formed on the laminated body 90Z. Each mask layer 19Z is formed at the arrangement position of the memory cell MC by photolithography, etching, or the like. For example, a certain mask layer 19Z is arranged above a certain plug 55 in the Z direction.

The mask layer 19Z has a size (thickness) Tz in the Z direction. For example, the size Tz of the mask layer 19Z is larger than the size T3 of the intermediate layer 30Z. In this case, the size Tz of the mask layer 19Z is larger than the size T1 of the member 1Z.

As shown in FIG. 9 , the laminated body 90X is processed by ion beam etching. For example, the ion beam IB1 is incident on the laminated body 90X from a direction inclined at a certain angle relative to a direction parallel to (or perpendicular to) the upper surface of the substrate 80 .

The laminated body 90X is etched using the inclined ion beam IB1. Thereby, conductive scattering matter generated due to etching of a conductor such as a magnetic layer is suppressed from adhering to the exposed side surface of the member 1X. As a result, the short circuit between the magnetic layers 11 and 13 caused by the conductor (hereinafter referred to as conductive attachment) attached to the side surface of the member 1X is reduced.

The side surfaces of the etched member 1X are tilted relative to a direction parallel (or perpendicular) to the upper surface of the substrate 80 according to the etching rate of each layer constituting the member 1X (the incident angle of the ion beam IB1).

As a result, the member 1X has a tapered structure. Regarding the size of the member 1X in a direction parallel to the surface of the substrate 80 (for example, the Y direction), the size D2a of the lower portion of the member 1X (the portion on the substrate 80 side) is larger than the size D2a of the upper portion of the member 1X (the portion on the mask layer 19X side). Size D1a.

For example, the etching rates of a plurality of constituent components (layers) under certain etching conditions may vary from component to component. In order to suppress the adhesion of the above-mentioned scattered matter and remove the conductive adhesion matter, the incident angle of the ion beam IB1 when processing the lower side of the member 1X is different from the incident angle of the ion beam IB1 when processing the upper side of the member 1X. As a result, as shown in the example of FIG. 9 , the taper angle of the upper side of the member 1X may be different from the taper angle of the lower side of the member 1X.

As shown in Fig. 10, immediately following the formation of the member 1Y, the intermediate layer 30Y is processed. The intermediate layer 30Y is etched by ion beam etching under the same conditions as the etching of the member (MTJ element) 1Y. The processed component 1Y functions as an etching mask for the intermediate layer 30Y.

In this embodiment, a material whose etching rate is higher than the etching rate of the mask layer 19Y and the plurality of constituent components of the component 1Y is used for the intermediate layer 30Y. The material of the middle layer 30Y including the plurality of air gaps 39 is a material with a lower density than the material of the mask layer 19Y.

Thereby, the intermediate layer 30Y is etched at a faster etching speed than the mask layer 19Y.

As shown in FIG. 11 , by etching using ion beam IB1 , the intermediate layer 30 is separated in units of memory cells MC.

For example, during the etching of the intermediate layer 30, the side surfaces of the MTJ element 1Y are etched, and the width of the tapered MTJ element 1Y is reduced.

By such etching using the ion beam IB1, the MTJ element 1 is formed.

The side surfaces of the etched intermediate layer 30 are substantially parallel to the direction perpendicular to the upper surface of the substrate 80 (Z direction). The angle formed by the upper surface of the substrate 80 and the side surface of the intermediate layer 30 is substantially perpendicular to the upper surface of the substrate 80 .

The upper surface of the member 2Z is used as an etching stop layer to temporarily stop (interrupt) the etching of the laminated body 90W.

The mask layer 19W is etched slowly using the ion beam IB1 at a slower etching speed than the MTJ element 1 (member 1Z) and the intermediate layer 30 (30Z). The Z-direction dimension Tw of the mask layer 19W becomes smaller than the dimension Tz during deposition.

As shown in FIG. 12 , in the processed laminated body 90V, the insulating layer 40Z is formed on the mask layer 19V, the MTJ element 1 and the intermediate layer 30 . The insulating layer 40Z covers the side surfaces of the MTJ element 1 and the intermediate layer 30 . The insulating layer 40Z is, for example, a silicon nitride film. The insulating layer 40Z has a thickness Tq in the X direction (or Y direction).

As shown in FIG. 13 , after the insulating layer 40Z is formed, the processing of the laminated body 90U is restarted. Thereby, the insulating layer 40Z and the member 2Z are etched. The insulating layer 40Z and the member 2Z are etched by, for example, anisotropic etching such as reactive ion etching. However, the etching of the insulating layer 40Z and the structure 2Z can also be performed by ion beam etching.

For example, when the member 2Z is etched by reactive ion etching, ion species of the etching gas are incident on the laminate 90U from a direction perpendicular to the upper surface of the substrate 80 (Z direction).

When the component 2Z is etched, in addition to the mask layer 19 and the MTJ element 1 and the intermediate layer 30 above the component 2Z, the insulating layer 40Z functions as an etching mask for the component 2Z.

By etching, the structure is 2Z in units of memory cells MC. Thereby, a plurality of switching elements 2, mask layers 19, and insulating layers 40 are formed.

Through the above steps, a plurality of memory cells MC are formed above the substrate 80 .

As a result of etching the laminated body 90 , the Z-direction dimension Tx of the mask layer 19 becomes smaller than the Z-direction dimension T3 of the intermediate layer 30 and the Z-direction dimension T1 of the MTJ element 1 .

For example, the mask layer 19 is not removed but used as a part of the upper electrode of the memory element 1 . However, the mask layer 19 may be removed after the laminate 90 is processed (formation of the memory cells MC).

As shown in FIG. 6 , the insulating layer 61 is formed on the insulating layer 60 and the memory cells MC in a manner that it is embedded in the areas between the plurality of memory cells MC. The insulating layer 61 is removed from the upper surface of the mask layer 19 to expose the mask layer 19 .

Thereafter, as shown in FIGS. 3 to 6 , a plurality of wirings 51 respectively extending along the X direction are formed on the insulating layer 61 and the mask layer 19 .

Thus, the memory cell array 110 of the memory device 100 of this embodiment is formed.

Thereafter, various components for connecting the memory cell array 110 and underlying circuits may be formed based on known techniques.

Through the above manufacturing steps, the memory device 100 of this embodiment is completed.

(3) Summary In a general memory device with a plurality of memory cells, a plurality of memory cells adjacent in the X direction or the Y direction may not be fully separated due to the narrowing of the distance between the memory cells. The above-mentioned memory cells include those arranged along the Z direction. Memory elements and selectors of different heights.

For example, when the MTJ element has a tapered structure for the purpose of preventing short circuits caused by attachments, the distance between the memory cells below the MTJ element becomes smaller, and the member further below the MTJ element ( For example, switching components) tend to become more difficult to separate.

In the memory device (eg MRAM) 100 of this embodiment, the intermediate layer 30 is provided between the memory element (eg MTJ element) 1 and the switching element (selector) 2 .

The etching rate of the intermediate layer 30 is higher than the etching rate of other components (eg, the mask layer 19 ). Therefore, even if the etching conditions of the intermediate layer 30 are the same as those of the MTJ device 1 , the intermediate layer 30 will not become a tapered structure, and the side surfaces of the intermediate layer 30 are substantially vertical relative to the upper surface of the substrate 80 .

Therefore, a relatively large space is generated between the plurality of adjacent intermediate layers 30 in the X direction and the Y direction. Even if the side surfaces of the MTJ element 1 and the side surfaces of the intermediate layer 30 are covered by the insulating layer 40 , a relatively large space can be formed between the intermediate layers 30 . As a result, in this embodiment, the distance (pitch) between the memory cells MC in the X direction and the Y direction can be ensured without increasing the distance between the components below the MTJ element 1 (for example, for composing the switching element 2 Multiple layers) space for processing.

Therefore, in this embodiment, the switching element 2 is separated in units of memory cells MC without causing processing defects in the components used to form the switching element 2 .

In this embodiment, even in a tapered MTJ element, when the size of the lower part of the MTJ element 1 is larger than the size of the upper part of the MTJ element 1 , the arrangement of the intermediate layer 30 and the etching of the intermediate layer 30 can also be used. To ensure space for processing the switching element 2 below the MTJ element 1. Therefore, the side surface of the MTJ element 1 can be irradiated with an ion beam tilted at an angle sufficient to remove conductive deposits.

Thereby, the memory device 100 of this embodiment can reduce defects caused by short circuits between the magnetic layers 11 and 13 caused by conductive attachments.

In this embodiment, by arranging the intermediate layer 30 to ensure the space between the memory cells MC, the thickness of the insulating layer 40 covering the MTJ element 1 can be increased. As a result, the memory device 100 of this embodiment can reduce damage to the MTJ element 1 caused by etching during processing of the switching element 2 .

Depending on the constituent members of the switching element 2, the flatness of the surface of the switching element 2 may be deteriorated. For example, when a silicon oxide layer is used as a variable resistance layer, a dopant (eg, arsenic) may be doped into the silicon oxide layer. In this case, the surface of the switching element 2 becomes rough. In the case where the MTJ element 1 is formed on the switching element 2 having a rough surface, the layers constituting the MTJ element 1 are adversely affected by the surface roughness of the switching element 2 . As a result, the characteristics of the MTJ element 1 may deteriorate.

In the memory device 100 of this embodiment, the intermediate layer 30 can reduce the surface roughness of the switching element 2 . Therefore, in this embodiment, it is possible to reduce the adverse effects that the layer constituting the MTJ element 1 receives from the rough surface of the switching element 2 below.

As a result, the memory device 100 of this embodiment can improve the characteristics of the MTJ element 1 .

In this embodiment, by disposing the intermediate layer 30 , the distance between the MTJ element 1 and the switching element 2 is increased. Therefore, the heat propagation between the MTJ element 1 and the switching element 2 is reduced. When the middle layer 30 includes metal, the heat dissipation characteristics of the memory cell MC are improved by the middle layer 30 . As a result, in this embodiment, the thermal stability of the MTJ element 1 is improved. Therefore, the operation reliability of the memory device 100 of this embodiment is improved.

As mentioned above, the memory device of the embodiment can reduce the defects of the memory device.

(4) Variations Modification examples of the memory device of the embodiment will be described with reference to FIGS. 14 to 16 .

FIG. 14 , FIG. 15 and FIG. 16 respectively show the cross-sectional structure of the memory cell MC of a variation of the memory device 100 of the embodiment.

As shown in FIG. 14 , the intermediate layer 30A does not need to be a porous layer, as long as it can ensure that the etching rate is greater than the etching rate of the hard mask (or the component of the memory element). In this case, the middle layer 30A does not include an air gap.

The intermediate layer 30A that does not contain air gaps (the intermediate layer of the non-porous layer) contains boron (B), silicon (Si), magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), Vanadium (V), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), hafnium (Hf), A layer (film) consisting of at least one component of iridium (Ir) and platinum (Pt).

Similar to the above example, the size of the intermediate layer 30A in the Z direction is larger than the size of the MTJ element 1 in the Z direction. In addition, the size of the intermediate layer 30A in the Z direction is larger than the size of the conductive layer 19 in the Z direction.

As shown in FIG. 15 , the intermediate layer 30B may also include a plurality of layers 301 and 302 . For example, the material of layer 301 is different from the material of layer 302. As an example, among the layers 301 and 302, one layer 301 is a porous layer including air gaps 39. Among the layers 301 and 302, the other layer 302 does not contain an air gap.

Layer 302 is provided between conductive layer 18A and porous layer 301. Thereby, the flatness of the base of the magnetic layer 14 (and the conductive layer 18A) is improved. As a result, the characteristics of the MTJ element 1 are improved.

For example, it is desirable that the Z-direction size (film thickness) of layer 302 is smaller than the Z-direction size of conductive layer 19 and the Z-direction size of layer 301 . Regarding the etching conditions of the MTJ element 1, it is ideal that the etching rate of the layer 302 is smaller than the etching rate of the conductive layer 19.

As an example of the material of the layer 301, the layer 301 includes, for example, a material selected from the group consisting of boron, carbon, silicon, magnesium, aluminum, scandium, titanium, vanadium, gallium, germanium, yttrium, zirconium, niobium, molybdenum, palladium, silver, hafnium, tantalum, One of tungsten, iridium and platinum.

Layer 302 is composed of well-known materials used for electrodes (conductive layers) in memory cells MC of MRAM.

Under certain etching conditions when processing memory cells, the etching rate of the entire intermediate layer 30B including the plurality of layers 301 and 302 is higher than the etching rate of the conductive layer (hard mask) 19 . Therefore, after the layers 301 and 302 are etched, the conductive layer 19 will remain on the MTJ element 1 .

In FIG. 15 , an example in which the intermediate layer 30B includes two layers 301 and 302 is shown. However, the intermediate layer 30B may include three or more layers.

As shown in FIG. 16 , the intermediate layer 30C may also be a layer in which an insulator 315 is provided in the space between the granular portions 310 instead of the air gap. For example, the insulator 315 is silicon oxide, silicon carbide or organic matter.

The middle layer 30C further includes a plurality of holes 319 .

The memory device of the modified example of FIG. 14 , FIG. 15 and FIG. 16 can achieve the same effect as the memory device of the above embodiment.

(5)Others In the above embodiment, MRAM is exemplified as the memory device 100 of this embodiment. However, the memory device 100 of this embodiment can also be a memory device other than MRAM, as long as it is a device in which an intermediate layer 30 is provided between the memory element 1 and the selector (switching element) 2 in the memory cell MC.

For example, the memory device 100 of the embodiment can also be a memory device that uses variable resistance elements (such as transition metal oxide elements) as memory elements (such as ReRAM (Resistance Random Access Memory, resistive random access memory), etc. Resistance change memory), memory devices that use phase change elements as memory elements (for example, phase change memories such as PCRAM (Phase Change Random Access Memory, phase change random access memory)), or use ferroelectric elements as memory Memory devices of components (for example, ferroelectric random access memories such as FeRAM (Ferroelectric Random Access Memory, ferroelectric random access memory)).

Even if the memory device 100 of this embodiment is a memory device other than MRAM, the effects described in the above embodiment can be obtained.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or variations thereof are included in the scope or gist of the invention, and are included in the scope of the invention described in the patent application and its equivalents. [Citations of related applications]

This application enjoys the priority of applications based on Japanese Patent Application No. 2022-033696 (filing date: March 4, 2022) and US Patent Application No. 17/884790 (filing date: August 10, 2022). This application incorporates the entire contents of the basic application by reference to the basic application.

1: Memory component 1X:Component 1Y: Component 1Z: Component 2: Selector 2Z: Component 11, 13: Magnetic layer 12: Tunnel barrier layer 14:Offset elimination layer 15: Non-magnetic layer 18A, 18B: Conductive layer 19:Conductive layer 19V: Mask layer 19W: Mask layer 19X: Mask layer 19Y: Mask layer 19Z: Mask layer 20: Variable resistance layer 21A, 21B: Electrode (conductive layer) 30:Middle layer 30A: middle layer 30B:Middle layer 30C: middle layer 30Y: middle layer 30Z: middle layer 39:Air gap 40:Insulation layer 40Z: Insulation layer 50:Wiring 51: Wiring (conductive layer) 55:Plug 60:Insulation layer 61: Insulation layer 80:Substrate 81:Insulation layer 90:Laminated body 90U:Laminated body 90V:Laminated body 90W:Laminated body 90X:Laminated body 100:Memory device 110: Memory cell array 120: Column control circuit 130: Row control circuit 140:Writing circuit 150: Readout circuit 160: Voltage generating circuit 170: Input and output circuit 180:Control circuit 301,302:layer 310: Granular part 311: Granular part 315:Insulator 319:hole 900:External device ADR: address BL(BL＜0＞, BL＜1＞, …, BL＜i-1＞): bit line CMD: command CNT: control signal D1a: size D1b: size D2: size D3: size DT:data IB1: Ion beam MC: memory cell T1: size T2: size T3: size Tq: film thickness Tx: size Tz: size (thickness) Tw: size WL(WL＜0＞, WL＜1＞, …, WL＜j-1＞): character line X: direction Y: direction Z: direction

FIG. 1 is a block diagram showing an example of the configuration of the memory device according to the embodiment. 2 is a diagram showing an example of the structure of a memory cell array of the memory device according to the embodiment. 3 is a bird's-eye view showing an example of the structure of a memory cell array of the memory device according to the embodiment. 4 is a cross-sectional view showing an example of the structure of a memory cell array of the memory device according to the embodiment. 5 is a cross-sectional view showing an example of the structure of a memory cell array of the memory device according to the embodiment. 6 is a cross-sectional view showing an example of the structure of a memory cell of the memory device according to the embodiment. 7 is a diagram illustrating an example of the structure of a memory cell of the memory device according to the embodiment. 8 is a cross-sectional step diagram showing one step of the manufacturing method of the memory device according to the embodiment. 9 is a cross-sectional step diagram showing one step of the manufacturing method of the memory device according to the embodiment. 10 is a cross-sectional step diagram showing one step of the manufacturing method of the memory device according to the embodiment. 11 is a cross-sectional step diagram showing one step of the manufacturing method of the memory device according to the embodiment. 12 is a cross-sectional step diagram showing one step of the manufacturing method of the memory device according to the embodiment. 13 is a cross-sectional step diagram showing one step of the manufacturing method of the memory device according to the embodiment. 14 is a cross-sectional view showing a variation of the memory device according to the embodiment. 15 is a cross-sectional view showing a variation of the memory device according to the embodiment. 16 is a cross-sectional view showing a variation of the memory device according to the embodiment.

1: Memory component

2: Selector

11,13: Magnetic layer

12: Tunnel barrier layer

14:Offset elimination layer

15: Non-magnetic layer

18A, 18B: conductive layer

19:Conductive layer

20: Variable resistance layer

21A, 21B: Electrode (conductive layer)

30:Middle layer

39:Air gap

40:Insulation layer

50:Wiring

51: Wiring (conductive layer)

55:Plug

60:Insulation layer

61: Insulation layer

80:Substrate

81:Insulation layer

90:Laminated body

D1a: size

D1b: size

D2: size

D3: size

MC: memory cell

T1: size

T2: size

T3: size

Tq: film thickness

Tx: size

X: direction

Y: direction

Z: direction

Claims (19)

A memory device, which is provided with: a memory element, which is arranged above the above-mentioned substrate in a first direction perpendicular to the first surface of the substrate; a switching element, which is arranged between the above-mentioned substrate and the above-mentioned memory element; and 1 layer, which is disposed between the above-mentioned memory element and the above-mentioned switching element; and The above-mentioned first layer includes boron, carbon, silicon, magnesium, aluminum, scandium, titanium, vanadium, gallium, germanium, yttrium, zirconium, niobium , molybdenum, palladium, silver, hafnium, tantalum, tungsten, iridium and platinum, and the first layer includes an air gap. The memory device of claim 1 further includes a first conductive layer, the first conductive layer is disposed above the memory element in the first direction, and the size of the first layer in the first direction is larger than the above-mentioned first layer. 1. The size of the conductive layer in the above-mentioned first direction. Such as the memory device of claim 2, wherein the above-mentioned first conductive layer is a tungsten layer or a molybdenum layer. Such as the memory device of claim 2, wherein the etching rate of the above-mentioned first layer is higher than the etching rate of the above-mentioned first conductive layer. The memory device of claim 1, wherein the size of the first layer in the first direction is greater than the size of the memory element in the first direction. Such as the memory device of claim 1, wherein the size of the lower part of the above-mentioned memory element is larger than the size of the upper part of the above-mentioned memory element. The memory device of claim 1, wherein the side surface of the first layer is parallel to the first direction. The memory device of claim 1 further includes: a first conductive layer, which is disposed above the memory element in the first direction; and a first insulating layer, which is continuously disposed on the side of the first conductive layer , on the side of the above-mentioned memory element and on the side of the above-mentioned first layer. A memory device, which is provided with: a memory element, which is arranged above the above-mentioned substrate in a first direction perpendicular to the first surface of the substrate; a switching element, which is arranged between the above-mentioned substrate and the above-mentioned memory element; and 1 layer, which is disposed between the above-mentioned memory element and the above-mentioned switching element; and The above-mentioned first layer includes boron, silicon, magnesium, aluminum, scandium, titanium, vanadium, gallium, germanium, yttrium, zirconium, niobium, molybdenum , at least one of the group consisting of palladium, silver, hafnium, iridium and platinum. The memory device of claim 9 further includes a first conductive layer, which is disposed above the memory element in the first direction, and the size of the first layer in the first direction is larger than the first conductive layer. 1. The size of the conductive layer in the above-mentioned first direction. The memory device of claim 10, wherein the etching rate of the first layer is higher than the etching rate of the first conductive layer. A method of manufacturing a memory device, which includes the following steps: forming a laminate including a first member, a second member and a first layer on a substrate, the first member being in a first direction perpendicular to the surface of the substrate Located above the above-mentioned substrate, the above-mentioned second member is located above the above-mentioned first member in the above-mentioned first direction, and the above-mentioned first layer is provided between the above-mentioned first member and the above-mentioned second member; In the above-mentioned first direction, in A mask layer is formed on the above-mentioned laminated body; Based on the shape of the above-mentioned mask layer, the above-mentioned second member and the above-mentioned first layer are etched to form a memory element from the above-mentioned second member; On the etched above-mentioned second member and the above-mentioned A first insulating layer is formed on the first layer; and the above-mentioned first component is etched to form a switching element from the above-mentioned first component; and the above-mentioned first layer contains a material selected from the group consisting of boron, carbon, silicon, magnesium, aluminum, scandium, and titanium. , at least one of the group consisting of vanadium, gallium, germanium, yttrium, zirconium, niobium, molybdenum, palladium, silver, hafnium, tantalum, tungsten, iridium and platinum; The above-mentioned first layer includes an air gap. The method of manufacturing a memory device of claim 12, wherein the etching rate of the first layer is higher than the etching rate of the mask layer. The manufacturing method of the memory device of claim 12, wherein the above-mentioned mask layer is a tungsten layer or a molybdenum layer. The manufacturing method of a memory device as claimed in claim 12, wherein the first dimension of the mask layer in the first direction before etching the first member is greater than the second dimension of the first layer in the first direction. , The third dimension of the mask layer in the first direction after etching the second member is smaller than the second dimension. The method of manufacturing a memory device according to claim 12, wherein the size of the first layer in the first direction is greater than the size of the memory element in the first direction. The manufacturing method of the memory device of claim 12, wherein the size of the upper part of the above-mentioned memory element is larger than the size of the lower part of the above-mentioned memory element. The manufacturing method of a memory device as claimed in claim 12, wherein the side surfaces of the etched first layer are parallel to the first direction. The method of manufacturing a memory device according to claim 12, wherein the etching of the second member and the first layer is performed using an ion beam, and the ion beam is irradiated to the laminated body from a direction inclined with respect to the surface of the substrate.