TW202335440A - Dynamic sampling rate tuning system - Google Patents

Abstract

The present invention provides a dynamic sampling rate adjustment system, which is set in coordination with a sampling frequency device. The sampling frequency device outputs a sampling frequency signal according to the sampling frequency. The dynamic sampling rate adjustment system includes a control device, a frequency adjustment device, and a sampling device. The input ends of the frequency adjustment device are respectively connected to the sampling frequency analysis device and the control device. The frequency adjustment device includes a comparison decision module, a noise adjustment module, a mapping module, and a frequency adjustment module. The frequency adjustment device starts a takeover mode when it detects that the sampling frequency of the sampling frequency signal exceeds the expected frequency range, updates the sampling frequency and outputs a sampling frequency stable signal. The sampling device samples the target signal according to the updated sampling frequency stable signal.

Description

Dynamic sampling rate adjustment system

The present invention provides a dynamic sampling rate adjustment system, especially a dynamic sampling rate adjustment system that can effectively reduce jitter noise.

In the field of signal processing, sampling is the process of converting signals from analog signals in the continuous time domain to discrete signals in the discrete time domain. The analog signal is first sampled by the sampling circuit at certain time intervals to obtain a time-discrete signal, and then is numerically discretized by an analog-to-digital converter (ADC), thereby obtaining a digital signal that is both numerically and time-discrete.

The discrete form of the signal thus obtained often brings some errors to the data, and the errors mainly come from two aspects, the sampling rate related to the spectrum of the continuous analog signal, and the word length used in quantization. Sampling rate refers to the frequency with which continuous signals are sampled. It represents the accuracy of discrete signals in the time and space domains. The word length (the number of bits) is used to represent the value of a discrete signal, which reflects the accuracy of the signal size.

The sampling rate (also called sampling speed or sampling frequency) defines the number of samples extracted from a continuous signal and composed into a discrete signal per second, which is expressed in Hertz (Hz). However, the sampling rate of commonly used sampling loops is sampled based on the input frequency. When the input frequency is inaccurate, the sampling rate will be inaccurate. When the sampling rate is inaccurate, the input buffer will overflow, causing system abnormalities. .

In order to solve the above problems, the present invention provides a dynamic sampling rate adjustment system, which is configured in conjunction with a sampling frequency device. The sampling frequency device outputs a sampling frequency signal according to the sampling frequency. The dynamic sampling rate adjustment system includes a control device, a frequency adjustment device and a sampling device. The control device outputs a control signal carrying information of an expected frequency range. The input end of the frequency adjustment device is connected to the sampling frequency device and the control device respectively. The frequency adjustment device includes a comparison decision-making module, a noise adjustment module set at the output of the comparison decision-making module, a mapping module set at the output of the noise adjustment module, and a frequency set at the output of the mapping module. Adjust the module. The input end of the comparison decision module is respectively connected to the output end of the sampling frequency device, the frequency adjustment module and the control device. The comparison decision-making module activates a takeover mode when detecting that the sampling frequency of the sampling frequency signal exceeds the expected frequency range. In the takeover mode, the comparison decision-making module determines to output a virtual virtual signal based on whether the sampling frequency exceeds the expected frequency range. Up and down wave signals. The noise adjustment module generates output codes based on the virtual up and down wave signals. The mapping module maps the output FM signal according to the output code. The frequency adjustment module updates the sampling frequency according to the frequency modulation signal and outputs a stable sampling frequency signal, and feeds back the updated sampling frequency to the comparison decision-making module to form a loop. The input end of the sampling device is connected to the frequency adjustment device, and the sampling device samples the target signal according to the updated sampling frequency stable signal.

Therefore, compared with the conventional technology, the present invention can stabilize the input frequency of the sampling rate, avoid input buffer overflow, and solve the problem of system abnormality caused by buffer overflow.

The detailed description and technical content of the present invention are described below with reference to the drawings.

The following is a description of one of the preferred embodiments of the present invention. Please refer to "Figure 1", "Figure 2" and "Figure 3", which are block diagrams (1) and (1) of the dynamic sampling rate adjustment system of the present invention respectively. 2) and block diagram (3), as shown in the figure:

Please refer to "Figure 1". This embodiment discloses a dynamic sampling rate adjustment system 100, which mainly includes a sampling frequency device 10, a control device 20, a frequency adjustment device 30 whose input ends are respectively connected to the sampling frequency device 10 and the control device 20, and The input is connected to the sampling device 40 of the frequency adjustment device 30 .

The combination of devices, modules, circuits or units and their corresponding functions in the dynamic sampling rate adjustment system 100 of the present invention can be executed collaboratively by a single chip or a combination of multiple chips. The number of these chips is not limited to The scope of the present invention is intended to be limited. In addition, the chip may include, but is not limited to, a processor (Processor), a Central Processing Unit (CPU), a microprocessor (Microprocessor), a Digital Signal Processor (DSP), special application Application Specific Integrated Circuits (ASIC), Programmable Logic Device (PLD) and other similar devices or combinations of these devices that can process information or signals, convert them for special purposes, are used here. No limitations are imposed on the invention.

The sampling frequency device 10 outputs a sampling frequency signal according to the sampling frequency. Specifically, the sampling frequency device 10 is configured with an oscillator and is used to determine the number of sampling times of the continuous time signal within a fixed time range. In one embodiment, the sampling frequency signal can be, for example, a square wave composed of 0s and 1s. For example, taking an asynchronous sample rate converter (ASRC) as an example, when the sampling frequency signal is in the up-frequency band, When the bit string value is 1, the current value of the signal is obtained. When the bit string value is 0, the current value of the signal is retained. When the bit string value of the sampling frequency signal in the down-frequency band is 1, the current value of the signal is obtained. The bit string value When it is 0, it takes no value. The sampling frequency device 10 may include, but is not limited to, a digital signal processor (DSP), a function generator (function generator), an arbitrary waveform generator (AWG), a signal generator (Signal generator) ) and other devices that can generate signals are not limited in the present invention.

The control device 20 outputs a control signal, and the control signal carries information of the expected frequency range. In one embodiment, the control device 20 is a processor. The aforementioned processor is not limited to a single one. When necessary, a plurality of processors can also be used to jointly execute the program and complete the work. In one implementation, the processor is, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor (Microprocessor), digital signal processor ( Digital Signal Processor (DSP), programmable controller, Application Specific Integrated Circuits (ASIC), Programmable Logic Device (PLD) or other similar devices or combinations of these devices, in There is no limitation in the present invention.

The frequency adjustment device 30 includes two input terminals respectively connected to the sampling frequency device 10 and the control device 20. When detecting that the sampling frequency of the sampling frequency signal exceeds the expected frequency range, it switches to the takeover mode and replaces the sampling frequency signal in the takeover mode. Sampling frequency device 10. Please refer to "Figure 2" together. The frequency adjustment device 30 includes a comparison decision module 32, a noise adjustment module 34 provided at the output of the comparison decision module 32, and a mapping module 36 provided at the output of the noise adjustment module 34. , and the frequency adjustment module 38 provided at the output of the mapping module 36. The input terminals of the aforementioned comparison decision module 32 are respectively connected to the output terminals of the sampling frequency device 10 , the frequency adjustment module 38 and the control device 20 . The comparison decision-making module 32 initially activates the sleep mode. In the sleep mode, the comparison decision-making module 32 directly outputs the sampling frequency signal of the sampling frequency device 10; the comparison decision-making module 32 detects the sampling frequency signal. When the sampling frequency exceeds the expected frequency range, the takeover mode is activated to take over the sampling frequency device 10 . In the takeover mode, the comparison decision module 32 determines to output the virtual up and down wave signals according to whether the sampling frequency exceeds the expected frequency range and determines to output the virtual up and down wave signals according to whether the sampling frequency exceeds the expected frequency range, wherein the above The above-mentioned sampling frequency is the sampling frequency of the sampling frequency signal of the sampling frequency device 10 for the first time, and the updated sampling frequency of the sampling frequency stable signal of the frequency adjustment module 38 from the second time; in one embodiment, the virtual rise and fall The wave can be a triangular wave, a sine wave, etc., which is not limited in the present invention; in one embodiment, the peak value and peak trough of the virtual rising and falling wave are between 0 and 1. The comparison decision module 32 includes at least one signal analyzer (Signal Analyzer) for converting discrete signals into numerical values. The signal analyzer may include but is not limited to a spectrum analyzer or other devices that can serve as signal conversion functions. , is not limited in the present invention.

Please also refer to "Figure 3". The noise adjustment module 34 outputs an output code based on the virtual up and down wave signal (virtual up wave or virtual down wave) output by the comparison decision module 32. In one embodiment, the noise adjustment module 34 includes a first adder A1, a second adder A2, a first delayer D1, a second delayer D2, a third delayer D3, a first multiplier M1, and a third delayer D3. A square multiplier M2, and a multi-level quantizer NQ. The input terminal of the first adder A1 is connected to the output of the volume control device 10, the output of the first multiplier M1, the output of the second multiplier M2, and the output of the third delayer D3; the output of the second adder A2 The input terminal is connected to the output of the first adder A1 and the output of the multi-level quantizer NQ, wherein an inverter is further included between the input terminal of the second adder A2 and the output of the first adder A1 (not shown) to form a subtraction loop; the input end of the first delayer D1 is connected to the output of the second adder A2, and the input of the first multiplier M1 is connected to the output of the first delayer D1 to form First-order delay feedback loop; the input end of the second delayer D2 is connected to the output of the first delayer D1, and the input of the second multiplier M2 is connected to the output of the second delayer D2 to form a second-order delay loop. , wherein the output of the second multiplier M2 and the first adder A1 further include an inverter (not shown) to form a subtraction loop; the input end of the third delayer D3 is connected to the second delayer D2 The output of the multi-level quantizer NQ forms a third-order delay loop; the input terminal of the multi-level quantizer NQ is connected to the output of the first adder A1, thereby converting the output of the first adder A1 (such as w[n]) into a quantization code.

The first adder A1 and the second adder A2 may include, but are not limited to, an adder, a half adder, a full adder, a ripple carry adder, and a carry-ahead. Adder implementation, or other digital circuits, logic gates, or combinations thereof for performing addition operations are not limited in the present invention.

The first delayer D1, the second delayer D2, and the third delayer D3 may include but are not limited to integrators, counters, and other circuits that can be used for signal delay or integration, or a combination thereof. , is not limited in the present invention.

The first multiplier M1 and the second multiplier M2 may include but are not limited to operational amplifiers (op amps), or circuits composed of a plurality of adders, or other similar devices, which are not included in the present invention. limit.

The mapping module 36 maps and outputs an FM signal based on the output code. The mapping module 36 may include a processor or an Arithmetic Logic Unit (ALU) with an associative array lookup function (lookup table). , is not limited in the present invention.

The frequency adjustment module 38 updates the sampling frequency according to the frequency modulation signal and outputs a stable sampling frequency signal to the sampling device 40, and feeds back the updated stable sampling frequency signal to the comparison decision module 32. Form a cyclical loop. In a preferred embodiment, the frequency adjustment module 38 may include but is not limited to a voltage-controlled oscillator (Voltage-Controlled Oscillator) or other other devices that can be used for frequency adjustment, which are not limited in the present invention.

The input end of the sampling device 40 is connected to the frequency adjustment device 30, and the target signal is sampled according to the updated sampling frequency stable signal. The aforementioned sampling device 40 is a sampling loop, which is a device or circuit that can sample and obtain time-discrete signals at certain time intervals, and is not limited in the present invention.

The above describes a specific embodiment of the hardware architecture of the present invention. The working method of the present invention will be further described below. Please refer to "Figure 4" for the working of the dynamic sampling rate adjustment system of the present invention. Process diagram:

The sampling frequency signal and the sampling frequency stable signal described in this embodiment are square waves composed of 0s and 1s. In other embodiments, the sampling frequency signal and the sampling frequency stabilization signal can be other waveforms, and the peak value of the waveform is not limited to the scope of the present invention, as will be explained here.

First, the control device 20 stores the expected frequency range according to user settings or factory settings, and outputs a control signal to the frequency adjustment device 30 according to the expected frequency range; the sampling frequency device 10 outputs the sampling frequency signal to the frequency adjustment device 30 (step S201).

In one embodiment, the aforementioned expected frequency range may be a user setting or an existing factory setting value; in another embodiment, the control device 20 obtains the expected frequency range from the expected frequency and the threshold range, and the expected frequency range is The upper limit of the frequency range is the desired frequency plus the threshold range, and the lower limit of the desired frequency range is the desired frequency minus the threshold range.

Next, the comparison decision module 32 of the frequency adjustment device 30 continues to detect the sampling frequency signal output by the sampling frequency device 10, and obtains the sampling frequency from the sampling frequency signal to confirm whether the sampling frequency exceeds the expected frequency range (step S202); if If not, repeat step S202 to continue detection, or set a delay and confirm again after a period of time, or set a trigger condition. signal, signal loss), perform detection again; if it is detected that the sampling frequency of the sampling frequency signal exceeds the expected frequency range, start a takeover mode (step S203), and continue the subsequent procedures; after starting the takeover mode , the comparison decision module 32 determines whether to output a virtual up and down wave signal based on whether the sampling frequency exceeds the expected frequency range (step S204). If so, continue to step 205. When the comparison decision module 32 detects that the sampling frequency of the feedback reaches an expected value within the expected frequency range (if not), it outputs a frequency lock signal. to the frequency adjustment module 32 and stop updating the sampling frequency (step S210).

In this embodiment, when the comparison decision module 32 receives the sampling frequency signal (or the sampling frequency stable signal received during the second or more loops) is higher than the upper limit of the expected frequency range, it outputs a virtual drop. wave signal; when the comparison decision module 32 receives that the sampling frequency signal (sampling frequency stable signal) is lower than the lower limit of the expected frequency range, it outputs a virtual rising wave signal.

Next, the noise adjustment module 34 generates and outputs codes to the mapping module 36 according to the virtual up and down wave signals (step S205).

In this embodiment, the noise adjustment module 34 outputs the output code according to the following relationship: ; ; in, is the value of the virtual rising and falling wave signal at nth order, is the output code at nth order, for The output code of the order, for The output code of the order, for The output code of the order, for and The intermediate transfer function, for and The intermediate transfer function, for and The intermediate transfer function, for and intermediate transfer function.

Among them, the The function is as follows: ; Among them, M is the preset level value of the multi-level quantizer, and floor() is a floor function.

Next, the mapping module 36 maps and outputs a frequency modulation signal to the frequency adjustment module 38 according to the received output code (step S206).

In this embodiment, the mapping module 36 maps and outputs the FM signal according to the following relationship: ; ; in, for the first This output code is staged into the mapping module 36, for the first The FM signal output by stage mapping, Z is a positive integer, It is Parts Per Million (PPM).

Next, the frequency adjustment module 38 receives the frequency modulation signal and the sampling frequency signal of the sampling frequency device 10 . The frequency adjustment module 38 updates the sampling frequency according to the frequency modulation signal and outputs a stable sampling frequency signal to the sampling device 40 (step S207 ).

In this embodiment, the frequency adjustment module 38 outputs the sampling frequency stable signal according to the following relationship: ; in, for the first The FM signal input to the frequency adjustment module 38 in one stage, for the first The sampling frequency input to the frequency adjustment module 38 in each stage (the sampling frequency of the sampling frequency signal for the first time, and the sampling frequency of the stable sampling frequency signal after the second time), For the frequency adjustment module 38th The sampling frequency of the stage output.

The frequency adjustment module 38 is used to obtain the sampling frequency After that, the sampling frequency is Generate a stable signal with the sampling frequency.

Finally, the sampling device 40 receives the sampling frequency stable signal from the frequency adjustment device 30 and samples the target signal according to the sampling frequency stable signal (step S208).

At the same time, the updated sampling frequency will be sent back to the comparison decision module 32 (step S209), and the process will return to step S204 to re-execute subsequent loops until the conditions of step S210 are met.

To sum up, compared with the conventional technology, the present invention can stabilize the input frequency of the sampling rate and avoid the problem of system abnormality caused by input buffer overflow.

The present invention has been described in detail above. However, what is described above is only one of the preferred embodiments of the present invention. It should not be used to limit the scope of the present invention. That is, anything based on the patent scope of the present invention is made. Equal changes and modifications should still fall within the scope of the patent of the present invention.

100:Dynamic sampling rate adjustment system 10: Sampling frequency device 20:Control device 30: Frequency adjustment device 32: Comparative Decision Module 34:Noise adjustment module A1: First adder A2: Second adder D1: first delayer D2: Second delayer D3: The third delayer M1: first multiplier M2: Second multiplier NQ: multi-level quantizer 36: Mapping module 38: Frequency adjustment module 40: Sampling device S201-210: Steps

Figure 1 is a block diagram (1) of the dynamic sampling rate adjustment system of the present invention.

Figure 2 is a block diagram (2) of the dynamic sampling rate adjustment system of the present invention.

Figure 3 is a block diagram (3) of the dynamic sampling rate adjustment system of the present invention.

Figure 4 is a schematic diagram of the work flow of the dynamic sampling rate adjustment system of the present invention.

100:Dynamic sampling rate adjustment system

10: Sampling frequency device

20:Control device

30: Frequency adjustment device

40: Sampling device

Claims (10)

A dynamic sampling rate adjustment system is configured in conjunction with a sampling frequency device. The sampling frequency device outputs a sampling frequency signal based on the sampling frequency. The dynamic sampling rate adjustment system includes: A control device outputs a control signal, and the control signal carries information in the expected frequency range; A frequency adjustment device, the input ends of which are respectively connected to the sampling frequency device and the control device. The frequency adjustment device includes a comparison decision-making module, a noise adjustment module set at the output of the comparison decision-making module, and a noise adjustment module set at the output of the comparison decision-making module. The noise adjustment module outputs a mapping module and a frequency adjustment module provided at the output of the mapping module. The input end of the comparison decision module is respectively connected to the sampling frequency device, the frequency adjustment module and the At the output end of the control device, the comparison decision-making module activates a takeover mode when detecting that the sampling frequency of the sampling frequency signal exceeds the expected frequency range. In the takeover mode, the comparison decision-making module determines whether the sampling frequency exceeds the expected frequency range. The expected frequency range determines the output of a virtual up and down wave signal. The noise adjustment module generates an output code based on the virtual up and down wave signal. The mapping module maps and outputs an FM signal based on the output code. The frequency adjustment module updates based on the FM signal. The sampling frequency is used to output a stable sampling frequency signal, and the updated stable sampling frequency signal is fed back to the comparison decision module to form a loop; and A sampling device, the input end of which is connected to the frequency adjustment device, the sampling device samples the target signal according to the updated sampling frequency stable signal. The dynamic sampling rate adjustment system as described in claim 1, wherein the input and output of the noise adjustment module comply with the following formula: ; ; in, is the value of the virtual rising and falling wave signal at nth order, is the output code at nth order, for and The intermediate transfer function, is a function of multi-level quantizer. The dynamic sampling rate adjustment system as described in claim 2, wherein the comparison decision-making module outputs a frequency locking signal when detecting that the sampling frequency of the feedback reaches an expected value within the expected frequency range. to the frequency adjustment module and stop updating the sampling frequency. The dynamic sampling rate adjustment system as described in claim 2, wherein the The function is as follows: ; Among them, M is the preset level value of the multi-level quantizer, and floor() is a floor function. The dynamic sampling rate adjustment system as described in claim 2, wherein the comparison decision-making module outputs a virtual downwave signal when it receives that the sampling frequency stable signal is higher than the upper limit of the expected frequency range; the comparison decision-making module receives When the stable sampling frequency signal is lower than the lower limit of the expected frequency range, a virtual rising wave signal is output. The dynamic sampling rate adjustment system as described in claim 2, wherein the control device obtains the expected frequency range from the expected frequency and the threshold range, and the upper limit of the expected frequency range is the expected frequency plus the threshold range. The lower limit of the frequency range is the desired frequency minus the threshold range. The dynamic sampling rate adjustment system as described in claim 6, wherein the comparison decision-making module outputs a virtual downwave signal when it receives that the sampling frequency stable signal is higher than the upper limit of the expected frequency range; the comparison decision-making module receives When the stable sampling frequency signal is lower than the lower limit of the expected frequency range, a virtual rising wave signal is output. The dynamic sampling rate adjustment system as described in claim 2, wherein the mapping module maps and outputs the frequency modulation signal according to the following relationship: ; ; in, for the first stage input to the output code of the mapping module, for the first The FM signal output by stage mapping, Z is a positive integer, It is Parts Per Million (PPM). The dynamic sampling rate adjustment system as described in claim 8, wherein the input and output of the frequency adjustment module comply with the following formula: ; in, for the first The FM signal input to the frequency adjustment module in one stage, for the first The sampling frequency input to the frequency adjustment module at the stage, For the frequency adjustment module No. The sampling frequency of the stage output. The dynamic sampling rate adjustment system as described in any one of claims 1 to 9, wherein the sampling frequency signal and the sampling frequency stable signal are a square wave composed of 0s and 1s.

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