TW202331845A - Improving metal contacts to group iv semiconductors by inserting interfacial atomic monolayers - Google Patents

Abstract

Techniques for reducing the specific contact resistance of metal – semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal – group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Description

Improved metal contacts to group IV semiconductors by intercalating interfacial atomic monolayers

The present invention relates to a monolayer of Group V or Group III atoms, or a double layer made of a Group V atom monolayer and a Group III atom monolayer, at the interface between a metal and a semiconductor. layer, or techniques for lowering the specific contact resistance of metal-semiconductor (Group IV) junctions by inserting multiple such bilayers.

When the size of the transistor is reduced to nanometer size, such as ultra-thin body (UTB) silicon-on-insulator (SOI) field effect transistor (FET), fin field effect transistor (FinFET) and nanowire field effect Transistor (nanowire FET) form, but with the source and drain of transistors bring unwelcome resistance and the performance of these components and integrated circuit products made using these transistors is increasingly serious burden. In addition, when the dimensions of transistor source and drain regions are reduced below about 10 nanometers (nm), it is theoretically expected and experimentally proven to reduce dopant activation. Dopant activation means donating desired free carriers (electrons or holes) by intentionally introducing impurity species into the semiconductor host. This reduction in nanoscale dopant activation further results in undesired high resistance. If the effective doping in the semiconductor is reduced, the resistance of the metal contact to the semiconductor will increase. This resistance increase is mainly due to the Schottky barrier at the metal-semiconductor contact.

It is well known that high doping in the shallow region of the semiconductor near the metal-semiconductor interface reduces the resistance of the metal-semiconductor contact by reducing the width of the Schottky barrier. While the barrier width is reduced from an electrical response point of view (eg, from current-voltage measurements), the Schottky height appears to be reduced. J. M. Shannon published the title "Control of Schottky barrier height using highly doped surface layer (Control of Schottky barrier height using highly Doped surface layers) were described in the early literature that surface doping can be used to achieve this "effective energy barrier height" reduction. It is also known that a so-called dopant segregation of metal silicides can be used to introduce high concentrations of dopant atoms into shallow regions of the semiconductor near metal contacts. A. Kikuchi and S. Sugaki reported in J. Appl. Phys, Issue 53, Volume 5, May 1982 that during the formation of PtSi, the implanted phosphorus atoms accumulate near the PtSi- Si interface and reduce the Schottky barrier measurement height of n-type silicon. The decrease in the measured (effective) barrier height of the Schottky diode is due to the steeper barrier caused by the accumulation of phosphorus atoms in the silicon. It is the effect described by Shannon in 1976 that produces this result.

For the past several decades, the silicon microelectronics industry has relied on high dopant concentrations in the silicon near metal-silicon contacts as a means of achieving acceptably low contact resistance for transistor sources and drains. The contact metal is mostly metal silicide, and more recently nickel silicide or nickel platinum silicide. This method of reducing contact resistance is anticipated in the future when transistor dimensions continue to shrink and this contact resistance becomes a larger portion of the total resistance between source and drain (and thus becomes a significant performance limiting factor). Will not be enough. According to the latest International Technology Roadmap for Semiconductors (ITRS) report released in 2011, it is expected that in 2014, the gate length of transistors will reach 18 nanometers, and the specified contact resistance (specific contact resistance) will not exceed 1.0x10 ^-8 ohms .square centimeter (Ohm.cm ² ), but there is no known solution to solve the problem of contact resistance in bulk MOS transistors. It is increasingly shown that it is necessary to reduce the Schottky energy barrier at the metal-semiconductor contact in order to reduce the contact resistance to an acceptable level. Taking the doped source/drain contacts of MOS transistors as an example, the contact resistance needs to be much lower than 1.0x10 ^-8 ohms. cm2. The technique of reducing the Schottky energy barrier and thus the resistance of contact with doped semiconductor regions can also be applied to so-called "metal source/drain transistors", which do not have a doped source and drain, but use the direct contact between the metal and the transistor channel (the transistor channel is a region containing free carriers, which can be controlled by the voltage on the gate and between the source and drain passing current between them).

In the literature published between 1991 and 1992, it was reported that Baroni, Resta, Baldereschi and other scholars made experimental confirmation of theoretical predictions. Experiments proved that a double intralayer formed by two different elements can establish an interface couple pole, which can not only modify the discontinuities of the heterojunction band discontinuities, but also generate band discontinuities in the homojunction. McKinley et al., J. Vac. Sci. Technol, May/June, No. A9(3), 1991, entitled "Controlling Ge Homojunction by Ultrathin Ga-As Dipole Layers". In the article "Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers)" and in the 1992 "Applied Surface Science" journal 56-58, pages 762-765 and titled "By ultrathin Ga-As dipole layers)" Thin Ga-As dipole layers control Ge homojunction band offsets (Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers)" first reported that Ge homojunctions in {111}-crystal orientation At 035 ~ 0.45 electron volts (eV).

Arsenic, gallium and germanium depositions were performed on p-type Ge(111) substrates at room temperature. The valence energy band shift was measured by in situ core level x-ray photoluminescence. The 3d core orbital domain of germanium (Ge) is split into two parts to confirm that the deposited Ge region (capping layer) has a valence energy band shift with respect to the Ge substrate; one part is caused by the Ge substrate and the other part is is caused by the Ge capping layer. Ga-As dipole inner layers (Ga-As dipole intralayers) can be introduced by using the growth order of "gallium (Ga) priority" or "arsenic (As) priority" to obtain positive valence energy band shift or Negative electricity prices can shift the band. At lower energies (ie, more confined), the band shift was found to be 0.35-0.45 eV, with the Ge valence band edge on the arsenic (As) side of the junction. According to Harrison's "theoretical chain" described in the article titled "Polar Heterojunction Interfaces (Polar Heterojunction Interfaces)" by WA Harrison et al. Alchemy" model to explain the dipole inner layer. Therefore, the use of intralayers to control band discontinuities can be applied to homojunctions to expand the potential field of band shift engineering beyond semiconductor heterojunctions.

In 1992, following the report by McKinley et al., Marsi et al. published the title "Homogeneous Junction Energy Microscopic manipulation of homojunction band lineups", J. Vac. Sci. Technol., J. Vac. Sci. Technol., July/August, 15 February 1992, issue A10(4 ) published an article titled "Homojunction band discontinuities induced by dipolar intralayers: Al-As in Ge using dipolar inner layers: Al-As in Ga" and published in August 1992 An article titled "Local nature of artificial homojunction band discontinuities (Local nature of artificial homojunction band discontinuities)" was published in the "Applied Physics" Journal Issue 72 Volume 4 on March 15. In this first paper, Marsi et al. report that valence-band gaps can be created at Si-Si and Ge-Ge homojunctions when an atomically thick III-V double inner layer is inserted at the interface. continuity. The valence energy band discontinuity was also measured by the in situ core orbital X-ray photoluminescence method. In germanium (Ge) samples, it can be confirmed that the deposited Ge region (cover layer) has an electric valence band shift with respect to the Ge substrate by splitting the 3d core orbital domain of germanium (Ge) into two parts; and by silicon (Si The splitting of the 2p core orbitals of ) can confirm that the deposited Si region has a valence band shift with respect to the Si substrate. The magnitude of the observed discontinuities ranges from 0.4 to 0.5 eV (eg 0.5 eV for Si-P-Ga-Si discontinuities and 0.4 eV for Si-P-Al-Si discontinuities), And although most theories expect dipole effects to cause large valence energy band discontinuities, this result is qualitatively in line with theoretical predictions. If the anions are deposited first, the III-V inner layer located at the IV homojunction systematically induces an artificial valence band discontinuity. It has also been reported that using an aluminum-phosphorus (Al-P) or gallium-phosphorus (Ga-P) inner layer at the Si-Si homojunction as an example, as expected, reversing the deposition order at the interface results in a valence energy band Discontinuity reversed.

In the second paper, X-ray photoluminescence was also used and it was shown that using aluminum-arsenic (Al-As) as a "dipolar inner layer" between two {111}-oriented germanium regions induces Similar band-shifting effects. In particular, an "anion-preferred" sequence of Ge (substrate)-As-Al-Ge (capping layer) yields a shift of 0.4eV, which is consistent with the results reported by McLinley for the "anion-preferred" As-Ga sequence , and the cover layer portion exhibits lower bonding energy compared to the substrate portion. The third article studies the multiple stacking of III-V bilayers (inner layers). The measured valence band offset values for a single bilayer, stacked two bilayers, and stacked three bilayers remained equal at 0.5 eV. The experiments performed on 2(Ga-P) and 2(P-Ga) are exactly the same as those performed on 2(Al-P) and 2(P-Al); changed from a single bilayer to two bilayers Or even changing to three double layers did not observe a substantial increase in the value of the valence energy band offset. It is therefore concluded that stacking multiple III-V bilayers at the interface does not enhance the effect of a single bilayer, contrary to the basic expectations based on multiple consecutive dipoles.

Grupp and Connelly in U.S. Patent Nos. 7,084,423; 7,176,483; There is an interfacial layer at the interface of the group semiconductor, so as to reduce the Schottky energy barrier at the contact and thereby reduce the specific resistivity of the contact. Possible embodiments or embodiments of the interfacial layer may include a monolayer of arsenic or nitrogen.

A notable feature of the present invention is the organization of deliberately introduced Group V or Group III atoms (or Group II or Group VI atoms) in a single ordered (eg, epitaxially oriented) interfacial monolayer. Furthermore, the present invention provides a process and structure in which metal contacts can be formed by deposition without using silicidation, which is characterized by allowing the use of a wider range of metals to form metal-semiconductor contacts, Especially metals with better properties than metal silicides for special applications, such as metals with higher conductivity, light transmission or ferromagnetism. Maximum metal conductivity in metal source/drain FETs is desired as the dimensions of these devices scale down to have critical dimensions (eg, source width and height) of 20 nm or less. Components such as spin-effect transistors in the field of so-called spintronics applications require efficient spin injection from semiconductors into ferromagnetic metals such as gadolinium. A spin-metal-oxide-semiconductor field-effect transistor (spin-MOSFET) with a ferromagnetic metal source and drain and a Group IV semiconductor channel is an example of a spin-effect transistor. In emissive displays it is often desirable to have metal contacts that allow good penetration of emitted light (high transparency) and at the same time can form low resistance contacts to active materials. Conversely, in optoelectronic components (eg, semiconductor lasers or semiconductor modules), it may be desirable for the metal contact resistors to be opaque so as to minimize losses due to light absorption. The undesired property of metal silicides to be somewhat transparent makes it possible for light energy to enter regions of the silicide located in the optical field of the optoelectronic element, causing light to be absorbed in the silicide.

The invention does not require doping of the semiconductor in the vicinity of the metal contacts, but it is also possible to implement the invention together with a semiconductor doping step. The present invention also does not require a metal silicidation step. Devices constructed according to embodiments of the present invention contain at least one ordered monolayer of Group V elements and/or an ordered monolayer of Group III elements at the interface between the semiconductor and metal contacts. The metal is deposited after forming at least one ordered monolayer of interfacial atoms.

Embodiments of the present invention provide an electrical contact between a Group IV semiconductor characterized by its crystalline lattice structure and single atoms formed by one or more atoms of a Group V material with one or more monolayers disposed between the metal and the metal. layer or a monolayer of monoatomic layers formed from one or more Group III material atoms, each monoatomic layer being epitaxially aligned with each other and of the semiconductor lattice; and embodiments of the present invention provide for forming such method of electrical contact.

A further embodiment of the invention provides an electrical contact comprising a metal and a Group IV semiconductor separated at the interface between the metal and the semiconductor by a monolayer of Group V atoms and optionally a monolayer of Group III atoms. Separate the metal and the semiconductor. The metal may be made of the same metal element atoms as the Group III metal atom monolayer, or the metal may be made of a metal element atom different from the Group III metal atom monolayer. In some examples, the group III atom can be any one or more of aluminum, gallium, indium, or boron, or a mixture of aluminum, gallium, boron, and/or indium. The group IV semiconductor can be: germanium, silicon, alloys of germanium and silicon, alloys of germanium and tin, silicon containing carbon and/or alloys or compounds of germanium. The group V atoms include any one or more of the following: nitrogen, phosphorus, arsenic and antimony. In some instances, a monolayer of Group III atoms will be proximate to the surface of the Group IV semiconductor. In other examples, a monolayer of Group V atoms will be proximate to the surface of the Group IV semiconductor. The surface of the Group IV semiconductor may be a {111}-oriented surface or a {100}-oriented surface.

The present invention also includes methods of forming electrical contacts such as those described above. In some examples, the method involves etching the {100}-oriented surface of the Group IV semiconductor using a crystallographically selective etch to uncover and expose one or more {111}-oriented surfaces. a semiconductor crystal plane; forming a monolayer of group V atoms on the {111} crystal plane; and subsequently depositing a monolayer of group III atoms on the monolayer of group V atoms. The group V and/or group III atomic monolayers can be fabricated by means of individual vapor deposition processes or individual chemical reactions. For example, in processes performed under ultra-high vacuum (UHV) conditions, the {111}-oriented crystal planes of the semiconductor may be cleaned in situ, as appropriate, prior to deposition of the group V atoms or group III atoms , and heat the semiconductor to a high enough temperature to obtain a rearranged structure, take {111} silicon surface as an example to obtain 7x7 rearranged structure, or take {111} silicon germanium surface as an example to obtain 5x5 rearranged structure, or take {111 A germanium surface for example can obtain a 2x8 recombination structure, after which the semiconductor can be heated to an elevated temperature during the deposition of group V atoms and/or group III atoms. After forming the first monolayer of Group V atoms and the first monolayer of Group III metal atoms, metal atoms may be deposited directly on the first bilayer (two monolayers), or deposited in the presence of metal atoms Additional monolayers of group V atoms and/or monolayers of group III atoms may be added to build up a stack of monolayers beyond a single bilayer prior to contact formation.

The above and further embodiments of the present invention are described in further detail below.

In view of the above-mentioned challenges, the inventors of the present invention realized that there is a need for a metal contact technology that can reduce the resistance of the metal contact to the doped S/D region, or a metal-semiconductor that can eliminate the Schottky energy barrier between the metal and the semiconductor as much as possible. technology. The low resistance metal-semiconductor contact technology will be used in any application requiring low resistance, for example in solar cell applications and in metal S/D field effect transistors (FETs). The present invention relates to the interface between a metal and a semiconductor by inserting a monolayer of group V or group III atoms, or a double layer formed by a monolayer of group V atoms and a monolayer of group III atoms , or techniques for lowering the specific contact resistance of metal-(Group IV) semiconductor junctions by inserting multiple such bilayers. The present invention includes a method of forming such a metal-semiconductor contact with an extremely low energy barrier height (close to zero) and an extremely low specific contact resistance by providing at least one single ordered atomic layer at the interface between the metal and the semiconductor. The formed low-resistance metal-Group IV semiconductor junction can be applied in semiconductor elements (including electronic elements, such as transistors, diodes, etc.) and optoelectronic elements (such as lasers, solar cells, light detection device) as low resistance electrodes, and/or can be applied in field effect transistors (FETs) as metal source and/or drain regions (or part of source/drain regions). A monolayer of Group V or Group III atoms adjacent to a semiconductor surface is primarily a layer of ordered atoms formed on and chemically bonded to the Group IV semiconductor surface.

The present invention differs from the earlier work of Grupp and Connelly (cited above) in that the focus of the present invention is on ordered monolayers, and the presence of a group V element (for example, phosphorus or antimony) and a group III element ( For example, aluminum, boron, gallium or indium). Furthermore, the work of Marsi et al. and McKinley et al. cited above states that an energy band shift is intended to be created between two regions of a semiconductor, without mentioning modification of the Schottky energy between the metal and the semiconductor. obstacles or even mention the possibility of doing so.

As described below, when both group III atoms and group V atoms are present, the double layer formed provides an electric dipole between the semiconductor and the host metal. Similar dipoles also arise when there is only a single group V atomic layer due to the formation of image charges within the host metal. Furthermore, in certain examples, multiple bilayers (eg, two or three such bilayers) can be used between the semiconductor and the host metal. Indeed, the dipole layers can be increased until the atoms rearrange themselves due to excess energy generated with increasing field.

Furthermore, although monolayers formed of pure Group V or Group III species are described herein, certain embodiments of the invention may employ a mixture of phosphorus atoms) or a monolayer of more than one group III atom. Therefore, when referring to a monolayer (whether part of a bilayer or otherwise) in the following and in the claims, the term should be deemed to cover a monolayer formed from a single type of Group V or Group III atom And monolayers formed of more than one group V or group III element atoms.

In the examples described herein, the semiconductor is a Group IV semiconductor, such as germanium, silicon, an alloy of silicon and germanium, or an alloy containing two or more of silicon, germanium, carbon and tin. Field Effect Transistors (FETs) or other electronic components made of compound semiconductors may also benefit from the use of the low resistance junctions provided in accordance with the present invention. Also in the following examples, it is described that the metal forming the interface with the semiconductor (and the interfacial layer formed by the ordered arrangement of Group V atoms) is a Group III metal. However, this is not necessarily the case. The metal does not have to be a Group III metal. Other metals such as low work function metals such as magnesium, lanthanum, ytterbium or gadolinium can also be used to obtain a low potential (low electric energy) energy barrier or high hole potential energy between the metal and the semiconductor barrier. Alternatively, a metal with a high work function, such as nickel, platinum, iridium, or ruthenium, can be selected to obtain a low hole barrier or a high electron barrier between the metal and the semiconductor. However, this does not exclude the use of higher work function metals such as platinum or ruthenium to make contacts with a low electronic energy barrier. Although the metal has a high work function, the fermi level of the metal is aligned with the semiconductor conduction band by creating a large dipole due to the presence of an ordered Vth element monolayer at the semiconductor interface. ) may have a very low energy barrier.

In many applications, the same metal is used to make contacts to both p-type and n-type doped semiconductor regions, such as forming source contacts and Drain contacts may be advantageous. In addition, the above approach is useful for barrier metals (for example, tantalum nitride (TaN) or titanium nitride (TiN) or ruthenium (Ru)) and will be used to fabricate both p-type and n-type doped semiconductor regions. It may also be extremely beneficial in terms of the metals that are in contact with them. In instances where the same metal is used to form low-barrier contacts for both the p-type and n-type doped semiconductor regions, the interfacial monolayer chemically bonded to the semiconductor surface will be the first in the order at the n-type contact. A group V atom interface layer, and what will be an ordered group III atom interface layer at the p-type contact. Likewise, when the same metal is used to form the metal source and/or drain of both n-channel and p-channel metal source/drain MOSFETs, the interfacial monolayer chemically bonded to the semiconductor surface will be at the Ordered group V atomic interface layer at source/drain junction of n-channel MOSFET and will be ordered group III atomic interface at source/drain junction of p-channel MOSFET layer.

Metal-semiconductor contacts with high spin injection efficiency can be obtained using ferromagnetic metals such as gadolinium, iron, nickel or cobalt or alloys of these elements or ferromagnetic alloys of manganese. In special applications where high electron spin injection efficiency is desired, the interfacial layer chemically bonded to the semiconductor surface is preferably an ordered interfacial layer of Group V atoms. A ferromagnetic metal can be deposited directly on the Group V monolayer, or a Group III metal monoatomic layer can be chemically bonded to the Group V atoms and a ferromagnetic metal deposited on the Group III monolayer.

Other metal materials can also be used, including alloys of pure metals, metal silicides (for example, nickel silicide or platinum silicide or cobalt silicide with the composition _Ni2Si , NiSi or _NiSi2 ) or even semimetals where the metal material is directly Adjacent to the Group V or Group III monolayer. In manufacturing, both the n-type and p-type semiconductor contacts use the same metal material, or use the same metal material as the metal source and/or drain of both n-channel and p-channel MOSFETs. feasible and probably the most convenient.

The ordered atomic monolayer may be an ordered group V atomic monolayer in order to obtain the desired metal-semiconductor contact with an extremely low energy barrier height for electrons throughout the contact and an extremely low resistance for electron conduction. The group V atom may be a nitrogen atom, a phosphorus atom, an arsenic atom or an antimony atom or a mixture of these group V atoms. In one embodiment of the present invention, the group V atomic monolayer is an atomic layer of arsenic, and the atomic layer of arsenic is epitaxially (or substantially epitaxially) aligned and aligned with the crystal lattice of the germanium or silicon or IV semiconductor alloy . Such extremely low-resistance contacts for electron conduction can be used to make electrical contact with n-type doped semiconductors (for example, n-type doped source and drain regions of n-channel FETs), or to make Metal source/drain regions (the metal source/drain regions are in direct contact with the electron channel in the n-channel FET).

In many instances, the metal contact is formed on the surface of the Group IV semiconductor and the surface of the Group IV semiconductor will be a {111}-oriented surface, and to the greatest extent possible, between the single ordered arrangement Each group V atom in the atomic layer forms a chemical bond with an atom in the {111} oriented surface of the semiconductor in a three-way coordination manner. However, in other examples, the contact surface of the Group IV semiconductor will be a {100} or {110} surface. In some instances a {100} surface may be preferred.

Before discussing embodiments of the invention in detail, it is helpful to review some underlying theory. At the contact interface between the metal and the semiconductor, it can be observed that the Fermi energy in the metal will be "pinned" at a specific energy in the energy gap of the semiconductor, causing each semiconductor to be at the Fermi level of the metal. An energy barrier is formed between the conduction energy band or the valence energy band in the semiconductor. Although the semiconductor is capable of conducting (e.g., with dopants), as shown in Fig. (1a), this Fermi energy _EF is fixed close to the semiconductor band edge E _C in the bulk crystal (when no voltage is applied, _EF is uniform throughout the system), _EC remains much higher than _EF at the interface. Therefore, the region of the semiconductor near the interface cannot be a good conductor. Only weak currents can flow between the metal and the highly conductive regions of the semiconductor. Electron flow into the conduction band can be conducted by thermionic emission (crossing the energy barrier by excitation) or by tunneling the energy barrier, and when the width of the energy barrier may be only tens of angstroms (Angstrom ), the tunneling probability tends to be smaller. More broadly, electrical current can be conducted between the metal and semiconductor by so-called "thermionic field emission", ie thermionic emission combined with tunneling of electrons across the energy barrier.

The present invention aims to eliminate or at least substantially reduce this energy barrier by inserting an electric dipole layer between the metal and the semiconductor, shifting the relative position of the band edge and the Fermi energy at the interface. The final energy is shown in Figure 1(b). The net result is that almost all of the energy barrier region is removed, leaving only the energy barrier region between the dipole layers.

Using the revised edition (2004) of "Elementary Electronic Structure" (Elementary Electronic Structure) written by WA Harrison of World Science Publishing House (Singapore, 1999) and the "Physical Review" journal (Phys. Rev. B 18, 4402) titled "Polar Heterojunction Interfaces (Polar Heterojunction Interfaces)" described in the "theoretical alchemy" can best understand how to complete the silicon-metal interface. Imagine removing a proton from each silicon nucleus that lies in the plane closest to the metal, converting the silicon nucleus to an aluminum nucleus (one of the elements on the left in the periodic table) and inserting the proton into the silicon lattice In the silicon core in the penultimate plane of , so that the silicon core becomes a phosphorus core. This method can effectively create a sheet of negative charges in the atomic plane closest to the metal and a sheet of positive charges in the penultimate plane, and form a dipole between the two atomic planes with a large electric field . In fact, this electric field will polarize the bonds in this layer, so that the bonds in this layer will shrink to the inverse multiple of the dielectric constant (1/12 = 0.083 for silicon), but the result is as in Section 5(a) The figure still has a large electric field and a large potential shift. In fact, not only the bonds in this dipolar layer are polarized, but also the bonds in adjacent layers, changing the effective charge of all atoms in the region and making the electric field become as in 5(b) As shown in the figure. However, a very similar net potential shift (estimated to be about 1.39eV for the (100) plane in silicon, with a bond length d = 2.35 Å) is sufficient to remove the major energy barrier.

We can repeat the process of theoretical alchemy, removing another proton from the aluminum nucleus, making the aluminum nucleus a magnesium nucleus, and inserting the proton into the phosphorus nucleus, making the phosphorus nucleus a sulfur nucleus. Applying the same concept, this doubles the charge on each plane and doubles the dipole offset. This is equivalent to inserting the plane of atoms in column II of the periodic table and inserting the plane of atoms in column VI instead of columns III and V. Even this method can be applied for the third time to insert the NaCl layer, but in the present invention, in most cases, this kind of deposition may make the silicon structure unable to maintain and continue to maintain the epitaxy, so that it is possible to form a neutral NaCl rock-salt plane, rather than a dipole layer. On the other hand, certain noble metal halides do form the tetrahedral structure of silicon, and it is expected that these noble metal halides can be grown epitaxially, corresponding to monolayers of elements in column VII and elements in column IB (noble metals) monolayer, and its dipole shift is estimated to be three times that of an aluminum-phosphorus (Al-P) bilayer. Therefore, the invention also includes the dipole shifts caused by the epitaxial layers in columns VI, VII, II and IB and in columns V and III.

If instead of theoretically converting the last two planar silicon atoms into phosphorus and aluminum, an actual single atomic layer of phosphorus or any other element of column V is inserted between the silicon and the metal and aluminum or other For single atomic layers of elements in column III, the result will not change. Any suitably corresponding Group V-Group III material bilayer can be used for the purpose of eliminating (or at least substantially reducing) the Schottky barrier, and such material bilayers can be selected based on convenience or other considerations, And likewise, any of the elements in columns IB, II, VI and VII can achieve the same effect as the elements mentioned in the above paragraphs. More specifically, ordered monolayers of group VI elements-sulfur and/or selenium and/or tellurium can be deposited in combination with ordered monolayers of group II elements-zinc and/or cadmium to form ordered II -Group VI double layer.

Returning now to Figure 2, Figure 2 illustrates a process example 10 for forming metal contacts with very low resistance to a semiconductor surface. In this process, a {100}-oriented surface of a Group IV semiconductor (or a compound or alloy of a Group IV semiconductor and/or carbon) is used (step 12), and the {100} is etched using a crystallographically selective etching method. - Orienting the surface to uncover and expose one or more {111}-semiconductor crystal planes (step 14). Subsequently, a monolayer of group V atoms is formed on the {111}-plane (step 16), followed by deposition of an appropriate group III metal (step 18) to form the contact. It should be noted that the monolayer of group V atoms is not necessarily a perfectly ordered monolayer. That is, the monolayer of Group V atoms may have some gaps or a slight excess of atoms in coverage. In other words, after depositing the ordered monolayer, some dangling bonds of the Group IV semiconductor may remain unsatisfied, or the number of Group V atoms exceeds the number of dangling bonds of the Group IV semiconductor earlier, Or a portion of the semiconductor or Group V atoms at the surface become disordered and fail to align with the semiconductor lattice. However, any of the foregoing is still considered a usable Group V atomic monolayer for the purposes of the present invention.

In an alternative process to that described in FIG. 2, the metal atoms in step 18 may be metal atoms other than Group III metal atoms. For example, the metal can be an alloy of pure metals, a metal silicide or a metal compound.

The group V atomic monolayer can be fabricated by vapor deposition process or chemical reaction. In one example of a vapor deposition process, the process includes exposing the semiconductor to a flow of the Group V atom vapor or a molecular flow of the Group V element at an elevated temperature. The Group V atom/molecular gas stream can be generated by vaporizing the source of Group V elements using heat. In one embodiment of the invention, the gas flow is a molecular flow of arsenic with a composition _As4 and can be utilized in a Knudsen cell (k-cell) in a manner known to practice molecular beam epitaxy. The heat vaporizes the elemental arsenic source to generate the _As4 molecular stream.

Various fabrication methods that can be used to deposit Group V and/or Group III monolayers include molecular beam epitaxy (MBE), gas source molecular beam epitaxy (GSMBE), metalorganic molecular beam epitaxy (MOMBE), Metalorganic chemical vapor deposition (MOCVD), metalorganic vapor phase epitaxy (MOVPE), atomic layer deposition (ALD), atomic layer epitaxy (ALE) and chemical vapor deposition (CVD), including electrodeposition Crystal-enhanced chemical vapor deposition (PECVD) or photon or laser-induced chemical vapor deposition (photon or laser-induced CVD).

Other vapor deposition processes that may be used in accordance with embodiments of the present invention involve depositing atoms of the Group V element on the semiconductor surface by dissociating the gas phase compound of the Group V element (eg, a Group V element hydride) . Suitable Group V hydride gases include ammonia (NH ₃ ) for the deposition of ammonia atoms, phosphine (PH ₃ ) for the deposition of phosphorus, arsine (AsH ₃ ) for the deposition of arsenic, and Antimony atomic layer of antimony hydrogen (SbH ₃ ). Alternatively, the gas-phase compound of the desired Group V element may be an organometallic compound, an example of such a compound being an alkyl arsine such as tertiary butyl arsine for the deposition of arsenic monolayers , or alkyl antimonides such as triethylstibine for the deposition of antimony monolayers.

During processing under ultra-high vacuum (UHV) conditions, the silicon with {111}-oriented crystal faces can be cleaned in situ before exposing the silicon to the vapor flow of the group V atoms or compounds, and the The silicon is heated to a temperature high enough to obtain a 7x7 rearrangement of the {111} silicon surface. Figure 3(a) (perspective view), Figure 3(b) (plan view of the original unit cell), and Figure 3(c) (side view of the original unit cell) provide views of such a 7x7 surface 20 . Atom 22 represents an atom in the underlying (1x1) host silicon material. Atom 24 represents a so-called rest atom (a layer of atoms located below an adatom). Atom 26 represents a dimer (paired surface silicon atoms). Atom 28 represents an attachment atom (silicon atom placed on the surface of the crystal). Reference numeral 30 then indicates a corner hole in the structure.

Thereafter, the silicon is maintained at a temperature in the range of about 20° C. to 750° C., both inclusive, during the period during which the silicon is exposed to the Group V atomic vapor or the Group V compound molecular vapor. The silicon surface may be exposed to a stream of group V atom or compound molecule vapor for one or several seconds or even several minutes. Keeping the silicon at an appropriate temperature forms an ordered monolayer of Group V atoms, and after formation, the monolayer prevents the deposition of additional Group V atoms or the deposition of other atoms (such as hydrogen or oxygen or carbon atoms) . Alternatively, the temperature of the semiconductor may be varied during exposure of the semiconductor to vapors of Group V atoms or Group V molecular compounds such that the temperature of the semiconductor begins to drop from a high temperature in the range of 600° C. to 800° C. to between 500° C. Lower temperatures in the range of °C to 20 °C.

As shown in FIG. 4, Group V atoms 32 (e.g., As, Sb, or P) bond directly to exposed silicon surface atoms 34 to form fully coordinated lattice terminations with no overhangs to the greatest possible extent. bond, Figure 4 is a side view of the resulting structure. Three of the 5 valence electrons of each group V atom form a bond with the silicon atom at the surface of the group IV semiconductor, and the remaining two valence electrons form "lone electrons" as shown in the figure pair (lone-pair) orbital.

Similar processes can be applied on silicon surfaces other than the {111} orientation, eg, {100} orientation, to obtain a monolayer of group V atoms. A similar process can also be applied on the surface of Group IV semiconductors other than silicon, for example on semiconductors including germanium, silicon germanium, silicon carbon, germanium tin or silicon germanium carbon, to obtain monolayers of group V atoms. In addition, a similar process can also be applied on the surface of a group IV semiconductor to obtain a monolayer of group VI atoms.

The heated semiconductor surface may be exposed to a flow of Group V atoms or compound molecules in an ultra-high vacuum (UHV) chamber, in a vacuum chamber, or in a reduced pressure chamber. If the process is performed in a chamber other than a UHV chamber, background or carrier gas may be present during the exposure. In one embodiment, arsine (AsH ₃ ) is delivered in dilute form as a gas mixture consisting essentially of hydrogen (H ₂ ) or nitrogen (N ₂ ). In the semiconductor manufacturing process, arsine is generally diluted to a concentration of several percent or even as low as 100ppm, or arsine is diluted to a concentration of several percent or even as low as 100ppm in ultra-pure hydrogen or nitrogen . Whether it is pure arsine or a diluted mixture containing 1% or several percent arsine in hydrogen or nitrogen, arsine will dissociate at the heated semiconductor surface to release free arsenic atoms, free Arsenic atoms bond directly to the exposed silicon surface to form fully coordinated lattice terminations with no or minimal dangling bonds.

A preferred process for depositing a monolayer of arsenic atoms on silicon with a hydride precursor gas (AsH ₄ ) begins by heating the silicon surface in a hydrogen atmosphere to a temperature sufficient to reduce any surface oxide, and then the silicon The surface is heated to a temperature in the range of 650°C to 750°C (optimally 675°C to 725°C) while exposing the surface to _AsH4 vapor for a period of between 10 seconds to 30 minutes (optimally between 20 seconds and 2 minutes). This process can be performed in a CVD system or an ALD system, and an ordered monolayer of arsenic atoms is formed. After this forming step, the monolayer resists the deposition of additional group V atoms or the deposition of other atoms such as hydrogen or oxygen or carbon atoms. Or the temperature of the semiconductor can be varied during the exposure of the semiconductor to _AsH vapor, starting from a high temperature in the range of 650°C to 750°C to a lower temperature in the range of 500°C to 20°C temperature.

As noted above, it is not strictly required that the Group V atoms form a perfect monolayer. Metal can be deposited on this Group V monolayer, or more silicon can be deposited followed by metal. Thus, there may be a charge monolayer at the interfacial layer (as above) or, if one, two or three silicon atomic layers are deposited respectively after the group V monolayer and before the metal - There may be a charge monolayer at the second, third or fourth plane from the metal interface. The advantage of having one or more layers of silicon atoms between and thereby separating the charged group V atom (ion) monolayer from the metal atom is that the metal atom can be increased The galvanic couples established between the layers are extremely small, and thus the Schottky energy barrier for electrons at the metal-semiconductor junction can be reduced considerably. On the other hand, the disadvantage of using one or more layers of silicon atoms to separate the charged group V atom (ion) monolayer from the metal atoms is that the dipole region has a large spatial extent that is not conducive to conducting charge across the energy barrier. . The only conceivable advantage of having a layer of silicon atoms between the group V atoms and the metal atoms is that it can be used in applications with a large Schottky barrier for p-type semiconductors.

In the embodiment shown in FIG. 5, after forming a coordinated monolayer 38 of group V atoms on the surface of the {111}-oriented group IV semiconductor 36, a monolayer 40 of group III atoms is deposited, followed by The metal contact (host metal atoms 42) is deposited to provide a low energy barrier and low resistance metal contact. In this embodiment of the invention, the monolayer 40 of metal atoms is a group III metal atomic layer, which may include aluminum, gallium or indium or a mixture of these group III metal atoms. In other embodiments of the invention, metals or metal alloys other than Group III metals may be used, or metals or metal alloys other than Group III metals may be used in combination with Group III metals. This monolayer of Group III metal atoms is optional and does not necessarily have to be present in all junctions formed in accordance with the present invention, the image charge formed in the host metal ) will be a balancing negative charge (further explained below).

If there is a monolayer of Group III metal atoms, the metal atoms in the monolayer of metal atoms preferably form a coordination with the monolayer of Group V atoms already present on the semiconductor surface, thereby forming an ordered layer of metal atoms. However, embodiments are also possible in which the metal atoms of the first layer form strong coordination bonds with the underlying Group V atom ordering layer without chemical bonding. The process then continues to deposit additional metal atoms 42, which may be the same metal element as the first layer of metal atoms or a different metal element than the first layer of metal atoms. Figure 5 illustrates the structure obtained if atoms 40 and 42 are the same element.

FIG. 5 shows a double layer comprising a monolayer 38 of group V atoms and a monolayer 40 of group III atoms disposed between the semiconductor atoms 36 and the host metal 42 . The graphs (a) and (b) in the figure represent the potential energy at different positions across the junction, and the graph (a) shows the first step in the theoretical alchemy that does not polarize adjacent bonds, And graph (b) is a curve drawn considering the relaxation effect (relaxation). Curve (b) is slightly exaggerated to emphasize the nature of the potential across the junction.

The group III metal atom monolayer can be fabricated by vapor deposition process or by chemical reaction. For example, in the example of a vapor deposition process, the metal atomic monolayer may be formed on the semiconductor surface by exposing the semiconductor surface to a stream of atomic vapors of a Group III metal element or a vapor stream of a compound of the metal element. . This exposing step can take place for less than a second or for as long as several seconds or even minutes.

The vapor deposition process may involve exposing the semiconductor having a monolayer of group V atoms to a stream of metal atom vapor or a stream of metal element molecules. The flux of metal atoms/molecules can be generated by vaporizing the metal source using heat. In one embodiment of the invention, the gas flow is accomplished by thermally evaporating the source of elemental aluminum in a Knudsen crucible (k-cell) or by heating the elemental aluminum using an electron beam, as is known in the practice of molecular beam epitaxy. A stream of aluminum atoms produced by evaporating it from a source. The semiconductor may be heated during deposition of the metal atoms. In an alternative vapor deposition process, vapor phase compounds of the metal (eg, organometallic compounds) can be dissociated to deposit the metal atoms on the semiconductor surface. Such processes are most commonly classified as chemical vapor deposition processes. Suitable organometallic compounds of aluminum include trimethylaluminum. More specifically, when a monolayer of metal atoms is deposited by dissociating a source of chemical vapor, if the metal atoms are epitaxially aligned and aligned with the semiconductor lattice, the process is called atomic layer epitaxy, or if the If some metal atoms are arranged epitaxially, the method is atomic layer deposition. In an alternative vapor deposition process, the metal atoms may be deposited by sputtering the metal atoms from a solid source, known as a physical vapor phase (PVD) process.

After depositing the monolayer of metal atoms, the process continues to deposit additional layers of metal atoms (the metal atoms and the monolayer of Group III atoms may be the same metal or different metals). The elemental composition and thickness of the additional metal atomic layer can be determined according to the requirements of the particular application of the metal-semiconductor contact being made. For example, as a contact of a nanoscale FET, the additional metal atomic layers may be barrier metal layers, such as tantalum nitride, titanium nitride or ruthenium. In common terms used herein and in the microelectronics industry, barrier metals are metals deposited typically using conformal deposition techniques such as atomic layer deposition (ALD), plasma-enhanced ALD, or chemical vapor deposition (CVD). The resulting thin metal layer provides a barrier against the diffusion of the copper metal layer into the semiconductor. Alternatively, the barrier metal may be deposited using an electrochemical deposition process or using reactive physical vapor deposition (PVD), which sputters the metal from a solid source or target. In an alternative embodiment, the additional atomic layer of metal may consist of a metal silicide, such as nickel silicide, platinum silicide, nickel platinum silicide, or cobalt silicide, of composition _Ni2Si , NiSi, or _NiSi2 , wherein the metal Silicide is directly adjacent to the Group V single layer or Group V-Group III bilayer.

In addition to depositing a monolayer of Group V material (e.g., arsenic, phosphorus, etc.) on the silicon surface as previously described, it is advantageous to deposit a portion of the Group V material at a sufficiently At high temperatures, some of the group V atoms get incorporated into the silicon itself. Alternatively, the silicon surface can be prepared in other known ways such that the group V is present close to the silicon surface. After this step, the Group V material is deposited in a suitable manner to form a monolayer on the silicon surface. The purpose of this is to favor the extra group V atoms in the silicon to form additional dipoles and have image charges in the metal deposited on the monolayer of the group V material, which helps to increase the overall dipole effect.

Figures 6(a) and 6(b) are further examples of metal-semiconductor contacts constructed according to embodiments of the present invention. In Figure 6(a), the contact 44 is similar to the contact shown in Figure 5, but the contact 44 includes an additional double layer formed of a Group V element and a Group III metal. An electric dipole is created across the long interlayer spacing (ie, the relatively long distance between the monolayers 38 and 40 that make up the bilayer). In Figure 6(b), contact 44' has an electric dipole spanning the short interlayer spacing (i.e., the relatively short distance between monolayer 38 and monolayer 40 making up the bilayer).

As shown in Figure 7, in order to obtain a metal-semiconductor contact with an extremely low energy barrier height for holes and an extremely low resistance for conduction holes through the contact, the ordered atomic monolayer is an ordered metal The atomic monolayer 40 also includes a monoatomic layer 38 of Group V atoms that is chemically bonded to the metal atomic monolayer and separated from the surface atoms of the semiconductor 36 by the metal atomic monolayer 40 . In some embodiments, the monoatomic layer formed by the metal atoms is a monolayer of Group III metal atoms, and the Group III atoms may be aluminum atoms, gallium atoms, or indium atoms or a mixture of these Group III metal atoms . In some examples, the Group III metal atom monolayer is an atomic layer of indium, and the atomic layer of indium is epitaxially (or substantially epitaxially) aligned and aligned with germanium or silicon or a Group IV semiconductor alloy crystalline lattice, and in phase Adjacent group V atom monolayers are chemically bonded to the metal atom monolayer. The group V atom may be a nitrogen atom, a phosphorus atom, an arsenic atom or an antimony atom or a mixture of these group V atoms. In some examples, the monolayer of Group V metal atoms is an atomic layer of arsenic, and the atomic layer of arsenic is arranged in order and aligned and chemically bonded with the Group III metal atoms, and the Group III metal atoms form a monolayer of atomic layer and forms crystalline alignment and chemical bonding with the surface atoms of the germanium or silicon or IV semiconductor alloy crystalline lattice. Two bilayers are shown between the semiconductor and the host metal, but embodiments comprising a single bilayer are also contemplated within the scope of the invention.

In some embodiments, it is desirable to form a very low resistance contact to the p-type semiconductor or to provide a very high conductivity source and/or drain for use in a p-channel field effect transistor, the contact The surface is a {111}-oriented semiconductor surface. In other embodiments, the contact surface of the semiconductor is a {100} oriented surface.

FIG. 8 illustrates a process 45 for establishing the contacts shown in FIG. 7 . Starting with a {100}-oriented semiconductor surface (step 46), the {100} surface is etched using a crystallographically selective etch to uncover and expose one or more {111}-oriented semiconductor planes ( Step 48). A monolayer of Group III metal atoms is formed on the {111} crystal face (step 50), followed by deposition of a monolayer of Group V atoms (step 52). Obviously, based on different device geometries or other considerations, the process can be directly started from the existing {111} surface.

After depositing the Group V atomic monolayer, the process continues to deposit additional metal layers (step 54). The elemental composition and thickness of this additional metal atomic layer can be determined according to the requirements of the specific application of the metal-semiconductor contact being made, and can be formed as described above for n-type semiconductors with very low resistance to electron conduction. .

Group III atomic monolayers can be fabricated using vapor deposition processes or chemical reactions. In one example of a vapor deposition process, the semiconductor is exposed to a vapor stream of the Group III metal atom or a molecular stream of the Group III metal element compound. The Group III atom/molecular gas stream can be generated by thermally evaporating a source of Group III elements. In one embodiment of the invention, the gas flow is a stream of indium atoms generated by thermally evaporating a source of elemental indium in a Knudsen crucible (k-cell) as is known in the practice of molecular beam epitaxy. In an alternative vapor deposition process, a vapor phase compound of a Group III element (eg, an organometallic compound of a Group III element) can be dissociated to deposit Group III atoms on the semiconductor surface. Dissociation of the gas-phase precursor of the Group III metal can be achieved by heating the semiconductor surface. If it is inappropriate to heat the semiconductor surface to a high temperature, plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD) type tools and processes can be used to achieve dissociation. Alternatively, a photon-induced process can be used to achieve dissociation of metal precursors.

Semiconductors with {111}-oriented surfaces, such as silicon, can be cleaned in situ before exposing them to a stream of Group III atoms or Group III molecular compounds. For example, the semiconductor can be heated to a high enough temperature under ultra-high vacuum conditions to obtain a 7x7 rearrangement of the {111} silicon surface. Subsequently, the semiconductor is maintained at a temperature in the range of about 20°C to 750°C, inclusive, during the period of exposure of the semiconductor to the Group III atom vapor or Group III molecular compound vapor. Alternatively, the temperature of the semiconductor may be varied during the exposure of the semiconductor to the Group III atom vapor or Group III molecular compound vapor such that the semiconductor temperature begins to drop from a high temperature in the range of 600°C to 800°C to between Lower temperatures in the range of 500°C to 20°C.

The semiconductor may be exposed to the Group III atom or compound vapor stream for a period of less than one second or as long as several seconds or even minutes. The Group III atoms are directly bonded to the exposed Group IV semiconductor surface to form a monolayer of Group III atoms, and the crystals of the Group III atoms are aligned to the semiconductor lattice to the greatest extent possible.

The surface of the semiconductor may be exposed to the flow of Group III atoms or molecular compound vapors in a UHV chamber, in a vacuum chamber, or in a reduced pressure chamber. If the process is performed in a chamber other than a UHV chamber, background or carrier gas may be present during the exposure. In one embodiment, the organometallic compound precursor (e.g., trimethylindium) is delivered in diluted form in a gas mixture consisting essentially of a carrier gas (e.g., hydrogen or nitrogen), and the organometallic compound precursor is The heated semiconductor surface dissociates to release free indium atoms, which are directly bonded to the exposed silicon. In another embodiment, the organometallic compound is trimethylaluminum or trimethylgallium, which react at the heated semiconductor surface to form a monolayer of aluminum atoms or gallium atoms, respectively single layer.

After forming a coordinated monolayer of Group III metal atoms on the surface of the {111}-oriented Group IV semiconductor, a monolayer of Group III atoms 40 is deposited, followed by a layer of Group V atoms to form a low energy barrier, low Resistive metal contacts. The group V atoms in the group V atomic layer are preferably coordinated with a monolayer of group III metal atoms on the surface of the semiconductor, thereby forming an ordered group V atomic layer. The process then continues to deposit additional metal atoms, which may be the same metal element as the first layer of metal atoms or a different metal element than the first layer of metal atoms.

In another embodiment of the invention, after formation of a monolayer of coordinated Group III metal atoms on the surface of a {100} or {111}-oriented Group IV semiconductor, deposition of metal to form a low-barrier, low-resistance metal contact. The metal need not be a Group V metal. The metal may be a metal with desirable properties, such as structural or chemical stability to ensure the reliability of the formed electrical contacts or electronic components. Examples of stable metals used to form contacts include platinum (Pt), tungsten (W), and the aforementioned "barrier metals": TaN, TiN, and Ru. The metal can be deposited directly on the Group III monolayer so that the Group III monolayer is located just at the interface between the metal and the semiconductor, or the Group IV semiconductor monolayer can be separated by one or two Group IV semiconductor monolayers. Group III monolayer with the metal. Thus, if one or two Group IV semiconductor atomic layers are interposed between the Group III monolayer and the metal, respectively, there may exist at the interface layer or at the third plane from the semiconductor-metal interface There is a monolayer charge brought by the III monolayer. The advantage of having one or several layers of silicon atoms between the charged III atom (ion) monolayer and the metal atoms and thereby separating the charged III atom (ion) monolayer from the metal atom is that the The galvanic couples established between the layers are extremely small and thus significantly reduce the Schottky energy barrier at the p-type semiconductor junction or the metal and p-type channel source/drain junctions of MOSFETs.

Another embodiment of the present invention forms a metal-semiconductor contact having a monolayer of Group V or Group III atoms at the metal-semiconductor interface and at the metal-semiconductor interface by Group V or Group III atoms are segregated from the material layer in contact with the semiconductor surface to form the Group V (eg, arsenic) monolayer or Group III (eg, boron) monolayer. The layer of material may be deposited on the semiconductor surface, for example using CVD or PVD. The Group V atoms are introduced into the material layer by incorporating the Group V atoms as dopants in a CVD or PVD deposition process or by ion implantation. Or the material layer can be formed by reacting another element or elements with the semiconductor surface, in which case the Group V or Group III can be implanted before or after the material is formed by chemical reaction atom. For example, the layer may be a silicon oxide or silicon nitride layer formed by subjecting the silicon surface to a thermal oxidation reaction, and ion implantation may be used to introduce Group V or Group III atoms into the silicon oxide or silicon nitride layer Inside. In another embodiment, the layer may be a deposited film of silicon oxide doped with a high concentration of a Group V element (eg, phosphorus) or a Group III element (eg, boron). The former is commonly known as "phosphosilicate glass (PSG)" and the latter is generally "borosilicate glass (BSG)", and the methods used to deposit these doped silicate glasses (e.g., CVD) are well known and widely Used in the microelectronics industry. Alternatively, the material layer may be a metal silicide formed by reacting a metal with a silicon surface, and ion implantation may be used to introduce Group V or Group III atoms into the metal silicide layer.

After introducing a concentration of Group V or Group III atoms into a layer of material in contact with a semiconductor surface, the entire layer structure is annealed at a temperature sufficiently high to cause segregation of the Group V or Group III atoms (segregate) to the interface, and an ordered Group V or Group III monolayer is formed at the interface, and the Group V or Group III atoms are bonded to the top layer of semiconductor atoms in epitaxial coordination. In instances where the material layer is doped silicon oxide (e.g., PSG or BSG) or silicon nitride and the semiconductor is silicon, the annealing cycle causes a portion of the Group V or Group III elements to segregate to the silicon - After the silicon oxide (or silicon nitride) interface, the silicon oxide (or silicon nitride) can then be removed using a selective wet chemical etch, leaving the coordinated Group V at the semiconductor surface or Group III atomic monolayers, and metal is deposited to form metal contacts to the semiconductor. In the case where the material layer is a metal silicide and the semiconductor is silicon, the metal silicide may be removed after the annealing cycle causes interfacial segregation of Group V or Group III elements to form an ordered interfacial monolayer , or leave the metal silicide in place, using the metal silicide itself as a metal contact.

Still other embodiments of the present invention relate to semiconductor surfaces using {100}-orientation. Figure 9 illustrates a contact comprising such a surface, the contact comprising a Group V atomic monolayer, and the Group V atomic monolayer can be deposited on a IV semiconductor {100} surface using any of the techniques described above layer. A monolayer of Group III metal atoms is then deposited on top of the Group V atoms, followed by deposition of additional metal layers. These additional metal atoms may be the same metal element as the first layer metal atoms, or these additional metal atoms may be different metal elements from the first layer metal atoms. The metal-semiconductor contact shown in Figure 9 provides an extremely low energy barrier height for electrons and provides an extremely low resistance for the electrical conduction of electrons through the contact. If the contact is intended to provide a very low energy barrier height for electrons and provide a very low resistance to the electrical conduction of holes through the contact, the positions of the group V atoms and the group III atoms in the double layer can be arranged relative to each other. Swap.

Experimental Schottky dipoles were fabricated to demonstrate the effect of an arsenic interfacial monolayer on the aluminum-silicon Schottky barrier for demonstration. These demonstration experiments do not represent typical process conditions, nor do they necessarily represent optimal process conditions. These exemplary experiments were performed on p-type doped silicon wafers with a {111}-oriented orientation and a boron concentration of approximately 1×10 ¹⁷ atoms/cm 3 . The Schottky dipoles used in the first set of experiments were fabricated under ultra-high vacuum conditions, and the Schottky dipoles used in the second set of experiments were fabricated under low-pressure chemical vapor deposition conditions in a hydrogen atmosphere.

The first set of dipoles was treated in the following manner: after heating the Si up to 800°C in ultra-high vacuum to clean the {111} Si surface and reorganize the {111} Si surface into a 7x7 rearranged structure, the temperature was changed from 800°C to The temperature was lowered to 700° C. and the silicon surface was then exposed to a flow of As ₂ arsenic molecules for 10 minutes, after which the flow of As ₂ was terminated. Using Rutherford back scattering analysis, it was confirmed that this exposure step resulted in an areal density of arsenic atoms equal to 7.30x10 ¹⁴ atoms/cm2, which is close to that known on 1x1 reconstituted {111} silicon surfaces. The areal density of surface atoms is 7.83x10 ¹⁴ atoms/cm2. Thus, it is reasonable to conclude that approximately a monolayer of arsenic atoms has been deposited. After cooling to room temperature, a layer of pure aluminum was deposited in the same UHV system and then patterned to provide a simple dipole structure for electrical measurements. For comparison, a similar wafer was processed using a similar sequence of steps, except that the silicon surface was not intentionally exposed to any arsenic atoms. Figure 10 shows the measured current-voltage characteristics of these experimental dipoles after measuring dipoles of the same size from each wafer (with and without arsenic). As shown in the measurement curve 72 of FIG. 10, the arsenic-free dipole at the interface on the wafer consistently exhibits a relatively small Schottky barrier height for p-type silicon. From the curve 72, the energy barrier height can be obtained by fitting the measured data with the standard dipole equation (thermionic emission model). The energy barrier height of the obtained dipole without arsenic exposure is 0.40eV (experimental error is about 0.03eV), which is consistent with the published energy barrier height value of a tight aluminum contact on p-type silicon . As shown in the data curve 70 of Fig. 10, the dipoles on the wafer that had exposed the silicon interface to arsenic to form an arsenic monolayer consistently exhibited a large Schottky barrier height for p-type silicon . According to the general rule that the sum of the n-type and p-type energy barrier heights is very close to the silicon band gap, a larger energy barrier height for p-type silicon means a smaller energy barrier height for n-type silicon . Therefore, it was proved experimentally that the introduction of a monolayer of arsenic atoms at the interface between the aluminum and the {111}-oriented silicon surface does provide a larger Schottky energy barrier for p-type silicon, which is comparable to that of the aluminum The Fermi level is consistent with a reduced electronic barrier between silicon conduction bands (ie, with a reduced Schottky barrier height for n-type silicon).

The second set of dipoles was treated in the following manner: after heating the silicon up to 900°C in flowing hydrogen to clean the {111} Si surface, the temperature was lowered from 900°C to 700°C and then the silicon surface was exposed to arsenic Hydrogen hydride (AsH ₃ ) molecular flow was maintained for 10 minutes, and the temperature was maintained at 700° C. until the AsH ₃ flow was terminated. Arsine was diluted to a concentration of about 2 ppm with a large amount of hydrogen gas (H ₂ ) with a total gas flow of 20.4 liters per minute. Using Rutherford backscatter analysis, it was confirmed that this exposure step resulted in an areal density of arsenic atoms equal to ^7.8x1014 atoms/cm2, which is close to the known areal density of surface atoms on a 1x1 reconstituted {111} silicon surface of 7.83 x10 ¹⁴ atoms/cm2. Thus, it is reasonable to conclude that approximately a monolayer of arsenic atoms has been deposited. After cooling to room temperature, a layer of pure aluminum was deposited by electron beam evaporation in an independent ultra-high vacuum system, and then the layer of pure aluminum was patterned to provide a simple dipole structure for the Conduct electrical measurements. For comparison, a similar wafer was processed using a similar sequence of steps, except that the silicon surface was not intentionally exposed to any arsenic atoms. Figure 11 shows the measured current-voltage characteristics of these experimental dipoles (with and without arsenic). As shown in the measurement curve 82 of FIG. 11, the arsenic-free dipole at the interface consistently exhibits a relatively small Schottky barrier height for p-type silicon on the wafer. From the curve 82, the energy barrier height can be obtained by fitting the measurement data with the standard dipole equation (thermionic emission model). The resulting energy barrier height of the unexposed dipole is 0.42eV (experimental error is about 0.03eV), which is consistent with the published energy barrier height value of close aluminum contacts on p-type silicon. As shown in the data curve 80 of FIG. 11, dipoles that have exposed the silicon interface to arsenic on the wafer to form an arsenic monolayer consistently exhibit a large Schottky energy for p-type silicon. barrier height. According to the general rule that the sum of n-type and p-type barrier heights is very close to the silicon bandgap, a larger barrier height for p-type silicon means a smaller barrier height for n-type silicon. Thus, it was demonstrated experimentally that the introduction of a monolayer of arsenic atoms at the interface between the aluminum and the {111}-oriented silicon surface does provide a larger Schottky energy barrier for p-type silicon, which is comparable to that of the aluminum The Fermi level is consistent with a reduced electronic barrier between silicon conduction bands (ie, with a reduced Schottky barrier height for n-type silicon).

Thus, several methods have been described to reduce the metal-semiconductor junction by inserting a single layer of Group V or Group III atoms or multiple monolayers of Group V and Group III atoms at the interface between the metal and the semiconductor. ratio of contact resistance techniques.

10: Process 12, 14, 16, 18: steps 20: surface 22, 24, 26, 28: atoms 30: Corner holes 32: Group V atoms 34:Silicon surface atoms 36: Group IV semiconductors 38: Monolayer of group V atoms 40: Group III atomic monolayer 42: metal atom 44: contact 45: Process 46, 48, 50, 52, 54: steps 70: curve 72: curve 80: curve 82: curve

The drawings in the accompanying drawings illustrate the present invention by way of example and are not intended to be limiting and are as follows:

Figures 1(a) and 1(b) illustrate the potential energy barrier at the metal-semiconductor junction; specifically, Figure 1(a) illustrates the semiconductor (left)-metal (right) interface have a fixed thick energy barrier that blocks current flow; and Figure 1(b) illustrates how a dipole layer interposed between a metal and a semiconductor eliminates the energy barrier except between a pair of atomic planes.

Figure 2 illustrates an example of a process for forming metal contacts with very low resistance to a semiconductor surface in accordance with an embodiment of the present invention.

Figures 3(a), 3(b) and 3(c) provide 7x7 views of a reorganized {111}-oriented silicon surface.

Figure 4 illustrates an example of Group V atoms bonding directly to exposed silicon surface atoms to form fully coordinated lattice terminations without dangling bonds.

Figure 5 illustrates the fabrication of contacts by inserting a bilayer (two monolayers) on the (111) surface of an n-type semiconductor using the process shown in Figure 2 according to an embodiment of the invention.

Figures 6(a) and 6(b) illustrate two bilayers at the (111) interface in n-type semiconductors with field regions spanning long or short interplanar spacings, respectively.

Fig. 7 shows two bilayers as shown in Fig. 6 but for p-type semiconductors according to a further embodiment of the present invention, which can provide a pole for hole conduction throughout the contact. low resistance.

FIG. 8 illustrates a process for creating the contacts shown in FIG. 7, according to an embodiment of the present invention.

Figure 9 illustrates a single bilayer (two monolayers) as shown in Figure 5 but not for a {111} surface, but for a {100} semiconductor surface.

Figures 10 and 11 illustrate Schottky dipole current-voltage characteristics experimentally obtained from aluminum-{111} crystal to p-type silicon contacts, and measured with a contact having a monolayer of arsenic atoms at the interface The data were compared with those of contacts without an arsenic interfacial layer.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

Claims (20)

An electrical contact comprising a metal and a Group IV semiconductor separated by an interfacial layer, the semiconductor comprising an n-type or p-type doped A heterogeneous semiconductor source or drain, the metal being a barrier metal, and when the semiconductor is an n-type doped semiconductor source or drain, the interfacial layer is an ordered arrangement of group V atoms adjacent to one of the semiconductors layer, and when the semiconductor is a p-type doped semiconductor source or drain, the interface layer is a Group III atomic layer arranged adjacent to one of the semiconductors. The electrical contact as claimed in claim 1, wherein the metal comprises tantalum nitride. The electrical contact of claim 1, wherein the metal comprises titanium nitride. The electrical contact as claimed in claim 1, wherein the metal comprises ruthenium. The electrical contact as claimed in claim 1, wherein a surface of the Group IV semiconductor on which the metal contact is formed is a {111}-oriented surface. The electrical contact as claimed in claim 1, wherein a surface of the Group IV semiconductor on which the metal contact is formed is a {110}-oriented surface. The electrical contact as claimed in claim 1, wherein a surface of the Group IV semiconductor on which the metal contact is formed is a {110}-oriented surface. The electrical contact as claimed in claim 1, wherein the interfacial layer comprises one or more bilayers, and at least one of the bilayers correspondingly comprises the ordered Group V atomic layer, or the ordered Group III atomic layer. The electrical contact as claimed in claim 8, wherein at least one of the intermediate bilayers further comprises a Group III atomic layer coordinated to the ordered Group V atomic layer, or a Group III atomic layer coordinated to the ordered Group V atomic layer, respectively. One of the group atomic layer coordination is the V group atomic layer. The electrical contact according to claim 9, wherein the metal comprises one of the following: tantalum nitride, titanium nitride, and ruthenium. An electrical contact comprising a metal and a Group IV semiconductor separated by an interfacial layer, the semiconductor comprising an n-type or p-type doped A heterogeneous semiconductor channel, the metal being a barrier metal source or drain of a transistor, and when the semiconductor is an n-type doped semiconductor source or drain, the interfacial layer is an orderly arrangement adjacent to the semiconductor The group V atomic layer, and when the semiconductor is a p-type doped semiconductor source or drain, the interface layer is a group III atomic layer arranged adjacent to one of the semiconductors. The electrical contact of claim 11, wherein the metal comprises tantalum nitride. The electrical contact of claim 11, wherein the metal comprises titanium nitride. The electrical contact as claimed in claim 11, wherein the metal comprises ruthenium. The electrical contact as claimed in claim 11, wherein a surface of the Group IV semiconductor on which the metal contact is formed is a {111}-oriented surface. The electrical contact as claimed in claim 11, wherein a surface of the Group IV semiconductor on which the metal contact is formed is a {100}-oriented surface. The electrical contact as claimed in claim 11, wherein a surface of the Group IV semiconductor on which the metal contact is formed is a {100}-oriented surface. The electrical contact as claimed in claim 11, wherein the interfacial layer comprises one or more bilayers, and at least one of the bilayers correspondingly comprises the ordered Group V atomic layer, or the ordered Group III atomic layer. The electrical contact as claimed in claim 18, wherein at least one of the intermediate bilayers further comprises a Group III atomic layer coordinated to the ordered Group V atomic layer, or a Group III atomic layer coordinated to the ordered Group III atomic layer, respectively. One of the group atomic layer coordination is the V group atomic layer. The electrical contact as claimed in claim 19, wherein the metal comprises one of the following: tantalum nitride, titanium nitride, and ruthenium.

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