TW202331575A - Using and/or reduce carry chains on programmable hardware - Google Patents

Abstract

The present disclosure relates to a carry chain logic system that leverages carry in and carry out signals from logic blocks to implement logic functions on programmable hardware (e.g., FPGA hardware). In particular, implementations of the carry chain logic system facilitate implementation of logic gates (e.g., AND/OR gates) having high number of input signals without incurring routing delays caused by routing output signals between logic components implemented across different logic stages. For example, implementations described herein involve feeding carry out signals between adders of a logic chain across multiple logic components on a common logic stage, thus reducing routing penalties caused by routing signals via a routing fabric of the programmable hardware.

Description

Use and/or reduce carry chains on programmable hardware

This disclosure relates to the use and/or reduction of carry chains on programmable hardware.

This application claims the benefit of and priority to U.S. Provisional Application No. 63/295,323, filed December 30, 2021, which is hereby incorporated by reference in its entirety.

Recent years have seen a growth in the use of programmable hardware to perform various computing tasks. In fact, many computing applications today often use programmable arrays of blocks to perform various tasks. Such programmable blocks of memory elements provide a useful alternative to application-specific integrated circuits with a more specialized or specific set of tasks. For example, field programmable gate arrays (FPGAs) provide programmable blocks that can be programmed independently and provide significant flexibility to perform various tasks.

As programmable hardware has increased in size and complexity, implementing hardware configurations that provide fast and efficient processing has become challenging. For example, because logic functions are configured to accept an increasing number of input signals, conventional hardware units (eg, logic modules) are often unable to generate outputs without incurring a certain amount of delay. In many cases, such delays are unacceptable and potentially cause other logic modules to produce incorrect outputs. Furthermore, conventional approaches to fixing such delays are often complex and difficult to implement on a given programmable hardware unit.

These and other problems exist with regard to implementing logic functions on programmable hardware units such as FPGAs.

In a first aspect, a method implemented on a carry chain of a logic module is disclosed, the method includes: receiving an input vector, including a plurality of input bits; receiving a bit vector, including a primer bit and a plurality of vectors bit; providing the primer bit and the first input bit of the plurality of input bits to a first adder in the carry chain; generating a first adder at the first adder based on the primer bit and the first input bit carry output bits; each vector bit from the plurality of vector bits and an associated input bit from the plurality of input bits is provided as input to an additional adder in the carry chain; and The last carry-out bit of the last adder of , the carry-out bit is provided from each adder to the next adder in the carry chain to produce the output.

In the second aspect, a carry chain logic function is disclosed, the carry chain logic function includes: a first logic module including a first adder and a second adder, the first logic module is configured to: An adder receives the first input and the primer bits of the bit vector to generate a first carry-out signal to feed to a second adder; the second adder receives the first carry-out signal as the first carry-in signal , a second input, and an associated second vector bit of the bit vector to generate a second carry output signal; a second logic module comprising a third adder and a fourth adder, the second logic module being configured being: receiving a second carry-out signal as a second carry-in signal at a third adder, a third input, and an associated third vector bit of the bit vector to generate a third carry-out signal; and The quad adder receives the third carry-out signal as the third carry-in signal, the fourth input, and the associated third vector bits of the bit vector to generate a fourth carry-out signal.

In a third aspect, a programmable hardware device is disclosed, the programmable hardware device comprising: a plurality of logic modules programmed in a logic chain including a plurality of adders, the plurality of logic modules configured to : Receive the input bit at the first adder of the plurality of adders, the adder is located in the first logic module of the plurality of logic modules; receive the vector bit at the first adder of the plurality of adders; A first adder of the plurality of adders uses the input bit and the vector bit to generate a carry-out bit; and the carry-out bit is provided to a next adder of the plurality of adders, and the next adder receives the carry-out bit The element is used as the carry input bit, and the next adder is in the second logic module of the plurality of logic modules.

This disclosure relates to the features and functionality of a carry chain logic system that utilizes carry-in and carry-out signals from logic blocks to implement AND/OR logic functions on programmable hardware (e.g., FPGA hardware) . In particular, embodiments of the carry-chain logic system described herein enable the implementation of large (e.g., large number of inputs) AND/OR logic gates within the framework of additional logic functions without the need for multiple logic module families ( For example, routing inputs between multiple logic levels) can cause significant delays.

As an illustrative example, one or more embodiments of a carry chain logic system may involve a method or series of actions implemented on a carry chain of a logic module implemented on programmable hardware. According to one or more embodiments described herein, a carry chain logic system may receive an input vector comprising a plurality of input bits. The carry chain logic system may further receive a bit vector separate from the input vector, including a plurality of vector bits. The carry chain logic system may cause the input bit to be the input of the first adder in the carry chain of the logic module. In some embodiments, the bit vector includes a primer bit (eg, the least significant bit (LSB) of the bit vector) that is used as a first or primer input to a first adder to start a logic chain. The carry chain logic system may then provide each vector bit and the associated bit from the plurality of inputs as input to additional adders in the carry chain. In one or more embodiments described herein, the carry-out signal from the adder may be provided as a carry-in signal to subsequent adders in the carry chain to produce an output based on the carry-out signal from the last adder in the carry chain .

As another example, a carry chain logic system may include a carry chain logic function that may be implemented on programmable hardware. According to one or more embodiments described herein, a carry chain logic system may include a first logic module having a first adder and a second adder, a second logic module having a third adder and a fourth adder , and any number of additional logic modules with additional adder components. In this example, the first logic module may be configured to receive the first input and the primer bits of the bit vector at the first adder to generate a carry out signal that is provided to the second adder. The first logic module may be further configured to receive the carry out signal from the first adder at the second adder to combine with the second input and the associated bit value from the bit vector to generate another carry out Signal. The carry out signal may be fed to additional adders on other logic modules in conjunction with additional inputs and additional bit values of the bit vector to implement logic functions according to one or more embodiments described herein.

The present disclosure includes several practical applications that provide benefits and/or solve problems associated with configuring logic functions on programmable hardware. Examples of some of these benefits are discussed in more detail below.

For example, features of the carry-chain logic system implement large input logic gates without incurring propagation delays due to multiple logic levels coupled together in series on programmable hardware. For example, conventional logic module configurations often involve logic modules that receive inputs and feed outputs from different logic levels in common hardware configurations. These additional logic levels result in longer propagation delays requiring additional sequencing buffers or lower clock frequencies.

The carry chain logic system additionally provides features that enable logic modules to combine at the same logic level to create a higher number of input AND/OR logic than any individual logic module. For example, a logic module may include hardware that limits a particular logic module to receive and process six inputs. Despite this limitation, carry-chain logic systems utilize carry-in and carry-out signals to increase the number of inputs that can be considered for a given logic gate without routing input and output signals between logic levels.

As a more specific example, wherein the lookup table (lookup table; LUT) in the conventional logic module can only support a fixed number of inputs (for example, six inputs), if only implemented in the LUT, such as AND/OR reduces Any operation with more than six inputs may require multiple logic levels. Thus, implementing operations that require more than the fixed number of inputs that the LUT is preconfigured to receive may involve routing the inputs between logic levels and result in delays due to routing the inputs through the programmable logic's routing structure.

In one or more embodiments, the carry chain logic system works by utilizing the carry-in and carry-out signals as inputs to additional logic functions (eg, at the same logic bits as the logic modules associated with the corresponding carry-in and carry-out functions standards) to improve this limitation of conventional systems. In fact, as will be discussed in more detail herein, the carry chain logic system can reduce reliance on input and output signals being routed through the routing structure of the programmable logic hardware. Since routing inputs between logic levels can take 100s of picoseconds or even nanoseconds, this delay can cause logic functions to fail or require complex sequencing buffer configurations and/or lower clock cycles. Conversely, by utilizing the carry-in and carry-out signals as inputs to logic modules on the same logic level (eg, the carry-in signal), this delay can be significantly reduced and involves a low gain of only a few (eg, 10) picoseconds. much delay.

The features described herein can be implemented in several ways to provide additional benefits and optimizations within programmable hardware systems. For example, in one or more embodiments described herein, the carry chain logic system can process the input to be reduced as a bit vector, which can be ORed by adding the input bit vector to the bit vector of all ones Reduced in-function implementation. Similarly, by adding the input bit vector in the least significant bit (LSB) to the bit vector 0 with the primer input 1, a 1 may not be considered unless all bits on the input are 1 Carry out signal, which provides an AND-reduce operation. This makes it possible to use the carry chain instead of the LUT to reduce performance for large numbers of inputs, since the carry chain generates faster signals than the LUT. This example and additional variations will be discussed below in connection with FIGS. 3-5 .

As indicated in the discussion above, the present disclosure utilizes various terms to describe the features and advantages of the carry chain logic system. Additional details regarding the meaning of some of these terms will now be provided.

As used herein, a "logic module" may refer to any discrete component of hardware capable of receiving a plurality of inputs and producing an output based on a logic function implemented thereon. In one or more embodiments, a logic module may include multiple components, such as LUTs, adders, registers, multiplexers, and routing components. In one or more embodiments described herein, a logic module refers to a configuration that allows N-input (e.g., 4-input, 6-input, 8-input) logic functions from any of several manufacturers, which can be Implemented in conjunction with additional logic modules on programmable hardware devices. In one or more embodiments, a programmable hardware device (eg, an FPGA device) has 100s, 1000s, or 1,000,000s of logic modules implemented thereon that are programmable to implement various kind of function.

As used herein, "logical level" may refer to a grouping of one or more logical modules separated by another grouping of one or more logical modules via a routing structure between the modules. For example, in one or more embodiments described herein, a logic level may refer to a carry chain of logic modules having a carry signal fed as a carry signal input between logic modules. Logic level logic modules can provide output signals to additional logic layers directly or through registers that can retrieve data from one clock cycle to the next. In one or more embodiments described herein, a logic chain of logic modules may refer to logic modules within a common logic level. In contrast, a series of logic modules or family of logic modules may refer to logic modules that feed signals to each other across different logic levels (eg, via routing structures).

As used herein, a bit vector may be a predetermined vector or set of bit values that may be used as input to one or more logic modules. A bit vector consists of a number of vector bits. The bit values of the vector bits may be based on the type of logic function being performed by the carry chain logic system. For example, and as will be discussed in more detail herein, a carry-chain logic system configured to perform an OR reduction may include a bit vector having a vector bit with a bit value of one. In some examples, a carry chain logic system configured to perform an AND reduction may include a bit vector having a vector bit with a bit value of zero, and a first vector bit having a bit value of one.

In one or more embodiments described herein, the first vector bits are referred to as primer bits. As used herein, a primer bit may be an initial bit that may be added to a first logic module of a carry chain logic system. The primer bits may have bit values based on the configuration of the carry chain logic system. For example, for an AND or OR reduction, the primer bit may have a bit value of one to allow the first logic module to perform the AND or OR reduction. In some embodiments, primer bits may be included in a bit vector as vector bits.

As used herein, an input vector may include a plurality of input bits for a carry chain logic system. Each logic module may receive input bits from an input vector. As discussed in more detail herein, the input bits of a bit vector may be received from other functions in programmable hardware. For example, an input bit may be the output of a logic function from a different logic level than the carry chain logic system. In some examples, the input bits may be outputs from other logic functions, combinations, subtractions, or any other functions performed on programmable hardware. In some embodiments, the input vector has a certain number of input bits. The number of logic modules in the carry chain logic system can be equal to the amount of input bits.

Additional details will now be discussed with respect to the carry chain logic system with respect to the illustrative figures depicting example embodiments. For example, FIG. 1A shows an example environment illustrating a programmable hardware device 100 on which a carry chain logic system 102 is implemented. As shown in FIG. 1 , carry chain logic system 102 may include a plurality of logic chains 104 that may independently include any number of logic modules 106 chained together, according to one or more examples discussed herein. In one or more embodiments, a programmable hardware device refers to an FPGA device on which any number of logic modules 106 are implemented.

Figure 1B shows an example implementation of a logic chain 104 on the carry chain logic system 102 shown in Figure 1B. The logic chain 104 may refer to any of the logic chains 104 on the carry chain logic system 102 implemented on the programmable hardware device 100 shown in FIG. 1A.

As shown in FIG. 1B , the example logic chain 104 may include any logic chain configured to receive an input (collectively 110 ) (eg, a plurality of input signals) and generate an output (collectively 112 ) (eg, one or more outputs). number of logic modules (collectively 106). As further illustrated, logic modules 106 may be configured to receive and provide carry signals (collectively 108 ) between respective logic modules 106 .

As an example, and as shown in FIG. 1B, a first logic module 106-1 may receive a first input 110-1, a first carry signal 108-1, and generate a first output 112-1 and a second carry signal 108-2. The first input 110-1 and/or the first carry signal 108-1 may be received from any source, such as an input vector or another logic module 106 (eg, from a different logic stage). In some embodiments, the first output 112-1 may also be provided to another logic module. As will be discussed in more detail below, logic module 106 may additionally receive as input a bit vector having a first bit that refers to a primer bit and an additional bit that causes logic module 106 to simulate a particular logic gate .

As further illustrated, logic modules 106 may receive and provide carry signals 108 between logic modules 106 of logic chain 104 . For example, each logic module 106 may receive a carry-in signal and provide a carry-out signal. As shown in FIG. 1B , the carry signal 1068 may refer to both the carry out signal of one logic module 106 and the carry in signal of another logic module 106 . For example, the second carry signal 108-2 can be the carry-out signal of the first logic module 106-1 and the carry-in signal of the second logic module 106-2. In one or more embodiments described herein, the carry-in signal is provided within the same or a different logic chain 104 as an input to the logic module 106 .

As shown in FIG. 1B, while each of the carry signals 108 may be fed as a carry input to another logic module 106, one or more embodiments may involve the carry signals being used as inputs to another logic function. For example, in one or more embodiments described herein, the carry signal 108 may be used as an AND/OR reduction function output 114 to expand the number of inputs to logic gates implemented by logic chains. In one or more embodiments, the carry signal 108 may be fed together as an input to another logic function. Additional examples will be discussed in conjunction with FIGS. 3-5.

As discussed herein, logic chain 104 may be of any length with carry signal 108 propagated through any number of logic modules 106 . For example, the logic chain 104 shown in FIG. 1B has a first logic module 106-1 receiving a first carry signal 108-1 and a first input 110-1. The first input 110-1 may include first vector bits from the bit vector and first input bits from the input vector. Therefore, the first logic module 106-1 can receive three inputs. The first logic module 106-1 can generate the first output 112-1 and the second carry signal 108-2 (eg, the carry output signal of the first logic module 106-1). In some embodiments, the second carry signal 108-2 may be the LSB of the result of the first logic module 106-1, and the first output 112-1 may be the MSB of the result.

The second logic module 106-2 may receive a second carry signal 108-2 (eg, a carry-in signal) and a second input 110-2 as inputs. The second input 110-2 may include the second vector bits from the bit vector and the second input from the input vector. Therefore, the second logic module 106-2 can receive three inputs. The second logic module 106 - 2 can generate the second output 112 - 2 and the carry signal 108 . The logic chain 104 can be continued indefinitely, thereby generating n carry signals 108-n. N logic modules 106-n can receive n-carry signal 108-n, n-input 110-n, and n-output 112-n. This may allow long logic chains 104 to process a large number of inputs at the same logic level with reduced processing delay.

Figure 2 illustrates a more detailed implementation of an example logic module in accordance with one or more embodiments. As shown in FIG. 2, a logic module may include various components that may be configured to provide logic gates for a predetermined number of inputs. In the example shown in Figure 2, the logic module can be configured to handle up to eight inputs.

As shown in FIG. 2, logic module 206 may include a look-up table (LUT) programmable to provide any of various Boolean functions for N inputs up to the limit of the logic module. As shown in FIG. 2, the logic module 206 may include two logic parts (collectively referred to as 218), including a first logic part 218-1 and a second logic part 218-2. Each logic section 218 may utilize LUT 216 to process a four-input LUT table function. In this way, two four-input LUT functions can process respective groups of inputs and produce two outputs.

As shown in Figure 2, the output from LUT 216 may be fed to two separate logic modules. In the illustrated embodiment, the logic modules are adders (collectively 220) that can be used to add two bits. Adder 220 may be a one-bit adder and is configured to process three one-bit inputs, including carry-in bit 222 , input bit 224 , and vector bit 226 . Adder 220 may process carry-in bits 222 , input bits 224 , and vector bits 226 to generate output (collectively 212 ) and carry-out bits (collectively 228 ). Output 212 may be passed to register 230, where the output may be routed to a different logic level or to other parts of the programmable hardware device. The carry-out bit 228 can be used as the carry-in bit 222 of another adder in the logic chain.

In the illustrated embodiment, logic module 206 may receive six LUT inputs 215 at LUT 216 . In the first logic portion 218-1, the LUT 216 may output a first input 224-1 to a first adder 220-1 and provide a first vector bit 226-1 to the first adder 220-1. The first adder 220-1 can receive the first carry-in bit 222-1. The first adder 220-1 can process the first carry-in bit 222-1, the first input 224-1, and the first vector bit 226-1, and generate the first output 212-1 and the first carry-out bit Yuan 228-1.

In the second logic section 218-2, the LUT 216 may generate a second input 224-2. LUT 216 may provide second input 224-2 and second vector bits 226-2 to second adder 220-2. The second adder 220-2 can receive the first carry-out bit 228-1 as the second carry-in bit 222-2. The second adder 220-2 can process the second carry-in bit 222-2, the second input 224-2, and the second vector bit 226-2 to generate the second output 212-2 and the second carry-out bit 228-2. The second carry-out bit 228 - 2 can be used at another logic module 206 on the same logic level as the carry-in bit 222 .

In one or more embodiments described herein, logic modules 206 may be configured as AND gates and OR gates and configured to sum inputs from respective logic portions of the logic modules.

As shown in FIG. 2 , the logic module 206 may include a plurality of registers 230 . As mentioned above, the register 230 can fetch data from one clock cycle to the next clock cycle. In one or more embodiments, logic module 206 may be configured to use register 230 to achieve a higher frequency than would be possible by bypassing adder 220 and/or register 230 .

As will be discussed in connection with several examples below, a logic module 206 may be combined with one or more additional logic modules 206 to create a logic gate with a greater number of inputs than may be used with a single logic module 206 . For example, a logic module 206 may be combined with a plurality of additional logic modules 206 to provide a large AND gate with a significantly higher number of inputs (eg, thirty, fifty, or hundreds of inputs) available in conventional configurations.

In one or more embodiments described herein, logic modules 206 may implement larger logic gates by implementing logic chains with a plurality of logic modules 206 configured to receive bit vectors, Input vector, and carry signal. In particular, the bit vector may comprise a vector of 1s and/or 0s, in addition to the primer bits fed to the first logic module 206 of the plurality of logic modules 206 in the logic chain. The bit vector may be fed as an input to the logic module 206 of the logic chain along with the logic gate applying the input vector of input bits.

In addition to the bit vector and input vector provided as input, the logic module 206 can use the carry input fed to the adder to create a ripple adder and based on the associated bit vector value, the input value, and the carry provided to the adder Signals are combined to produce a two-bit value with a most significant bit (MSB) and a least significant bit (LSB). In one or more embodiments described herein, the MSB becomes the carry out bit of the adder or logic module, and the LSB becomes the output of the corresponding adder or logic module.

It will be appreciated that the MSB and/or LSB may be used in different ways depending on the specific logic gates that the logic module is programmed to provide. In addition, the specific value of the bit vector including the set of 0 and/or 1 and the primer bits can be determined as the specific value based on the logic gates that the logic module has been programmed to provide.

Additional details will now be discussed in connection with several example embodiment approaches. For example, Figure 3 shows a first example OR reduction logic chain and a first example AND reduction logic chain.

FIG. 3-1 is a representation of a bit vector 332 including a plurality of vector bits 326 and an input vector 334 including a plurality of input bits 324 . As an illustrative example, bit vector 332 includes four vector bits 326, including bl, b2, b3, and b4, where bl is referred to herein as a primer bit (Pr). The primer bit Pr may be the initial bit used in the first logic module of the logic chain. The input vector 334 includes four input bits, including a1, a2, a3, and a4.

3-2 is a representation of a general logic chain 304 including four adders (collectively 320 ), in accordance with at least one embodiment of the present disclosure. The first adder 320 - 1 receives the preamble bit Pr and the first input bit a1 from the input vector 334 . The first adder outputs a first carry signal C1. The second adder 320 - 2 receives the first carry signal C1 , the second vector bit b1 from the bit vector 332 , and the second input bit a1 from the input vector 334 as inputs. The second adder 320-2 can generate the second carry signal C2. In one or more embodiments, the first adder 320-1 and the second adder 320-2 may be part of the first logic module.

The third adder 320 - 3 can receive the second carry signal C2 , the third vector bit b3 of the bit vector 332 , and the third input bit a3 from the input vector 334 as inputs. The third adder 320-3 can generate a third carry signal C3. The fourth adder 320 - 4 can receive the third carry signal C3 , the fourth vector bit b4 of the bit vector 332 , and the fourth input bit of the input vector 334 as inputs. The fourth adder 320-4 can generate a fourth carry signal C4. The third adder 320-3 and the fourth adder 320-4 may be part of the second logic module. Thus, the embodiment shown in Figure 3-2 may represent two logic modules, each including two adders. Depending on the unique hardware and specifications of the logic modules, other implementations may include different groupings of adders and modules.

As shown in FIG. 3-2 , reduce output 336 may be provided as an output of logic chain 304 . The reduce output 336 may receive the fourth carry signal C4 and perform a reduce function on the fourth carry signal C4 and/or any other output of the logic chain 304 . As discussed herein, because each of adders 320 is at the same logic level, decrease output 336 can be generated on fourth carry signal C4 with less processing delay. It can be seen that logic chain 304 may include more or less than four adders 320 .

As shown in FIGS. 3-3, the OR reduction logic chain 304 includes four adders 320, which may be implemented within logic modules according to one or more embodiments described herein. For example, the first adder 320-1 and/or the second adder 320-2 may be implemented within similar logic modules as discussed above in connection with FIG. 2 . The third adder 320-3 and/or the fourth adder 320-4 may be implemented within another logic module having similar features and functions as discussed above in connection with FIG. 2 .

As shown in FIGS. 3-3, an input vector 334 having values a1, a2, a3, and a4 may be provided as an input to a logic module. For example, a1 and a2 may be provided as inputs to a first logic module, and a3 and a4 may be provided as inputs to a second logic module. In conjunction with input vector 334, predefined bit vector 332 may be provided as an input to the logic module. As shown in FIGS. 3-3 , individual bits of bit vector 332 may be provided to each of the adders in conjunction with corresponding bit values of input vector 334 . By way of example, and as shown in FIG. 3, a first bit of bit vector 332 may be provided in conjunction with a1 as an input to first adder 320-1 (e.g., on a first logic module), and bit The second bit of vector 332 may be provided in conjunction with a2 as an input to a second adder 320-2 (eg, on the first logic module). Additionally, the third bit of bit vector 332 may be provided in combination with a3 as an input to third adder 320-3 (e.g., on the second logic module), while the fourth bit of bit vector 332 may be combined with a4 Provided as input to a fourth adder 320-4 (eg, on the second logic module). Other configurations may include any number of input bits and corresponding bit vector bits provided to additional adders on additional logic modules.

As mentioned above, the specific value of the bit vector 332 may be determined based on the specific logic gates to be implemented by the logic modules of the logic chain 304 . For example, in the configuration shown, the bit vector 332 may include a first primer input (e.g., a "1" bit value) provided to the first adder in conjunction with an additional "1" input, providing those inputs with Extra adder to OR reduce logic chain.

In the example shown in Figures 3-3, adder 320 will produce two bit outputs. Adder 320 will propagate the input carry if any of the input bits (eg, the input bit and the corresponding vector bit) is true. If both are true, adder 320 generates an output carry. In one or more embodiments, this configuration includes a ripple-carry adder. In one or more embodiments, the LSB can be ignored and the MSB can be provided as a carry-in signal to the next adder in the OR-reduce logic chain. In one or more embodiments, the LSB is provided as an output to one or more additional logic functions on the programmable hardware device.

As mentioned above, FIGS. 3-4 further illustrate an example AND reduction logic chain 304 . As shown in FIGS. 3-4, the AND reduce logic chain 304 includes four adders 320, similar to the four adders 320 described above in connection with the OR reduce logic chain. Such adders 320 may be implemented within logic modules similar to OR-reduce logic chains. As further illustrated, the logic module may receive an input vector 334 combined with a bit vector 332 having specific values based on the intent to implement an AND gate function (as opposed to an OR gate). For example, in the example shown in FIG. 3, the bit vector 332 may include a vector of all "0" values, wherein the first vector bit is "1". Using logic similar to the adder block discussed above, the AND reduction framework can generate AND gates for any number of inputs using a plurality of logic modules on the same logic chain of logic modules (e.g., on a common logic channel). Output.

Figure 4-1 shows an example implementation illustrating a variation of the example discussed above in connection with Figure 3 in accordance with at least one embodiment of the present disclosure. The example functions described in Figure 4-1 illustrate similar principles discussed in conjunction with similar components shown in Figure 3 . For example, Figure 4-1 illustrates a general logic chain 404 having a plurality of adders (collectively 420). Each adder 420 can receive a plurality of inputs, including a carry input signal, input bits a1 , a2 , a3 , a4 , and vector bits b1 , b2 , b3 , b4 from a bit vector.

The input bits may include the output of the LUT reduction function 438 . The LUT reduction function 438 may receive multiple bits and reduce the multiple inputs to a single input for the adder 420 . For example, the LUT reduction function 438 may reduce six bits at a time from the bit vector to produce respective inputs al, a2, a3, a4. In this way, rather than each input from a bit vector being an independent input to adder 420, LUT reduction function 428 may perform an initial reduction of input bits, thereby reducing the number of logic modules available when performing a given operation total. The output of adder 420 may then be used in reduce output 436 .

FIG. 4-2 shows an example OR reduction logic function in logic chain 404 . The OR reduction logic chain 404 may include a chain of adders 420 implemented within logic modules, which may include similar features to the logic modules discussed above in connection with FIG. 2 . In this example, each of adders 420 may receive input bits a1, a2, a3, a4, and bit vector bits, and carry input values c1, c2, c3, c4 from another adder component .

In the example shown in Figure 4-2, the input bits may refer to the output from the LUT. More specifically, in one or more embodiments, a LUT may be used to reduce the bit vector six bits at a time and use a chain of adders to reduce the result. Thus, instead of having a single input bit for each bit of a bit vector, an OR reduction logic chain can use a LUT to reduce up to six bits (or other predetermined number of inputs, based on the capabilities of the logic module). This can significantly reduce the number of logic modules in a given carry chain when logic gates are configured with a large number of inputs.

Referring to the specific example shown in FIG. 4-2, the first LUT OR reduction can reduce the input A1 to A6 to generate the first input bit a1. The first adder 420 - 1 may receive a first input bit a1 and a vector bit with a value of 1 (eg, a primer bit). The output of the first adder 420-1 may include a first carry bit C1.

A second LUT OR reduction may reduce input A7 to A12 to generate a second input bit a2. The second adder 420-2 may receive the second input bit a2, the bit vector with a value of 1, and the first carry bit C1. The output of the second adder 420-2 may include a second carry bit C2.

A third LUT OR reduction reduces input A13 to A18 to generate a third input bit a3. The third adder 420-3 can receive the third input bit a3, the bit vector with a value of 1, and the second carry bit C2. The output of the third adder 420-3 may include a third carry bit C3.

A fourth LUT OR reduction reduces input A19 to A24 to produce a fourth input bit a4. The fourth adder 420-4 can receive the third input bit a4, the bit vector with a value of 1, and the third carry bit C3. The output of the fourth adder 420-4 may include a fourth carry bit C4.

OR-reduce may receive the fourth carry bit C4 and perform an OR-reduce. In this way, the carry chain 404 can perform an OR-reduce on a 24-bit input vector in a single logic level, thereby reducing the total number of logic modules used to perform the OR-reduce and increasing the speed of the OR-reduce.

4-3 are representations of example AND reduce carry chain 404 logic functions in accordance with one or more embodiments described herein. Similar features to the OR reduction logic chain 404 are applicable to the AND reduction logic chain 404 . For example, a LUT can be used to reduce the bits of a bit vector with values specific to AND gate logic. In this example, four adders 420 may be used to process AND reduction gates for four LUTs each receiving up to six inputs (or another number of inputs, based on the capabilities of the logic module).

Referring to the specific example shown in FIGS. 4-3, the first LUT AND reduction can reduce the input A1 to A6 to generate the first input bit a1. The first adder 420 - 1 may receive a first input bit a1 and a bit vector with a value of 1 (eg, a primer bit). The output of the first adder 420-1 may include a first carry bit C1.

A second LUT AND reduction may reduce input A7 to A12 to produce a second input bit a2. The second adder 420-2 may receive the second input bit a2, the bit vector having a value of 0, and the first carry bit C1. The output of the second adder 420-2 may include a second carry bit C2.

A third LUT AND reduction may reduce input A13 to A18 to produce a third input bit a3. The third adder 420-3 can receive the third input bit a3, the bit vector with a value of 0, and the second carry bit C2. The output of the third adder 420-3 may include a third carry bit C3.

A fourth LUT AND reduction reduces input A19 to A24 to produce a fourth input bit a4. The fourth adder 420-4 can receive the third input bit a4, the bit vector with a value of 0, and the third carry bit C3. The output of the fourth adder 420-4 may include a fourth carry bit C4.

An OR decrease may receive the fourth carry bit C4 and perform an AND decrease. In this way, the carry chain 404 can perform an AND reduction on a 24-bit input vector in a single logic level, thereby reducing the total number of logic modules used to perform the AND reduction and increasing the speed of the AND reduction.

FIG. 5 is a representation of a carry chain 504 logic system in accordance with at least one embodiment of the present disclosure. For example, FIG. 5 shows an example configuration of logic chain 504 in which the input vectors include inputs from any LUT combinatorial logic. For example, logic chain 504 may utilize the combinational logic of a LUT and feed the output of the LUT to logic chain 504 in the event that additional combinatorial logic is required. This enables logic chain 504 to include combinational logic and AND/OR reduction to a single logic level, rather than across multiple logic levels.

An example implementation of this configuration may include a counter configured to increment or decrement based on a certain detected condition. In this example, a scratch function may be configured and driven as an input to an adder (eg, on a chain of adders). Where this would conventionally be performed by providing an output from a logic module of another logic layer, this framework enables feeding the carry signal as an input to a logic chain within the same logic layer and significantly reduces the The latency introduced by routing signals through routing structures between logical layers. As shown in Figure 5, this combination of any combinatorial logic with a framework of reduce logic functions can be applied to both AND reduce and OR reduce configurations.

Figure 6 illustrates another example logic chain 604 framework according to one or more embodiments described herein. For example, Figure 6 shows an example where the AND/OR reduction is fed into an adder 520 (eg, a counter). In this case, the carry out signal may feed from the adder 520 the carry in value of the adder 520 as a counter.

For example, a first logic function (eg, a subtractor function) may supply a carry out indicative of the result of the comparison operation. This can be provided in conjunction with a different set of combined signals for providing the carry-in value to another counter. Therefore, this framework can be used to implement the entire logic of multiple logic functions using the carry chain configuration described in this paper.

As shown in FIG. 5, the "T" and "R" signals may refer to two inputs that refer to pointers to sets of values (eg, a queue of inputs with a specific order, such as inputs issued by a processor) . The carry-out signal may refer to the carry-out of the most significant stage of the subtraction and may be combined with another signal to produce a logic function. This logistic function can be fed as input to another function. In particular, as shown in FIG. 5, the carry-out signal can be used to drive additional logic that shares a logic level (eg, without routing the signal via a routing structure between logic lanes).

As a general example, the example shown illustrates a first logical function (eg, a subtraction function). The result of the logic function is fed to an abort stage (eg, second logic function), which is fed to an adder function (eg, third logic function). This implementation enables logic chains to be implemented as more complex functions that would typically involve multiplexers (MUXs) or other functions involving multiple logic stages that have the potential to result in unacceptable amounts of latency. In effect, the configuration described herein enables logic chains to consider multiple conditions within a single logic stage by using the carry-out signal to drive additional logic functions.

From a more general point of view, similar principles to the above examples can be implemented to combine multiple logic functions before or after a reduction logic function (e.g., AND reduction, OR reduction), such as before a subtraction function as shown in FIG. 5 or after. Where conventional systems typically involve complex or robust combinations of logic modules across multiple levels of logic, embodiments described herein enable combinations of various logic functions, including unrelated logic functions, without incurring penalties.

Example implementations may include incrementing a queue, making comparisons and using them as logic functions without routing penalties, updating read pointers, aborting functions, or any other combinational logic.

FIG. 7 is a flowchart of a method 740 implemented on programmable hardware in accordance with at least one embodiment of the present disclosure. At 742, method 740 includes receiving an input vector comprising a plurality of input bits at the logic module. At 744, the logic module receives the bit vector. A bit vector includes a primer bit and a plurality of vector bits. At 746, the logic module provides the primer bit, the first vector bit of the plurality of vector bits, and the first input bit of the plurality of input bits to a first adder in the carry chain.

At 748, the first adder generates a first carry-out bit based on the preamble bit, the first vector bit, and the first input bit. At 750, the logic module provides each vector bit from the plurality of vector bits and the associated input bit from the plurality of input bits as input to an additional adder in the carry chain. At 752, the programmable hardware provides a carry-out bit from each adder to the next adder in the carry chain to generate an output based on the last carry-out bit from the last adder in the carry chain.

In some embodiments, the input vectors include input values based on outputs from combinatorial logic of additional logic modules implemented on programmable hardware. In some embodiments, the additional logic module is implemented on the same logic level as the carry chain of the logic module. In some embodiments, the input value includes a carry-out signal from an adder of an additional logic module.

In some embodiments, the value of the bit vector is based on the configuration of the logic module to be used as the corresponding logic function. In some embodiments, the value of the bit vector includes a primer bit and a set of 1-bit values based on a logic module configured to function as an AND reduction logic function. In some embodiments, the values of the bit vector include a set of primer bits, 1 bit values of the first vector bits, and zero bit values based on a logic module configured to function as an OR reduction logic function. In some embodiments, the primer bit is a 1-bit value.

The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof unless specifically described as being implemented in a particular manner. Any features described as modules, components or the like may also be implemented together in an integrated logic device or independently as discrete but interoperable logic devices. If implemented in software, the techniques may be implemented at least in part by a non-transitory processor-readable storage medium containing instructions that, when executed by at least one processor, perform one or more of the methods described herein . Instructions may be organized as routines, programs, objects, components, data structures, etc., which may perform particular tasks and/or implement particular data types, and may be combined or dispersed as desired in various embodiments.

The steps and/or actions of the methods described herein may be interchanged with one another without departing from the scope of the claimed claims. In other words, unless a specific order of steps or actions is required for proper operation of the method described, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claimed claim.

The term "determining" covers a variety of actions, and thus "determining" may include computing, computing, processing, deriving, investigating, looking up (eg, a lookup table, database, or another data structure), validating, and the like. In addition, "determining" may include receiving (eg, receiving information), accessing (eg, accessing data in memory), and the like. Additionally, "determining" may include solving, selecting, choosing, establishing, and the like.

The terms "comprising", "including", and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Furthermore, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure are not intended to be interpreted as excluding additional embodiments that also incorporate the recited features. For example, any element or feature described with respect to an embodiment herein may be combined with any element or feature of any other embodiment described herein, where compatible.

The disclosure may be embodied in other specific forms without departing from its spirit or characteristics. The described embodiments are considered to be illustrative and not restrictive. Accordingly, the scope of the present disclosure is indicated by the appended claims rather than by the foregoing description. Changes within the meaning and range of equivalents of claims are intended to be embraced within their scope.

100: programmable hardware device 102: Carry chain logic system 104: logic chain 106:Logic module 106-1: The first logic module 106-2: Second logic module 106-n: n logic modules 108-1: First carry signal 108-2: Second carry signal 108-n:n-carry signal 110-1: first input 110-2: second input 110-n:n-input 112-1: first output 112-2: Second output 112-n:n-output 114: AND/OR reduction function output 206: Logic Module 215: LUT input 216:LUT 218-1: First logical part 218-2: Second logical part 220-1: First adder 220-2: second adder 222-1: First carry input bit 222-2: Second carry input bit 224-1: first input 224-2: second input 226-1: the first vector bit 226-2: second vector bit 228-1: First carry output bit 228-2: Second carry output bit 230: temporary register 304: General logic chain 320-1: first adder 320-2: second adder 320-3: The third adder 320-4: The fourth adder 324: input bit 326: vector bit 332:Bit vector 334: Input vector 336: Reduce output 404: General logic chain 420-1: first adder 420-2: second adder 420-3: The third adder 420-4: Fourth Adder 436: Reduce output 438:LUT reduction function 504: logic chain 604: logic chain 740: method a1: first input bit a2: second input bit a3: the third input bit a4: The fourth input bit b1: second vector bit b2: the second vector bit b3: the third vector bit b4: the fourth vector bit C1: first carry bit C2: second carry bit C3: The third carry bit C4: The fourth carry bit

Figure 1A illustrates an example environment including an example carry chain logic system in accordance with one or more embodiments.

Figure 1B illustrates an example logic chain implemented within a carry chain logic system in accordance with one or more embodiments.

Figure 2 illustrates an example implementation of logic cells that may be implemented within logic chains in accordance with one or more embodiments.

Figure 3-1 shows bit vectors and input vectors according to one or more embodiments.

Figure 3-2 illustrates a generalized carry chain in accordance with one or more embodiments.

Figures 3-3 illustrate example implementations of OR reduction logic chains.

Figures 3-4 illustrate example implementations of AND reduction logic chains.

Figures 4-1 through 4-3 illustrate other example implementations of logic chains including OR reduction logic chains and AND reduction logic chains in accordance with one or more embodiments.

Figure 5 illustrates another example implementation of an OR reduction logic chain and an AND reduction logic chain in accordance with one or more embodiments.

Figure 6 illustrates an example configuration of a logic function implemented in conjunction with an AND/OR reduction chain in accordance with one or more embodiments.

Figure 7 shows a flowchart of a method implemented on programmable hardware according to one or more embodiments.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

104: logic chain

106-1: The first logic module

106-2: Second logic module

106-n: n logic modules

108-1: First carry signal

108-2: Second carry signal

108-n:n-carry signal

110-1: first input

110-2: second input

110-n:n-input

112-1: first output

112-2: Second output

112-n:n-output

114: AND/OR reduction function output

Claims (20)

A method implemented on a unary chain of a logic module, the method comprising the steps of: receiving an input vector, including a plurality of input bits; Receive a one-bit vector, including a primer bit and a plurality of vector bits; providing the primer bit and a first input bit of the plurality of input bits to a first adder in the carry chain; generating a first carry-out bit at the first adder based on the primer bit and the first input bit; providing each vector bit from the plurality of vector bits and an associated input bit from the plurality of input bits as input to an additional adder in the carry chain; and A carry-out bit is provided from each adder to a next adder in the carry chain to produce an output based on a last carry-out bit from a last adder in the carry chain. The method of claim 1, wherein the input vector includes an input value based on an output from combinatorial logic of an additional logic module implemented on the programmable module. The method of claim 2, wherein the additional logic module is implemented at the same logic level as the carry chain of logic modules. The method of claim 2, wherein the input values include carry output signals from adders of the additional logic modules. The method of claim 1, wherein the value of the bit vector is determined for use as an associated logic function based on a configuration of the logic modules. The method of claim 5, wherein the values of the bit vector comprise the primer bits and a set of 1-bit values based on the logic modules configured for use as an AND-reduce logic function. The method of claim 5, wherein the values of the bit vector include the primer bits having a 1-bit value and zeros based on the logic modules configured to function as an OR reduction logic function A collection of bit values. The method of claim 1, wherein the primer bit is a 1-bit value. A carry chain logic function, the carry chain logic function includes: A first logic module includes a first adder and a second adder, the first logic module is configured as: receiving a first input and an introductory bit of a bit vector at the first adder to generate a first carry output signal to feed to the second adder; receiving the first carry-out signal at the second adder as a first carry-in signal, a second input, and an associated second vector bit of the bit vector to generate a second carry-out signal ; A second logic module includes a third adder and a fourth adder, the second logic module is configured to: receiving the second carry-out signal at the third adder as a second carry-in signal, a third input, and an associated third vector bit of the bit vector to generate a third carry-out signal ;as well as receiving the third carry out signal at the fourth adder as a third carry in signal, a fourth input, and an associated third vector bit of the bit vector to produce a fourth carry out signal . The carry chain logic function as described in claim 9, wherein based on a combination of the first input, the second input, the third input, and the fourth input received by the corresponding adder of the carry chain logic function , a final carry output signal of the carry chain logic function including the first logic module and the second logic module is an output of a logic gate. The carry chain logic function as described in claim 9, wherein the first input, the second input received at the first adder, the second adder, the third adder, and the fourth adder One or more of , the third input, and the fourth input refer to an output of a combinational logic function at the same or a different logic level as the carry chain logic function. The carry chain logic function of claim 9, wherein the vector bits of the bit vector are based on a specific logic function that the carry chain logic function is configured to simulate. The carry chain logic function according to claim 12, wherein the carry chain logic function is implemented as an OR reduction logic gate, and the vector bits of the bit vector are all 1 values. The carry chain logic function as described in claim item 12, wherein the carry chain logic function is implemented as an AND reduction logic gate based on the carry chain logic function, the first vector bit of the bit vector is a 1 value and the remaining vector bits of the bit vector Elements are all zero values. A programmable hardware device comprising: A plurality of logic modules programmed in a logic chain, including a plurality of adders, the plurality of logic modules programmed to: receiving an input bit at a first adder of the plurality of adders, the adder being located in a first logic module of the plurality of logic modules; receiving a vector of bits at the first adder of the plurality of adders; generating a carry-out bit using the input bit and the vector bit at the first adder of the plurality of adders; and The carry output bit is provided to the next adder of the plurality of adders, the next adder receives the carry output bit as a carry input bit, and the next adder is in the plurality of logic modules In a second logic module of . The programmable hardware device as recited in claim 15, wherein the input bit is received from a LUT in the first logic module. The programmable hardware device of claim 16, wherein the LUT performs a reduction on a plurality of inputs from an input vector. The programmable hardware device of claim 16, wherein the LUT performs combinatorial logic on a plurality of inputs from an input vector. The programmable hardware device of claim 15, wherein the next adder is at the same logic level as the adder. The programmable hardware device of claim 15, wherein the plurality of hardware devices are programmed to provide a last carry output bit from a last adder of the plurality of adders to a reduce function.