TW202329265A - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
TW202329265A
TW202329265A TW111101117A TW111101117A TW202329265A TW 202329265 A TW202329265 A TW 202329265A TW 111101117 A TW111101117 A TW 111101117A TW 111101117 A TW111101117 A TW 111101117A TW 202329265 A TW202329265 A TW 202329265A
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Taiwan
Prior art keywords
electronic package
circuit structure
electronic
manufacturing
encapsulation layer
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TW111101117A
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Chinese (zh)
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TWI825552B (en
Inventor
任泰欣
余國華
羅育民
洪維伸
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW111101117A priority Critical patent/TWI825552B/en
Priority to CN202210059920.5A priority patent/CN116469860A/en
Priority to US17/956,566 priority patent/US20230223316A1/en
Publication of TW202329265A publication Critical patent/TW202329265A/en
Application granted granted Critical
Publication of TWI825552B publication Critical patent/TWI825552B/en

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
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Abstract

An electronic package is provided in which an electronic component is arranged on the upper side of a circuit structure and is covered with an encapsulation layer, a function structure is embedded in the encapsulation layer and exposed from the surface of the encapsulation layer, and at least one bonding element is arranged on the lower side of the circuit structure and corresponding to the position of the function structure to form a thermal conduction between the bonding element and the function structure. Therefore, a laser can transfer heat energy to the bonding element through the function structure, such that a solder material on the bonding element can be reflowed.

Description

電子封裝件及其製法 Electronic package and its manufacturing method

本發明係有關一種半導體封裝製程，尤指一種具散熱機制之電子封裝件及其製法。 The invention relates to a semiconductor packaging process, especially an electronic package with a heat dissipation mechanism and its manufacturing method.

隨著科技的演進，電子產品需求趨勢朝向高密度線路/高傳輸速度/高疊層數/大尺寸設計之高階產品邁進。該些產品隨著晶片尺寸加大、及接點(I/O)數增多，而對熱反應更為敏感，故在封裝作業中的熱製程，如回銲(reflow)製程，極易因各材料之間不同的熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)而使整體結構發生翹曲(warpage)，且也會因結構內部之熱應力集中之情況而發生信賴性不良之問題。 With the evolution of technology, the demand trend of electronic products is moving toward high-end products with high-density circuit/high transmission speed/high stacking number/large-size design. These products are more sensitive to thermal response as the size of the chip increases and the number of contacts (I/O) increases. Therefore, the thermal process in the packaging operation, such as the reflow process, is very easy to be caused by various The different coefficients of thermal expansion (CTE) between materials cause warpage of the overall structure, and the problem of poor reliability also occurs due to the concentration of thermal stress inside the structure.

目前雷射輔助接合(laser assisted bonding，簡稱LAB)製程可選擇性局部加熱，且具備快速升溫的特性，故可大幅縮減熱製程之時間，因而能降低結構內部的熱應力集中之情況，且藉由控制雷射波長及局部加熱的特性，能大幅縮減翹曲之程度。 The current laser assisted bonding (LAB) process can be selectively heated locally and has the characteristics of rapid temperature rise, so it can greatly reduce the time of the thermal process, thereby reducing the concentration of thermal stress inside the structure, and by By controlling the laser wavelength and the characteristics of local heating, the degree of warpage can be greatly reduced.

圖1係為習知半導體封裝件1之示意圖。如圖1所示，該半導體封裝件1係於一具有介電層100與佈線層101之基板結構10上以覆晶方式(藉由銲錫凸 塊13)設置半導體晶片11，再以封裝層12包覆該半導體晶片11。之後，該基板結構10下側之導電凸塊14,15可藉由LAB製程將複數銲錫材料16,17接置於一電路板1a之接點19上。 FIG. 1 is a schematic diagram of a conventional semiconductor package 1 . As shown in FIG. 1 , the semiconductor package 1 is flip-chip on a substrate structure 10 having a dielectric layer 100 and a wiring layer 101 (by solder bumps). Block 13) The semiconductor wafer 11 is disposed, and then the semiconductor wafer 11 is covered with the encapsulation layer 12 . Afterwards, the conductive bumps 14, 15 on the lower side of the substrate structure 10 can be connected to a plurality of solder materials 16, 17 on the contact point 19 of a circuit board 1a through the LAB process.

然而，於進行LAB製程時，雷射L之熱能只能穿透該半導體晶片11而無法穿透該封裝層12，導致該封裝層12下方之導電凸塊14之熱能不足，因而造成該處之銲錫材料16發生未濕潤(non-wetting)之問題。 However, when carrying out the LAB process, the thermal energy of the laser L can only penetrate the semiconductor chip 11 but cannot penetrate the encapsulation layer 12, resulting in insufficient thermal energy of the conductive bump 14 below the encapsulation layer 12. The problem of non-wetting occurs in the solder material 16 .

因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an urgent problem to be solved at present.

鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：線路結構，係具有相對之第一側與第二側；電子元件，係配置於該線路結構之第一側；封裝層，係配置於該線路結構之第一側以包覆該電子元件；作用結構，係嵌埋於該封裝層中並位於該電子元件的周圍，其中，該作用結構係外露於該封裝層之上表面並連通至該線路結構之第一側；以及接合元件，係對應該作用結構之位置而配置於該線路結構之第二側上，以令該接合元件與該作用結構之間形成熱導通。 In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a circuit structure having opposite first and second sides; electronic components are arranged on the first side of the circuit structure; The encapsulation layer is arranged on the first side of the circuit structure to cover the electronic component; the functional structure is embedded in the encapsulation layer and located around the electronic component, wherein the functional structure is exposed on the encapsulation layer The upper surface is connected to the first side of the circuit structure; and the bonding element is arranged on the second side of the circuit structure corresponding to the position of the active structure, so that heat is formed between the bonding element and the active structure. conduction.

本發明復提供一種電子封裝件之製法，係包括：提供一線路結構，其具有相對之第一側與第二側；將電子元件配置於該線路結構之第一側；形成封裝層於該線路結構之第一側，以令該封裝層包覆該電子元件，且於該封裝層中對應該電子元件的周圍係嵌埋有作用結構，其中，該作用結構係外露於該封裝層之上表面並連通至該線路結構之第一側；以及形成接合元件於該線路結構之第二 側上，使該接合元件對應該作用結構之位置，以令該接合元件與該作用結構之間形成熱導通。 The present invention further provides a method for manufacturing an electronic package, which includes: providing a circuit structure having opposite first and second sides; disposing electronic components on the first side of the circuit structure; forming a packaging layer on the circuit The first side of the structure, so that the encapsulation layer covers the electronic component, and an active structure is embedded in the encapsulation layer corresponding to the surrounding of the electronic component, wherein the active structure is exposed on the upper surface of the encapsulation layer and connected to the first side of the wiring structure; and forming bonding elements on the second side of the wiring structure On the side, make the joint element correspond to the position of the active structure, so as to form thermal conduction between the joint element and the active structure.

前述之製法中，該作用結構係先形成於該線路結構之第一側上，再將該封裝層一併包覆該作用結構與該電子元件。 In the aforementioned manufacturing method, the active structure is firstly formed on the first side of the circuit structure, and then the encapsulation layer covers the active structure and the electronic component together.

前述之製法中，該線路結構之第一側上設置該電子元件後，先令該封裝層包覆該電子元件，再於該封裝層上形成外露該第一側之穿孔，之後，填充金屬材於該穿孔中形成該作用結構。 In the aforementioned manufacturing method, after the electronic component is arranged on the first side of the circuit structure, the packaging layer is first used to cover the electronic component, and then a through hole is formed on the packaging layer exposing the first side, and then the metal material is filled. The active structure is formed in the through hole.

前述之電子封裝件及其製法中，該作用結構係包含無電性功能之柱體。 In the aforementioned electronic package and its manufacturing method, the functional structure includes columns with no electrical function.

前述之電子封裝件及其製法中，該作用結構係連接該線路結構之功能部。 In the aforementioned electronic package and its manufacturing method, the functional structure is a functional part connected to the circuit structure.

前述之電子封裝件及其製法中，該線路結構係包含扇出型重佈線路層。 In the aforementioned electronic package and its manufacturing method, the circuit structure includes a fan-out redistribution circuit layer.

前述之電子封裝件及其製法中，該作用結構係包含柱體，其係作為中心並以其半徑之2至3倍形成一圓形熱影響區，以令該熱影響區由該第一側朝該第二側之方向垂直投影，以於該線路結構中定義出熱通道，使該接合元件至少局部對應落入該熱通道之範圍中。 In the aforementioned electronic package and its manufacturing method, the functional structure includes a cylinder, which is used as the center and forms a circular heat-affected zone with 2 to 3 times its radius, so that the heat-affected zone is formed from the first side Vertical projection towards the direction of the second side defines a thermal passage in the wiring structure, so that the bonding element at least partially falls within the scope of the thermal passage.

前述之電子封裝件及其製法中，該作用結構係包含複數柱體，以令單一該接合元件對應至少二該柱體。 In the aforementioned electronic package and its manufacturing method, the functional structure includes a plurality of pillars, so that a single bonding element corresponds to at least two pillars.

前述之電子封裝件及其製法中，該作用結構係包含至少一柱體，以令單一該柱體對應複數該接合元件。 In the aforementioned electronic package and its manufacturing method, the functional structure includes at least one pillar, so that a single pillar corresponds to a plurality of the bonding elements.

前述之電子封裝件及其製法中，該作用結構係包含至少一柱體，且該柱體與該接合元件的直徑比例為0.2至0.4或0.8至1.2。 In the aforementioned electronic package and its manufacturing method, the functional structure includes at least one column, and the diameter ratio of the column to the bonding element is 0.2 to 0.4 or 0.8 to 1.2.

由上可知，本發明之電子封裝件及其製法中，主要藉由該作用結構嵌埋於該封裝層中並外露於該封裝層之表面，使雷射可藉由該作用結構將熱能傳遞至該線路結構第二側的接合元件，因而得以回銲該接合元件上之銲錫材料，故相較於習知技術，本發明可有效改善該接合元件上之銲錫材料未濕潤之問題。 It can be seen from the above that in the electronic package and its manufacturing method of the present invention, the functional structure is embedded in the encapsulation layer and exposed on the surface of the encapsulation layer, so that the laser can transfer heat energy to the The bonding element on the second side of the circuit structure can thus reflow the solder material on the bonding element, so compared with the prior art, the present invention can effectively improve the problem of non-wetting of the solder material on the bonding element.

1:半導體封裝件 1: Semiconductor package

1a,3a:電路板 1a, 3a: circuit board

10:基板結構 10: Substrate structure

100:介電層 100: dielectric layer

101,201:佈線層 101, 201: wiring layer

11,41:半導體晶片 11,41: Semiconductor wafer

12,22:封裝層 12,22: encapsulation layer

13:銲錫凸塊 13: Solder bumps

14,15:導電凸塊 14,15: Conductive bumps

16,17,26,27,46:銲錫材料 16,17,26,27,46: Solder material

19:接點 19: contact

2:電子封裝件 2: Electronic package

2a:作用結構 2a: Action structure

20:線路結構 20: Line structure

20a:第一側 20a: First side

20b:第二側 20b: Second side

200:絕緣層 200: insulating layer

202:功能部 202: Function Department

21:電子元件 21: Electronic components

21a:作用面 21a: Action surface

21b:非作用面 21b: Non-active surface

211:導電凸塊 211: Conductive bump

212:絕緣材 212: insulating material

22a:表面 22a: surface

23:第一柱體 23: The first column

23a:端面 23a: end face

24:接合元件 24: Joining elements

25:導電元件 25: Conductive element

28:第二柱體 28: Second cylinder

30:接點 30: Contact

4:堆疊型封裝件 4: Stacked package

4a:封裝模組 4a: Encapsulation module

40:穿孔 40: perforation

9:支撐板 9: Support plate

A,A1,A2,A3,A4:熱影響區 A, A1, A2, A3, A4: heat affected zone

D:半徑 D: Radius

L:雷射 L: Laser

R,R1,R2:直徑 R, R1, R2: Diameter

S:熱通道 S: hot aisle

Y:切割路徑 Y: cutting path

圖1係為習知半導體封裝件之剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package.

圖2A至圖2D係為本發明之電子封裝件之製法之剖視示意圖。 2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

圖2E係為圖2D之後續製程之剖視示意圖。 FIG. 2E is a schematic cross-sectional view of the subsequent manufacturing process of FIG. 2D .

圖3A至圖3D係為圖2D之局部底視示意圖。 3A to 3D are partial bottom views of FIG. 2D .

圖4A係為圖2B至圖2C之另一方式之剖視示意圖。 FIG. 4A is a schematic cross-sectional view of another mode of FIG. 2B to FIG. 2C .

圖4B係為圖2D之後續製程之另一方式之剖視示意圖。 FIG. 4B is a schematic cross-sectional view of another mode of the subsequent manufacturing process of FIG. 2D .

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「下」、「第一」、「第二」及「一」等之用語，亦僅為 便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this invention without affecting the effect and purpose of the present invention. The technical content disclosed by the invention must be within the scope covered. At the same time, terms such as "upper", "lower", "first", "second" and "one" quoted in this specification are only It is convenient for the clarity of the description, but not intended to limit the scope of the present invention. Changes or adjustments of their relative relationships shall also be regarded as the scope of the present invention without substantial changes in the technical content.

圖2A至圖2D係為本發明之電子封裝件2之製法的剖面示意圖。 2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

如圖2A所示，於一支撐板9上配置一線路結構20，再於該線路結構20上形成一包含複數第一柱體23與第二柱體28之作用結構2a。 As shown in FIG. 2A , a circuit structure 20 is disposed on a support plate 9 , and then an active structure 2 a including a plurality of first pillars 23 and second pillars 28 is formed on the circuit structure 20 .

於本實施例中，該支撐板9係例如為半導體材質(如矽或玻璃)之板體，且該線路結構20係例如為具有核心層之封裝基板、無核心層(coreless)形式之封裝基板、具導電矽穿孔(Through-silicon via，簡稱TSV)之矽中介板(Through Silicon interposer，簡稱TSI)或其它板型，其具有相對之第一側20a與第二側20b，以令該線路結構20以其第二側20b結合至該支撐板9上。例如，該線路結構20係包含至少一絕緣層200及至少一結合該絕緣層200之佈線層201，如至少一扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且該線路結構20復具有至少一功能部202，如傳遞訊號用或接地用。應可理解地，該線路結構20亦可為其它承載晶片之基材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等，並不限於上述。 In this embodiment, the support plate 9 is, for example, a board made of semiconductor material (such as silicon or glass), and the circuit structure 20 is, for example, a packaging substrate with a core layer or a packaging substrate in the form of a coreless layer. , a silicon interposer (TSI for short) with a conductive through-silicon via (TSV for short), or other plate types, which have opposite first sides 20a and second sides 20b, so that the circuit structure 20 is bonded to the support plate 9 with its second side 20b. For example, the circuit structure 20 includes at least one insulating layer 200 and at least one wiring layer 201 combined with the insulating layer 200, such as at least one fan-out (redistribution layer, RDL), and the The circuit structure 20 further has at least one functional part 202, such as for transmitting signals or for grounding. It should be understood that the circuit structure 20 can also be other chip-carrying substrates, such as lead frames, wafers, or other boards with metal wiring (routing), and are not limited to the above. .

再者，該複數第一與第二柱體23,28係立設於該線路結構20之第一側20a上，且該第二柱體28可依需求連接該線路結構20之功能部202。例如，形成該第一與第二柱體23,28之材質係為如銅之金屬材、銲錫材或其它易於導熱之材質。 Furthermore, the plurality of first and second pillars 23, 28 are erected on the first side 20a of the circuit structure 20, and the second pillar 28 can be connected to the functional portion 202 of the circuit structure 20 as required. For example, the material forming the first and second columns 23 , 28 is a metal material such as copper, solder material or other materials that are easy to conduct heat.

又，該線路結構20之佈線方式為扇出型重佈線路層(簡稱FORDL)，故該佈線層201之線距(pitch)從第一側20a之較小線距扇出至第二側20b之較大線距，即該佈線層201於該第一側20a之線距小於其於該第二側20b之線距。 Moreover, the wiring method of the wiring structure 20 is fan-out redistributed wiring layer (FORDL for short), so the pitch of the wiring layer 201 is fanned out from the smaller pitch of the first side 20a to the second side 20b The line pitch of the wiring layer 201 on the first side 20a is smaller than the line pitch on the second side 20b.

如圖2B所示，於該線路結構20之第一側20a上設置至少一電子元件21，且該第一柱體23未電性連接該電子元件21，以作為虛連通件(dummy via)。 As shown in FIG. 2B , at least one electronic component 21 is disposed on the first side 20 a of the circuit structure 20 , and the first column 23 is not electrically connected to the electronic component 21 to serve as a dummy via.

於本實施例中，該電子元件21係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如為半導體晶片，且該被動元件係例如為電阻、電容及電感。於本實施例中，該電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，該作用面21a具有複數電極墊，以藉由複數如銲錫材料、金屬柱(pillar)或其它等之導電凸塊211利用覆晶方式設於該線路結構20之第一側20a上並電性連接該較小線距之佈線層201，使該些高密度之電極墊或導電凸塊211能藉由該線路結構20朝外扇出至第二側20b之較大線距之接點，且以如底膠或非導電底部填充薄膜(NCF)等絕緣材212包覆該些導電凸塊211；或者，該電子元件21可藉由複數銲線(圖未示)以打線方式電性連接該線路結構20之佈線層201；亦或，該電子元件21可直接接觸該線路結構20之佈線層201。因此，有關電子元件21電性連接線路結構20之方式繁多，並不限於上述。 In this embodiment, the electronic component 21 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic element 21 is a semiconductor chip, which has an opposite active surface 21a and a non-active surface 21b. The active surface 21a has a plurality of electrode pads, so as to be connected by a plurality of solder materials, metal pillars (pillar) Or other conductive bumps 211 are provided on the first side 20a of the circuit structure 20 by means of flip-chip and electrically connected to the wiring layer 201 of the smaller line pitch, so that these high-density electrode pads or conductive bumps 211 can fan out to the second side 20b through the wiring structure 20 outwards to the contacts of larger line spacing, and these conductive bumps are covered with insulating materials 212 such as primer or non-conductive underfill film (NCF). block 211; or, the electronic component 21 can be electrically connected to the wiring layer 201 of the circuit structure 20 by a plurality of bonding wires (not shown); or, the electronic component 21 can directly contact the circuit structure 20 wiring layer 201. Therefore, there are various ways for the electronic components 21 to be electrically connected to the circuit structure 20 , which are not limited to the above.

再者，該第一與第二柱體23,28係位於該電子元件21的周圍，如環繞該電子元件21，且將該第一與第二柱體23,28作為中心並以其半徑D之2至3倍形成一圓形熱影響區A，以令該熱影響區A由該第一側20a朝該第二側20b之方向垂直投影，以於該線路結構20中定義出一圓筒狀熱通道S。可理解的是，該圓形熱影響區A的大小會隨著該些柱體的材質熱擴散率而改變，且本實施例中該些柱體使用銅材材質，但不限於此。 Moreover, the first and second columns 23, 28 are located around the electronic component 21, such as surrounding the electronic component 21, and the first and second columns 23, 28 are taken as the center and the radius D 2 to 3 times to form a circular heat-affected zone A, so that the heat-affected zone A is vertically projected from the first side 20a to the second side 20b, so as to define a cylindrical shape in the circuit structure 20 hot aisle S. It can be understood that the size of the circular heat-affected zone A will vary with the thermal diffusivity of the material of the pillars, and the pillars are made of copper in this embodiment, but is not limited thereto.

應可理解地，於其它實施例中，亦可於該線路結構20上先設置該電子元件21，再形成該第一及第二柱體23,28。 It should be understood that, in other embodiments, the electronic component 21 may also be disposed on the circuit structure 20 first, and then the first and second pillars 23 , 28 are formed.

如圖2C所示，於該線路結構20之第一側20a上形成一封裝層22，以令該封裝層22一併包覆該電子元件21與該作用結構2a，且令該作用結構2a之部分表面(如該第一與第二柱體23,28之上表面)外露於該封裝層22。 As shown in FIG. 2C, an encapsulation layer 22 is formed on the first side 20a of the circuit structure 20, so that the encapsulation layer 22 covers the electronic component 21 and the active structure 2a together, and makes the active structure 2a Part of the surface (such as the upper surface of the first and second pillars 23 , 28 ) is exposed to the encapsulation layer 22 .

於本實施例中，該封裝層22係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。 In this embodiment, the encapsulation layer 22 is an insulating material, such as polyimide (PI for short), dry film (dry film), encapsulation colloid or encapsulation material (molding compound) such as epoxy resin (epoxy). ).

再者，可藉由整平製程，使該封裝層22之表面22a齊平該電子元件21之非作用面21b與該第一及第二柱體23,28之端面23a,28a，以令該電子元件21之非作用面21b與該第一及第二柱體23,28之端面23a,28a外露於該封裝層22之表面22a。例如，該整平製程係藉由研磨方式，移除該電子元件21之部分材質、該作用結構2a之部分材質與該封裝層22之部分材質。應可理解地，該封裝層22亦可採用開孔形式外露該電子元件21之非作用面21b與該第一及第二柱體23,28之端面23a,28a。 Furthermore, the surface 22a of the encapsulation layer 22 can be flushed with the non-active surface 21b of the electronic component 21 and the end surfaces 23a, 28a of the first and second pillars 23, 28 through a leveling process, so that the The non-active surface 21b of the electronic component 21 and the end surfaces 23a, 28a of the first and second columns 23, 28 are exposed on the surface 22a of the encapsulation layer 22 . For example, the leveling process removes part of the material of the electronic component 21 , part of the material of the functional structure 2 a and part of the material of the encapsulation layer 22 by grinding. It should be understood that the encapsulation layer 22 may also expose the non-active surface 21b of the electronic component 21 and the end surfaces 23a, 28a of the first and second pillars 23, 28 in the form of openings.

又，於另一實施例中，如圖4A所示，於該線路結構20上設置該電子元件21後，亦可先形成封裝層22，再於該封裝層22上形成至少一或複數外露該絕緣層200(甚至外露該功能部202)之穿孔40，之後，於該穿孔40中形成易導熱材，供作為該作用結構2a。 Moreover, in another embodiment, as shown in FIG. 4A, after the electronic component 21 is disposed on the circuit structure 20, the encapsulation layer 22 can also be formed first, and then at least one or a plurality of exposed elements can be formed on the encapsulation layer 22. The perforation 40 of the insulating layer 200 (even exposing the functional part 202 ), and then, a heat-conducting material is formed in the perforation 40 to serve as the functional structure 2 a.

如圖2D所示，移除該支撐板9，以露出該線路結構20之第二側20b，且沿如圖2C所示之切割路徑Y進行切單製程。接著，於該線路結構20之第二側20b上形成複數接合元件24及複數導電元件25，以形成本發明之電子封裝件2，其中，該些接合元件24與該些導電元件25係電性連接該佈線層201，以令該電子元件21電性導通至該些導電元件25及該些接合元件24。 As shown in FIG. 2D , the support plate 9 is removed to expose the second side 20 b of the circuit structure 20 , and a singulation process is performed along the cutting path Y shown in FIG. 2C . Then, a plurality of bonding elements 24 and a plurality of conductive elements 25 are formed on the second side 20b of the circuit structure 20 to form the electronic package 2 of the present invention, wherein the bonding elements 24 and the conductive elements 25 are electrically connected. The wiring layer 201 is connected so that the electronic element 21 is electrically connected to the conductive elements 25 and the bonding elements 24 .

於本實施例中，該第一及第二柱體23,28與該接合元件24的位置分設於該線路結構20的第一側20a與第二側20b，並使該第一及第二柱體23,28與該接合元件24呈現上下位置相互對應之配置。 In this embodiment, the positions of the first and second columns 23, 28 and the bonding element 24 are respectively located on the first side 20a and the second side 20b of the circuit structure 20, so that the first and second The cylinders 23, 28 and the engaging element 24 are arranged in a position corresponding to each other up and down.

再者，該接合元件24與該導電元件25均為如銅或其它導電材之金屬凸塊，且該接合元件24、該導電元件25與該導電凸塊211之材質可相同或相異。 Furthermore, the bonding element 24 and the conductive element 25 are metal bumps such as copper or other conductive materials, and the materials of the bonding element 24 , the conductive element 25 and the conductive bump 211 can be the same or different.

又，該接合元件24係至少局部係對應落入該圓形熱影響區A所定義出之熱通道S之範圍中。例如，該接合元件24以相對該第一柱體23呈同心圓方式全部對應落入該熱通道S之範圍中，如圖3A所示；或者，該接合元件24以相對該第一柱體23呈偏心圓方式全部對應落入該熱通道S之範圍中，如圖3B所示。換言之，該第一柱體23與該接合元件24的相對位置可呈中心對齊關係(如圖3A所示)或不對齊關係(如圖3B所示)，只要該接合元件24之位置交集該熱通道S即可。 Moreover, the joining element 24 is at least partially corresponding to fall within the scope of the heat channel S defined by the circular heat-affected zone A. For example, the joining element 24 is concentric with respect to the first cylinder 23 and all correspondingly fall into the scope of the heat channel S, as shown in FIG. 3A; The eccentric circles all correspond to fall within the range of the heat passage S, as shown in FIG. 3B . In other words, the relative positions of the first cylinder 23 and the bonding element 24 can be center-aligned (as shown in FIG. 3A ) or non-aligned (as shown in FIG. 3B ), as long as the position of the bonding element 24 intersects the heat Channel S is enough.

應可理解地，該接合元件24對應落入該熱通道S之方式繁多，如圖3C所示之接合元件24之位置部分交集該熱通道S(四個圓形熱影響區A1,A2,A3,A4)，並無特別限制。 It should be understood that there are many ways for the bonding element 24 to fall into the heat channel S. The position of the bonding element 24 shown in FIG. ,A4), there is no special limitation.

另外，可將單一該接合元件24對應複數個柱體，如圖3C所示之四個第一柱體23，且該些第一柱體23係相對該接合元件24對稱排列，並使該接合元件24僅局部對應落入由四個熱影響區A1,A2,A3,A4所定義出之熱通道S之範圍中，其中，該第一柱體23的直徑R1(或如圖2D所示之第二柱體28之直徑R2)與該接合元件24的直徑R之比例(R1/R或R2/R)可介於0.2至0.4之間。或者，將單一柱體對應複數該接合元件24，如圖3D所示之一個第一柱體23對應四個接合元件24，且該些接合元件24係相對該第一柱體23對稱排列並完全對應落入該熱通道S之範圍中，其中，該第一柱體23的直徑R1(或如圖2D所示之第二柱體28之直徑R2)與該接合元件24的直徑R之比例(R1/R或R2/R)可介於0.8至1.2之間。另需注意，前述圖3A~圖3D主要以第一柱體23作為說明，而接合元件24亦可同樣至少局部係對應落入該第二柱體28之圓形熱影響區A所定義出之熱通道S，於此不再贅述。 In addition, a single joint element 24 can be corresponding to a plurality of cylinders, such as the four first cylinders 23 shown in FIG. The element 24 only partially corresponds to fall in the range of the heat channel S defined by the four heat-affected zones A1, A2, A3, A4, wherein the diameter R1 of the first column 23 (or as shown in FIG. 2D The ratio (R1/R or R2/R) of the diameter R2) of the second cylinder 28 to the diameter R of the engaging element 24 may be between 0.2 and 0.4. Alternatively, a single cylinder corresponds to a plurality of joint elements 24, and a first cylinder 23 as shown in FIG. Correspondingly fall within the range of the heat channel S, wherein the ratio of the diameter R1 of the first cylinder 23 (or the diameter R2 of the second cylinder 28 shown in FIG. 2D ) to the diameter R of the joining element 24 ( R1/R or R2/R) may be between 0.8 and 1.2. It should also be noted that the aforementioned Figures 3A to 3D mainly use the first cylinder 23 as an illustration, and the bonding element 24 can also at least partially correspond to the circular heat-affected zone A defined by the second cylinder 28. The hot channel S will not be described in detail here.

應可理解地，該第一柱體23與該接合元件24之數量與位置均可視需求針對該熱影響區A,A1,A2,A3,A4的分布進行調整，並不限於上述。 It should be understood that the number and positions of the first pillars 23 and the joint elements 24 can be adjusted according to the requirements for the distribution of the heat-affected zones A, A1, A2, A3, A4, and are not limited to the above.

於後續製程中，如圖2E所示，該電子封裝件2可以其接合元件24與導電元件25藉由銲錫材料26,27接置於一電路板3a之接點30上，再進行回銲製程，以藉由雷射L輔助加熱回銲該銲錫材料26,27，其中，該雷射L係由該封裝層22朝向該線路結構20之方向照射，故該雷射L除了穿透該電子元件21將熱能傳遞至該線路結構20之第二側20b，更可藉由加熱路徑(即從該作用結構2a至該熱通道S)將熱能傳遞至該線路結構20之第二側20b，以強化加熱回銲該接合元件24上之銲錫材料26及加熱回銲該導電元件25上之銲錫材料27。應可理解地，因雷射L無法穿透該封裝層22，故該作用結構2a之第一及第二柱體23,28需外露於該封裝層22且需貫穿該封裝層22，以令該第一及第二柱體23,28從該封裝層22連通至該線路結構20。 In the subsequent process, as shown in FIG. 2E , the electronic package 2 can be placed on the contact 30 of a circuit board 3a by connecting the bonding element 24 and the conductive element 25 with the solder material 26, 27, and then the reflow process is performed. , to heat and resolder the solder materials 26, 27 assisted by laser L, wherein the laser L is irradiated from the encapsulation layer 22 toward the direction of the circuit structure 20, so the laser L not only penetrates the electronic component 21 transfer heat energy to the second side 20b of the circuit structure 20, and transfer heat energy to the second side 20b of the circuit structure 20 through the heating path (ie from the active structure 2a to the heat channel S) to strengthen The solder material 26 on the bonding element 24 is heated and reflowed, and the solder material 27 on the conductive element 25 is heated and reflowed. It should be understood that since the laser L cannot penetrate the encapsulation layer 22, the first and second pillars 23, 28 of the functional structure 2a need to be exposed to the encapsulation layer 22 and penetrate the encapsulation layer 22, so that The first and second pillars 23 , 28 communicate from the encapsulation layer 22 to the wiring structure 20 .

或者，如圖4B所示，於後續製程中，可於該第一及第二柱體23,28外露於該封裝層22之端面上藉由銲錫材料46堆疊至少一封裝模組4a，以形成堆疊型封裝件4(Package on Package，簡稱PoP)，其中，該封裝模組4a係包含至少一半導體晶片41，故該封裝模組4a可依需求設計，如可類似圖2D之電子封裝件2之態樣，並無特別限制。 Alternatively, as shown in FIG. 4B , in subsequent processes, at least one packaging module 4a can be stacked with solder material 46 on the end faces of the first and second pillars 23, 28 exposed on the packaging layer 22 to form Stacked package 4 (Package on Package, referred to as PoP), wherein the package module 4a includes at least one semiconductor chip 41, so the package module 4a can be designed according to requirements, such as the electronic package 2 similar to FIG. 2D There are no special restrictions on the form.

因此，本發明之製法中，主要藉由該作用結構2a埋設於該封裝層22中，以作為雷射輔助接合(laser assisted bonding，簡稱LAB)製程的導熱途徑，使雷射L可藉由該些貫穿該封裝層22的第一及第二柱體23,28穿過該封裝層22而加熱該熱通道S下方的接合元件24，且該第一及第二柱體23,28與接合元件24之位置呈上下對應，因而得以強化回銲該接合元件24上之銲錫材料26，故相較於習知技術，本發明之製法能有效改善該銲錫材料26未濕潤(non-wetting)之問題，使該接合元件24上之銲錫材料26能順利融熔並接固該電路板3a。 Therefore, in the manufacturing method of the present invention, the functional structure 2a is mainly buried in the encapsulation layer 22 as a heat conduction path for the laser assisted bonding (LAB) process, so that the laser L can pass through the encapsulation layer 22. Some first and second pillars 23, 28 penetrating through the encapsulation layer 22 pass through the encapsulation layer 22 to heat the bonding element 24 below the heat channel S, and the first and second pillars 23, 28 and the bonding element The position of 24 corresponds up and down, so that the solder material 26 on the joining element 24 can be strengthened for reflow. Therefore, compared with the prior art, the method of the present invention can effectively improve the non-wetting problem of the solder material 26 , so that the solder material 26 on the bonding element 24 can be smoothly melted and bonded to the circuit board 3a.

再者，藉由該接合元件24的位置落在該熱通道S之範圍中，以提升LAB製程之加熱效能。 Furthermore, the heating performance of the LAB process is improved by the position of the bonding element 24 falling within the range of the heat channel S.

進一步，於LAB製程中，若該線路結構20屬於較易發生翹曲之無核心層(coreless)形式之封裝基板時，則藉由該第一柱體23之設計，更能凸顯改善熱應力問題之效益。 Furthermore, in the LAB process, if the wiring structure 20 is a coreless packaging substrate that is more likely to warp, the design of the first pillar 23 can significantly improve the problem of thermal stress benefits.

另外，若該作用結構2a(如第二柱體28)連接該線路結構20之接地用功能部202，則除了作為該LAB製程的熱傳導路徑，還可提供屏蔽(shielding)功能，且若該作用結構2a(如第二柱體28)連接傳遞訊號用之功能部202，還可提供該堆疊型封裝件4的上下連通之電性路徑。 In addition, if the functional structure 2a (such as the second column 28) is connected to the grounding functional part 202 of the circuit structure 20, it can also provide a shielding function in addition to being a heat conduction path for the LAB process. The structure 2 a (such as the second pillar 28 ) is connected to the functional part 202 for signal transmission, and can also provide an electrical path for the stacked package 4 to connect up and down.

本發明亦提供一種電子封裝件2，其包括：一線路結構20、至少一電子元件21、一封裝層22、一作用結構2a以及至少一接合元件24。 The present invention also provides an electronic package 2 , which includes: a circuit structure 20 , at least one electronic component 21 , a packaging layer 22 , an active structure 2 a and at least one bonding component 24 .

所述之線路結構20係具有相對之第一側20a與第二側20b。 The circuit structure 20 has a first side 20a and a second side 20b opposite to each other.

所述之電子元件21係配置於該線路結構20之第一側20a。 The electronic component 21 is disposed on the first side 20 a of the circuit structure 20 .

所述之封裝層22係配置於該線路結構20之第一側20a以包覆該電子元件21。 The encapsulation layer 22 is disposed on the first side 20 a of the circuit structure 20 to cover the electronic component 21 .

所述之作用結構2a係嵌埋於該封裝層22中並連通至該線路結構20之第一側20a且位於該電子元件21的周圍，其中，該作用結構2a係外露於該封裝層22之表面22a。 The active structure 2a is embedded in the encapsulation layer 22 and connected to the first side 20a of the circuit structure 20 and is located around the electronic component 21, wherein the active structure 2a is exposed on the encapsulation layer 22 Surface 22a.

所述之接合元件24係對應該作用結構2a之位置而配置於該線路結構20之第二側20b上，以令該接合元件24與該作用結構2a之間形成熱導通。 The bonding element 24 is disposed on the second side 20b of the circuit structure 20 corresponding to the position of the active structure 2a, so as to form thermal conduction between the bonding element 24 and the active structure 2a.

於一實施例中，該作用結構2a係包含無電性功能之第一柱體23。 In one embodiment, the functional structure 2a includes a first pillar 23 with no electrical function.

於一實施例中，該作用結構2a係包含第二柱體28，其連接該線路結構20之功能部202。 In one embodiment, the functional structure 2 a includes a second column 28 connected to the functional portion 202 of the circuit structure 20 .

於一實施例中，該線路結構20係包含如扇出型重佈線路層之佈線層201。 In one embodiment, the circuit structure 20 includes a wiring layer 201 such as a fan-out redistribution wiring layer.

於一實施例中，該第一及第二柱體23,28係作為中心並以其半徑D之2至3倍形成一圓形熱影響區A,A1,A2,A3,A4，以令該熱影響區A,A1,A2,A3,A4由該第一側20a朝該第二側20b之方向垂直投影，以於該線路結構20中定義出熱通道S，使該接合元件24至少局部對應落入該熱通道S之範圍中。 In one embodiment, the first and second columns 23, 28 are used as the center and form a circular heat-affected zone A, A1, A2, A3, A4 with 2 to 3 times the radius D, so that the The heat-affected zones A, A1, A2, A3, A4 are vertically projected from the first side 20a toward the second side 20b, so as to define a heat channel S in the circuit structure 20, so that the bonding element 24 at least partially corresponds to Fall into the scope of the hot channel S.

於一實施例中，單一該接合元件24係對應複數該柱體(至少包含複數第一柱體23，可依需求包含該第二柱體28)。 In one embodiment, a single joint element 24 corresponds to a plurality of columns (including at least a plurality of first columns 23 , and may include a plurality of second columns 28 as required).

於一實施例中，單一該第一柱體23或第二柱體28係對應複數該接合元件24。 In one embodiment, a single first column 23 or second column 28 corresponds to a plurality of the joint elements 24 .

於一實施例中，該第一柱體23與該接合元件24的直徑比例(R1/R)係為0.2至0.4或0.8至1.2，且該第二柱體28與該接合元件24的直徑比例(R2/R)係為0.2至0.4或0.8至1.2。 In one embodiment, the diameter ratio (R1/R) of the first cylinder 23 to the joint element 24 is 0.2 to 0.4 or 0.8 to 1.2, and the diameter ratio of the second cylinder 28 to the joint element 24 (R2/R) is 0.2 to 0.4 or 0.8 to 1.2.

綜上所述，本發明之電子封裝件及其製法，係藉由該作用結構埋設於該封裝層中，使雷射可藉由該作用結構穿過該封裝層而加熱該熱通道下方的接合元件，因而得以將熱能傳遞至該接合元件以回銲其上之銲錫材料，故本發明能有效改善該銲錫材料未濕潤之問題。 In summary, the electronic package and its manufacturing method of the present invention are embedded in the encapsulation layer through the active structure, so that the laser can pass through the encapsulation layer through the active structure to heat the joint under the heat channel Components, so heat energy can be transferred to the bonding components to reflow the solder material thereon, so the present invention can effectively improve the problem of non-wetting of the solder material.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patent application described later.

2:電子封裝件 2: Electronic package

2a:作用結構 2a: Action structure

20:線路結構 20: Line structure

20a:第一側 20a: First side

20b:第二側 20b: Second side

200:絕緣層 200: insulating layer

201:佈線層 201: wiring layer

21:電子元件 21: Electronic components

22:封裝層 22: Encapsulation layer

23:第一柱體 23: The first column

24:接合元件 24: Joining elements

25:導電元件 25: Conductive element

28:第二柱體 28: Second cylinder

A:熱影響區 A: Heat affected zone

R,R1,R2:直徑 R, R1, R2: Diameter

S:熱通道 S: hot aisle

Claims (18)

一種電子封裝件，係包括： An electronic package, comprising: 線路結構，係具有相對之第一側與第二側； a circuit structure having opposing first and second sides; 電子元件，係配置於該線路結構之第一側； Electronic components are arranged on the first side of the circuit structure; 封裝層，係配置於該線路結構之第一側以包覆該電子元件； An encapsulation layer is disposed on the first side of the circuit structure to cover the electronic component; 作用結構，係嵌埋於該封裝層中並位於該電子元件的周圍，其中，該作用結構係外露於該封裝層之上表面並連通至該線路結構之第一側；以及 An active structure is embedded in the encapsulation layer and located around the electronic component, wherein the active structure is exposed on the upper surface of the encapsulation layer and connected to the first side of the circuit structure; and 接合元件，係對應該作用結構之位置而配置於該線路結構之第二側上，以令該接合元件與該作用結構之間形成熱導通。 The bonding element is arranged on the second side of the wiring structure corresponding to the position of the active structure, so as to form thermal conduction between the bonding element and the active structure. 如請求項1所述之電子封裝件，其中，該作用結構係包含無電性功能之柱體。 The electronic package as claimed in claim 1, wherein the functional structure includes pillars with no electrical function. 如請求項1所述之電子封裝件，其中，該作用結構係連接該線路結構之功能部。 The electronic package according to claim 1, wherein the functional structure is a functional part connected to the circuit structure. 如請求項1所述之電子封裝件，其中，該線路結構係包含扇出型重佈線路層。 The electronic package as claimed in claim 1, wherein the wiring structure includes a fan-out redistribution wiring layer. 如請求項1所述之電子封裝件，其中，該作用結構係包含柱體，其係作為中心並以其半徑之2至3倍形成一圓形熱影響區，以令該熱影響區由該第一側朝該第二側之方向垂直投影，俾於該線路結構中定義出熱通道，而使該接合元件至少局部對應落入該熱通道之範圍中。 The electronic package as claimed in claim 1, wherein the functional structure includes a column, which is used as a center and forms a circular heat-affected zone with 2 to 3 times its radius, so that the heat-affected zone is formed by the The first side is vertically projected toward the second side, so as to define a thermal channel in the circuit structure, so that the bonding element at least partially falls within the scope of the thermal channel. 如請求項1所述之電子封裝件，其中，該作用結構係包含複數柱體，以令單一該接合元件對應至少二該柱體。 The electronic package according to claim 1, wherein the functional structure includes a plurality of pillars, so that a single bonding element corresponds to at least two pillars. 如請求項1所述之電子封裝件，其中，該作用結構係包含至少一柱體，以令單一該柱體對應複數該接合元件。 The electronic package as claimed in claim 1, wherein the functional structure includes at least one pillar, so that a single pillar corresponds to a plurality of the bonding elements. 如請求項1所述之電子封裝件，其中，該作用結構係包含至少一柱體，且該柱體與該接合元件的直徑比例為0.2至0.4或0.8至1.2。 The electronic package as claimed in claim 1, wherein the active structure includes at least one pillar, and the diameter ratio of the pillar to the bonding element is 0.2 to 0.4 or 0.8 to 1.2. 一種電子封裝件之製法，係包括： A method for manufacturing an electronic package, comprising: 提供一線路結構，其具有相對之第一側與第二側； providing a circuit structure having opposite first and second sides; 將電子元件配置於該線路結構之第一側； disposing electronic components on the first side of the circuit structure; 形成封裝層於該線路結構之第一側，以令該封裝層包覆該電子元件，且於該封裝層中對應該電子元件的周圍嵌埋作用結構，其中，該作用結構係外露於該封裝層之上表面並連通至該線路結構之第一側；以及 forming an encapsulation layer on the first side of the circuit structure, so that the encapsulation layer covers the electronic component, and embeds an active structure in the encapsulation layer corresponding to the surrounding of the electronic element, wherein the active structure is exposed to the encapsulation The upper surface of the layer is connected to the first side of the wiring structure; and 形成接合元件於該線路結構之第二側上，且使該接合元件對應該作用結構之位置，以令該接合元件與該作用結構之間形成熱導通。 A joint element is formed on the second side of the wiring structure, and the position of the joint element corresponds to the active structure, so that heat conduction is formed between the joint element and the active structure. 如請求項9所述之電子封裝件之製法，其中，該作用結構係包含無電性功能之柱體。 The method for manufacturing an electronic package according to claim 9, wherein the functional structure includes pillars with no electrical function. 如請求項9所述之電子封裝件之製法，其中，該作用結構係連接該線路結構之功能部。 The method for manufacturing an electronic package according to Claim 9, wherein the functional structure is a functional part connected to the circuit structure. 如請求項9所述之電子封裝件之製法，其中，該線路結構係包含扇出型重佈線路層。 The method for manufacturing an electronic package according to Claim 9, wherein the wiring structure includes a fan-out redistribution wiring layer. 如請求項9所述之電子封裝件之製法，其中，該作用結構係包含柱體，其係作為中心並以其半徑之2至3倍形成一圓形熱影響區，以令該熱影響區由該第一側朝該第二側之方向垂直投影，俾於該線路結構中定義出熱通道，而使該接合元件至少局部對應落入該熱通道之範圍中。 The method for making an electronic package as described in claim 9, wherein the functional structure includes a column, which is used as a center and forms a circular heat-affected zone with 2 to 3 times its radius, so that the heat-affected zone A vertical projection from the first side toward the second side is used to define a thermal channel in the wiring structure, so that the bonding element at least partially falls within the range of the thermal channel. 如請求項9所述之電子封裝件之製法，其中，該作用結構係包含複數柱體，以令單一該接合元件對應至少二該柱體。 The method for manufacturing an electronic package according to claim 9, wherein the functional structure includes a plurality of pillars, so that a single bonding element corresponds to at least two pillars. 如請求項9所述之電子封裝件之製法，其中，該作用結構係包含至少一柱體，以令單一該柱體對應複數該接合元件。 The method for manufacturing an electronic package according to claim 9, wherein the functional structure includes at least one pillar, so that a single pillar corresponds to a plurality of the bonding elements. 如請求項9所述之電子封裝件之製法，其中，該作用結構係包含至少一柱體，且該柱體與該接合元件的直徑比例為0.2至0.4或0.8至1.2。 The method for manufacturing an electronic package according to claim 9, wherein the functional structure includes at least one pillar, and the ratio of the diameter of the pillar to the bonding element is 0.2 to 0.4 or 0.8 to 1.2. 如請求項9所述之電子封裝件之製法，其中，該作用結構係先形成於該線路結構之第一側上，再將該封裝層一併包覆該作用結構與該電子元件。 The method for manufacturing an electronic package as claimed in Claim 9, wherein the active structure is first formed on the first side of the circuit structure, and then the encapsulation layer covers the active structure and the electronic component together. 如請求項9所述之電子封裝件之製法，其中，該線路結構之第一側上設置該電子元件後，先令該封裝層包覆該電子元件，再於該封裝層上形成外露該第一側之穿孔，之後，填充金屬材於該穿孔中形成該作用結構。 The method for manufacturing an electronic package as described in Claim 9, wherein after the electronic component is placed on the first side of the circuit structure, the packaging layer is firstly used to cover the electronic component, and then the packaging layer is formed to expose the second A perforation on one side, and then, a filler metal material is formed in the perforation to form the active structure.
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