TW202324181A - Photosensitive device - Google Patents
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- TW202324181A TW202324181A TW110144732A TW110144732A TW202324181A TW 202324181 A TW202324181 A TW 202324181A TW 110144732 A TW110144732 A TW 110144732A TW 110144732 A TW110144732 A TW 110144732A TW 202324181 A TW202324181 A TW 202324181A
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
Abstract
Description
本發明是有關於一種感光裝置。The invention relates to a photosensitive device.
近年來,隨著光電科技的發展,感光裝置的應用層面越來越廣,且感光裝置的感測能力與感測品質也日益提升。以用於感測X光的感光裝置來說,因其便利性及良好影像品質,在醫療上的應用與發展都相當活躍。為了達到更好的感測品質甚至感測動態影像,感光裝置中之感光元件被要求具有高收光面積。一般來說,感光裝置中設置有感光元件以及用於控制感光元件的控制電路,這些控制電路限制了感光元件的面積。因此,高性能感光裝置仍存在有改進的空間。In recent years, with the development of optoelectronic technology, the application level of photosensitive devices has become wider and wider, and the sensing ability and sensing quality of photosensitive devices have also been improved day by day. For the photosensitive device used for sensing X-rays, due to its convenience and good image quality, its application and development in medical treatment are very active. In order to achieve better sensing quality and even detect dynamic images, the photosensitive element in the photosensitive device is required to have a high light-receiving area. Generally speaking, a photosensitive device is provided with a photosensitive element and a control circuit for controlling the photosensitive element, and these control circuits limit the area of the photosensitive element. Therefore, there is still room for improvement in high-performance photosensitive devices.
本發明提供一種感光裝置,其感光元件具有高收光面積的優點。The invention provides a photosensitive device, the photosensitive element of which has the advantage of high light receiving area.
本發明的至少一實施例提供一種感光裝置。感光裝置包括基板、多條傳輸線、多條訊號線、第一感光單元以及第二感光單元。傳輸線與訊號線位於基板之上。傳輸線沿著第一方向延伸。訊號線沿著第二方向延伸。第二方向交錯於第一方向。第一感光單元以及第二感光單元位於基板之上,且連接傳輸線以及訊號線。第一感光單元以及第二感光單元各自包括控制電路以及感光元件。感光元件電性連接控制電路,且包括依序堆疊的第一電極、感光層以及第二電極。第二感光單元之感光元件位於第一感光單元之感光元件的第一方向。第一感光單元之感光元件的第一電極、感光層以及第二電極重疊於連接第二感光單元之對應的訊號線中的至少一條。At least one embodiment of the present invention provides a photosensitive device. The photosensitive device includes a substrate, a plurality of transmission lines, a plurality of signal lines, a first photosensitive unit and a second photosensitive unit. The transmission lines and signal lines are located on the substrate. The transmission line extends along the first direction. The signal line extends along the second direction. The second direction is staggered with the first direction. The first photosensitive unit and the second photosensitive unit are located on the substrate and connected to the transmission line and the signal line. The first photosensitive unit and the second photosensitive unit each include a control circuit and a photosensitive element. The photosensitive element is electrically connected to the control circuit, and includes a first electrode, a photosensitive layer and a second electrode stacked in sequence. The photosensitive element of the second photosensitive unit is located in the first direction of the photosensitive element of the first photosensitive unit. The first electrode, the photosensitive layer and the second electrode of the photosensitive element of the first photosensitive unit overlap at least one of the corresponding signal lines connected to the second photosensitive unit.
圖1A是依照本發明的一實施例的一種感光裝置的上視示意圖。圖1B是圖1A的感光裝置的控制電路的上視示意圖。為了方便說明,圖1A與圖1B省略繪示了感光裝置的基板與絕緣層。圖2是圖1A的線a-a’的剖面示意圖。FIG. 1A is a schematic top view of a photosensitive device according to an embodiment of the present invention. FIG. 1B is a schematic top view of a control circuit of the photosensitive device shown in FIG. 1A . For convenience of illustration, the substrate and insulating layer of the photosensitive device are omitted in FIG. 1A and FIG. 1B . Fig. 2 is a schematic cross-sectional view of line a-a' in Fig. 1A.
請參考圖1A與圖2,感光裝置1包括基板100、多條傳輸線、多條訊號線、第一感光單元10以及第二感光單元20。傳輸線、訊號線、第一感光單元10以及第二感光單元20位於基板100之上。第一感光單元10以及第二感光單元20連接傳輸線以及訊號線。第二感光單元20位於第一感光單元10的第一方向D1。Please refer to FIG. 1A and FIG. 2 , the
在本實施例中,訊號線包括第一訊號線VL1、第二訊號線VL2、第三訊號線VL3、第四訊號線VL4、第五訊號線VL5以及第六訊號線VL6,且傳輸線包括第一傳輸線HL1、第二傳輸線HL2以及第三傳輸線HL3。第一傳輸線HL1、第二傳輸線HL2以及第三傳輸線HL3沿著第一方向D1延伸,第一訊號線VL1、第二訊號線VL2、第三訊號線VL3、第四訊號線VL4、第五訊號線VL5以及第六訊號線VL6沿著第二方向D2延伸,第一方向D1交錯於第二方向D2。In this embodiment, the signal lines include the first signal line VL1, the second signal line VL2, the third signal line VL3, the fourth signal line VL4, the fifth signal line VL5 and the sixth signal line VL6, and the transmission line includes the first The transmission line HL1, the second transmission line HL2 and the third transmission line HL3. The first transmission line HL1, the second transmission line HL2 and the third transmission line HL3 extend along the first direction D1, the first signal line VL1, the second signal line VL2, the third signal line VL3, the fourth signal line VL4, the fifth signal line The VL5 and the sixth signal line VL6 extend along the second direction D2, and the first direction D1 intersects with the second direction D2.
第一感光單元10以及第二感光單元20各自包括控制電路CC以及感光元件LD。為了方便說明第一感光單元10的控制電路CC以及第二感光單元20的控制電路CC,圖1B繪示了半導體圖案層SML、第一導電圖案層M1以及第二導電圖案層M2,並省略繪示其他膜層。在圖1B中,相同的膜層以相同的填充圖案表示。The first
請參考圖1B與圖2,半導體圖案層SML位於基板100之上。在本實施例中,半導體圖案層SML直接形成於基板100上,但本發明不以此為限。在其他實施例中,半導體圖案層SML與基板100之間夾有其他緩衝層。Please refer to FIG. 1B and FIG. 2 , the semiconductor pattern layer SML is located on the
在本實施例中,半導體圖案層SML包括彼此相連或互相分離的多個通道層CH。通道層CH的位置以及數量可以依照實際需求而進行調整。In this embodiment, the semiconductor pattern layer SML includes a plurality of channel layers CH connected to each other or separated from each other. The position and quantity of the channel layer CH can be adjusted according to actual needs.
在一些實施例中,基板100之材質可為玻璃、石英、有機聚合物、或是不透光/反射材料(例如:導電材料、金屬、晶圓、陶瓷或其他可適用的材料)或是其他可適用的材料。若為阻絕基板雜質影響元件特性時,則在基板100上覆蓋一層或多層絕緣層。在一些實施例中,半導體圖案層SML之材質可為非晶矽、多晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導體材料(例如:銦鋅氧化物、銦鎵鋅氧化物或是其他合適的材料、或上述材料之組合)或其他合適的材料或上述材料之組合。In some embodiments, the material of the
第一導電圖案層M1位於基板100之上。在本實施例中,第一導電圖案層M1與基板100之間以及第一導電圖案層M1與半導體圖案層SML之間夾有閘極絕緣層102,閘極絕緣層102例如與第一導電圖案層M1具有相同的圖案,但本發明不以此為限。在其他實施例中,除了設置有導電孔(例如對應源極/汲極的導電孔)的位置以外,閘極絕緣層102整面地覆蓋於基板100上。The first conductive pattern layer M1 is located on the
在本實施例中,第一導電圖案層M1包括多個閘極G以及連接結構CL1。閘極G至少部分重疊於對應的通道層CH。在本實施例中,各通道層CH包括至少一個通道區CR以及多個源極/汲極區SDR,源極/汲極區SDR的摻雜濃度不同於通道區CR的摻雜濃度。舉例來說,源極/汲極區SDR的摻雜濃度大於通道區CR的摻雜濃度。閘極G重疊於通道層CH的通道區CR。In this embodiment, the first conductive pattern layer M1 includes a plurality of gates G and a connection structure CL1. The gate G at least partially overlaps the corresponding channel layer CH. In this embodiment, each channel layer CH includes at least one channel region CR and a plurality of source/drain regions SDR, and the doping concentration of the source/drain regions SDR is different from that of the channel region CR. For example, the doping concentration of the source/drain region SDR is greater than that of the channel region CR. The gate G overlaps the channel region CR of the channel layer CH.
在一些實施例中,第一導電圖案層M1之材質可為鉻、金、銀、銅、錫、鉛、鉿、鎢、鉬、釹、鈦、鉭、鋁、鋅等金屬、上述合金、上述金屬氧化物、上述金屬氮化物或上述之組合或其他導電材料。In some embodiments, the material of the first conductive pattern layer M1 can be chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above-mentioned alloys, the above-mentioned Metal oxides, the aforementioned metal nitrides, or combinations thereof, or other conductive materials.
第一絕緣層110位於第一導電圖案層M1上。第一絕緣層110具有重疊部分半導體圖案層SML的多個通孔及重疊部分第一導電圖案層M1的多個通孔。在一些實施例中,第一絕緣層110亦可稱為層間絕緣層。The first
第二導電圖案層M2位於第一絕緣層110上。在本實施例中,第二導電圖案層M2包括多個第一源極/汲極E1、多個第二源極/汲極E2以及沿著第二方向D2延伸的多條訊號線。訊號線包括第一訊號線VL1、第二訊號線VL2、第三訊號線VL3、第四訊號線VL4、第五訊號線VL5以及第六訊號線VL6。第一源極/汲極E1以及第二源極/汲極E2位於對應的第一傳輸線VL1以及第二傳輸線VL2之間。第二導電圖案層M2填入第一絕緣層110的通孔中以構成導電孔110h,第二導電圖案層M2透過導電孔110h而電性連接至半導體圖案層SML以及第一導電圖案層M1。The second conductive pattern layer M2 is located on the first
在一些實施例中,第二導電圖案層M2之材質可為鉻、金、銀、銅、錫、鉛、鉿、鎢、鉬、釹、鈦、鉭、鋁、鋅等金屬、上述合金、上述金屬氧化物、上述金屬氮化物或上述之組合或其他導電材料。In some embodiments, the material of the second conductive pattern layer M2 can be chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above-mentioned alloys, the above-mentioned Metal oxides, the aforementioned metal nitrides, or combinations thereof, or other conductive materials.
在本實施例中,半導體圖案層SML、第一導電圖案層M1以及第二導電圖案層M2構成多個控制電路CC,其中每個控制電路CC包括第一主動元件T1、第二主動元件T2、第三主動元件T3、第四主動元件T4以及第五主動元件T5。第一主動元件T1、第二主動元件T2、第三主動元件T3、第四主動元件T4以及第五主動元件T5各自包括閘極G、通道層CH、第一源極/汲極E1以及第二源極/汲極E2。In this embodiment, the semiconductor pattern layer SML, the first conductive pattern layer M1 and the second conductive pattern layer M2 form a plurality of control circuits CC, wherein each control circuit CC includes a first active element T1, a second active element T2, The third active element T3, the fourth active element T4 and the fifth active element T5. The first active element T1, the second active element T2, the third active element T3, the fourth active element T4 and the fifth active element T5 each include a gate G, a channel layer CH, a first source/drain E1 and a second Source/Drain E2.
圖3是圖1B的感光裝置的控制電路的電路示意圖。請同時參考圖3與圖1B,第一主動元件T1的閘極G電性連接至第一訊號線VL1,其中第一訊號線VL1例如用於接收第一掃描訊號SL1。第一主動元件T1的第一源極/汲極E1電性連接至第三訊號線VL3,其中第三訊號線VL3例如用於接收參考訊號Vref。在本實施例中,第一主動元件T1的第一源極/汲極E1電性連接至連接結構CL1,且透過連接結構CL1而電性連接至第三訊號線VL3,其中連接結構CL1跨過第二訊號線VL2。FIG. 3 is a schematic circuit diagram of a control circuit of the photosensitive device of FIG. 1B . Please refer to FIG. 3 and FIG. 1B at the same time, the gate G of the first active device T1 is electrically connected to the first signal line VL1 , wherein the first signal line VL1 is for example used to receive the first scan signal SL1 . The first source/drain E1 of the first active device T1 is electrically connected to the third signal line VL3, wherein the third signal line VL3 is for example used to receive the reference signal Vref. In this embodiment, the first source/drain E1 of the first active device T1 is electrically connected to the connection structure CL1, and is electrically connected to the third signal line VL3 through the connection structure CL1, wherein the connection structure CL1 straddles the The second signal line VL2.
第二主動元件T2的閘極G電性連接至第一主動元件T1的第二源極/汲極E2。第二主動元件T2的第一源極/汲極E1電性連接至感光元件LD的第一電極BE(請同時參考圖1A、圖1B與圖2)。The gate G of the second active device T2 is electrically connected to the second source/drain E2 of the first active device T1 . The first source/drain E1 of the second active device T2 is electrically connected to the first electrode BE of the photosensitive device LD (please refer to FIG. 1A , FIG. 1B and FIG. 2 ).
第三主動元件T3的閘極G跨過第二訊號線VL2以及第三訊號線VL3,並電性連接至第四訊號線VL4,其中第四訊號線VL4例如用於接收讀取訊號Read。第三主動元件T3的第一源極/汲極E1電性連接至第二主動元件T2的第二源極/汲極E2。舉例來說,第三主動元件T3的第一源極/汲極E1與第二主動元件T2的第二源極/汲極E2連成一體。第三主動元件T3的第二源極/汲極E2電性連接至第三傳輸線HL3(請參考圖1A與圖1B),其中第三傳輸線HL3電性連接至電流轉電壓電路ICV(請參考圖3)。在一些實施例中,電流轉電壓電路ICV包括放大器OP以及與放大器OP並連之電容C2與開關CLR,但本發明不以此為限。The gate G of the third active device T3 straddles the second signal line VL2 and the third signal line VL3, and is electrically connected to the fourth signal line VL4, wherein the fourth signal line VL4 is for example used to receive the read signal Read. The first source/drain E1 of the third active device T3 is electrically connected to the second source/drain E2 of the second active device T2. For example, the first source/drain E1 of the third active device T3 is integrated with the second source/drain E2 of the second active device T2. The second source/drain E2 of the third active element T3 is electrically connected to the third transmission line HL3 (please refer to FIG. 1A and FIG. 1B ), wherein the third transmission line HL3 is electrically connected to the current-to-voltage circuit ICV (please refer to FIG. 3). In some embodiments, the current-to-voltage circuit ICV includes an amplifier OP, a capacitor C2 and a switch CLR connected in parallel to the amplifier OP, but the invention is not limited thereto.
第四主動元件T4的閘極G跨過第二訊號線VL2至第五訊號線VL5,並電性連接至第六訊號線VL6,其中第六訊號線VL6例如用於接收第三掃描訊號SL3。第四主動元件T4的第一源極/汲極E1電性連接至感光元件LD的第一電極BE(請參考圖1A與圖1B)。第四主動元件T4的第二源極/汲極E2電性連接至第二訊號線VL2,其中第二訊號線VL2例如用於接收電壓訊號VSS。The gate G of the fourth active element T4 straddles the second signal line VL2 to the fifth signal line VL5, and is electrically connected to the sixth signal line VL6, wherein the sixth signal line VL6 is for example used to receive the third scan signal SL3. The first source/drain E1 of the fourth active device T4 is electrically connected to the first electrode BE of the photosensitive device LD (please refer to FIG. 1A and FIG. 1B ). The second source/drain E2 of the fourth active element T4 is electrically connected to the second signal line VL2, wherein the second signal line VL2 is for example used to receive the voltage signal VSS.
第五主動元件T5的閘極G跨過第二訊號線VL2至第四訊號線VL4,並電性連接至第五訊號線VL5,其中第五訊號線VL5例如用於接收第二掃描訊號SL2。第五主動元件T5的第一源極/汲極E1電性連接至感光元件LD的第一電極BE(請參考圖1A與圖1B)。第五主動元件T5的第二源極/汲極E2電性連接至第二傳輸線HL2(請參考圖1A與圖1B),其中第二傳輸線HL2電性連接至電流源I(請參考圖3)。The gate G of the fifth active element T5 straddles the second signal line VL2 to the fourth signal line VL4 and is electrically connected to the fifth signal line VL5, wherein the fifth signal line VL5 is for example used to receive the second scan signal SL2. The first source/drain E1 of the fifth active device T5 is electrically connected to the first electrode BE of the photosensitive device LD (please refer to FIG. 1A and FIG. 1B ). The second source/drain E2 of the fifth active element T5 is electrically connected to the second transmission line HL2 (please refer to FIG. 1A and FIG. 1B ), wherein the second transmission line HL2 is electrically connected to the current source I (please refer to FIG. 3 ). .
在本實施例中,第二主動元件T2的閘極G與第一主動元件T1的第二源極/汲極E2共同電性連接至點S,第二主動元件T2的第一源極/汲極E1、第四主動元件T4的第一源極/汲極E1以及第五主動元件T5的第一源極/汲極E1共同電性連接至點A,點S與點A之間設置有電容C1。In this embodiment, the gate G of the second active element T2 and the second source/drain E2 of the first active element T1 are electrically connected to the point S, and the first source/drain of the second active element T2 The electrode E1, the first source/drain E1 of the fourth active element T4, and the first source/drain E1 of the fifth active element T5 are electrically connected to point A, and a capacitor is arranged between point S and point A C1.
圖1A、圖1B與圖3示意了一種控制電路CC的電路布局,但其目的並非在於限制本發明之控制電路CC的電路布局。本發明之控制電路CC的電路布局可以依照實際需求而進行調整。舉例來說,控制電路CC中之主動元件的數量與位置可以依照實際需求而調整。FIG. 1A , FIG. 1B and FIG. 3 illustrate a circuit layout of a control circuit CC, but the purpose is not to limit the circuit layout of the control circuit CC of the present invention. The circuit layout of the control circuit CC of the present invention can be adjusted according to actual needs. For example, the number and position of active components in the control circuit CC can be adjusted according to actual needs.
請接著參考圖1A與圖2,第一平坦層PL1位於控制電路CC之上。舉例來說,第一平坦層PL1位於第二導電圖案層M2以及第一絕緣層110之上。在一些實施例中,第一平坦層PL1與第二導電圖案層M2之間以及第一平坦層PL1與第一絕緣層110之間更包含第一緩衝層BP1,但本發明不以此為限。在一些實施例中,第一平坦層PL1的厚度例如為0微米至5微米。第一平坦層PL1具有重疊部分第二導電圖案層M2的多個通孔。Please refer to FIG. 1A and FIG. 2 , the first flat layer PL1 is located on the control circuit CC. For example, the first planar layer PL1 is located on the second conductive pattern layer M2 and the first insulating
第三導電圖案層M3位於第一平坦層PL1上。第三導電圖案層M3填入第一平坦層PL1的通孔以構成多個第一導電孔PL1h。The third conductive pattern layer M3 is located on the first planar layer PL1. The third conductive pattern layer M3 fills the through holes of the first planar layer PL1 to form a plurality of first conductive holes PL1h.
在本實施例中,第三導電圖案層M3包括多個第一電極BE、連接結構CL2以及連接結構CL3。第二主動元件T2的第一源極/汲極E1、第四主動元件T4的第一源極/汲極E1以及第五主動元件T5的第一源極/汲極E1共同電性連接至第一電極BE。具體地說,第一電極BE透過貫穿第一平坦層PL1的第一導電孔PL1h而電性連接至第二主動元件T2的第一源極/汲極E1、第四主動元件T4的第一源極/汲極E1以及第五主動元件T5的第一源極/汲極E1。連接結構CL2透過貫穿第一平坦層PL1的第一導電孔PL1h而電性連接至第五主動元件T5的第二源極/汲極E2。連接結構CL3透過貫穿第一平坦層PL1的第一導電孔PL1h而電性連接至第三主動元件T3的第二源極/汲極E2。In this embodiment, the third conductive pattern layer M3 includes a plurality of first electrodes BE, a connection structure CL2 and a connection structure CL3. The first source/drain E1 of the second active element T2, the first source/drain E1 of the fourth active element T4, and the first source/drain E1 of the fifth active element T5 are electrically connected to the first active element T5. An electrode BE. Specifically, the first electrode BE is electrically connected to the first source/drain electrode E1 of the second active element T2 and the first source of the fourth active element T4 through the first conductive hole PL1h penetrating through the first planar layer PL1. The pole/drain E1 and the first source/drain E1 of the fifth active element T5. The connection structure CL2 is electrically connected to the second source/drain E2 of the fifth active device T5 through the first conductive hole PL1h penetrating through the first planar layer PL1 . The connection structure CL3 is electrically connected to the second source/drain E2 of the third active device T3 through the first conductive hole PL1h penetrating through the first planar layer PL1 .
在一些實施例中,第三導電圖案層M3之材質可為鉻、金、銀、銅、錫、鉛、鉿、鎢、鉬、釹、鈦、鉭、鋁、鋅等金屬、上述合金、上述金屬氧化物、上述金屬氮化物或上述之組合或其他導電材料。In some embodiments, the material of the third conductive pattern layer M3 can be chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above-mentioned alloys, the above-mentioned Metal oxides, the aforementioned metal nitrides, or combinations thereof, or other conductive materials.
多個感光層SR位於第一電極BE之上。舉例來說,感光層SR直接形成於第一電極BE上。在一些實施例中,感光層SR包括半導體堆疊層,例如包括P型半導體、本質半導體以及N型半導體的堆疊層。在其他實施例中,感光層SR的材質包括富矽氧化矽層、富矽氮化矽層、富矽氮氧化矽層、富矽碳化矽層、富矽碳氧化矽層、氫化富矽氧化矽層、氫化富矽氮化矽層、氫化富矽碳化矽層、氫化非晶矽、氫化微晶矽、氫化多晶矽或其組合。A plurality of photosensitive layers SR are located on the first electrode BE. For example, the photosensitive layer SR is directly formed on the first electrode BE. In some embodiments, the photosensitive layer SR includes semiconductor stacked layers, for example, stacked layers including P-type semiconductors, intrinsic semiconductors, and N-type semiconductors. In other embodiments, the material of the photosensitive layer SR includes a silicon-rich silicon oxide layer, a silicon-rich silicon nitride layer, a silicon-rich silicon oxynitride layer, a silicon-rich silicon carbide layer, a silicon-rich silicon carbide layer, and a hydrogenated silicon-rich silicon oxide layer. layer, hydrogenated silicon-rich silicon nitride layer, hydrogenated silicon-rich silicon carbide layer, hydrogenated amorphous silicon, hydrogenated microcrystalline silicon, hydrogenated polycrystalline silicon, or a combination thereof.
多個第二電極TE位於感光層SR上。舉例來說,第二電極TE直接形成於感光層SR上。在本實施例中,第二電極TE與感光層SR具有相似的投影形狀,第二電極TE與感光層SR可以藉由相同或不同的圖案化製程(蝕刻製程)所定義。當第二電極TE與感光層SR藉由相同的圖案化製程所定義時,第二電極TE與感光層SR的側壁切齊,藉此節省圖案化製程所需要的光罩數量,但本發明不以此為限。在其他實施例中,第二電極TE與感光層SR的側壁不切齊。A plurality of second electrodes TE are located on the photosensitive layer SR. For example, the second electrode TE is directly formed on the photosensitive layer SR. In this embodiment, the second electrode TE and the photosensitive layer SR have similar projected shapes, and the second electrode TE and the photosensitive layer SR may be defined by the same or different patterning processes (etching processes). When the second electrode TE and the photosensitive layer SR are defined by the same patterning process, the second electrode TE is aligned with the sidewall of the photosensitive layer SR, thereby saving the number of photomasks required for the patterning process, but the present invention does not This is the limit. In other embodiments, the second electrode TE is not aligned with the sidewall of the photosensitive layer SR.
在一些實施例中,第二電極TE包括透明導電材料,例如銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鎵鋅氧化物、或是上述至少二者之堆疊層。In some embodiments, the second electrode TE includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or a stack of at least two of the above layer.
在本實施例中,多個第一電極BE、多個感光層SR以及多個第二電極TE構成多個感光元件LD。在本實施例中,每個感光元件LD包括依序堆疊的第一電極BE、感光層SR以及第二電極TE。In this embodiment, a plurality of first electrodes BE, a plurality of photosensitive layers SR, and a plurality of second electrodes TE constitute a plurality of photosensitive elements LD. In this embodiment, each photosensitive element LD includes a first electrode BE, a photosensitive layer SR and a second electrode TE stacked in sequence.
在本實施例中,第一感光單元10以及第二感光單元20各自包括感光元件LD以及控制電路CC,第二感光單元20之感光元件LD位於第一感光單元10之感光元件LD的第一方向D1,且第一感光單元10之感光元件LD分離於第二感光單元20之感光元件LD。感光元件LD電性連接控制電路CC,且第一平坦層PL1位於控制電路CC與感光元件LD之間。在一些實施例中,第一平坦層PL1中設置有貫穿第一平坦層PL1的多個第一導電孔PL1h,且感光元件LD之感光層SR與第二電極TE不重疊於第一導電孔PL1h。在本實施例中,感光元件LD的感光層SR包括凹槽GV。舉例來說,第二感光單元20之感光元件LD的凹槽GV位於第二感光單元20之感光元件LD靠近第一感光單元10的一側。In this embodiment, the first
在一些實施例中,第一平坦層PL1在靠近第一導電孔PL1h的位置處容易出現表面不平整的問題,因此,為了避免感光元件LD因為不平整而導致良率不佳,將感光層SR避開第一導電孔PL1h的位置設置,換句話說,感光層SR的凹槽GV對應於第一導電孔PL1h設置。在本實施例中,凹槽GV重疊於控制電路CC中的部分主動元件(例如包括部分第二主動元件T2、部分第三主動元件T3以及部分第五主動元件T5)。此外,在本實施例中,第二電極TE亦具有類似於感光層SR的凹槽GV之凹槽,且第二電極TE之凹槽的位置對應於感光層SR的凹槽GV的位置。第一電極BE亦具有類似凹槽GV的凹槽,然而,為了使第一電極BE可以電性連接至控制電路CC,第一電極BE需要重疊於其中一個第一導電孔PL1h,導致第一電極BE的凹槽形狀與感光層SR的凹槽GV略為不同。In some embodiments, the surface of the first flat layer PL1 is prone to unevenness near the first conductive hole PL1h. Therefore, in order to avoid poor yield of the photosensitive element LD due to unevenness, the photosensitive layer SR The position avoiding the first conductive hole PL1h is set, in other words, the groove GV of the photosensitive layer SR is set corresponding to the first conductive hole PL1h. In this embodiment, the groove GV overlaps part of the active devices in the control circuit CC (eg including part of the second active device T2 , part of the third active device T3 and part of the fifth active device T5 ). In addition, in this embodiment, the second electrode TE also has a groove similar to the groove GV of the photosensitive layer SR, and the position of the groove of the second electrode TE corresponds to the position of the groove GV of the photosensitive layer SR. The first electrode BE also has a groove similar to the groove GV. However, in order for the first electrode BE to be electrically connected to the control circuit CC, the first electrode BE needs to overlap one of the first conductive holes PL1h, resulting in the first electrode BE The groove shape of BE is slightly different from the groove GV of the photosensitive layer SR.
若每個感光單元中之感光元件只重疊於連接至自己的訊號線,而不重疊於連接至相鄰之感光單元的訊號線,感光元件的位置(例如第一電極、感光層或第二電極的位置)於圖1A中如虛線LD’所示。在本實施例中,藉由使每個感光單元中之感光元件LD往鄰近的其他感光單元靠近,藉此使感光元件LD具有較大的收光面積。舉例來說,在一些實施例中,感光元件LD的左側LD1相較於虛線LD’的左側LD1’的位置往右(往第一方向D1)偏移距離X1,且感光元件LD的右側LD2相較於虛線LD’的右側LD2’的位置往右(往第一方向D1)偏移距離X2。左側LD1與左側LD1’在第二方向D2上的長度L1小於右側LD2與右側LD2’在第二方向D2上的長度L2,因此,感光元件LD的面積比虛線LD’所定義的面積更大。在一些實施例中,距離X1與距離X2介於0微米至100微米。If the photosensitive element in each photosensitive unit only overlaps the signal line connected to itself, and does not overlap the signal line connected to the adjacent photosensitive unit, the position of the photosensitive element (such as the first electrode, photosensitive layer or second electrode) position) in Figure 1A as shown by the dotted line LD'. In this embodiment, by making the photosensitive element LD in each photosensitive unit approach other adjacent photosensitive units, the photosensitive element LD has a larger light receiving area. For example, in some embodiments, the position of the left side LD1 of the photosensitive element LD is shifted to the right (toward the first direction D1) by a distance X1 compared to the position of the left side LD1' of the dotted line LD', and the right side LD2 of the photosensitive element LD is the same as Compared with the position of the right side LD2' of the dotted line LD', the position is shifted to the right (towards the first direction D1) by a distance X2. The length L1 of the left side LD1 and the left side LD1' in the second direction D2 is smaller than the length L2 of the right side LD2 and the right side LD2' in the second direction D2, therefore, the area of the photosensitive element LD is larger than the area defined by the dotted line LD'. In some embodiments, the distance X1 and the distance X2 are between 0 μm and 100 μm.
在本實施例中,第一感光單元10之感光元件LD的第一電極BE、感光層SR以及第二電極TE在垂直基板100的第三方向D3上重疊於連接第二感光單元20之對應的訊號線中的至少一條(例如連接第二感光單元20之第一訊號線VL1)。藉此,使感光元件LD具有較大的收光面積。In this embodiment, the first electrode BE, the photosensitive layer SR, and the second electrode TE of the photosensitive element LD of the first
第二平坦層PL2位於感光元件LD之上。舉例來說,第二平坦層PL2位於第三導電圖案層M3以及第二電極TE之上。在一些實施例中,第二平坦層PL2與第二電極TE之間以及第二平坦層PL2與第三導電圖案層M3之間更包含第二緩衝層BP2,但本發明不以此為限。在一些實施例中,第二平坦層PL2的厚度例如為0微米至5微米。第二平坦層PL2具有重疊部分第三導電圖案層M3以及第二電極TE的多個通孔。The second flat layer PL2 is located on the photosensitive element LD. For example, the second planar layer PL2 is located on the third conductive pattern layer M3 and the second electrode TE. In some embodiments, a second buffer layer BP2 is further included between the second planar layer PL2 and the second electrode TE and between the second planar layer PL2 and the third conductive pattern layer M3 , but the present invention is not limited thereto. In some embodiments, the thickness of the second planar layer PL2 is, for example, 0 micrometers to 5 micrometers. The second flat layer PL2 has a plurality of through holes overlapping portions of the third conductive pattern layer M3 and the second electrode TE.
第四導電圖案層M4位於第二平坦層PL2上。第四導電圖案層M4填入第二平坦層PL2的通孔以構成多個第二導電孔PL2h。在本實施例中,第四導電圖案層M4包括第一傳輸線HL1、第二傳輸線HL2以及第三傳輸線HL3。第一傳輸線HL1透過第二導電孔PL2h而電性連接至感光元件LD的第二電極TE。第二傳輸線HL2透過第二導電孔PL2h而電性連接至連接結構CL2,並透過連接結構CL2而電性連接至第五主動元件T5的第二源極/汲極E2。第三傳輸線HL3透過第二導電孔PL2h而電性連接至連接結構CL3,並透過連接結構CL3而電性連接至第三主動元件T3的第二源極/汲極E2。The fourth conductive pattern layer M4 is located on the second planar layer PL2. The fourth conductive pattern layer M4 fills the through holes of the second planar layer PL2 to form a plurality of second conductive holes PL2h. In this embodiment, the fourth conductive pattern layer M4 includes a first transmission line HL1 , a second transmission line HL2 and a third transmission line HL3 . The first transmission line HL1 is electrically connected to the second electrode TE of the photosensitive element LD through the second conductive hole PL2h. The second transmission line HL2 is electrically connected to the connection structure CL2 through the second conductive hole PL2h, and is electrically connected to the second source/drain E2 of the fifth active device T5 through the connection structure CL2. The third transmission line HL3 is electrically connected to the connection structure CL3 through the second conductive hole PL2h, and is electrically connected to the second source/drain E2 of the third active device T3 through the connection structure CL3.
在本實施例中,第一感光單元10之控制電路CC與第二感光單元20之控制電路CC電性連接至同一條第一傳輸線HL1、同一條第二傳輸線HL2以及同一條第三傳輸線HL3。In this embodiment, the control circuit CC of the first
第三平坦層PL3位於第四導電圖案層M4以及第二平坦層PL2之上。在一些實施例中,第三平坦層PL3與第四導電圖案層M4之間以及第三平坦層PL3與第二平坦層PL2之間更包含第三緩衝層BP3,但本發明不以此為限。The third planar layer PL3 is located on the fourth conductive pattern layer M4 and the second planar layer PL2. In some embodiments, a third buffer layer BP3 is further included between the third planar layer PL3 and the fourth conductive pattern layer M4 and between the third planar layer PL3 and the second planar layer PL2, but the present invention is not limited thereto. .
圖4A是依照本發明的一實施例的一種感光裝置的上視示意圖。圖4B是圖4A的感光裝置的控制電路的上視示意圖。為了方便說明,圖4A與圖4B省略繪示了感光裝置的基板與絕緣層。FIG. 4A is a schematic top view of a photosensitive device according to an embodiment of the present invention. FIG. 4B is a schematic top view of the control circuit of the photosensitive device shown in FIG. 4A . For convenience of illustration, the substrate and insulating layer of the photosensitive device are omitted in FIG. 4A and FIG. 4B .
在圖4A中,第一感光單元10a以及第二感光單元20a各自包括控制電路CC以及感光元件LD。為了方便說明第一感光單元10a的控制電路CC以及第二感光單元20a的控制電路CC,圖4B繪示了半導體圖案層SML、第一導電圖案層M1以及第二導電圖案層M2,並省略繪示其他膜層。在圖4B中,相同的膜層以相同的填充圖案表示。In FIG. 4A , the first
請參考圖4A與圖4B,感光裝置2包括基板(未繪出)、多條傳輸線、多條訊號線、第一感光單元10a以及第二感光單元20a。傳輸線、訊號線、第一感光單元10a以及第二感光單元20a位於基板之上。第一感光單元10a以及第二感光單元20a連接傳輸線以及訊號線。第二感光單元20a位於第一感光單元10a的第一方向D1。Please refer to FIG. 4A and FIG. 4B , the
在本實施例中,半導體圖案層SML包括彼此相連或互相分離的多個通道層CH,第一導電圖案層M1包括彼此相連或互相分離的多個閘極G。第二導電圖案層M2包括多個第一源極/汲極E1、多個第二源極/汲極E2以及沿著第一方向D1延伸的第一傳輸線HL1與第二傳輸線HL2,第三導電圖案層M3包括多個第一電極BE、連接結構CL2、連接結構CL3以及連接結構CL4,第四導電圖案層M4包括沿著第二方向D2延伸的第一訊號線VL1、第二訊號線VL2、第三訊號線VL3、以及第四訊號線VL4。In this embodiment, the semiconductor pattern layer SML includes a plurality of channel layers CH connected to or separated from each other, and the first conductive pattern layer M1 includes a plurality of gates G connected to or separated from each other. The second conductive pattern layer M2 includes a plurality of first source/drain electrodes E1, a plurality of second source/drain electrodes E2, and a first transmission line HL1 and a second transmission line HL2 extending along the first direction D1. The pattern layer M3 includes a plurality of first electrodes BE, connection structures CL2, connection structures CL3, and connection structures CL4. The fourth conductive pattern layer M4 includes first signal lines VL1, second signal lines VL2, The third signal line VL3 and the fourth signal line VL4.
在本實施例中,半導體圖案層SML、第一導電圖案層M1以及第二導電圖案層M2構成多個控制電路CC,其中每個控制電路CC包括第一主動元件T1、第二主動元件T2以及第三主動元件T3。第一主動元件T1、第二主動元件T2以及第三主動元件T3各自包括閘極G、通道層CH、第一源極/汲極E1以及第二源極/汲極E2。In this embodiment, the semiconductor pattern layer SML, the first conductive pattern layer M1 and the second conductive pattern layer M2 form a plurality of control circuits CC, wherein each control circuit CC includes a first active element T1, a second active element T2 and The third active element T3. The first active device T1 , the second active device T2 and the third active device T3 each include a gate G, a channel layer CH, a first source/drain E1 and a second source/drain E2 .
第一主動元件T1的閘極G電性連接至第一傳輸線HL1。第一主動元件T1的第一源極/汲極E1電性連接至第一訊號線VL1。舉例來說,第一主動元件T1的第一源極/汲極E1透過連接結構CL2而電性連接至第一訊號線VL1。The gate G of the first active device T1 is electrically connected to the first transmission line HL1. The first source/drain E1 of the first active device T1 is electrically connected to the first signal line VL1. For example, the first source/drain E1 of the first active device T1 is electrically connected to the first signal line VL1 through the connection structure CL2.
第二主動元件T2的閘極G電性連接至第二傳輸線HL2。第二主動元件T2的第一源極/汲極E1電性連接至感光元件LD的第一電極BE。第二主動元件T2的第二源極/汲極E2電性連接至第二訊號線VL2。舉例來說,第二主動元件T2的第二源極/汲極E2透過連接結構CL3而電性連接至第二訊號線VL2。The gate G of the second active device T2 is electrically connected to the second transmission line HL2. The first source/drain E1 of the second active device T2 is electrically connected to the first electrode BE of the photosensitive device LD. The second source/drain E2 of the second active device T2 is electrically connected to the second signal line VL2. For example, the second source/drain E2 of the second active device T2 is electrically connected to the second signal line VL2 through the connection structure CL3.
第三主動元件T3的閘極G電性連接至第二主動元件T2的第一源極/汲極E1,第三主動元件T3的第一源極/汲極E1電性連接至第一主動元件T1的第二源極/汲極E2。第三主動元件T3的第二源極/汲極E2電性連接至第四訊號線VL4。舉例來說,第三主動元件T3的第二源極/汲極E2透過連接結構CL4而電性連接至第四訊號線VL4。The gate G of the third active device T3 is electrically connected to the first source/drain E1 of the second active device T2, and the first source/drain E1 of the third active device T3 is electrically connected to the first active device. The second source/drain E2 of T1. The second source/drain E2 of the third active device T3 is electrically connected to the fourth signal line VL4. For example, the second source/drain E2 of the third active device T3 is electrically connected to the fourth signal line VL4 through the connection structure CL4.
感光元件LD的第二電極TE電性連接至第三訊號線VL3。The second electrode TE of the photosensitive element LD is electrically connected to the third signal line VL3.
在本實施例中,各控制電路CC電性連接至第一訊號線VL1、第二訊號線VL2、第三訊號線VL3以及第四訊號線VL4,且各控制電路CC電性連接至第一傳輸線HL1以及第二傳輸線HL2。在本實施例中,第一感光單元10a之控制電路CC與第二感光單元20a之控制電路CC電性連接至同一條第一傳輸線HL1以及同一條第二傳輸線HL2。In this embodiment, each control circuit CC is electrically connected to the first signal line VL1, the second signal line VL2, the third signal line VL3, and the fourth signal line VL4, and each control circuit CC is electrically connected to the first transmission line HL1 and the second transmission line HL2. In this embodiment, the control circuit CC of the first
在本實施例中,第一感光單元10a以及第二感光單元20a各自包括感光元件LD以及控制電路CC,第二感光單元20a之感光元件LD位於第一感光單元10a之感光元件LD的第一方向D1,且第一感光單元10a之感光元件LD分離於第二感光單元20a之感光元件LD。感光元件LD電性連接控制電路CC,且第一平坦層(請參考圖2)位於控制電路CC與感光元件LD之間。在一些實施例中,第一平坦層中設置有貫穿第一平坦層的多個第一導電孔PL1h,且感光元件LD之感光層SR與第二電極TE不重疊於第一導電孔PL1h。在本實施例中,第二感光單元20a之感光元件LD的感光層SR包括凹槽GV,其中凹槽GV位於第二感光單元20a之感光元件LD靠近第一感光單元10a的一側。In this embodiment, the first
在一些實施例中,第一平坦層在第一導電孔PL1h的位置處容易出現表面不平整的問題,因此,為了提升感光元件LD的良率,將感光層SR需要盡量避開第一導電孔PL1h的位置設置。在本實施例中,感光層SR的兩側分別設置有凹槽GV1、GV2。藉由凹槽GV1、GV2的設置,感光層SR僅重疊於連接至感光元件LD的一個第一導電孔PL1h,而不重疊於未連接至感光元件LD的其他第一導電孔PL1h。在本實施例中,第一電極BE與第二電極TE均具有類似於感光層SR的凹槽GV1、GV2。In some embodiments, the first flat layer is likely to have uneven surface at the position of the first conductive hole PL1h. Therefore, in order to improve the yield of the photosensitive element LD, the photosensitive layer SR needs to avoid the first conductive hole as much as possible. Position setting for PL1h. In this embodiment, the two sides of the photosensitive layer SR are provided with grooves GV1 and GV2 respectively. With the arrangement of the grooves GV1 and GV2 , the photosensitive layer SR only overlaps one first conductive hole PL1h connected to the photosensitive element LD, and does not overlap other first conductive holes PL1h not connected to the photosensitive element LD. In this embodiment, both the first electrode BE and the second electrode TE have grooves GV1 and GV2 similar to the photosensitive layer SR.
若每個感光單元中之感光元件只重疊於連接至自己的訊號線,而不重疊於連接至相鄰之感光單元的訊號線,感光元件的位置(例如第一電極、感光層或第二電極的位置)於圖4A中如虛線LD’所示。在本實施例中,藉由使每個感光單元中之感光元件往鄰近的其他感光單元靠近,藉此使感光元件LD具有較大的收光面積。舉例來說,在一些實施例中,感光元件LD的下側LD3相較於虛線LD’的下側LD3’的位置往上(往第一方向D1)偏移距離Y1,且感光元件LD的上側LD4相較於虛線LD’的上側LD4’的位置往上(往第一方向D1)偏移距離Y2。下側LD3與下側LD3’在第二方向D2上的長度L3小於上側LD4與上側LD4’在第二方向D2上的長度L4,因此,感光元件LD的面積比虛線LD’所定義的面積更大。在一些實施例中,距離Y1與距離Y2介於0微米至100微米。If the photosensitive element in each photosensitive unit only overlaps the signal line connected to itself, and does not overlap the signal line connected to the adjacent photosensitive unit, the position of the photosensitive element (such as the first electrode, photosensitive layer or second electrode) position) in Figure 4A as shown by the dotted line LD'. In this embodiment, by making the photosensitive element in each photosensitive unit approach other adjacent photosensitive units, the photosensitive element LD has a larger light receiving area. For example, in some embodiments, the position of the lower side LD3 of the photosensitive element LD is offset upwards (towards the first direction D1) by a distance Y1 compared to the position of the lower side LD3' of the dotted line LD', and the upper side of the photosensitive element LD The position of LD4 on the upper side of the dotted line LD' is shifted upwards (towards the first direction D1 ) by a distance Y2 . The length L3 of the lower side LD3 and the lower side LD3' in the second direction D2 is smaller than the length L4 of the upper side LD4 and the upper side LD4' in the second direction D2. Therefore, the area of the photosensitive element LD is smaller than the area defined by the dotted line LD'. big. In some embodiments, the distance Y1 and the distance Y2 are between 0 micrometers and 100 micrometers.
在本實施例中,第一感光單元10a之感光元件LD的第一電極BE、感光層SR以及第二電極TE在垂直基板100的方向上重疊於連接第二感光單元20a之對應的訊號線中的至少一條(例如連接第二感光單元20a之第一訊號線VL1)。藉此,使感光元件LD具有較大的收光面積。In this embodiment, the first electrode BE, the photosensitive layer SR, and the second electrode TE of the photosensitive element LD of the first
1, 2:感光裝置 10, 10a:第一感光單元 20, 20a:第二感光單元 100:基板 110h:通孔 110:第一絕緣層 a-a’:線 BE:第一電極 BP1:第一緩衝層 BP2:第二緩衝層 BP3:第三緩衝層 CH:通道層 CL1, CL2, CL3:連接結構 CR:通道區 D1:第一方向 D2:第二方向 D3:第三方向 E1:第一源極/汲極 E2:第二源極/汲極 G:閘極 GV, GV1, GV2:凹槽 HL1:第一傳輸線 HL2:第二傳輸線 HL3:第三傳輸線 L1, L2, L3, L4:長度 LD:感光元件 LD1, LD1’:左側 LD2, LD2’:右側 LD3, LD3’:下側 LD4, LD4’:上側 LD’:虛線 M1:第一導電圖案層 M2:第二導電圖案層 M3:第三導電圖案層 M4:第四導電圖案層 PL1:第一平坦層 PL1h:第一導電孔 PL2h:第二導電孔 PL2:第二平坦層 PL3:第三平坦層 SDR:源極/汲極區 SML:半導體圖案層 SR:感光層 T1:第一主動元件 T2:第二主動元件 T3:第三主動元件 T4:第四主動元件 T5:第五主動元件 TE:第二電極 VL1:第一訊號線 VL2:第二訊號線 VL3:第三訊號線 VL4:第四訊號線 VL5:第五訊號線 VL6:第六訊號線 X1, X2, Y1, Y2:距離 1, 2: photosensitive device 10, 10a: The first photosensitive unit 20, 20a: Second photosensitive unit 100: Substrate 110h: through hole 110: the first insulating layer a-a': line BE: first electrode BP1: The first buffer layer BP2: Second buffer layer BP3: The third buffer layer CH: channel layer CL1, CL2, CL3: connection structure CR: channel area D1: the first direction D2: Second direction D3: Third direction E1: first source/drain E2: Second source/drain G: gate GV, GV1, GV2: groove HL1: first transmission line HL2: second transmission line HL3: third transmission line L1, L2, L3, L4: Length LD: photosensitive element LD1, LD1’: left side LD2, LD2': Right side LD3, LD3’: Lower side LD4, LD4’: upper side LD': dotted line M1: the first conductive pattern layer M2: Second conductive pattern layer M3: The third conductive pattern layer M4: The fourth conductive pattern layer PL1: the first flat layer PL1h: the first conductive hole PL2h: Second conductive hole PL2: second flat layer PL3: third flat layer SDR: source/drain region SML: semiconductor pattern layer SR: photosensitive layer T1: The first active component T2: The second active component T3: The third active component T4: The fourth active element T5: fifth active element TE: second electrode VL1: the first signal line VL2: The second signal line VL3: The third signal line VL4: The fourth signal line VL5: fifth signal line VL6: the sixth signal line X1, X2, Y1, Y2: Distance
圖1A是依照本發明的一實施例的一種感光裝置的上視示意圖。 圖1B是圖1A的感光裝置的控制電路的上視示意圖。 圖2是圖1A的線a-a’的剖面示意圖。 圖3是圖1B的感光裝置的控制電路的電路示意圖。 圖4A是依照本發明的一實施例的一種感光裝置的上視示意圖。 圖4B是圖4A的感光裝置的控制電路的上視示意圖。 FIG. 1A is a schematic top view of a photosensitive device according to an embodiment of the present invention. FIG. 1B is a schematic top view of a control circuit of the photosensitive device shown in FIG. 1A . Fig. 2 is a schematic cross-sectional view of line a-a' in Fig. 1A. FIG. 3 is a schematic circuit diagram of a control circuit of the photosensitive device of FIG. 1B . FIG. 4A is a schematic top view of a photosensitive device according to an embodiment of the present invention. FIG. 4B is a schematic top view of the control circuit of the photosensitive device shown in FIG. 4A .
1:感光裝置 1: photosensitive device
10:第一感光單元 10: The first photosensitive unit
20:第二感光單元 20: Second photosensitive unit
a-a’:線 a-a': line
BE:第一電極 BE: first electrode
CL2,CL3:連接結構 CL2, CL3: connection structure
D1:第一方向 D1: the first direction
D2:第二方向 D2: Second direction
GV:凹槽 GV: Groove
HL1:第一傳輸線 HL1: first transmission line
HL2:第二傳輸線 HL2: second transmission line
HL3:第三傳輸線 HL3: third transmission line
L1,L2:長度 L1, L2: Length
LD:感光元件 LD: photosensitive element
LD1,LD1’:左側 LD1, LD1': left side
LD2,LD2’:右側 LD2, LD2': right side
LD’:虛線 LD': dotted line
M3:第三導電圖案層 M3: The third conductive pattern layer
M4:第四導電圖案層 M4: The fourth conductive pattern layer
PL1h:第一導電孔 PL1h: the first conductive hole
PL2h:第二導電孔 PL2h: Second conductive hole
T1:第一主動元件 T1: The first active component
T2:第二主動元件 T2: The second active component
T3:第三主動元件 T3: The third active component
T4:第四主動元件 T4: The fourth active element
T5:第五主動元件 T5: fifth active element
TE:第二電極 TE: second electrode
VL1:第一訊號線 VL1: the first signal line
VL2:第二訊號線 VL2: The second signal line
VL3:第三訊號線 VL3: The third signal line
VL4:第四訊號線 VL4: The fourth signal line
VL5:第五訊號線 VL5: fifth signal line
VL6:第六訊號線 VL6: the sixth signal line
X1,X2:距離 X1, X2: distance
Claims (11)
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