TW202322285A - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure includes a substrate, a bit line structure, a first conductive pillar, an interface layer, a second conductive pillar, and an intermediate structure. The substrate has an active area and an isolation structure. The bit line structure is disposed on the active area. The first conductive pillar is disposed on the active area. The interface layer is disposed on the top surface of the first conductive pillar. The second conductive pillar is disposed on the interface layer. The intermediate structure is disposed between the first conductive pillar and the bit line structure.

Description

Semiconductor structures and methods of forming them

The present invention relates to a semiconductor structure and its forming method, in particular to a semiconductor structure which can be used as a memory device after processing and its forming method.

Dynamic Random Access Memory (DRAM), which is a volatile memory, has the advantages of high storage unit density, fast access speed and low cost, so it is widely developed.

However, with the trend of miniaturization of semiconductor devices, the size of memory devices continues to shrink, which increases the capacitive coupling between adjacent elements or parts of the interconnection structure, causing problems of leakage current and/or short circuit. adversely affect the performance of the device.

Therefore, existing semiconductor structures and methods of forming them have not fully met the requirements in all aspects. Therefore, there are still some problems to be overcome with respect to semiconductor structures that can be further processed as memory devices and methods of forming them.

In view of the above problems, the present invention reduces the cost of the dielectric plug and the bit line structure by arranging the first conductive pillar, the interface layer, the second conductive pillar and the intermediary structure together as a dielectric plug. The risk of short circuit between them, thereby improving the electrical characteristics of the semiconductor structure. For example, by adjusting the relative positions of the first conductive pillar, the interface layer, the second conductive pillar and the intermediary structure, the contact area with each other and/or the type of material, the relationship between the first conductive pillar and the second conductive pillar can be improved. Contact area. For example, as the contact area is increased to change the current path flowing through the dielectric plug, the overall resistance of the dielectric plug is reduced. Accordingly, the parasitic capacitance between the bit line structure and the dielectric plug is effectively reduced, thereby reducing the short circuit risk between the dielectric plug and the bit line structure.

According to some embodiments, a semiconductor structure is provided. The aforementioned semiconductor structure includes: the semiconductor structure includes a substrate, a bit line structure, a first conductive pillar, an interface layer, a second conductive pillar and an intermediate structure. The substrate has an active area and an isolation structure. The bit line structure is disposed on the active area. The first conductive column is disposed on the active area. The interface layer is disposed on the top surface of the first conductive pillar. The second conductive column is disposed on the interface layer. The intermediate structure is disposed between the first conductive column and the bit line structure.

According to some embodiments, a method of forming a semiconductor structure is provided. The method for forming the aforementioned semiconductor structure includes: forming an active region in the substrate. A plurality of bit line structures are formed on the active area. There are openings between adjacent bit line structures. A dielectric structure is formed in the opening. The active area is etched to form a recess in the opening. A first conductive pillar is formed on the concave portion. An interfacial layer is formed on the top surface of the first conductive pillar. A second conductive pillar is formed on the interface layer.

1, the semiconductor structure includes: a substrate 100, an isolation structure 110, an active area (active area) AA, a bit line (bit line) BL, a word line (word line) WL and a storage node contact (storage node contact ) CC. For ease of description, FIG. 1 simply shows the aforementioned components, but the semiconductor structure of the present disclosure may further include other components. Furthermore, the shape of the aforementioned components is not limited to the shape shown in FIG. 1 , and the size can be adjusted according to the requirements of the manufacturing process or application.

In some embodiments, the first direction D1 and the second direction D2 are different from each other, for example, the first direction D1 and the second direction D2 are perpendicular to each other, but the disclosure is not limited thereto. For example, the first direction D1 and the second direction D2 may intersect at an angle.

There may be multiple bit lines BL and they may be disposed on the substrate 100 . Each bit line BL may extend along the first direction D1. Adjacent bit lines BL are arranged at intervals in a second direction D2 different from the first direction D1. Adjacent bit lines BL may be separated by the same distance.

The word lines WL can be plural and can be disposed on the substrate 100 . Each word line WL may extend along the second direction D2. Adjacent word lines WL are arranged at intervals along the first direction D1. Adjacent word lines WL may be spaced apart by the same distance. In some embodiments, the word lines WL may be buried word lines. For example, the gate structure of the word line WL may be lower than the top surface of the substrate 100 . In other embodiments, the gate structure of the word line WL may not be lower than the top surface of the substrate 100 .

The isolation structure 110 may be formed in the substrate 100, so that the range of the active area AA is defined by the isolation structure 110, and two adjacent active areas AA are electrically separated from each other. The active area AA can be plural and can be formed in the substrate 100 . Each active area AA extends along a direction having an included angle with the first direction D1. The shape of the active area AA is just an example, and the present disclosure is not limited thereto.

As shown in FIG. 1, each active area AA spans two word lines WL and one bit line BL. Each active area AA and the corresponding bit line BL have an overlapping area and non-overlapping areas on both sides of the overlapping area. In each active area AA, there is a bit line contact BC in the overlapping area and a storage node contact CC in the non-overlapping area. In some embodiments, two storage node contacts CC corresponding to an active area AA are respectively disposed outside two word lines WL passing through the active area AA. The storage node contact CC may be in contact with a capacitor, and thus may also be called a capacitor contact. In some embodiments, the storage node contacts CC are located on the substrate 100, and each storage node contact CC is located between two adjacent bit lines BL and between two adjacent word lines WL. . In some embodiments, when each bit line BL crosses the corresponding word line WL, the bit line contact BC can be used to electrically connect the corresponding region between the two word lines WL.

Figures 2 to 14 are schematic cross-sectional views taken along line XX' as shown in Figure 1 .

Referring to FIG. 2, in some embodiments, a substrate 100 is provided. The substrate 100 may be a wafer such as a silicon wafer, a semiconductor-on-insulation (SOI) substrate or a bulk semiconductor substrate. In some embodiments, the substrate 100 may be a multilayer substrate or a gradient substrate. In some embodiments, the substrate 100 can be an elemental semiconductor, including silicon and germanium; a compound semiconductor, including: silicon carbide, gallium arsenide, gallium phosphide, phosphorus Indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or any combination thereof , but the present disclosure is not limited thereto. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate.

As shown in FIG. 2 , the active area AA and the isolation structure 110 are formed in the substrate 100 . For example, the active area AA is formed in the upper portion of the substrate 100 first, and then the isolation structure 110 is formed between adjacent active areas AA. In some embodiments, the isolation structure 110 may be formed first, and then the active area AA is formed in the substrate 100 . The isolation structure 110 can be an oxide such as silicon oxide. In some embodiments, the isolation structure 110 can be formed by an etching process and a deposition process.

The etching process may include dry etching, wet etching, or other suitable etching methods. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. In addition, the etching process can also be pure chemical etching, pure physical etching or a combination thereof. The deposition process can be chemical deposition, physical deposition or a combination thereof. The deposition process may include chemical vapor deposition (chemical vapor deposition, CVD), metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD), atomic layer deposition (Atomic Layer Deposition, ALD), a combination thereof, or similar processes , but not limited to this. The isolation structure 110 may be a shallow trench isolation (STI). In addition, required doped regions can be further formed according to the electrical requirements of the semiconductor structure.

As shown in FIG. 2, in some embodiments, the bit line structure BLS is formed on the active area AA. There may be plural bit line structures BLS. The bit line structure BLS may include a first conductive layer 220 , a second conductive layer 230 and a mask layer 240 . The first conductive layer 220 is disposed on the active area AA; the second conductive layer 230 is disposed on the first conductive layer 220 ; and the mask layer 240 is disposed on the second conductive layer 230 . The first conductive layer 220 and/or the second conductive layer 230 can be a single-layer or multi-layer structure. In some embodiments, the materials of the first conductive layer 220 and the second conductive layer 230 may be sequentially deposited on the substrate 100 first, and then the patterned mask layer 240 is formed on the second conductive layer 230 . Afterwards, an etching process is performed to pattern the materials of the first conductive layer 220 and the second conductive layer 230 to obtain the first conductive layer 220 and the second conductive layer 230 .

The first conductive layer 220 and/or the second conductive layer 230 may include a conductive material. The conductive material may include polycrystalline silicon, amorphous silicon, metals such as tungsten, gold, silver, copper, cobalt, or the like, metal nitrides, conductive metal oxides, other suitable materials, or the like. combination. For example, the first conductive layer 220 may include polysilicon, and the second conductive layer 230 may include tungsten. In some embodiments, mask layer 240 may be a hard mask layer. The material of the mask layer 240 may include oxide, nitride, oxynitride, carbide or combinations thereof. In some embodiments, the mask layer 240 may be a nitride such as silicon nitride.

As shown in FIG. 2 , in some embodiments, a bit line dielectric layer 210 is formed on the isolation structure 110 . In some embodiments, the bit line dielectric layer 210 is formed on the isolation structure 110 before the first conductive layer 220 is formed on the substrate 100 . It should be noted here that since FIG. 2 shows a schematic cross-sectional view taken along line XX' in FIG. 1, a bit line dielectric layer is formed on the isolation structure 110 between the two active regions AA in the middle. 210. The bit line dielectric layer 210 may include oxide, nitride, oxynitride, high-k materials, or combinations thereof. In some embodiments, the bit line dielectric layer 210 may include an oxide such as silicon oxide. In some embodiments, the bit line dielectric layer 210 may be an insulating layer. In some embodiments, the bit line dielectric layer 210 may be formed by a deposition process. In this embodiment, the bit line structures BLS above the leftmost and rightmost active regions AA in FIG. 2 can be electrically connected to the bit line contacts BC shown in FIG. 1, or the bit line The line structure BLS can be part of the bit line contact BC.

As shown in FIG. 2 , in some embodiments, a spacer structure 250 may be further formed on the side surface and the top surface of the bit line structure BLS. The spacer structure 250 can provide the BLS isolation characteristic of the bit line structure. The spacer structure 250 can be an oxide, a nitride, or a combination thereof. In some embodiments, the spacer structure 250 can be silicon oxide or silicon nitride.

The spacer structure 250 may be a single-layer structure or a multi-layer structure. For example, the spacer structure 250 may include a first spacer 251 , a second spacer 252 and a third spacer 253 . In some embodiments, the first spacer 251 may be disposed on a side surface of the bit line structure BLS. Specifically, the first spacer 251 contacts the isolation structure 110 , the first conductive layer 220 , the second conductive layer 230 and the mask layer 240 . In some embodiments, the first spacer 251 contacts the bit line dielectric layer 210 . The second spacer 252 may be disposed on a side surface of the first spacer 251, and the first spacer 251 is interposed between the second spacer 252 and the bit line structure BLS. The third spacer 253 may be disposed on the side surface of the second spacer 252 , and the second spacer 252 is interposed between the first spacer 251 and the third spacer 253 . In some embodiments, the third spacer 253 may be disposed on the second spacer 252 , the first spacer 251 and the mask layer 240 in a blanket manner.

The aforementioned spacer structure 250 can be formed by the aforementioned deposition process and etching process. In some embodiments, the first spacer 251 and the third spacer 253 may include silicon nitride, and the second spacer 252 may include silicon oxide, so the spacer structure 250 may be a nitride-oxide-nitride ( Nitride-oxide-nitride, NON) structure, but the present disclosure is not limited thereto.

In some embodiments, the liner 260 can be conformally formed on the active area AA, the isolation structure 110 , the spacer structure 250 and the bit line structure BLS. In some embodiments, liner 260 may be a nitride such as silicon nitride. In some embodiments, the liner 260 may be a single layer or a multi-layer structure, or the liner 260 may be omitted. The liner 260 may be formed by using a deposition process.

As shown in FIG. 2, there is an opening OP between adjacent bit line structures BLS. The opening OP can be formed on the lining layer 260 , and the opening OP can be formed corresponding to the shape of the lining layer 260 . Fig. 2 is a schematic cross-sectional view taken along line XX' as shown in Fig. 1, and it shows two openings OP. However, the number of openings OP is just an example, and the number of openings OP will vary with the schematic cross-sectional views taken along different line segments in FIG. 1 , so the present disclosure is not limited thereto. In some embodiments, the opening OP has a first height H1 and a first width W1.

Hereinafter, the dielectric plug formed in the opening OP and electrically connected to the capacitor will be described in detail.

Referring to FIG. 3, a dielectric material 270 is formed in the opening OP. The dielectric material 270 may be formed by a deposition process so that the dielectric material 270 fills the opening OP. In some embodiments, the dielectric material 270 completely fills the opening OP. The dielectric material 270 contacts the side surface and the bottom surface of the opening OP. The dielectric material 270 may include oxides, nitrides, oxynitrides, carbides, or combinations thereof. In some embodiments, the dielectric material 270 may be silicon oxide.

Referring to FIG. 4 , a photoresist layer PR is formed on the dielectric material 270 . The photoresist layer PR covers the liner layer 260 and the dielectric material 270 . In some embodiments, the photoresist layer PR covers a portion of the dielectric material 270 and exposes another portion of the dielectric material 270 . The width of the photoresist layer PR covering the dielectric material 270 is the second width W2. The second width W2 is smaller than the first width W1. In some embodiments, the photoresist layer PR covers 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90% or any of the aforementioned values of the total area of the top surface of the dielectric material 270. The combined range is used to adjust the area ratio of the dielectric material 270 and the top surface of the subsequently formed first conductive pillar. That is, the width of the subsequent interposer structure can be adjusted by the coverage area of the photoresist layer PR.

Referring to FIG. 5, following the above, an etching process is performed to pattern the dielectric material 270 by using the photoresist layer PR as an etching mask, thereby forming a patterned dielectric material 271 and exposing the side surface S1 of the opening OP. and the bottom surface S2. The dielectric material 271 covers one of the opposite side surfaces of the opening OP, and exposes the other one of the opposite side surfaces S1. The dielectric material 271 exposes a portion of the bottom surface S2 of the opening OP. The width of the patterned dielectric material 271 is substantially the same as the second width W2. The width of the dielectric material 271 can be adjusted according to electrical requirements. The dielectric material 271 may cover the top surface of the isolation structure 110 . In some embodiments, the dielectric material 271 may further cover the top surface of the active area AA. In some embodiments, a removal process such as an ashing process and/or a wet strip can be performed to remove the photoresist layer PR.

Referring to FIG. 6, following the above, the first etching process is performed to reduce the height of the dielectric material 271, so that the top surface of the dielectric material 271 is lower than the top surface of the bit line structure BLS, and the dielectric structure 272 is formed in the opening. In the OP. In some embodiments, the dielectric structure 272 has a second height H2. The second height H2 is smaller than the first height H1. In some embodiments, the height of the dielectric structure 272 is substantially the same as the height of the second conductive layer 230 . Since larger parasitic capacitance is easily generated adjacent to the second conductive layer 230 , when the height of the dielectric structure 272 is substantially the same as that of the second conductive layer 230 , the parasitic capacitance can be reduced by the dielectric structure 272 . In some embodiments, the second height H2 of the dielectric structure 272 can be adjusted according to electrical requirements. In some embodiments, the first etching process is an etch-back process. The etch-back depth can be controlled by etch-back process parameters, thereby controlling the height of the dielectric structure 272 .

As shown in FIG. 6 , a second etching process is performed on the active area AA to form a recess 273 in the opening OP. Specifically, a second etching process is performed on the active region AA and part of the liner 260 to remove part of the liner 260 and a part of the active region AA to form a recess 273 with a depth D. Referring to FIG. In some embodiments, the recess 273 is interposed between adjacent isolation structures 110 . After performing the second etching process, the active area AA is exposed. In some embodiments, the bottom surface of the recess 273 is lower than the top surface of the active area AA. In some other embodiments, the second etching process is performed until the active area AA is exposed and then stopped, in other words, only the active area AA is exposed without removing a part of the active area AA.

It should be noted that performing the second etching process to remove a part of the active area AA can increase the contact area between the subsequently formed dielectric plug and the active area AA. Specifically, the contact area between the dielectric plug and the active area AA may further include contacting a portion of the side surface of the active area AA. For example, the side surface of the recess 273 in the active area AA can also be in contact with a subsequently formed dielectric plug. Therefore, the current path flowing through the active area AA and the dielectric plug can be adjusted by increasing the contact area between the dielectric plug and the active area AA, thereby reducing the distance between the dielectric plug and the bit line structure. Risk of short circuit.

Furthermore, in some embodiments, the first etching process for reducing the height of the dielectric material 271 and the second etching process for forming the recess 273 may be performed in the same process. For example, while performing the first etching process to reduce the height of the dielectric material 271, the lining can be simultaneously etched by controlling the etching selectivity and etching parameters of the dielectric material 271 and the lining layer 260 and the material of the active region AA. layer 260 and the active area AA to remove the liner layer 260 exposed through the dielectric structure 272 and to recess the active area AA. Therefore, the manufacturing cost can be reduced. In some embodiments, the first etching process for reducing the height of the dielectric material 271 and the second etching process for forming the recess 273 may be performed sequentially in different processes.

Referring to FIG. 7 , the first conductive pillar 300 is formed on the concave portion 273 . In some embodiments, the material of the first conductive pillar 300 is blanket formed in the opening OP, and then the material of the first conductive pillar 300 is removed by an etch-back process, so that the top surface of the first conductive pillar 300 flush with the top surface of the dielectric structure 272 . The first conductive pillar 300 may include a conductive material. The conductive material may include polycrystalline silicon, amorphous silicon, metals such as tungsten, gold, silver, copper, cobalt, or the like, metal nitrides, conductive metal oxides, other suitable materials, or the like. combination. In some embodiments, the first conductive pillar 300 may include polysilicon.

The first conductive pillar 300 is disposed on the active area AA. In some embodiments, the first conductive pillar 300 covers a portion of the exposed side surface S1 of the opening OP. For example, the first conductive pillar 300 covers the lower portion of the side surface S1 of the opening OP and exposes the upper portion of the side surface S1 of the opening OP. In some embodiments, the first conductive pillar 300 completely covers the bottom surface S2 of the exposed opening OP. In some embodiments, the first conductive pillar 300 contacts one of the opposite side surfaces S1 of the opening OP, the dielectric structure 272 contacts the other of the opposite side surfaces S1 of the opening OP, and the first conductive pillar 300 and the dielectric structure 272 contact the other of the opposite side surfaces S1 of the opening OP. The electrical structure 272 is in direct contact. In some embodiments, the first conductive pillar 300 is in contact with the liner 260 , the dielectric structure 272 , the isolation structure 110 and the active area AA. In some embodiments, the dielectric structure 272 is interposed between the first conductive pillar 300 and the bit line structure BLS. In some embodiments, the top surface of the first conductive pillar 300 is a flat surface, so the reliability of the first conductive pillar 300 can be improved. In some embodiments, the shape of the first conductive pillar 300 is not limited to a pillar shape.

Referring to FIG. 8, the dielectric structure 272 is removed by an etching process. In some embodiments, the first conductive pillar 300 can be used as an etching mask, and the dielectric structure 272 is removed by a wet etching process. The dielectric structure 272 is removed to expose the side surface and the bottom surface of the opening OP located between the first conductive pillar 300 and the bit line structure BLS.

Referring to FIG. 9 , an interface layer 400 is formed on the top surface of the first conductive pillar 300 . In some embodiments, interfacial layer 400 is formed after dielectric structure 272 is removed. In some embodiments, the interface layer 400 is conformally formed on the top surface and the side surface of the first conductive pillar 300 . In other words, the interface layer 400 may include the extension portion 410 . The extension portion 410 of the aforementioned interface layer 400 can be disposed on the side surface of the first conductive pillar 300 . In some embodiments, the extension portion 410 of the aforementioned interface layer 400 may be interposed between the first conductive pillar 300 and the bit line structure BLS. In other embodiments, the interface layer 400 may be formed on the top surface of the first conductive pillar 300 , and the interface layer 400 may at least cover a part of the side surface of the first conductive pillar 300 . In still other embodiments, the interface layer 400 may be formed on the top surface of the first conductive pillar 300 , and the interface layer 400 may completely expose the side surface of the first conductive pillar 300 . In the semiconductor structure of the present disclosure, factors that have a greater impact on resistance include the contact area between the first conductive pillar 300 and the active area AA, so in the case where the interface layer 400 is formed at least on the top surface of the first conductive pillar 300 In this way, the semiconductor structure of the present disclosure can be effectively operated. In some embodiments, the interface layer 400 may be in the shape of a cane, an inverted L, or other suitable shapes.

The interfacial layer 400 can serve as a buffer layer for improving compatibility, so as to improve the reliability of the dielectric plug of the subsequently formed semiconductor structure. In some embodiments, the interface layer 400 may include cobalt silicide. Since the interface layer 400 includes cobalt silicide, the interface layer 400 can improve the compatibility between the first conductive pillar 300 and the second conductive pillar subsequently formed on the interface layer 400 to improve the reliability of the overall dielectric plug.

Referring to FIG. 10 , a second conductive pillar 600 is formed on the interface layer 400 to obtain the semiconductor structure 1 of the present disclosure. In some embodiments, the material and method used to form the second conductive pillar 600 may be the same as or different from those used to form the first conductive pillar 300 . In some embodiments, the second conductive pillar 600 includes tungsten.

As shown in FIG. 10 , an interposer structure 500 may be formed under the second conductive pillar 600 . In some embodiments, the interposer structure 500 is disposed between the first conductive pillar 300 and the bit line structure BLS. In some embodiments, the top surface of interposer 500 may be flush with the top surface of interface layer 400 . In some embodiments, the material and method used to form the interposer 500 are the same as or different from those used to form the second conductive pillar 600 .

In some embodiments, the material of the interposer 500 is the same as that of the second conductive pillar 600 . In some embodiments, both the interposer structure 500 and the second conductive pillar 600 are made of tungsten. For example, a material such as tungsten is blanket deposited on the liner layer 260 and the interface layer 400 to simultaneously form the interposer 500 and the second conductive pillar 600 . Next, a planarization process is performed to make the top surface of the second conductive pillar 600 flush with the top surface of the liner layer 260 . In other words, the intermediary structure 500 and the second conductive pillar 600 can be integrally formed. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process, but the disclosure is not limited thereto. In some embodiments, after the dielectric structure 272 is removed, the interposer structure 500 and the second conductive pillar 600 are integrally formed in the opening OP as shown in FIG. 9 .

In some embodiments, when blanket depositing the material of the interposer 500 and the second conductive pillar 600, the second width W2 as shown in FIG. 5 and the second height as shown in FIG. 6 can be adjusted. H2, to change the aspect ratio of the trench between the liner 260 and the extension portion 410 of the interface layer 400 . Therefore, by adjusting the aspect ratio of the trenches, the deposition parameters and deposition profiles of the materials of the deposition intermediary structure 500 and the second conductive pillar 600 can be adjusted. In some embodiments, the material of the interposer 500 and the second conductive pillar 600 is blanket deposited such that the material of the interposer 500 and the second conductive pillar 600 completely fills the extended portion between the liner 260 and the interface layer 400 410 between the grooves. In other words, the interposer 500 is surrounded by the liner 260 , the extension portion 410 of the interface layer 400 and the second conductive pillar 600 . In some embodiments, when taking the central axis of the second conductive pillar 600 as the axis of symmetry, the present disclosure provides a dielectric plug with an asymmetric structure.

In this embodiment, the extension portion 410 of the interface layer 400 is interposed between the interposer structure 500 and the first conductive pillar 300 . In some embodiments, the interposer structure 500 is interposed between the extension portion 410 and the bit line structure BLS. The interposer 500 is interposed between the extension portion 410 and the liner 260 . The bottom surface of the first conductive pillar 300 is lower than the bottom surface of the interposer 500 . Therefore, the contact area between the first conductive pillar 300 and the interposer 500 and the second conductive pillar 600 can be increased. Accordingly, by providing the interposer structure 500 to adjust the current path flowing through the integral dielectric plug, the risk of short circuit between the dielectric plug and the bit line structure BLS is reduced. For example, the short circuit risk between the first conductive pillar 300 and the first conductive layer 220 and/or the second conductive layer 230 in the bit line structure BLS is reduced.

In other embodiments, the material of the interposer structure 500 is different from that of the second conductive pillar 600 . In this embodiment, the interposer structure 500 may be formed first, and then the second conductive pillar 600 is formed.

As shown in Fig. 10, it is a schematic cross-sectional view taken along the line segment XX' in Fig. 1 . In this cross-sectional view, five isolation structures 110 and four active regions AA are straddled along the second direction D2 as shown in FIG. between. In this case, the bit line dielectric layer 210 and the bit line structure BLS are provided on the isolation structure 110 in the middle, and the integration of the bit line dielectric layer 210 and the bit line structure BLS can be regarded as a dummy ( dummy) bit line structure. In other words, FIG. 10 shows a schematic cross-sectional view of a dummy bit line structure between two adjacent bit line structures BLS. In FIG. 10, an interposer structure 500 is disposed adjacent to the bit line structure BLS and away from the dummy bit line structure. In some embodiments, the interposer structure 500 and the first conductive pillar 300 are interposed between the bit line structure BLS and the dummy bit line structure. Wherein, compared with the first conductive pillar 300 , the interposer structure 500 is closer to the bit line structure BLS. Taking the central axis of the dummy bit line structure as the axis of symmetry, the first conductive pillar 300 , the interface layer 400 , the intermediary structure 500 and the second conductive pillar 600 can be arranged symmetrically. In other words, when the central axis of the dummy bit line structure is taken as the axis of symmetry, the present disclosure provides a symmetric structure.

Referring to FIG. 11 , it shows a schematic cross-sectional view of the semiconductor structure 2 of the present disclosure. For ease of description, similar and repeated descriptions are omitted. FIG. 11 is a schematic cross-sectional view of a further process following the semiconductor structure shown in FIG. 9 . Following FIG. 9 , as shown in FIG. 11 , a second conductive pillar 600 is formed on the interface layer 400 to obtain the semiconductor structure 2 of the present disclosure. In this embodiment, by adjusting the aspect ratio of the trench between the liner 260 and the extension 410 of the interface layer 400 , the deposition profile of the blanket deposited interposer 500 material is varied.

In this embodiment, an intervening member 510 is formed under the second conductive pillar 600 , and an air gap AG is formed under the intervening member 510 . In some embodiments, the interposer 500 material is deposited in opening OP as shown in FIG. 9 such that the bottom surface of the interposer 500 material is between the top and bottom surfaces of the interface layer 400 . For example, the bottom surface of the material of the interposer 500 may be between the top surface of the interface layer 400 and the bottom surface of the extension portion 410 .

In some embodiments, the material of the intermediate component 510 and the material of the second conductive pillar 600 may be the same. In other words, the intermediary component 510 and the second conductive pillar 600 are integrally formed. For example, the material of the second conductive pillar 600 is blanket-deposited to simultaneously form the second conductive pillar 600 and the interposer structure 500 including the interposer member 510 and the air gap AG. In other words, when the material of the second conductive pillar 600 is blanket-deposited, the material of the second conductive pillar 600 may partially fill the trench between the liner layer 260 and the extension portion 410 of the interface layer 400 , to form the air gap AG. In some embodiments, both the intervening member 510 and the second conductive pillar 600 are made of tungsten.

In some embodiments, the interposer 510 and the air gap AG can be regarded as the interposer structure 500 as a whole. In some embodiments, the areas of the interposer structure 500 occupied by the interposer 510 and the air gap AG can be adjusted according to the aspect ratio of the trench and the parameters of the deposition process. In some embodiments, the area of the interposer structure 500 occupied by the interposer member 510 may be less than, substantially equal to, or greater than the area occupied by the air gap AG of the interposer structure 500 . In some embodiments, the top surface of the air gap AG may be lower than or flush with the top surface of the first conductive pillar 300 or the interface layer 400 . In some embodiments, the interposer 510 contacts the first conductive pillar 300 , the interface layer 400 and the second conductive pillar 600 .

In some embodiments, the air gap AG may include inert gas, air, or be in a vacuum state. In this embodiment, since the interposer 500 may include the air gap AG disposed under the interposer 510, the parasitic capacitance can be effectively reduced, thereby reducing the short circuit risk between the dielectric plug and the bit line structure BLS. .

Referring to FIG. 12 , it shows a schematic cross-sectional view of the semiconductor structure 3 of the present disclosure. For ease of description, similar and repeated descriptions are omitted. FIG. 12 is a schematic cross-sectional view of a further process following the semiconductor structure shown in FIG. 9 . Following FIG. 9 , as shown in FIG. 12 , a second conductive pillar 600 is formed on the interface layer 400 to obtain the semiconductor structure 3 of the present disclosure. As shown in FIG. 12 , the bottom surface of the second conductive pillar 600 is flush with the top surface of the interface layer 400 , and an air gap AG is formed under the second conductive pillar 600 . In some embodiments, the air gap AG directly contacts the second conductive pillar 600 . In this embodiment, the air gap AG can be regarded as an interposer. Therefore, in the case that the interposer structure is substantially the air gap AG, the parasitic capacitance between the first conductive pillar 300 and the bit line structure BLS can be effectively reduced, thereby reducing the risk of short circuit.

Referring to FIG. 13 , it shows a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure. For ease of description, similar and repeated descriptions are omitted. FIG. 13 is a schematic cross-sectional view of a further process following the semiconductor structure shown in FIG. 7 . Following FIG. 7 , as shown in FIG. 13 , an interface layer 400 is formed on the top surface of the first conductive pillar 300 . In some embodiments, since the interfacial layer 400 may include cobalt silicide, the first conductive pillar 300 may include polysilicon, and the dielectric structure 272 may include silicon oxide. Due to the compatibility of materials, the interface layer 400 may only be formed on the top surface of the first conductive pillar 300 . In this embodiment, the dielectric structure 272 is reserved between the first conductive pillar 300 and the bit line structure BLS, so as to omit the process steps of removing the dielectric structure 272 and/or further forming the interposer structure, thereby reducing the process cost. In some embodiments, since the interface layer 400 can be formed by polysilicon in the first conductive pillar 300 , the top surface of the interface layer 400 is flush with the top surface of the dielectric structure 272 .

As shown in FIG. 14 , a second conductive pillar 600 is formed on the structure shown in FIG. 13 to obtain the semiconductor structure 4 of the present disclosure. In some embodiments, the second conductive pillar 600 contacts the interface layer 400 and the dielectric structure 272 . In some embodiments, the bottom surface of the second conductive pillar 600 is flush with the top surfaces of the interface layer 400 and the dielectric structure 272 . In this embodiment, the dielectric structure 272 can be regarded as an interposer. Since the dielectric structure 272 can be used as an etching mask in the aforementioned process and as an intermediary structure disposed between the first conductive pillar 300 and the bit line structure BLS, the process steps can be reduced and the process cost can be reduced. In addition, since the dielectric structure 272 may include a dielectric material such as silicon oxide, the parasitic capacitance can be reduced to reduce the risk of a short circuit between the first conductive pillar 300 and the bit line structure BLS.

In some embodiments, further processes may be performed on the semiconductor structures 1 , 2 , 3 and/or 4 of the present disclosure to form memory devices. For example, in some embodiments, a doping process may be performed according to electrical requirements. In some embodiments, the dopant may be a P-type dopant such as boron or an N-type dopant such as phosphorus.

To sum up, the semiconductor structure of the present disclosure includes the first conductive pillar, the interface layer, the second conductive pillar and the intermediate structure as the dielectric plug used to connect the capacitor in the memory device.

In the present disclosure, an intermediary structure made of the same material as that of the second conductive post is disposed between the first conductive post and the bit line structure, and the intermediary structure is regarded as an extension of the second conductive post to increase the second conductive post and the second conductive post. The contact area of a conductive pillar is used to reduce the short circuit risk between the first conductive pillar and the bit line structure. The present disclosure reduces the parasitic capacitance of the dielectric plug by disposing an intermediary structure including an air gap or an overall air gap between the first conductive pillar and the bit line structure, thereby reducing the size of the first conductive pillar and the bit line structure. risk of short circuit between. The present disclosure reduces the parasitic capacitance of the dielectric plug and/or reduces the number of process steps to reduce the size of the first conductive pillar by disposing an interposer structure including a dielectric material such as silicon oxide between the first conductive pillar and the bit line structure. Short circuit risk between the bit line structure and/or reduce the process cost of the forming method.

In addition, the present disclosure increases the contact area of the first conductive pillar with the second conductive pillar and/or the intermediary structure by disposing the first conductive pillar with a bottom surface lower than the second conductive pillar and the intermediate structure. Therefore, the risk of short circuit can be reduced by adjusting the current flowing through the first conductive pillar, the second conductive pillar and the intermediate structure. Furthermore, the present disclosure enhances the compatibility of the first conductive pillar and the second conductive pillar by providing an inverted L-shaped interface layer, so as to improve the reliability of the first conductive pillar and the second conductive pillar. At the same time, the present disclosure provides a semiconductor structure having a dummy bit line structure between adjacent bit line structures, so when viewed in the cross-sectional direction, a semiconductor structure having a structure symmetrical to the dummy bit line structure can be obtained. Accordingly, by disposing the interposer away from the dummy bit line structure and adjacent to the dummy bit line structure, the risk of short circuit is reduced.

The foregoing summary summarizes components of several embodiments of the present disclosure so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for changing, substituting, substituting and/or modifying other processes and structures, so as to achieve the same purpose as the embodiments described herein and /or achieve the same advantages. It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes herein without departing from the spirit and scope of the present disclosure. , replacement and change.

1, 2, 3, 4: Semiconductor structure 100: Substrate 110: Isolation structure 210: bit line dielectric layer 220: the first conductive layer 230: second conductive layer 240: mask layer 250: spacer structure 251: first spacer 252: second spacer 253: The third spacer 260: lining 270, 271: Dielectric materials 272:Dielectric structure 273: Concave 300: the first conductive column 400: interface layer 410: extension 500: intermediary structure 510: Intermediary components 600: the second conductive column AA: active area AG: air gap BC: bit line contact BL: bit line BLS: Bit Line Structure CC: storage node contacts D: Depth D1: the first direction D2: Second direction H1: first height H2: second height OP: opening PR: photoresist layer S1: side surface S2: bottom surface W1: first width W2: second width WL: character line

FIG. 1 is a schematic diagram illustrating a circuit layout of a semiconductor structure according to some embodiments of the present invention. FIG. 2 to FIG. 14 are schematic cross-sectional views illustrating various stages of forming a semiconductor structure according to some embodiments of the present invention.

1: Semiconductor structure

100: Substrate

110: Isolation structure

210: bit line dielectric layer

220: the first conductive layer

230: second conductive layer

240: mask layer

250: spacer structure

251: first spacer

252: second spacer

253: The third spacer

260: lining

300: the first conductive column

400: interface layer

410: extension

500: intermediary structure

600: the second conductive column

AA: active area

BLS: Bit Line Structure

Claims (11)

A semiconductor structure comprising: A substrate with an active area and an isolation structure; a bit line structure disposed on the active area; a first conductive column disposed on the active area; an interface layer disposed on the top surface of the first conductive pillar; a second conductive column disposed on the interface layer; and An intermediate structure is arranged between the first conductive column and the bit line structure. The semiconductor structure of claim 1, wherein the bottom surface of the first conductive pillar is lower than the bottom surface of the interposer. The semiconductor structure as claimed in claim 1, wherein the interface layer has an extension portion disposed on a side surface of the first conductive pillar. The semiconductor structure as claimed in claim 1, wherein the intermediate structure further comprises: an intermediary component disposed under the second conductive pillar; and An air gap is arranged under the intermediary component. The semiconductor structure of claim 1, wherein the interposer is an air gap. A method of forming a semiconductor structure, comprising: forming an active region in a substrate; forming a plurality of bit line structures on the active area, and an opening is formed between adjacent bit line structures; forming a dielectric structure in the opening; etching the active area to form a recess in the opening; forming a first conductive column on the concave portion; forming an interfacial layer on the top surface of the first conductive pillar; and A second conductive column is formed on the interface layer. The forming method as described in claim item 6, further comprising: Before forming the interfacial layer, the dielectric structure is removed. The forming method as described in claim item 7, further comprising: After removing the dielectric structure, an intermediate structure is formed in the opening, so that the intermediate structure contacts the interface layer and the second conductive pillar. The forming method as claimed in item 8, wherein forming the intermediary structure in the opening further comprises: The interposer material is deposited in the opening such that the bottom surface of the interposer material is between the top and bottom surfaces of the interfacial layer. The forming method according to claim 6, wherein forming the dielectric structure in the opening further comprises: filling a dielectric material in the opening; patterning the dielectric material to expose side surfaces and bottom surfaces of the opening; The dielectric material is etched such that the top surface of the dielectric material is lower than the top surface of the plurality of bit line structures to form the dielectric structure. The forming method according to claim 10, wherein the step of etching the dielectric material and the step of etching the active region are performed in the same process.

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