TW202318692A - Integrated chip structure and method of forming the same - Google Patents

Abstract

The present disclosure relates an integrated chip structure. The integrated chip structure includes a bottom electrode disposed within a dielectric structure over a substrate. A top electrode is disposed within the dielectric structure over the bottom electrode. A switching layer and an ion source layer are between the bottom electrode and the top electrode. A barrier structure is between the bottom electrode and the top electrode. The barrier structure includes a metal nitride configured to mitigate a thermal diffusion of metal during a high temperature fabrication process.

Description

Diffusion barriers for mitigation of direct short-circuit leakage in inductively bridged random access memories

Embodiments of the present invention relate to a diffusion barrier for mitigating direct short circuit leakage in an inductively bridged random access memory.

Many modern electronic devices contain memory configured to store data digitally. The memory in the electronic device can be a volatile memory or a non-volatile memory. Volatile memory stores data when it is powered on, while non-volatile memory stores data when it is powered off. Inductively bridged random access memory (CBRAM) is a promising candidate for a next-generation non-volatile memory technology because it can operate at high speeds with low power consumption and can be fabricated by integrating with existing CMOS Manufactured using a process compatible process.

An embodiment of the present invention relates to an integrated chip structure, comprising: a bottom electrode disposed in a dielectric structure above a substrate; a top electrode disposed in the dielectric structure above the bottom electrode; a a conversion layer, located between the bottom electrode and the top electrode; an ion source layer, disposed between the bottom electrode and the top electrode; and a barrier structure, disposed between the bottom electrode and the top electrode, wherein the The barrier rib structure includes a metal nitride configured to mitigate thermal diffusion of the metal during a high temperature manufacturing process.

An embodiment of the present invention relates to an integrated chip structure, comprising: an inductive bridging random access memory (CBRAM) device disposed on a substrate, wherein the inductive bridging random access memory (CBRAM) device comprises: a The conversion layer is arranged between a first electrode and a second electrode; an ion source layer is arranged between the conversion layer and the second electrode; and a barrier structure is arranged between the conversion layer and the ion source layer wherein the barrier layer is configured to mitigate thermal diffusion of the metal between the conversion layer and the ion source layer.

An embodiment of the present invention relates to a method of forming an integrated wafer structure, comprising: forming a lower interconnect in a lower interlayer dielectric (ILD) structure above a substrate; forming an inductive bridge random access memory (CBRAM) stack on the lower interlayer dielectric structure and the lower interconnect; pattern the inductive bridging random access memory stack according to a mask to define an inductive bridging random access memory device, the inductive bridging random access memory device The bridging random access memory device comprises a conversion layer and an ion source layer between a first electrode and a second electrode, wherein a barrier structure is also disposed between the first electrode and the second electrode; and forming an upper interconnection in an upper interlayer dielectric structure above the inductive bridge random access memory device, the upper interconnection being coupled to the second electrode.

This application claims priority to U.S. Patent Application Serial No. 63/273,380, filed October 29, 2021, and U.S. Patent Application Serial No. 63/300,333, filed January 18, 2022, the disclosures of which are hereby incorporated in their entirety by Incorporated by reference.

This disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description a first component is formed over or on a second component may include embodiments in which the first component and the second component are formed in direct connection, and may also include embodiments in which additional components may be formed on Between the first component and the second component, the embodiment that the first component and the second component may not be directly connected. In addition, the present disclosure may repeat element symbols and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatially relative terms such as "under", "under", "below", "above", "on" and the like may be used in the present disclosure to describe an element or The relationship of a component to another element(s) or component, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly.

An inductively bridged random access memory (CBRAM) device typically includes an ion source layer (ISL) and a switching layer (SL) disposed between a first electrode and a second electrode. CBRAM devices operate by selectively forming and dissolving conductive filaments of metallization ions within a switching layer to switch between resistive states. When conductive filaments are present in the switching layer, the CBRAM device has a first resistance that corresponds to a first data state (eg, logical "1"). When the conductive filaments are not present in the switching layer, the CBRAM device has a second resistance that corresponds to a second data state (eg, logic "0").

For example, during a set operation, a first bias voltage applied to the first electrode and/or the second electrode will cause metal ions to drift from the ion source layer to the conversion layer to form conductive filaments extending through the conversion layer And endow the CBRAM device with a first resistance (eg, a low resistance state). During a reset operation, one polarity of the bias voltage changes and metal ions are driven from the switching layer back into the ion source layer, thereby dissolving the conductive filaments and changing the CBRAM device from a first resistance to a second resistance (e.g., high resistance state).

During fabrication, a CBRAM device may be exposed to high temperature processes (eg, bonding processes, soldering processes, or the like). It should be understood that during such high temperature processes, metals (eg, metal ions and/or metal atoms) in the ion source layer may thermally diffuse into the conversion layer. Thermal diffusion of metal into the switching layer can result in the presence of unwanted metal within the switching layer without applying a bias voltage across the CBRAM device. This unwanted metal can cause leakage between the top and bottom electrodes and/or even disable the CBRAM device (e.g. the unwanted metal can form an unwanted conductive bridge within the switching layer, switching between resistive states is impossible).

The present disclosure relates to an integrated wafer structure including a CBRAM device having a barrier structure configured to prevent thermal diffusion of metal into a conversion layer during a high temperature manufacturing process (the barrier structure prevents thermal diffusion from back end Short-circuit current problems caused by ion migration in the thermal process of the process (BEOL). In some embodiments, the integrated chip structure may include a bottom electrode and a top electrode disposed within a dielectric structure above a substrate. A conversion layer and an ion source layer are located between the bottom electrode and the top electrode. A barrier structure is disposed between the conversion layer and the ion source layer. The barrier structure is configured to mitigate thermal diffusion of metal (eg, metal ions) between the ion source layer and the conversion layer during high temperature processing that can occur during fabrication of the integrated wafer structure. The barrier rib structure can prevent unwanted metal in the conversion layer and improve the performance and/or yield of the CBRAM device by mitigating the thermal diffusion of the metal during the high temperature manufacturing process, for example, according to the wafer acceptance test (WAT), the barrier rib structure can Prevent and/or reduce leakage current between the top and bottom electrodes.

1 illustrates a cross-sectional view of some embodiments of an integrated wafer structure 100 comprising an inductively bridged random access memory (CBRAM) device having A barrier structure configured to reduce metal diffusion caused by high temperature manufacturing processes.

The integrated chip structure 100 includes an inductively bridged random access memory (CBRAM) device 108 disposed within a dielectric structure 104 above a substrate 102 . The dielectric structure 104 includes a plurality of stacked interlayer dielectric (ILD) layers. In some embodiments, the plurality of stacked ILD layers may include a lower ILD structure 104L disposed between the CBRAM device 108 and the substrate 102 and an upper ILD structure 104U surrounding the CBRAM device 108 . In some embodiments, the lower ILD structure 104L includes one or more lower ILD layers surrounding one or more lower interconnects 106 disposed below the CBRAM device 108 .

CBRAM device 108 includes a conversion layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118 . During operation, a bias voltage will cause metals (eg, metal ions such as silver ions, copper ions, aluminum ions, etc.) to move between the ion source layer 116 and the conversion layer 112 to selectively form and/or dissolve A conductive filament (e.g., a conductive bridge) in switching layer 112, for example, when a first bias voltage is applied across CBRAM device 108, metal ions will move from ion source layer 116 to switching layer 112 to A conductive filament is formed in switching layer 112 and imparts to CBRAM device 108 a first resistance (eg, a low resistance state corresponding to a first data state). Alternatively, when a second bias voltage is applied across the CBRAM device 108, metal ions will migrate from the conversion layer 112 back to the ion source layer 116 and impart a second resistance to the CBRAM device 108 (e.g., corresponding to a second data state one of the high resistance states).

The CBRAM device 108 also includes a barrier rib structure 114 disposed between the bottom electrode 110 and the top electrode 118 . The barrier structure 114 is configured to mitigate thermal diffusion of metals (eg, metal ions). In some embodiments, the barrier structure 114 can be disposed between the conversion layer 112 and the ion source layer 116. In such an embodiment, the barrier structure 114 can be configured for use in manufacturing an integrated wafer structure (such as an integrated wafer structure). Bulk wafer) during a high temperature process (such as a manufacturing process performed at a temperature greater than or equal to about 300°C, about 400°C, about 500°C, or other similar temperatures) to reduce the transfer of metal from the ion source layer 116 to the conversion layer 112 thermal diffusion. By mitigating the thermal diffusion of metal from the ion source layer 116 to the switching layer 112 during the high temperature process, the formation of unwanted metal (eg, an unwanted conductive filament) in the switching layer 112 can be avoided, thereby improving the performance of the CBRAM device 108 and/or yield.

2A illustrates a cross-sectional view of some additional embodiments of an integrated wafer 200 that includes a CBRAM device having a barrier structure configured to reduce metal diffusion.

Bulk chip 200 includes a CBRAM device 108 disposed within a dielectric structure 104 over a substrate 102 . In some embodiments, the dielectric structure 104 includes a lower ILD structure 104L and an upper ILD structure 104U above the lower ILD structure 104L. The lower ILD structure 104L includes one or more lower ILD layers 104 a - 104 b laterally surrounding one or more lower interconnects 106 . In some embodiments, the lower ILD structure 104L may include a first lower ILD layer 104a and a second lower ILD layer 104b. In some embodiments, one or more lower interconnects 106 may include conductive contacts, interconnect conductive lines, and/or interconnect holes. The upper ILD structure 104U laterally surrounds the CBRAM device 108 . In some embodiments, the lower ILD structure 104L and/or the upper ILD structure 104U may include silicon dioxide, carbon-doped silicon oxide (SiCOH), phosphosilicate glass (PSG), boron-doped phosphosilicate glass ( One or more of BPSG), fluorosilicate glass (FSG), undoped silica glass (USG), or the like. In some embodiments, one or more lower interconnects 106 may include one or more of copper, aluminum, tungsten, ruthenium, or the like.

In some embodiments, one or more lower interconnects 106 are configured to couple the CBRAM device 108 to an access device 202 disposed within the substrate 102 . In some embodiments, the access device 202 may include a MOSFET device having a gate structure 202c disposed laterally between a source region 202a and a drain region 202b. In some embodiments, gate structure 202c may include a gate electrode separated from substrate 102 by a gate dielectric. In some such embodiments, source region 202a is coupled to connected to a source line SL and the gate structure 202c is coupled to a word line WL. In various embodiments, the MOSFET device may comprise a planar FET, fin field effect transistor (FinFET), gate all-around (GAA) device, or the like. In other embodiments, the access device 202 may include a HEMT (high-electron-mobility transistor, high electron mobility transistor), a BJT (bipolar junction transistor, bipolar junction transistor), a JFET (junction- gate field-effect transistor, junction gate field-effect transistor), or similar.

A lower insulating structure 204 is disposed over the lower ILD structure 104L. The lower insulating structure 204 includes sidewalls defining an opening extending through the lower insulating structure 204 . In some embodiments, the lower insulating structure 204 may include a first dielectric layer 204a and a second dielectric layer 204b above the first dielectric layer 204a. In some embodiments, the first dielectric layer 204a may comprise a different material than the second dielectric layer 204b. In various embodiments, the first dielectric layer 204a may include silicon oxide, silicon carbide, silicon dioxide, silicon nitride, or the like, while the second dielectric layer 204b may include silicon carbide, silicon nitride, silicon oxide, or the like.

A bottom electrode hole 206 is disposed between sidewalls of the lower insulating structure 204 . Bottom electrode hole 206 extends from one of lower interconnects 106 to a top of lower insulating structure 204 . In some embodiments, the bottom electrode hole 206 may include a barrier layer 206a and a conductive core 206b surrounded by the barrier layer 206a. In some embodiments, the barrier layer 206a may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some embodiments, the conductive core 206b may include one or more of aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or the like.

The CBRAM device 108 is disposed on the bottom electrode hole 206 . In some embodiments, the CBRAM device 108 includes a bottom electrode 110 separated from a top electrode 118 by a conversion layer 112 and an ion source layer 116 . In some embodiments, the bottom electrode 110 and the top electrode 118 may include metals such as tantalum, titanium, tantalum nitride, titanium nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like. In some embodiments, the bottom electrode 110 may have a first work function (eg, about 4.2 eV) and the top electrode 118 may have a second work function (eg, about 4.15 eV), which is smaller than the first work function. In some embodiments, the conversion layer 112 may include an oxide, a nitride, or the like. For example, in some embodiments, the conversion layer 112 may include a metal oxide, a chalcogenide, silicon nitride, Hafnium oxide, aluminum oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon oxide, or the like. In some embodiments, the ion source layer 116 may include copper, silver, aluminum, or the like.

The CBRAM device 108 further includes a barrier rib structure 114 disposed between the bottom electrode 110 and the top electrode 118 . In some embodiments, the barrier structure 114 has a lower surface and an upper surface, the lower surface contacts the conversion layer 112 , and the upper surface contacts the ion source layer 116 . In some embodiments, the barrier structure 114 includes a nitride and/or a metal nitride. For example, in various embodiments, the barrier structure 114 may include titanium nitride, amorphous titanium nitride, tantalum nitride, nitrogen Tungsten nitride, aluminum nitride, silicon nitride, tungsten nitride, ceramic aluminum nitride or the like. In some embodiments, barrier rib structure 114 may have a thickness 208 that is less than or equal to about 75 Å, less than or equal to about 50 Å, less than or equal to about 40 Å, or other similar values. If the thickness 208 of the barrier rib structure 114 is too large (eg, greater than about 75 Å, greater than about 50 Å, or other similar values), the barrier rib structure 114 can hinder the movement of metal ions during the operation of the CBRAM device 108, thereby affecting the operation of the CBRAM device 108. have negative impacts.

A first conductive filament 210 (eg, a conductive bridge) extends through the barrier structure 114 . The first conductive filament 210 contains a plurality of metal ions (such as gold ions, copper ions, aluminum ions, or the like) and continuously extends from a top surface of the barrier structure 114 to a bottom surface of the barrier structure 114 . In some embodiments, the first conductive filament 210 extends through the barrier rib structure 114 during storage of a first data state and a second data state, and a second conductive filament (not shown) A period of storage of either of the second data states exists in the conversion layer 112 .

An upper interconnect structure 120 is disposed within the upper ILD structure 104U and is coupled to the top electrode 118 . The upper interconnection structure 120 may include an interconnection hole 120a and/or an interconnection wire 120b. In some embodiments, the upper interconnect structure 120 may include aluminum, copper, tungsten, or the like. In some embodiments, the upper interconnection structure 120 is further coupled to a bit line BL.

FIG. 2B illustrates a schematic diagram of some embodiments of a memory circuit 212 including a disclosed CBRAM device.

The memory circuit 212 includes a memory array 214 including a plurality of CBRAM memory cells 216 _1,1 to 216 _n,m . A plurality of CBRAM memory cells 216 _1,1 to 216 _n,m are arranged in rows and/or rows in the memory array 214 . A plurality of CBRAM memory cells 216x _,1 to _216x,m within a row are operatively coupled to word lines _WLx (x=1-m). A plurality of CBRAM memory cells 216 _1,x to 216 _n,x within a column are operatively coupled to bit lines BL _x (x=1-n) and source lines SL _x (x=1-n ).

The word lines WL ₁ to WL _m , the bit lines BL ₁ to BL _n , and the source lines SL ₁ to SL _n are coupled to the control circuit 218 . In some embodiments, the control circuit 218 includes a word line decoder 220 coupled to the word lines WL ₁ through WL _m , a bit line decoder 222 coupled to the bit lines BL ₁ through BL _n , and a source line decoder 224 coupled to the source lines SL ₁ to SL _n . In some embodiments, the control circuit 218 further includes a sense amplifier 226 coupled to the bit lines BL ₁ to BL _n or the source lines SL ₁ to SL _n . In some embodiments, the control circuit 218 further includes a control unit 228 configured to transmit the address information _SADR to the word line decoder 220, the bit line decoder 222, and/or the source line decoder 224. , so that the control circuit 218 can selectively access one or more of the plurality of CBRAM memory cells 216 _1,1 to 216 _n,m .

For example, during operation, control circuit 218 is configured to provide address information S _ADR to word line decoder 220 , bit line decoder 222 , and source line decoder 224 . Based on the address information S _ADR , the word line decoder 220 is configured to selectively apply a bias voltage to one of the word lines WL ₁ to WL _m , and simultaneously, the bit line decoder 222 is configured to configured to selectively apply a bias voltage to one of the bit lines BL ₁ to BL _n and/or the source line decoder 224 is configured to selectively apply a bias voltage to the source line SL ₁ to one of SL _n . By applying bias voltages to selected ones of word lines WL ₁ through WL _m , bit lines BL ₁ through BL _n , and/or source lines SL ₁ through SL _n , memory circuit 212 can be operated to write Different data states to and/or read _{data states from the plurality of CBRAM memory cells 216 1,1 to} 216 _{n ,m} .

3A-3B illustrate cross-sectional views of some embodiments of a CBRAM device in operation, having a barrier structure configured to reduce metal diffusion.

FIG. 3A illustrates a cross-sectional view 300 of a CBRAM device 108 during a set operation. During a set operation, a set voltage _VS is applied across a bottom electrode 110 and a top electrode 118 of the CBRAM device 108 (eg, through a bottom electrode hole 206 and an upper interconnect structure 120). A first conductive filament 210 (eg, a first conductive bridge) exists in the barrier structure 114 disposed between a conversion layer 112 and an ion source layer 116 . The set voltage V _S causes the metal ions to travel from the ion source layer 116 to the conversion layer 112 , thereby forming the second conductive filament 302 (eg, a second conductive bridge) in the conversion layer 112 . The first conductive filament 210 and the second conductive filament 302 jointly extend between a top surface of the barrier structure 114 and a bottom surface of the conversion layer 112 . Because the first conductive filament 210 and the second conductive filament 302 jointly extend through the barrier structure 114 and the switching layer 112, there is a conductive path through the barrier structure 114 and the switching layer 112, thereby imparting a first resistance to the CBRAM device 108, It corresponds to a first data state (eg logic "1").

FIG. 3B illustrates a cross-sectional view 304 of CBRAM device 108 during a reset operation. During reset operations, a reset voltage _VR is applied across the bottom electrode 110 and the top electrode 118 . The reset voltage _VR causes the metal ions to travel from the conversion layer 112 to the ion source layer 116, thereby at least partially dissolving the second conductive filaments (302 of FIG. 3A ) in the conversion layer 112 without removing the first conductive filaments. Silk 210. Because at least a portion of the second conductive filament 302 is removed, there is no conductive path through the barrier structure 114 and the switching layer 112, thereby imparting a second resistance to the CBRAM device 108, which corresponds to a second data state (e.g., logic "0").

4A-4B illustrate some additional embodiments of an integrated wafer structure comprising a CBRAM device having a barrier structure configured to reduce metal diffusion.

FIG. 4A illustrates a cross-sectional view of an integrated chip 400 including a CBRAM device 108 disposed within a dielectric structure 104 above a substrate 102 . The CBRAM device 108 includes a conversion layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118 . A barrier structure 114 is located between the conversion layer 112 and the ion source layer 116 . Barrier structure 114 includes a metal nitride configured to mitigate thermal diffusion of metal (eg, metal ions) between conversion layer 112 and ion source layer 116 . In some embodiments, barrier rib structure 114 may comprise a ratio of nitrogen to metal that is less than 1, less than about 70%, between about 70% and about 40%, or other similar values, for example, barrier rib structure 114 may A ratio of atomic percent nitrogen to atomic percent aluminum is comprised between about 40% and about 70%.

In some embodiments, the barrier structure 114 includes a gradient nitrogen content (eg, doping concentration, atomic percent, or the like) that varies continuously over a height of the barrier structure 114, for example, FIG. 4B illustrates a graph 402, It shows the atomic percent of nitrogen (on the y-axis) within the barrier structure as a function of position (x-axis) within the CBRAM device. As shown in graph 402 (taken along line AA' of FIG. 4A ), barrier rib structure 114 has a first nitrogen content _N1 along a bottom surface of barrier rib structure 114 and has a - a second nitrogen content _N2 . In some embodiments, the first nitrogen content N ₁ is less than the second nitrogen content N ₂ . In some embodiments, the nitrogen content continuously changes (eg, increases) between the first nitrogen content _N1 and the second nitrogen content _N2 .

FIG. 5 illustrates a cross-sectional view of some additional embodiments of an integrated wafer structure 500 including a CBRAM device having a multilayer barrier structure.

Integrated wafer structure 500 includes a CBRAM device 108 disposed within a dielectric structure 104 over a substrate 102 . The CBRAM device 108 includes a conversion layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118 . A barrier structure 114 is located between the conversion layer 112 and the ion source layer 116 . In some embodiments, the barrier rib structure 114 includes a plurality of barrier rib layers 114 a to 114 b stacked on each other. The plurality of barrier rib layers 114a to 114b have different nitrogen contents (eg, doping concentration, atomic percentage, or the like), so as to impart a plurality of discrete (eg, discontinuous) nitrogen to the barrier rib structure 114 over a height of the barrier rib structure 114. content. In some embodiments, a first barrier layer 114 a along a bottom surface of the barrier structure 114 has a first nitrogen content greater than a first nitrogen content of a second barrier layer 114 along a top surface of the barrier structure 114 Dinitrogen content. In some embodiments, the plurality of barrier rib layers 114 a to 114 b may have gradient contents that are discontinuous with each other along interfaces between adjacent ones of the plurality of barrier rib layers 114 a to 114 b.

6A-6B illustrate some additional embodiments of integrated wafer structures comprising a CBRAM device having a disclosed barrier rib structure.

FIG. 6A illustrates a cross-sectional view 600 of an integrated chip structure. As shown in cross-sectional view 600 , the IC structure includes a CBRAM device 108 disposed within a dielectric structure 104 over a substrate 102 . CBRAM device 108 includes a conversion layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118 . A barrier structure 114 is located between the conversion layer 112 and the ion source layer 116 . One or more sidewall spacers 602 extend along the outer sidewalls of the conversion layer 112 , the barrier structure 114 , the ion source layer 116 , and/or the top electrode 118 . One or more sidewall spacers 602 comprise a dielectric material (eg, silicon oxide, silicon nitride, silicon carbide, or the like).

FIG. 6B illustrates a plan view 604 of the integrated wafer structure taken along the line A-A' of the cross-sectional view 600 . Sectional view 600 is taken along line B-B' of plan view 604. As shown in plan view 604 , one or more sidewall spacers 602 wrap around an outer boundary of barrier rib structure 114 and separate barrier rib structure 114 from dielectric structure 104 .

Although FIGS. 1-6B illustrate a CBRAM device having a single barrier structure disposed between a conversion layer and an ion source layer, it should be understood that in various additional embodiments, the barrier structure may be positioned within the disclosed CBRAM device. Various locations and/or one or more additional barrier rib structures may be provided within the CBRAM device. 7A-7C illustrate cross-sectional views of some additional embodiments of integrated wafer structures comprising a CBRAM device having one or more barrier rib structures between a top electrode and a bottom electrode.

7A illustrates a cross-sectional view of an integrated wafer 700 comprising a CBRAM device 108 with a CBRAM device 108 disposed between a top electrode 118 and an upper surface of an ion source layer 116 facing the top electrode 118. barrier structure 114 . Without proper barrier structure 114 , metals (eg, metal atoms and/or metal ions) can thermally diffuse between ion source layer 116 and top electrode 118 , thereby increasing leakage within CBRAM device 108 . Barrier structure 114 is configured to prevent thermal diffusion of metal between ion source layer 116 and top electrode 118, thereby mitigating leakage and/or CBRAM failure. In some embodiments, barrier rib structure 114 may have a thickness 208 that is less than about 75 angstroms (Å), less than about 50 Å, less than about 40 Å, or other similar values.

7B illustrates a cross-sectional view of an integrated wafer 702 comprising a CBRAM device 108 having a barrier disposed between a bottom electrode 110 and a lower surface of a switching layer 112 facing the bottom electrode 110. Structure 114. Without proper barrier structure 114 , metals (eg, metal atoms and/or metal ions) can thermally diffuse between ion source layer 116 and bottom electrode 110 , thereby increasing leakage within CBRAM device 108 . Barrier structure 114 is configured to prevent thermal diffusion of metal between ion source layer 116 and bottom electrode 110 , thereby mitigating leakage and/or failure of CBRAM device 108 .

7C illustrates a cross-sectional view of an integrated wafer 704 comprising a CBRAM device 108 having a barrier disposed between a bottom electrode 110 and a lower surface of a conversion layer 112 facing the bottom electrode 110. Structure 114. In some embodiments, a first additional barrier structure 706 is disposed between a top electrode 118 and an upper surface of an ion source layer 116 facing the top electrode 118 . The first additional barrier structure 706 is configured to mitigate thermal diffusion of metal (eg, metal atoms and/or metal ions) between the ion source layer 116 and the top electrode 118 .

7D illustrates a cross-sectional view of an integrated wafer 708 including a CBRAM device 108 having a barrier structure 114 disposed between a conversion layer 112 and an ion source layer 116 . In some embodiments, a first additional barrier structure 706 is disposed between the bottom electrode 110 and the conversion layer 112 . The first additional barrier structure 706 is configured to mitigate thermal diffusion of metal (eg, metal atoms and/or metal ions) between the ion source layer 116 and the bottom electrode 110 . In some embodiments, a second additional barrier structure 710 is disposed between the ion source layer 116 and the top electrode 118 . The second additional barrier structure 710 is configured to mitigate thermal diffusion of the metal between the ion source layer 116 and the top electrode 118 . In some alternative embodiments (not shown), the integrated wafer may have a barrier structure 114 between the conversion layer 112 and the ion source layer 116, a second additional barrier structure between the ion source layer 116 and the top electrode 118. structure 710 , but without the first additional barrier structure 706 between the bottom electrode 110 and the conversion layer 112 . In some additional alternative embodiments, the integrated wafer may have a barrier structure 114 between the conversion layer 112 and the ion source layer 116 , a first additional barrier structure 706 between the bottom electrode 110 and the conversion layer 112 , But there is no second additional barrier structure between the ion source layer 116 and the top electrode 118 .

In some embodiments, the barrier rib structure 114, the first additional barrier rib structure 706, and the second additional barrier rib structure 710 may include a metal nitride. In some embodiments, barrier rib structure 114 may include a first metal nitride (eg, aluminum nitride, silicon nitride, tungsten nitride, or the like), and first additional barrier rib structure 706 and/or second additional The barrier rib structure 710 may include an additional metal nitride different from the first metal nitride (eg, titanium nitride, tantalum nitride, tungsten nitride, or the like). In some embodiments, the barrier rib structure 114 and the first additional barrier rib structure 706 and/or the second additional barrier rib structure 710 may have different nitrogen contents. In some embodiments, barrier rib structure 114 may have a different maximum nitrogen content than first additional barrier rib structure 706 and/or second additional barrier rib structure 710, for example, barrier rib structure 114 may have a lower maximum nitrogen content than first additional barrier rib structure 706 and/or second additional barrier rib structure 710. 706 and/or the maximum nitrogen content of the second additional barrier rib structure 710 . In some embodiments, the barrier structure 114 has a first ratio of nitrogen to metal, the first additional barrier structure 706 has a second ratio of nitrogen to metal, the second ratio is different from the first ratio, and the second additional The barrier structure 710 has a third ratio of nitrogen to metal, the third ratio being different from the first ratio. In some embodiments, the first ratio is less than 1 and the second ratio and/or the third ratio is greater than 1.

In some embodiments, barrier rib structure 114 , first additional barrier rib structure 706 , and/or second additional barrier rib structure 710 may include a bilayer structure (eg, a structure having more than one layer). In some embodiments, the first additional barrier structure 706 may include a first layer closer to the bottom electrode 110 and a second layer closer to the conversion layer 112 . In some embodiments, the first layer may have a lower resistivity than the second layer. In some embodiments, the second layer may include, or be a nitride. In some embodiments, the second additional barrier structure 710 may include a third layer closer to the top electrode 118 and a fourth layer closer to the ion source layer 116 . In some embodiments, the third layer may have a lower resistivity than the fourth layer. In some embodiments, the fourth layer may include, or be a nitride.

8A-8B illustrate some additional embodiments of an integrated wafer structure comprising a CBRAM device having a barrier rib structure configured to reduce metal diffusion.

FIG. 8A illustrates a cross-sectional view 800 of an integrated wafer including a CBRAM device 108 disposed within a dielectric structure 104 above a substrate 102 . CBRAM device 108 includes a conversion layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118 . A barrier structure 114 is located between the conversion layer 112 and the ion source layer 116 .

8A further illustrates a graph 802 showing the atomic percentages of different elements within the CBRAM device 108 as a function of location within the CBRAM device 108 (taken along line A-A' of cross-sectional view 800). Graph 802 shows atomic percent nitrogen 804 , titanium atomic percent 806 , aluminum atomic percent 808 , tungsten atomic percent 810 , and oxygen atomic percent 812 over a height of CBRAM device 108 . As shown in graph 802, the atomic percent 804 of nitrogen within barrier structure 114 varies as a function of position. In some embodiments, the atomic percentage 804 of nitrogen in the barrier structure 114 is greater at a top surface facing the ion source layer 116 than at a bottom surface facing the conversion layer 112 .

In some embodiments, the atomic percentage 804 of nitrogen in the barrier structure 114 is greater than the atomic percentage 804 of nitrogen in the ion source layer 116 . In some embodiments, the atomic percentage 804 of nitrogen in the barrier structure 114 may be greater than or equal to about 40%, while the atomic percentage 804 of nitrogen in the ion source layer 116 may be less than about 40%, and the nitrogen in the conversion layer 112 may be Atomic percentage 804 may be less than about 10%, less than about 5%, or other similar values. In some embodiments, the barrier rib structure 114 has a maximum nitrogen content that is separated from a top and a bottom of the barrier rib structure 114 by a non-zero distance. In some embodiments, the barrier rib structure 114 has a nitrogen content that has a maximum value between a top and a bottom of the barrier rib structure 114 and is asymmetric with respect to the middle of the barrier rib structure 114 . In some embodiments, the ratio of nitrogen atomic percent 804 to aluminum atomic percent 808 within barrier rib structure 114 is less than one.

FIG. 8B illustrates a cross-sectional view 814 of an integrated wafer including a CBRAM device 108 disposed within a dielectric structure 104 above a substrate 102 . CBRAM device 108 includes a conversion layer 112 and an ion source layer 116 disposed between a bottom electrode 110 and a top electrode 118 . A barrier structure 114 is disposed between the ion source layer 116 and the top electrode 118 .

FIG. 8B further illustrates a graph 816 showing the atomic percentages of different elements within the CBRAM device 108 as a function of location within the CBRAM device 108 (taken along line B-B' of cross-sectional view 814). Graph 816 shows atomic percent nitrogen 818 , titanium atomic percent 820 , and aluminum atomic percent 822 over a height of CBRAM device 108 . As shown in graph 816, the atomic percent 818 of nitrogen within barrier structure 114 varies as a function of position. In some embodiments, the atomic percentage 818 of nitrogen within the barrier structure 114 is greater at the interface with the top electrode 118 than at the interface with the ion source layer 116 . In some embodiments, the atomic percentage 818 of nitrogen at the interface between the barrier structure 114 and the top electrode 118 is about 10%, or more, than the atoms of nitrogen at the interface between the barrier structure 114 and the ion source layer 116 Percentage 818.

In some embodiments, the atomic percent 818 of nitrogen in the barrier structure 114 is greater than the atomic percent 818 of nitrogen in the top electrode 118 or the ion source layer 116 . In some embodiments, the atomic percent 818 of nitrogen within the barrier structure 114 can be greater than about 50%, while the atomic percent 818 of nitrogen within the top electrode 118 can be less than about 50%, and the atomic percent of nitrogen within the ion source layer 116 818 may be less than about 20%. In some embodiments, the ratio of nitrogen atomic percent 818 to titanium atomic percent 820 within barrier rib structure 114 is greater than one.

FIG. 9 illustrates a cross-sectional view of some additional embodiments of an integrated wafer 900 including a CBRAM device having a disclosed barrier rib structure.

The integrated chip 900 includes a base body 102 including an embedded memory area 902 and a logic area 904 . A dielectric structure 104 is disposed above the base 102 . The dielectric structure 104 includes a lower ILD structure 104L, and the lower ILD structure 104L includes a plurality of lower ILD layers 104a-104b. In some embodiments, two or more adjacent ones of the plurality of lower ILD layers 104a-104b may be separated by an etch stop layer (not shown). In various embodiments, the etch stop layer may include a nitride (eg, silicon nitride), a carbide (eg, silicon carbide), or the like.

The embedded memory area 902 includes an access device 202 disposed on and/or within the substrate 102 . Access device 202 is coupled to lower interconnects 106 disposed within lower ILD layers 104a-104b. A lower insulating structure 204 is disposed over the plurality of lower ILD layers 104a-104b. In some embodiments, the lower insulating structure 204 may include two or more stacked dielectric layers 204a-204b.

A bottom electrode hole 206 extends through the lower insulating structure 204 between one of the plurality of lower interconnects 106 and a CBRAM device 108 overlying the lower insulating structure 204 . The CBRAM device 108 is disposed within an upper ILD structure 104U on the lower insulating structure 204 . In some embodiments, one or more sidewall spacers 602 are disposed on opposite sides of the CBRAM device 108 . An etch stop layer 908 is disposed on the lower insulating structure 204 and extends along opposite sides of the CBRAM device 108 and the one or more sidewall spacers 602 . In some embodiments, a hard mask 906 may be disposed between the top electrode 118 and a lower surface of the etch stop layer 908 .

Logic region 904 includes a transistor device 910 disposed on and/or within substrate 102 . Transistor device 910 is coupled to a plurality of interconnects 912 - 918 surrounded by dielectric structure 104 . In some embodiments, the plurality of interconnections 912 to 918 include a conductive contact 912 and a first interconnection wire 914 surrounded by the lower ILD structure 104L, and an interconnection hole 916 and a first interconnection hole surrounded by the upper ILD structure 104U. Two interconnecting wires 918 . In some such embodiments, the interconnect hole 916 is spaced laterally from the CBRAM device 108 and the second interconnect wire 918 is spaced laterally from the upper interconnect structure 120 . In some embodiments, the plurality of interconnects 912-918 may include one or more of copper, tungsten, aluminum, or the like.

FIGS. 10-19 illustrate cross-sectional views 1000-1900 showing some embodiments of a method of forming an integrated wafer structure comprising a CBRAM device having a barrier structure configured to reduce metal density. thermal diffusion. Although FIG. 10 to FIG. 19 are described with respect to a method, it should be understood that the structure disclosed in FIG. 10 to FIG. 19 is not limited to this method, but can exist independently as a structure independent of the method.

As shown in the cross-sectional view 1000 of FIG. 10 , a substrate 102 is provided. In various embodiments, the substrate 102 can be any type of semiconductor body (eg, silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more dies on a wafer, and related with any other type of semiconductor and/or epitaxial layer.

In some embodiments, one or more lower interconnects 106 may be formed within a lower ILD structure 104L formed over substrate 102 . In some embodiments, one or more lower interconnects 106 may include one or more of a conductive contact, an interconnect wire, and/or an interconnect hole. One, or one or more, lower interconnects 106 may be formed by forming lower ILD structure 104L over substrate 102, selectively etching lower ILD structure 104L to define a hole and/or a trench, forming a conductive material such as copper , aluminum, etc.) in the holes and/or trenches, and by performing a planarization process (eg, a chemical mechanical planarization process) to remove excess conductive material from above the lower ILD structure 104L.

As shown in the cross-sectional view 1100 of FIG. 11 , a lower insulating structure 204 is formed over the lower ILD structure 104L. In some embodiments, the lower insulating structure 204 includes a plurality of stacked dielectric layers 204 a to 204 b. For example, in some embodiments, the lower insulating structure 204 includes a first dielectric layer 204 a and a first dielectric layer 204 a above a second dielectric layer 204b. In some embodiments, the first dielectric layer 204a may include silicon-rich oxide, silicon carbide, silicon nitride, or the like. In some embodiments, the second dielectric layer 204b may include silicon carbide, silicon nitride, or the like. In some embodiments, the lower insulating structure 204 may be deposited by one or more deposition processes, such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PE-CVD) ) process, or the like) to form.

As shown in cross-sectional view 1200 of FIG. 12 , lower insulating structure 204 is selectively patterned to form an opening 1202 extending through lower insulating structure 204 and exposing an upper surface of plurality of lower interconnects 106 . One or more conductive materials 1204 - 1206 are subsequently formed within opening 1202 and over an upper surface of lower insulating structure 204 . In some embodiments, one or more conductive materials 1204 - 1206 may include a diffusion barrier layer 1204 and a metal layer 1206 above the diffusion barrier layer 1204 . In some embodiments, the diffusion barrier layer 1204 and the metal layer 1206 may be formed by a deposition process (eg, a PVD process, a CVD process, a PE-CVD process, or the like).

As shown in the cross-sectional view 1300 of FIG. 13, one or more conductive materials (1204 to 1206 of FIG. 12) are removed to form a bottom electrode hole 206. The bottom electrode hole 206 has a barrier layer 206a and a barrier layer 206a. surrounding a conductive core 206b. In some embodiments, a planarization process (such as a chemical mechanical planarization (CMP) by removing excess material of one or more conductive materials (1204-1206 of FIG. ) process) to remove a portion of one or more conductive materials ( 1204 to 1206 of FIG. 12 ). In other embodiments, portions of one or more conductive materials ( 1204 to 1206 in FIG. 12 ) are removed by means of an etch-back process.

As shown in the cross-sectional view 1400 of FIG. 14 , a CBRAM stack 1401 is formed above the lower insulating structure 204 and the bottom electrode hole 206 . In some embodiments, the CBRAM stack 1401 includes a bottom electrode layer 1402, an intermediate conversion layer 1404 above the bottom electrode layer 1402, an intermediate barrier structure 1406 above the intermediate conversion layer 1404, an intermediate barrier structure 1406 above the intermediate barrier structure 1406 The middle ion source layer 1408 , and a top electrode layer 1410 above the middle ion source layer 1408 . In some embodiments, the bottom electrode layer 1402, the middle conversion layer 1404, the middle barrier structure 1406, the middle ion source layer 1408, and the top electrode layer 1410 can be deposited by a deposition process (such as a PVD process, a CVD process, a PE- CVD process, or the like) to form.

In other embodiments (not shown), the CBRAM stack 1401 includes a bottom electrode layer, an intermediate conversion layer above the bottom electrode layer, an intermediate ion source layer 1408 above the intermediate conversion layer, an intermediate ion source layer 1408 above the ion source layer. The middle barrier structure, and a top electrode layer above the middle barrier structure. In still other embodiments (not shown), the CBRAM stack 1401 includes a bottom electrode layer, an intermediate barrier structure above the bottom electrode layer, an intermediate switching layer 1404 above the intermediate barrier structure, an intermediate switching layer above the intermediate switching layer The middle ion source layer, and a top electrode layer above the middle ion source layer. In other embodiments, the CBRAM stack 1401 may comprise any combination of the above CBRAM stacks (eg, with intermediate barrier structures in two or more of the above disclosed locations).

In some embodiments, the bottom electrode layer 1402 and/or the top electrode layer 1410 may include a metal, such as titanium, tantalum, titanium nitride, tantalum nitride, or the like. In some embodiments, the intermediate conversion layer 1404 may comprise an oxide, a nitride, or the like. For example, in some embodiments, the intermediate conversion layer 1404 may comprise silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide , titanium oxide aluminum oxide, silicon oxide, or the like. In some embodiments, the intermediate barrier structure 1406 includes a metal nitride. For example, in various embodiments, the intermediate barrier structure 1406 may include titanium nitride, amorphous titanium nitride, tantalum nitride, tungsten nitride, nitrogen silicon nitride, aluminum nitride, tungsten nitride, or the like. In some embodiments, the intermediate ion source layer 1408 may include copper, silver, aluminum, or the like. In some embodiments, the intermediate ion source layer 1408 may include cobalt, iron, boron, nickel, ruthenium, iridium, platinum, or the like.

As shown in the cross-sectional view 1500 of FIG. 15 , a mask 1502 is formed on the CBRAM stack 1401 directly over the bottom electrode hole 206 . In some embodiments, mask 1502 may include a photosensitive material (eg, photoresist). In some embodiments, the photosensitive material may be deposited by a spin-coating process. In other embodiments, mask 1502 may comprise a hard mask (eg, titanium, titanium nitride, tantalum, silicon nitride, silicon carbide, etc.).

As shown in cross-sectional view 1600 of FIG. 16 , an etch process is performed to selectively pattern the CBRAM stack ( 1401 of FIG. 15 ) according to mask 1502 to form a CBRAM device 108 . In some embodiments, the CBRAM device 108 includes a switching layer 112 disposed between a bottom electrode 110 and a top electrode 118 , a barrier structure 114 , and an ion source layer 116 . In some embodiments, the patterning process selectively exposes the CBRAM stack to a first etchant 1602 according to the mask 1502 . In some embodiments, the first etchant 1602 may include a dry etchant (eg, having a fluorine- or chlorine-based etch chemistry).

As shown in the cross-sectional view 1700 of FIG. 17 , an upper ILD structure 104U is formed above the CBRAM device 108 . In some embodiments, the upper ILD structure 104U may be formed by a deposition process such as PVD, CVD, PE-CVD, ALD, or the like. In some embodiments, the upper ILD structure 104U may include a nitride, a carbide, an oxide, or the like.

An upper interconnect structure 120 is formed within the upper ILD structure 104U. In some embodiments, the upper interconnect structure 120 may be formed by performing a planarization process that forms one or more openings 1702 (eg, vias and/or trenches) in the upper ILD structure 104U. One or more openings 1702 extend through upper ILD structure 104U to expose top electrode 118 . One or more conductive materials are disposed within the one or more openings 1702 . A planarization process (eg, a CMP process) is then performed to remove excess one or more conductive materials and form the upper interconnect structure 120 within the upper ILD structure 104U. In some embodiments, the one or more conductive materials may include aluminum, copper, tungsten, or the like.

As shown in the cross-sectional view 1800 of FIG. temperature). In some embodiments, the high temperature process 1802 may be performed for a time greater than or equal to about 30 minutes, greater than or equal to about 60 minutes, about 60 minutes, or other similar values. During the high temperature process 1802, the barrier structure 114 is configured to mitigate the thermal diffusion of metal (eg, metal ions) from the ion source layer 116 to the conversion layer 112, thereby mitigating the unwanted leakage. In some embodiments, high temperature process 1802 may include fabrication processes used during fabrication of a BEOL interconnect, a FBEOL (front-end-end-of-line) structure, or the like. In some embodiments, the high temperature process may include a bonding process, a reliability test process, a tin bump process, or other similar processes. In some embodiments, the high temperature process 1802 may be used to form a passivation layer on one of the dies configured to bond to an external die structure (eg, another die, a circuit board, a package, or the like). Do this after bonding over the pad.

As shown in the cross-sectional view 1900 of FIG. 19 , a formation process is performed on the CBRAM device 108 . The forming process forms a first conductive filament 210 in the barrier structure 114 and a second conductive filament 302 in the conversion layer 112 . In some embodiments, the forming process may be performed by applying a bias voltage across the CBRAM device 108 . The bias voltage may be greater than the bias voltage used during set and/or reset operations on the CBRAM device 108 .

20 illustrates a flow diagram of some embodiments of a method 2000 of forming an integrated wafer structure comprising a CBRAM device having a barrier structure configured to reduce metal diffusion.

Although method 2000 is illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be construed in a limiting sense, as, for example, some actions may occur in a different order and/or or concurrently with other acts or events in addition to those illustrated and/or described herein. Moreover, not all illustrated acts are required to implement one or more aspects or embodiments described herein. Furthermore, one or more acts described herein may be performed as one or more separate acts and/or phases.

In act 2002, a lower interconnect is formed in a lower ILD structure over a substrate. FIG. 10 illustrates a cross-sectional view 1000 corresponding to some embodiments of act 2002 .

In act 2004, a lower insulating structure is formed over the lower interconnect and lower ILD structures. FIG. 11 illustrates a cross-sectional view 1100 corresponding to some embodiments of act 2004 .

In act 2006, a bottom electrode hole is formed in the lower insulating structure. 12-13 illustrate cross-sectional views 1200-1300 of some embodiments corresponding to act 2006.

In act 2008, a CBRAM stack including an intermediate barrier structure between a top electrode layer and a bottom electrode layer is formed over the bottom electrode holes. FIG. 14 illustrates a cross-sectional view 1400 corresponding to some embodiments of act 2008 . In some embodiments, a CBRAM stack may be formed according to acts 2010-2018.

In act 2010, a bottom electrode layer is formed over the bottom electrode holes.

In act 2012, an intermediate conversion layer is formed over the bottom electrode layer.

In act 2014, an intermediate barrier structure is formed above the intermediate conversion layer.

In act 2016, an intermediate ion source layer is formed above the intermediate barrier structure.

In act 2018, a top electrode layer is formed above the middle ion source layer.

In act 2020, the CBRAM stack is patterned to form a CBRAM device. CBRAM devices include a barrier rib structure disposed between a bottom electrode and a top electrode. 15-16 illustrate cross-sectional views 1500-1600 corresponding to some embodiments of act 2020.

In act 2022, an upper interconnect structure is formed in an upper ILD structure formed over the CBRAM device. FIG. 17 illustrates a cross-sectional view 1700 corresponding to some embodiments of act 2022 .

In act 2024, a high temperature process is performed. In some embodiments, the high temperature process may include performing a fabrication process at a temperature greater than about 400°C. FIG. 18 illustrates a cross-sectional view 1800 corresponding to some embodiments of act 2024 .

In act 2026, conductive filaments (eg, conductive bridges) are formed in the barrier structure and a conversion layer. FIG. 19 illustrates a cross-sectional view 1900 corresponding to some embodiments of act 2026 .

Accordingly, in some embodiments, the present disclosure relates to an integrated wafer structure comprising an inductively bridged random access memory (CBRAM) device, an inductively bridged random access memory (CBRAM) device There is a barrier rib structure configured to reduce thermal diffusion of metals (eg, metal ions) due to high-temperature manufacturing processes.

In some embodiments, the disclosure relates to an integrated wafer structure. The integrated chip structure includes: a bottom electrode disposed in a dielectric structure above a substrate; a top electrode disposed in the dielectric structure above the bottom electrode; a conversion layer located between the bottom electrode and the between the top electrodes; an ion source layer disposed between the bottom electrode and the top electrode; and a barrier structure disposed between the bottom electrode and the top electrode, the barrier structure having a metal nitride, the metal Nitride systems are configured to mitigate thermal diffusion of metals during a high temperature manufacturing process. In some embodiments, the barrier structure is disposed between the conversion layer and the ion source layer. In some embodiments, the integrated wafer structure further includes: a first additional barrier structure disposed between a bottom of the conversion layer and a top of the bottom electrode; and a second additional barrier structure disposed on the between the top of one of the ion source layers and the bottom of one of the top electrodes. In some embodiments, the barrier structure includes a gradient nitrogen content between a first nitrogen content along a bottom surface of the barrier structure and a second nitrogen content along a top surface of the barrier structure The second nitrogen content is higher than the first nitrogen content. In some embodiments, the barrier rib structure has a maximum nitrogen content that is separated from the top surface and the bottom surface of the barrier rib structure by a non-zero distance. In some embodiments, the barrier structure includes a first barrier layer having a first nitrogen content along a bottom surface of the barrier structure and a second barrier layer having A second nitrogen content along a top surface of the barrier rib structure, the second nitrogen content being discontinuous from the first nitrogen content. In some embodiments, the barrier structure includes titanium nitride, tantalum nitride, aluminum nitride, silicon nitride, or tungsten nitride. In some embodiments, the barrier structure is disposed between a top of the ion source layer and a bottom of the top electrode. In some embodiments, the integrated wafer structure further includes: an additional barrier structure including an additional metal nitride disposed between the ion source layer and the top electrode, the barrier structure and the additional The barrier structures have different nitrogen contents.

In other embodiments, the present disclosure relates to an integrated wafer structure. The integrated chip structure includes: an inductive bridging random access memory (CBRAM) device disposed above a substrate, and the inductive bridging random access memory device includes: a switching layer disposed between a first electrode and between a second electrode; an ion source layer disposed between the conversion layer and the second electrode; and a barrier structure disposed between the conversion layer and the ion source layer, the barrier layer is configured to Thermal diffusion of metal between the conversion layer and the ion source layer is mitigated. In some embodiments, a first conductive filament extends through the barrier structure during storage of a first data state and a second data state; and a second conductive filament is configured to be in the first data state extending through the conversion layer during storage but not during storage of the second data state. In some embodiments, the barrier rib structure includes a ratio of nitrogen to aluminum between about 40% and about 70%. In some embodiments, the barrier rib structure includes a nitrogen content that has a maximum between a top and a bottom of the barrier rib structure and is asymmetric with respect to the middle of the barrier rib structure. In some embodiments, the integrated wafer structure further includes: a first additional barrier structure disposed between a bottom of the conversion layer and a top of the first electrode, the barrier structure has a first nitrogen pair metal a ratio, the first ratio is less than one, and the first additional barrier structure has a second ratio of nitrogen to metal, the second ratio is greater than one. In some embodiments, the barrier structure includes silicon nitride, aluminum nitride, or tungsten nitride. In some embodiments, the barrier rib structure has a thickness less than about 50 angstroms. In some embodiments, the barrier structure includes a first barrier layer and a second barrier layer, the first barrier layer has a first gradient nitrogen content, the second barrier layer has a second gradient nitrogen content, the first barrier layer The second gradient of nitrogen content is discontinuous from the first gradient of nitrogen content. In some embodiments, the barrier structure has a first non-zero atomic percentage of nitrogen that is greater than about 50%, and the ion source layer has a second non-zero atomic percentage of nitrogen that is greater than about 50%. Two non-zero atomic percents are less than about 20%.

In yet other embodiments, the present disclosure relates to a method of forming an integrated wafer structure. The method includes: forming a lower interconnect in a lower interlayer dielectric (ILD) structure over a substrate; forming an inductive bridging random access memory (CBRAM) stack between the lower ILD structure and the lower interconnect connecting; patterning the inductive bridging random access memory stack according to a mask to form an inductive bridging random access memory device, the inductive bridging random access memory device being comprised between a first electrode and a a conversion layer and an ion source layer between the second electrodes, a barrier structure is also disposed between the first electrode and the second electrode; and forming an upper interconnection in the inductive bridge random access memory In an upper ILD structure above the device, the upper interconnect is coupled to the second electrode. In some embodiments, the method further includes: performing a high temperature process at a temperature greater than 400° C. after patterning the inductive bridging random access memory stack, the barrier rib structure being configured for the high temperature process During this process, the thermal diffusion of metal ions from the ion source layer to the conversion layer is mitigated.

The foregoing outlines features of several implementations so that those of ordinary skill in the art may better understand aspects of the disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for the design or modification of other processes and structures for the same purposes as the embodiments presented herein, and/or to achieve the same advantage. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure. .

100: Integrated Wafer Structure 102: Substrate 104: Dielectric Structure 104a: (First) Lower ILD Layer 104b: (Second) Lower ILD Layer 104L: Lower ILD Structure 104U: Upper ILD Structure 106: Lower Interconnect 108: Inductor CBRAM device 110: bottom electrode 112: conversion layer 114: barrier structure 114a: (first) barrier layer 114b: (second) barrier layer 116: ion source layer 118: top electrode 120: Upper interconnection structure 120a: interconnection hole 120b: interconnection wire 200: integrated chip 202: access device 202a: source region 202b: drain region 202c: gate structure 204: lower insulating structure 204a: (first) Dielectric layer 204b: (second) dielectric layer 206: Bottom electrode hole 206a: Barrier layer 206b: Conductive core 208: Thickness 210: First conductive filament 212: Memory circuit 214: Memory array 216 _1,1 To 216 _n,m : CBRAM memory cell 218: control circuit 220: word line decoder 222: bit line decoder 224: source line decoder 226: sense amplifier 228: control unit 300: cutaway view 302: Second conductive filament 304: cross-sectional view 400: integrated wafer 402: diagram 500: integrated wafer structure 600: cross-sectional view 602: sidewall spacer 604: plan view 700: integrated wafer 702: integrated wafer 704: integrated wafer 706: first additional barrier structure 708: integrated wafer 710: second additional barrier structure 800: cross-sectional view 802: chart 804: atomic percentage of nitrogen 806: atomic percentage of titanium 808: atomic percentage of aluminum 810: of tungsten Atomic percent 812: Atomic percent of oxygen 814: Profile diagram 816: Chart 818: Atomic percent of nitrogen 820: Atomic percent of titanium 822: Atomic percent of aluminum 900: Integrated chip 902: Memory area 904: Logical area 906: Hard Mask 908: Etch Stop Layer 910: Transistor Device 912: Interconnect/Conductive Contact 914: Interconnect/First Interconnect Wire 916: Interconnect/Interconnect Hole 918: Interconnect/Second Interconnect Wire 1000: Cross section 1100: Cross section 1200: Cross section 1202: Opening 1204: Conductive material/diffusion barrier layer 1206: Conductive material/metal layer 1300: Cross section 1302: Line 1400: Cross section 1401: CBRAM stack 1402: Bottom electrode layer 1404: Intermediate conversion layer 1406: intermediate barrier structure 1408: intermediate ion source layer 1410: top electrode layer 1500: sectional view 1502: mask 1600: sectional view 1602: first etchant 1700: sectional view 1702: opening 1800: sectional view 1802: High Temperature Process 1900: Profile 2000: Method 2002: Action 2004: Action 2006: Action 2008: Action 2010: Action 2012: Action 2014: Action 2016: Action 2018: Action 2020: Action 2022: Action 2024: Action 2026: Action BL: Bit line N ₁ : first nitrogen content N ₂ : second nitrogen content SL: source line S _ADR : address information V _R : reset voltage V _S : set voltage WL: word line

Aspects of the present disclosure are best understood from the following Detailed Description when read with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various components are not drawn to scale. In particular, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

Figure 1 illustrates a cross-sectional view of some embodiments of an integrated wafer structure comprising an inductively bridged random access memory (CBRAM) device having a barrier structure, the barrier rib structure is configured to reduce metal diffusion due to high temperature manufacturing process.

2A-2B illustrate some additional embodiments of an integrated wafer structure comprising a CBRAM device having a barrier structure configured to reduce metal diffusion.

3A-3B illustrate cross-sectional views of some embodiments showing the operation of a CBRAM device having a barrier structure configured to reduce metal diffusion.

4A-4B illustrate some additional embodiments of an integrated wafer structure comprising a CBRAM device having a barrier structure configured to reduce metal diffusion.

5-7D illustrate some additional embodiments of integrated wafer structures comprising a CBRAM device having a barrier structure configured to reduce metal diffusion.

8A-8B illustrate some additional embodiments of an integrated wafer structure comprising a CBRAM device having a barrier structure configured to reduce metal diffusion.

Figure 9 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure comprising a logic region and an embedded memory region, the embedded memory region comprising a CBRAM device having a barrier structure , the barrier structure is configured to reduce metal diffusion.

10-19 illustrate cross-sectional views showing some embodiments of methods of forming an integrated wafer structure including a CBRAM device having a barrier structure configured to reduce metal diffusion.

20 illustrates a flow diagram of some embodiments of a method of forming an integrated wafer structure comprising a CBRAM device having a barrier structure configured to reduce metal diffusion.

100: Integrated Chip Structure

102: matrix

104: Dielectric structure

104L: Lower ILD structure

104U: Upper ILD structure

106: Lower interconnection

108: Inductive bridge random access memory (CBRAM) device

110: Bottom electrode

112: Conversion layer

114: Barrier structure

116: ion source layer

118: top electrode

120: Upper interconnect structure

Claims (20)

An integrated wafer structure comprising: a bottom electrode disposed in a dielectric structure above a substrate; a top electrode disposed within the dielectric structure above the bottom electrode; a conversion layer located between the bottom electrode and the top electrode; an ion source layer disposed between the bottom electrode and the top electrode; and A barrier structure is disposed between the bottom electrode and the top electrode, wherein the barrier structure includes a metal nitride configured to mitigate thermal diffusion of metal during a high temperature manufacturing process. The integrated wafer structure as claimed in claim 1, wherein the barrier structure is disposed between the conversion layer and the ion source layer. The integrated chip structure as described in Claim 1, further comprising: a first additional barrier rib structure disposed between a bottom of the conversion layer and a top of the bottom electrode; and A second additional barrier rib structure is disposed between a top of the ion source layer and a bottom of the top electrode. The integrated wafer structure of claim 1, wherein the barrier rib structure comprises a gradient nitrogen content between a first nitrogen content along a bottom surface of the barrier rib structure and a nitrogen content along one of the barrier rib structures The top surface varies continuously between a second nitrogen content that is higher than the first nitrogen content. The integrated wafer structure of claim 4, wherein the barrier rib structure has a maximum nitrogen content that is separated from the top surface and the bottom surface of the barrier rib structure by a non-zero distance. The integrated wafer structure as claimed in claim 1, wherein the barrier structure comprises a first barrier layer and a second barrier layer, the first barrier layer has a first nitrogen content along a bottom surface of the barrier structure , the second barrier layer has a second nitrogen content along a top surface of the barrier structure, the second nitrogen content being discontinuous from the first nitrogen content. The integrated wafer structure according to claim 1, wherein the barrier structure comprises titanium nitride, tantalum nitride, aluminum nitride, silicon nitride, or tungsten nitride. The integrated wafer structure of claim 1, wherein the barrier structure is disposed between a top of the ion source layer and a bottom of the top electrode. The integrated chip structure as described in Claim 1, further comprising: An additional barrier structure includes an additional metal nitride disposed between the ion source layer and the top electrode, wherein the barrier structure and the additional barrier structure have different nitrogen contents. An integrated wafer structure comprising: An inductive bridging random access memory (CBRAM) device disposed over a substrate, wherein the inductive bridging random access memory device comprises: a conversion layer, disposed between a first electrode and a second electrode; an ion source layer disposed between the conversion layer and the second electrode; and A barrier structure is disposed between the conversion layer and the ion source layer, wherein the barrier layer is configured to alleviate thermal diffusion of metal between the conversion layer and the ion source layer. The integrated chip structure as described in Claim 10, wherein a first conductive filament extends through the barrier structure during storage of a first data state and a second data state; and One of the second conductive filaments is configured to extend through the switching layer during storage of the first data state but not during storage of the second data state. The integrated wafer structure of claim 10, wherein the barrier structure comprises a ratio of nitrogen to aluminum between about 40% and about 70%. The integrated wafer structure as claimed in claim 10, wherein the barrier rib structure includes a nitrogen content having a maximum value between a top and a bottom of the barrier rib structure and relative to the median of the barrier rib structure is asymmetrical. The integrated chip structure as described in Claim 10, further comprising: a first additional barrier structure disposed between a bottom of the conversion layer and a top of the first electrode, wherein the barrier structure has a first ratio of nitrogen to metal, the first ratio is less than 1, and the The first additional barrier structure has a second ratio of nitrogen to metal, the second ratio being greater than one. The integrated wafer structure according to claim 10, wherein the barrier structure comprises silicon nitride, aluminum nitride, or tungsten nitride. The integrated wafer structure of claim 10, wherein the barrier rib structure has a thickness less than about 50 angstroms. The integrated wafer structure as claimed in claim 10, wherein the barrier structure comprises a first barrier layer and a second barrier layer, the first barrier layer has a first gradient nitrogen content, and the second barrier layer has a first Two nitrogen content gradients, the second nitrogen content gradient is discontinuous with the first nitrogen content gradient. The integrated wafer structure of claim 10, wherein the barrier structure has a first non-zero atomic percentage of nitrogen, the first non-zero atomic percentage is greater than about 50%, and the ion source layer has a second non-zero nitrogen Atomic percent nitrogen, the second non-zero atomic percent being less than about 20%. A method of forming an integrated wafer structure, comprising: forming a lower interconnect in a lower interlayer dielectric (ILD) structure above a substrate; forming an inductive bridging random access memory (CBRAM) stack over the lower ILD structure and the lower interconnect; Patterning the inductive bridging random access memory stack according to a mask to define an inductive bridging random access memory device included in a first electrode and a second electrode between a conversion layer and an ion source layer, wherein a barrier structure is also disposed between the first electrode and the second electrode; and An upper interconnect is formed in an upper ILD structure above the inductive bridge random access memory device, the upper interconnect is coupled to the second electrode. The method as described in Claim 19, further comprising: After patterning the inductively bridged random access memory stack, a high temperature process is performed at a temperature greater than about 400° C., wherein the barrier structure is configured to relieve a flow from the ion source layer to the high temperature process during the high temperature process. Thermal diffusion of metal ions in the conversion layer.

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