TW202318190A - Apparatus and method for implementing vector mask in vector processing unit - Google Patents

Abstract

The mask data corresponding to each data element of the issued instruction may be handled by a mask queue, where only the valid mask data are stored to the mask queue. The mask data of multiple vector instructions may be stored in the mask queue. The corresponding mask data may be accessed from the mask queue when the vector instruction(s) is issued from the execution queue to the functional unit for execution. In the case of 512-bit wide mask data is needed, the dispatching of the vector instruction from the decode/issue unit to the execution queue may be stalled until the mask queue is available. In some embodiments, one mask queue may be dedicated to one execution queue. Alternatively, one mask queue may be shared between two different execution queues. In the disclosure, resources are conserved without dedicating additional storage space for handling mask data of the vector instruction.

Description

Microprocessor and method for handling mask data for vector instructions

The present invention relates to a microprocessor, and more particularly to a method and microprocessor for processing vector instructions.

The Single Instruction Multiple Data (SIMD) architecture achieves high performance by concurrently executing multiple data elements specified by SIMD instructions (also known as vector instructions), while scalar instructions only process one data element or a pair of data elements ( That is, two source operands). Each of the data elements may represent an individual piece of data (eg, primitive data, graphics coordinates, etc.) stored in a scratchpad or other storage location, along with other data elements that are typically of the same size. The number of data elements specified by a vector instruction varies greatly based on the data element size and a vector length multiplier (LMUL). For example, when LMUL is 1, a 512-bit wide vector data may have 64 8-bit wide data elements, 32 16-bit wide data elements, sixteen 32-bit wide data elements, and so on. When LMUL is 8, 512-bit wide vector data can have 512 8-bit wide data elements, 256 16-bit wide data elements, 128 32-bit wide data elements data elements etc.

In the processing of vector instructions, each data element of the vector register will be appended with a mask bit which, when enabled, masks the corresponding data element to a specified operation. In the worst case scenario, all 512 bits of the mask vector register would be used for five hundred and twelve 8-bit wide data elements. On the other hand, only 16 bits of the 512-bit mask vector register are required for 512-bit wide vector data with sixteen 32-bit wide data elements. Although not all vector instructions are worst-case scenarios (i.e., all 512 bits are required), each vector instruction still issues 512 bits of mask data to cover all possibilities of prediction regardless of all 512 bits Whether mask data is required for vector instructions (ie, "enforcement of mask data"). Such implementations with mask profiles for vector instructions occupy much storage area and power for multiple queued vector instructions in multiple execution pipelines of a vector scratchpad.

The present invention provides a mask queue that manages mask data corresponding to data elements of vector instructions dispatched from a decode/issue unit to an execution queue.

The microprocessor of the present invention includes a decode/transmit unit and an execution queue. Execution queues consist of multiple queue entries and mask queues. In an embodiment, the execution queue is configured to assign to the first queue entry a first instruction dispatched from the decode/issue unit and operating on data having a first plurality of data elements. The mask queue includes a plurality of mask entries, and when the first instruction is assigned to the first queue entry in the execution queue, first mask data corresponding to the first instruction is written to the first number of masks entries, wherein the first number is determined based on the width of the first data element.

The method for handling mask data of vector instructions of the present invention includes the following steps. A first instruction operating on data having a plurality of first data elements is dispatched to an execution queue including a mask queue. The first instruction is assigned to a first queue entry in the execution queue. writing first mask data corresponding to the first command to a first number of mask entries in the mask queue, wherein the first number is determined based on a width of the first data element .

In the present invention, mask data corresponding to data elements of dispatched instructions may be handled or managed by an introduced mask queue, where only valid mask data for all vector instructions in the execution queue are stored to the mask queue. In the present disclosure, mask data for multiple vector instructions can be stored in a mask queue. When a vector instruction is issued from the execution queue to a functional unit for execution, corresponding mask data can be accessed from the mask queue. Dispatch of vector instructions from the decode/issue unit to the execution queue may be stopped if the mask queue does not have enough entries available. In some embodiments, one mask queue may be dedicated to one execution queue. In some other embodiments, a mask queue can be shared between two different execution queues.

Based on the above, in the present invention, resources are reserved without dedicating additional storage space to handling mask data for vector instructions. That is, when the vector instruction is dispatched to the execution queue, the mask queue will only read the mask data required by the vector instruction from the mask register. The implementation of mask queues greatly reduces the resources required to manage the masks used to process data elements of vector instructions.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include that additional features may be formed between the first feature and the second feature. An embodiment in which the second features are formed such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. The present disclosure introduces a mask queue that manages mask data corresponding to data elements of dispatched vector instructions. In "Brute Force of Mask Operations," every instruction with the entire mask register (eg, 512 bits) is dispatched to the execution queue regardless of whether all mask data will be needed by the register. If the execution queue has 8 entries, the mask storage will be 4096 bits (ie, 512 x 8). If there were 8 execution queues, then the mask storage would be 32768 bits (ie, 512 x 8 x 8). Since not all vector instructions will use a 512-bit mask, the forced mask storage is wasteful. In the present disclosure, when the vector instruction is dispatched to the execution queue, the mask queue will only read the mask data required by the vector instruction from the mask register. The implementation of mask queues greatly reduces the resources required to manage the masks used to process data elements of vector instructions.

Referring to FIG. 1 , a schematic diagram of a data processing system 1 including a microprocessor 10 and a memory 30 is shown according to some embodiments. Microprocessor 10 is implemented to perform various data processing functionality by executing instructions stored in memory 30 . The memory 30 may include a level 2 (level 2; L2) cache memory and a level 3 (level 3; L3) cache memory and the main memory of the data processing system 1, wherein the L2 cache memory and the L3 cache memory Memory has faster access times than main memory. Memory can include random access memory (random access memory; RAM), dynamic random access memory (dynamic random access memory; DRAM), static random access memory (static random access memory; SRAM), read-only memory Body (read only memory; ROM), programmable read only memory (programmable read only memory; PROM), electrically programmable read only memory (electrically programmable read only memory; EPROM), electrically erasable programmable design At least one of an electrically erasable programmable read only memory (EEPROM) and a flash memory.

The microprocessor 10 may be a general-purpose processor (eg, central processing unit) or a special-purpose processor (eg, network processor, communication processor, DPS, embedded processor, etc.). The processor may have any one of the following instruction set architectures: Complex Reduced Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), Very Long Instruction Word (VLW) Instruction Word; VLIW), its hybrids, or other types of instruction set architectures. In some of the embodiments, the microprocessor is a RISC processor that performs prediction or masking on vector instructions. Microprocessors implement instruction-level parallelism within a single microprocessor and achieve high performance by executing multiple instructions per clock cycle. Multiple instructions are issued to different functional units for concurrent execution. A superscalar microprocessor may employ out-of-order (OOO) execution, wherein a second instruction without any dependency on the first instruction may be executed before the first instruction. In traditional out-of-order microprocessor designs, instructions may be executed out-of-order, but must be retired in-order to the microprocessor's scratchpad due to control hazards such as branch mispredictions, interrupts, and precise exceptions. Temporary storage such as reorder buffers and scratchpad renames are used for result data until an orderly retirement of an instruction from the execution pipeline. As long as the instruction has no data dependencies and control hazards, microprocessor 10 can execute and retire instructions out of order by writing the resulting data back out of order to the register bank.

Referring to FIG. 1, the microprocessor 10 may include an instruction cache memory 11, a branch prediction unit (branch prediction unit; BPU) 12, a decode/issue unit 13, a register set 14, a scoreboard 15, a read/write Into control unit 16, load/store unit 17, data cache memory 18, multiple execution queues (execution queue; EQ) 19A to execution queue 19E, and multiple functional units (functional unit, FUNT) 20A to function Unit 20C. Microprocessor 10 also includes read bus 31 and result bus 32 . Read bus 31 is coupled to load/store unit 17, functional unit 20A to functional unit 20C, and register bank 14 for transferring operational metadata from registers in register bank 14 to load/store The storage unit 17 and the functional unit 20A to the functional unit 20C can also be referred to as the operation of reading the operation metadata from the register set 14 . Results bus 32 is coupled to data cache 18, functional unit 20A to functional unit 20C, and scratchpad bank 14 for transferring data from data cache 18 or functional unit 20A to functional unit 20C to scratchpad This may also be referred to as an operation of writing back result data to the scratchpad bank 14. Elements referred to herein by a specific reference number followed by a letter will be referred to collectively by a single reference number. For example, execution queue 19A to execution queue 19E and functional unit 20A to functional unit 20C may be collectively referred to as execution queue 19 and functional unit 20 , respectively, unless otherwise specified. Some embodiments of the present disclosure may use more, fewer or different components than those shown in FIG. 1 .

In some embodiments, instruction cache 11 is coupled (not shown) to memory 30 and to decode/issue unit 13 and is configured to store instructions fetched from memory 30 and dispatch the instructions to decode/issue Unit 13. Instruction cache 11 contains a number of cache lines of consecutive instruction bytes from memory 30 . Cache lines are organized as direct-mapped, fully-associative-mapped, or set-associative-mapped, etc. Direct mapping, fully associative mapping, and set associative mapping are well known in the related art, so detailed descriptions about the above mappings are omitted.

The instruction cache memory 11 may include a tag array (not shown) and a data array (not shown) for respectively storing a part of addresses and data of instructions frequently used by the microprocessor 10 . Each tag in the tag array corresponds to a cache line in the data array. When the microprocessor 10 needs to execute an instruction, the microprocessor 10 first checks the existence of the instruction in the instruction cache 11 by comparing the address of the instruction with the tags stored in the tag array. If the instruction address matches one of the tags in the tag array (ie, a cache hit), then the corresponding cache line is fetched from the data array. If the instruction address does not match any entry in the tag array (ie, a cache miss), microprocessor 10 may access memory 30 to find the instruction. In some embodiments, the microprocessor 10 further includes an instruction queue (not shown), which is coupled to the instruction cache 11 and the decode/issue unit 13 for sending the instruction to the decode/issue unit 13. The issue unit 13 previously stores instructions from the instruction cache 11 or the memory 30 .

BPU 12 is coupled to instruction cache 11 and is configured to speculatively fetch instructions following a branch instruction. The BPU 12 may provide a prediction of the branch direction (taken or not taken) of the branch instruction based on the past behavior of the branch instruction and provide the predicted branch target address of the taken branch instruction. Branch directions may be "taken," wherein subsequent instructions are fetched from the branch target address of the taken branch instruction. A branch direction may be "not taken," wherein subsequent instructions are fetched from memory locations consecutive to the branch instruction. In some embodiments, the BPU 12 implements basic block branch prediction for predicting the end of the basic block from the starting address of the basic block. The starting address of the basic block (eg, the address of the first instruction of the basic block) may be the target address of a previously taken branch instruction. The end address of a basic block is the instruction address after the last instruction of the basic block, which may be the start address of another basic block. A basic block may contain multiple instructions, and the basic block ends when a branch in the basic block jumps to another basic block.

The decode/issue unit 13 can decode instructions received from the instruction cache 11 . An instruction can contain the following fields: operation code (or operation code), operands (for example, source operand and destination operand), and immediate value. The job code specifies what operation to perform (for example, ADD, SUBTRACT, SHIFT, STORE, LOAD, etc.). An operand may specify the index (i.e., address) of a register in the register bank 14, where the source operand indicates the register from which the operation is to be read from the register bank, and the destination operand Indicates the register in the register group to which the result data of the operation will be written back. It should be noted that source operand and destination operand may also be referred to as source register and destination register, which are used interchangeably hereinafter. In an embodiment, an operand will require a 5-bit index to identify a register in a bank of 32 registers. Some instructions may use immediate values instead of register data as specified in the instruction. Each instruction will be executed in functional unit 20 or load/store unit 17 . Each instruction will have an execution latency and throughput time based on the type of operation specified by the jobcode and the availability of resources (eg, registers, functional units, etc.). Execution latency (or latency) is the amount of time (ie, the number of clock cycles) it takes to perform the operation specified by an instruction to complete and write back the resulting data. Throughput time refers to the amount of time (ie, the number of clock cycles) when the next instruction can enter the functional unit 20 .

In an embodiment, instructions are decoded in the decode/issue unit 13 to obtain execution latency, throughput time, and instruction type based on the job code. Multiple commands can be dispatched to an execution queue 19 where the throughput times of the multiple commands are accumulated. Given the previously dispatched instructions in execution queue 19, the accumulated throughput time indicates when the next instruction to issue may enter functional unit 20 for execution (ie, the amount of time an instruction must wait before entering functional unit 20). The time defined when the instruction to be issued can be sent to the functional unit 20 is called the read time (from the scratchpad bank), and the time defined when the instruction is completed by the functional unit 20 is called the write time (to the scratchpad bank). Group). Instructions are dispatched to an execution queue 19, with each dispatched instruction having a scheduled fetch time to issue to a corresponding functional unit 20 or load/store unit 17 for execution. At the dispatch of an instruction, the cumulative throughput time of the dispatched instructions in the execution queue 19 is the fetch time of the instruction to be dispatched. When an instruction is dispatched to the next available entry in the execution queue 19, the execution latency of the instruction to be dispatched is added to the accumulated throughput time to generate the write time. The modified execution latency will be referred to herein as the write time of the most recently dispatched instruction, and the modified start time will be referred to herein as the read time of the next instruction to issue. Write time and read time may also be collectively referred to as access time, which describes the writing of dispatched instructions to or reading from the scratchpads of scratchpad bank 14. A specific point in time at which an instruction is dispatched. Since the source register is scheduled to be read from the register bank 14 just in time for the execution of the functional unit 20, the source register does not require a temporary register in the execution queue, which is why the microprocessor of this embodiment Advantages of other microprocessors compared to other embodiments. Since the destination register is scheduled to be written back to the scratchpad bank 14 from the functional unit 20 or data cache 18 at an exact time in the future, even with other functional units 20 or data caches in other embodiments If there is a conflict in the body 18, then there is no need for a temporary register to store the result data, which is also an advantage compared to other microprocessors. For parallel issue of more than one instruction, the write time and read time of the second instruction may be further adjusted based on the first instruction issued before the second instruction.

For vector processing, decode/issue unit 13 reads mask data from mask vector register v(0) of register set 14 and attaches the mask data with the vector instructions to execute queue 19 . Each execution queue 19 includes a mask queue 21 for storing mask data for each vector instruction issued in the execution queue 19 . When an instruction is issued from the execution queue 19 to the functional unit 20, mask data is read from the mask queue 21 (if masking is enabled) and sent to the functional unit 20 along with the instruction.

In an embodiment, the decode/transmit unit 13 is configured to check and resolve all possible conflicts before issuing an instruction. Instructions can have the following four basic types of conflicts: (1) Data dependencies, which include write-after-read (WAR), read-after-write (RAW), and write-after-write ( write-after-write; WAW) dependency; (2) Availability of a read port to read data from the register bank to the functional unit; (3) Write data back from the functional unit to the register bank Availability of the write port; and (4) availability of the functional unit 20 for executing the data. Before an instruction can be dispatched to execution queue 19, decode/issue unit 13 may access scoreboard 15 to check for data dependencies. Furthermore, the register bank 14 has a limited number of read and write ports, and issued instructions must arbitrate or reserve the read and write ports for accessing the register bank 14 at a future time. The decode/issue unit 13 can access the read/write control unit 16 to check the availability of the read port and the write port of the register bank 14 in order to schedule the access times of the instructions (i.e., the read and write times ). In other embodiments, one of the write ports may be dedicated to commands with unknown write times that do not use write port control, and one of the read ports may be reserved for commands with unknown read times that do not use read port control commands. The read ports of the register bank 14 can be dynamically reserved (not dedicated) for read operations with unknown access times. In this case, the functional unit 20 must ensure that the read port is not busy when attempting to read data from the register set 14 . In an embodiment, the availability of functional units 20 may be resolved by coordinating with the execution queue 19 where the throughput time of queued instructions (ie, previously dispatched to the execution queue) is accumulated. Based on the cumulative throughput time in the execution queue, instructions may be dispatched to execution queue 19, where the instruction may be scheduled to be issued to functional unit 20 at a specific time in the future when functional unit 20 becomes available.

FIG. 2 is a block diagram illustrating a register bank 14 and a scoreboard 15 according to some embodiments of the present disclosure. The register set 14 may include a plurality of vector registers v(0) to vector registers v(N), read ports (not shown) and write ports (not shown), wherein N is greater than 1 an integer of . In an embodiment, register bank 14 may include scalar registers and/or vector registers. The present disclosure does not intend to limit the number of registers, read ports, and write ports in the register bank 14 . In an embodiment, one of the vector registers contained in the register set 14 will be used to present masking material for vector processing, and therefore unless otherwise specified, occurrences of the term "register" hereinafter are Points to the scratchpad. The scoreboard 15 includes a plurality of entries 150(0) to 150(N), and each scoreboard entry corresponds to a register in the register set 14 and records information related to the corresponding register. In an embodiment, scoreboard 15 has the same number of entries as scratchpad bank 14 (ie, N number of entries), but the present disclosure does not wish to limit the number of entries in scoreboard 15 .

3A-3B are diagrams illustrating various structures of scoreboard entries according to some embodiments of the present disclosure. In an embodiment, the scoreboard 15 may include a first scoreboard 151 for handling write-back operations to the scratchpad bank 14 and a second scoreboard for handling read operations from the scratchpad bank 14 plate 152. The first scoreboard 151 and the second scoreboard 152 may or may not coexist in the microprocessor 10 . The present disclosure is not intended to be limited in this regard. In other embodiments, first scoreboard 151 and second scoreboard 152 may be implemented or viewed as one scoreboard 15 that handles both read and write operations. FIG. 3A shows a first scoreboard 151 for the destination register of issued instructions. Figure 3B shows the scoreboard 15 for the source register of issued instructions. Referring to FIG. 3A , each entry 1510(0) through entry 1510(N) of the first scoreboard 151 includes an unknown field ("unknown") 1511, a write count field ("cnt") 1513, and a functional unit field bit("funit") 1515. Each of these fields records information related to the corresponding destination register to be written by the issued command. These fields for scoreboard entries can be set when an order is issued.

Unknown field 1511 contains a bit value indicating whether the write time of the scratchpad corresponding to the scoreboard entry is known or unknown. For example, unknown field 1511 may contain one bit or any number of bits, where a non-zero value indicates that the register has an unknown write time, and a value of zero indicates that the register has an unknown write time as indicated by write count field 1513. The indicated known write time. The unknown field 1511 can be set or modified at the issue time of the command and reset after resolving the unknown register write time. For example, the reset operation can be performed by the decode/transmit unit 13, the load/store unit 17 (e.g., after a data hit), or the functional unit 20 (e.g., after an INT DIV integer division operation parses the number of digits that need to be divided). number) and other units in the microprocessor that involve executing instructions with unknown write times. Write count field 1513 records a write count value (ie, write time) indicating the number of clock cycles before the scratchpad can be accessed by the next instruction (to be issued). In other words, the write count field 1513 records the number of clock cycles in which a previously issued instruction will complete the operation and write the resulting data back to the scratchpad. The write count value of the write count field 1513 is set based on the write time of the command (also referred to as execution latency) at the time when the command is issued. Then, the write count value counts down (ie, decreases by one) for each clock cycle until the count value becomes zero (ie, self-reset counter). The functional unit field 1515 of the scoreboard entry specifies the functional unit 20 (specified by the issued command) to be written back to the scratchpad.

Referring to FIG. 3B, the second scoreboard 152 has a structure of scoreboard entry 1520(0) to scoreboard entry 1520(N), and the second scoreboard 152 is used to parse WAR data before dispatching instructions. Dependencies, that is, resolving conflicts between writing to the destination register and reading the register corresponding to the scoreboard entry. This scoreboard can also be referred to as the WAR scoreboard for resolving dependencies of WAR data. Each of scoreboard entry 1520(0) through scoreboard entry 1520(N) includes an unknown field 1521 and a read count field 1523 . The functional unit field may be omitted in a WAR scoreboard implementation. Unknown field 1521 contains a bit value indicating whether the read time of the scratchpad corresponding to the scoreboard entry is known or unknown. For example, unknown field 1521 may contain a bit where a non-zero value indicates that the register has an unknown read time, and a value of zero indicates that the register has a known read time as indicated by read count field 1523 . Similar to unknown field 1511 in FIG. 3A , unknown field 1521 may contain any number of digits to indicate that there have been one or more issued commands with unknown read times. The operation and functionality of unknown field 1521 is similar to unknown field 1511, and thus, its details are omitted for the sake of brevity. The read count field 1523 records the count value, which indicates the number of clock cycles after which the issued instruction will be read from the corresponding register for the last time. The read count value counts down (ie, decreases by one) for each clock cycle until the read count value reaches zero. Unless specified, the operation and functionality of the read count field 1523 is similar to the write count field 1513, and details thereof are therefore omitted.

Referring to FIG. 1 , the read/write control unit 16 is configured to record the availability of the read port and/or write port of the scratchpad bank 14 at multiple clock cycles in the future for use in scheduling the availability of instructions to be issued. access. When issuing a command, the decode/transmit unit 13 accesses the read/write control unit 16 to check the availability of the read port and/or write port of the register set 14 based on the access time specified by the command. In detail, the read/write control unit 16 selects an available read port at a future time as the scheduled read time for reading source operands to the functional unit 20, and selects an available write port at a future time as a write-back Scheduled write time for result data from functional unit 20. In an embodiment, the read/write control unit 16 may include a read shifter (not shown) and a write shifter (not shown) for scheduling the read port and the write port. Each of the read shifter and the write shifter contains a plurality of shifter entries, where each entry corresponds to a future clock cycle and records the scratchpad to be accessed and the scratchpad to be stored at the corresponding clock cycle. Fetch the address of the functional unit of the scratchpad. In an embodiment, one entry will be shifted out every clock cycle. In some embodiments, each read port and each write port of register set 14 may correspond to a read shifter and a write shifter.

Vector execution queue 19 is configured to hold issued vector instructions scheduled for issue to functional units 20 . In an embodiment, each vector execution queue 19 includes a mask queue 21 that stores mask data corresponding to the vector instructions dispatched to the execution queue 19 . Referring to FIG. 1 , vector execution queue 19A includes mask queue 21A, vector execution queue 19B includes mask queue 21B, vector execution queue 19C includes mask queue 21C, and so on. The functional unit 20 may include but not limited to: integer multiplication, integer division, arithmetic logic unit (arithmetic logic unit; ALU), floating-point unit (floating-point unit; FPU), branch execution unit (branch execution unit; BEU), receiving A unit or similar that decodes instructions and performs operations. In an embodiment, each of the execution queues 19 is coupled to or dedicated to one of the functional units 20 . For example, the execution queue 19A is coupled between the decode/transmit unit 13 and the corresponding functional unit 20A to sequentially issue the instructions to the corresponding functional unit 20A. Similarly, execute queue 19B is coupled between decode/transmit unit 13 and corresponding functional unit 20B, and execute queue 19C is coupled between decode/transmit unit 13 and corresponding functional unit 20C. In an embodiment, execute queue 19D, execute queue 19E are coupled between decode/issue unit 13 and load/issue unit 17 to handle load/store instructions.

FIG. 4 is a diagram illustrating a vector execution queue 19 according to some embodiments of the present disclosure. Vector execution queue 19 may include a plurality of execution queue entries 190(0) through 190(Q) for recording information about vector instructions issued from decode/issue unit 13, where Q is greater than 1 an integer of . In an embodiment, each entry of the execution queue 19 includes, but is not limited to, a valid field ("v") 191, an execution control data field ("ex_ctrl") 193, an address field ("vd") 195, A throughput time field ("xput_cnt") 197 and a micro-op count field ("mop_cnt") 198 . The embodiments are not intended to limit the information or number of fields included in each entry of the vector execution queue 19 . In alternative embodiments, more or fewer fields may be used to record less or more information in each execution queue. It should also be noted that each of functional unit 20A through functional unit 20C may be coupled to a vector execution queue that is the same or similar to that shown in FIG. 4 , with vector execution queue 19A through vector execution queue 19C Each of these receives a dispatched vector instruction from decode/issue unit 13 and issues the received vector instruction to a corresponding functional unit 20A-20C.

Valid field 191 indicates whether the entry is valid (eg, valid entries are indicated by "1" and invalid entries are indicated by "0"). The execution control data field 193 indicates the execution control information of the corresponding functional unit 20 of the received vector instruction. The address field 195 records the address of the register accessed by the vector instruction. The throughput time field 197 records a throughput time value representing the number of clock cycles for the functional unit 20 to accept the vector instruction corresponding to the execution queue entry. In other words, functional unit 20 will be free to accept vector instructions in vector execution queue 19 after the number of clock cycles specified in throughput time field 197 has expired. The throughput time value counts down (ie, decreases by one) for each clock cycle until the throughput time value reaches zero. When the throughput time value reaches 0, the execution queue 19 issues the vector instruction corresponding to the execution queue entry to the functional unit 20 . The micro-op field 198 records the number of micro-ops specified by the vector instruction executing the queue entry. The micro-operation count value is decremented by one for each dispatch of a micro-operation until the micro-operation count value reaches zero. When the micro-operation count value and the throughput time value of the current execution queue entry count down to 0, the current execution queue entry becomes an invalid entry, and subsequent valid execution queue entries can be processed.

The execution queue 19 may include or be coupled to an accumulation counter 199 for storing an accumulation count value acc_cnt that counts down by one for each clock cycle until the counter value becomes zero. A cumulative count of zero indicates that the execution queue 19 is empty. The accumulative count value acc_cnt of the accumulative counter 199 indicates the time in the future (i.e., the number of clock cycles) at which the next instruction in the decode/issue unit 13 can issue to the functional unit 20 or the load/store unit 17 via the execute queue 19 ). In some embodiments, the fetch time of an instruction is the cumulative count value, and the cumulative count value is set according to the sum of the current acc_cnt and the instruction throughput time (inst_xput_time) of the next instruction (acc_cnt = acc_cnt + inst_xput_time). In some other embodiments, the read time may be modified and the accumulative count value acc_cnt is set according to the sum of the instruction's fetch time (rd_cnt) and the instruction's throughput time (acc_cnt = rd_cnt + inst_xput_time) of the next instruction. In some embodiments, the read shifter 161 and the write shifter 163 are designed to be synchronized with the execution queue 19 . For example, the execution queue 19 may issue instructions to the functional unit 20 or the load/store unit 17 while reading the source register from the register set 14 according to the read shifter 161, and from the function The result data of the unit 20 or the load/store unit 17 is written back to the register set 14 according to the write shifter 163 .

For example, two execution queue entries 190(0), 190(1) are active and respectively record a first instruction and a second instruction issued after the first instruction. The first instruction in execution queue entry 190(0) has a throughput time of 5 clock cycles as recorded in throughput time value 197 and a micro-op count of 4 as recorded in mop_cnt field 198 . In an example, for every 5 clock cycles, one uop of the first instruction will be sent to the functional unit 20 until the uop count reaches zero. The overall execution throughput time for the first instruction in the first execution queue entry 190(0) will be 20 clock cycles (ie, 5 clock cycles x 4 uops). Similarly, the overall execution throughput time for the second instruction in the second execution queue entry 190(1) will be 16 clock cycles since there are 8 micro-ops each having an execution throughput time of 2 clock cycles. The cumulative throughput timer 199 will be set to 36 clock cycles, which will be used to dispatch the third instruction to the next available execution queue entry (ie, the third execution queue entry 190(2)).

Referring to FIG. 1 , load/store unit 17 is coupled to decode/issue unit 13 to handle load instructions and store instructions. In an embodiment, the decode/issue unit 13 issues the load/store instruction as two micro-operations (micro operations/micro-ops) including a label micro-operation and a data micro-operation. The execution queue 19D and the execution queue 19E are respectively called the tag execution queue (TEQ) 19D and the data execution queue (data execution queue; DEQ) 19E, wherein the tag micro-operation is sent to the TEQ 19D and the data micro-operation Send to DEQ 19E. In some embodiments, the throughput time of the micro-operation of the load/store instruction is 1 cycle. TEQ 19D and DEQ 19E are independent operations, and TEQ 19D issues tag micro-ops for tag operations before DEQ 19E issues data micro-ops for data operations.

The data cache 18 is coupled to the register set 14 , the memory 30 and the load/store unit 17 , and is configured to temporarily store data retrieved from the memory 30 . The load/store unit 17 accesses the data cache memory 18 for loading data or storing data. Data cache 18 contains a number of cache lines of sequential instruction bytes from memory 30 . The cache lines of data cache 18 are organized as direct mapped, fully associative mapped or set associative mapped similarly to instruction cache 11 , but need not be the same as instruction cache 11 . The data cache memory 18 may include a tag array (TA) 22 and a data array (DA) 24 for storing part of frequently used addresses and data by the microprocessor 10 respectively. Each tag in tag array 22 corresponds to a cache line in data array 24 . When the microprocessor 10 needs to execute a load/store instruction, the microprocessor 10 first checks the load/store data in the data cache by comparing the load/store address with the tags stored in the tag array 22. Whether it exists in body 18. The TEQ 19D issues tag operations to the address generation unit (AGU) 171 of the load/store unit 17 to calculate the load/store address. Load/store addresses are used to access tag array (TA) 22 of data cache 18 . If the load/store address matches one of the tags in the tag array (cache hit), then the corresponding cache line in the data array 24 is accessed for the load/store data. If the load/store address does not match any entry in tag array 22 (cache miss), microprocessor 10 may access memory 30 to find the data. In the case of a cache hit, the execution latency of the load/store instruction is known. In the case of a cache miss, the execution latency of the load/store instruction is unknown. In some embodiments, load/store instructions may be issued based on a known execution latency assuming a cache hit, which may be a predetermined count value (e.g., 2, 3, 6, or any number clock cycles). When a cache miss is encountered, the issuance of a load/store instruction may configure the scoreboard 15 to indicate that the corresponding register has a data dependency with an unknown execution latency.

In the following, the process of issuing instructions with known access times by using the scoreboard 15, the cumulative throughput time of the instructions in the execution queue 19, and the read/write control unit 16 will be explained.

When decode/issue unit 13 receives an instruction from instruction cache 11, decode/issue unit 13 accesses scoreboard 15 to check for any data dependencies before issuing the instruction. Specifically, the unknown field and the count field of the scoreboard entry corresponding to the register are checked for determining whether a previously issued command has a known access time. In some embodiments, the current accumulated count value of the accumulated counter 199 may also be accessed for checking the availability of the functional unit 20 . If a previously dispatched instruction (ie, the first instruction) and a received instruction to be dispatched (ie, the second instruction) access the same register, then the second instruction may have a data dependency. The second instruction will wait to dispatch after the first instruction. In general, data dependencies can be classified into write-after-write (WAW) dependencies, read-after-write (RAW) dependencies, and write-after-read (WAR) dependencies. A WAW dependency refers to a situation where a second instruction must wait for a first instruction to write result data back to the same register before the second instruction can write to the same register. A RAW dependency refers to a situation where a second instruction must wait for a first instruction to write back to the same register before a second instruction can read data from the register. A WAR dependency refers to a situation where a second instruction must wait for a first instruction to read data from the same scratchpad before a second instruction can write to the same scratchpad. Through the scoreboard 15 and execution queue 19 described above, instructions with known access times can be issued and scheduled to a future time to avoid these data dependencies.

In an embodiment that handles RAW data dependencies, if the count value of the count field 1513 is equal to or less than the read time of the command to issue (i.e., rd_cnt), then there is no RAW dependency and the decode/issue unit may issue the instruction. If the count value of the count field 1513 is greater than the sum of the command fetch time and 1 (ie, rd_cnt+1), then there is a RAW data dependency and the decode/issue unit 13 must stop issuing commands. If the count value of the count field 1513 is equal to the sum of the command fetch time and 1 (ie, rd_cnt+1), then the result data may be forwarded from the functional unit recorded in the functional unit field 1515 . In such cases, commands with RAW data dependencies can still be issued. Functional unit field 1515 may be used to forward result data from the recorded functional unit to the functional unit of the command to be issued. In an embodiment that handles WAW data dependencies, if the count value of count field 1513 is greater than or equal to the write time of the command to issue, then there is a WAW data dependency and decode/issue unit 13 must stop issuing commands. In an embodiment that handles WAR data dependencies, if the count value of the count field 1523 (which records the last read time of a previously issued command) is greater than the write time of the command, then there is a WAR data dependency and the decode/launch Unit 13 must stop issuing commands. If the count value of count field 1523 is less than or equal to the write time of the command, then there is no WAR data dependency and decode/issue unit 13 may issue the command.

Based on the count value in the count field of scoreboard 15, decode/issue unit 13 may predict the availability of the register and schedule execution of the instruction to execution queue 19, which may be retrieved from decode/issue unit 13 The order in which instructions are received sends instructions to the functional units 20 in sequence. The execution queue 19 may accumulate the throughput times of all instructions in the execution queue 19 to predict the clock cycles that the execution queue 19 will be available to execute the next instruction. The decode/transmit unit 13 can also enable the read port and write port of the register bank 14 by accessing the read/write control unit 16 to check the availability of the read port and the write port of the register bank 14 before issuing the command. Write port sync. For example, the cumulative throughput time of the first instruction in execution queue 19 indicates that functional unit 20 will take 11 clock cycles by the first instruction. If the write time of the second instruction is 12 clock cycles, then the result data will be written back from the functional unit 20 to the register bank 14 after 23 clock cycles (or the 23rd clock cycle from now). In other words, the decode/issue unit 13 will ensure the availability of the scratchpad and the read port at the 11th clock cycle, and the write port for the writeback operation at the 23rd clock cycle at the issue time of the second instruction. Availability at clock cycles. If the read port or the write port is busy for the corresponding clock cycle, the decode/transmit unit 13 may stop for one clock cycle and check the register and read/write port availability again.

Mask queue 21 handles mask data for vector instructions dispatched to execution queue 19 . FIG. 5 is a diagram illustrating a mask queue 21 according to some embodiments of the present disclosure. The mask queue 21 is logically structured to include a plurality of mask entries 210(0) to 210(M), where M is an integer greater than one. Each mask entry includes a plurality of mask data (eg, 16 bits), wherein each bit of the mask data corresponds to an element of the vector data. The mask bit indicates whether the result data of the element should be written back to the register bank 14 , ie if the mask bit is 1, then the result data of the element should be written back to the register bank 14 . If the mask bit is 0, then result data should not be written back to scratchpad bank 14. In an embodiment, the minimum number of elements in a vector register is 16 (when the elements are 32-bit wide data), so the mask entry is set to have 16 mask bits in an embodiment. The resulting data for each element is indicated by individual mask bits for writing back to register set 14 . For example, mask bits (data) 1111_1111_0000_1111 indicate that elements 5-8 (ie, bits bits 4 to 7 of the mask data) are blocked from being written back to register set 14 . In an embodiment, the maximum number of data elements in a vector register is 64 (when the elements are 8-bit wide data), thus requiring 4 mask entries (each mask entry has 16 mask bits) so that 64 elements can be written back to the scratchpad bank 14 . In an embodiment, the maximum vector length multiplier (LMUL) is 8, in which case the vector instruction can write result data back to the 8 vector registers of register bank 14 . Since each vector register can have 64 data elements where each data element is 8 bits wide, a vector instruction can have a maximum of 512 data elements (i.e., 8 vector registers each with 64 elements), which may hereinafter be referred to as the worst-case vector instruction (or "worst-case scenario"). The mask queue 21 needs to have at least 512 mask bits for the worst case vector instruction, and therefore, the mask queue 21 is structured to have 32 mask entries with 16 bits each mask. That is, in order to perform a mask operation for a single vector instruction, every bit of the mask register is necessary. It should be noted that a 512-bit wide mask register is used here for illustration purposes only. The disclosure can be applied to other mask registers of various sizes without departing from the disclosure. For example, the mask register size can be 32, 64, 128, 1024 or any other number. Furthermore, the mask queue may be logically structured to have a different number of mask entries and/or a different number of bits per mask entry without departing from the scope of the present disclosure. For example, a mask queue with 16 mask entries for 32 bits or 64 mask entries for 8 bits may be used to handle 512-bit mask data. In yet other embodiments, a mask queue with 64 entries of 16 bits or 32 entries of 32 bits may be used to handle 1024-bit mask data. In the above description, the size of the mask queue 21 may depend on the width of the register set 14 . However, the disclosure does not intend to limit the size of the mask queue 21 . In an alternative embodiment, the total number of mask bits in the mask queue 21 may be independent of the width of the register set. For example, mask queue 21 may have 40 entries for 16-bit mask entries totaling 640 mask bits.

Mask operations can be expressed in predictive operands or conditional control operands or conditional vector operation control operands. In an embodiment, masking operations may be enabled based on bit 25 of the vector instruction. In other words, bit 25 of the vector instruction indicates whether the vector instruction is a masked vector instruction or an unmasked vector instruction. Other bits in the vector instructions may be used to enable masking operations, as this disclosure is not intended to be limited. The mask data in mask queue 21 can be used to predict, conditionally control, or mask whether individual results of operations are to be stored as data elements of destination operands and/or whether operations associated with vector instructions are to be stored in source operands Executed on the data element of the meta. Typically, a mask bit will be attached to each data element of a vector instruction. The number of mask data varies based on vector data length (VLEN), data element width (ELEN) and vector length multiplier (LMUL). The vector length multiplier represents the number of vector registers combined to form a vector register group. The value of the vector length multiplier can be 1, 2, 4, 8, etc. The number of data elements can be calculated by dividing the vector data length by the data element width (VLEN/ELEN), and when masking is enabled, each data element will require mask bits. With the vector length multiplier, a single vector instruction can contain various numbers of micro-ops, and each of the micro-ops also requires mask data to perform the mask operation. In the case of a vector length multiplier of 8, ie, LMUL=8, the number of data elements used for a single instruction is increased by 8 times compared to LMUL=1 (ie, (VLEN × LMUL) / ELEN). In the case of 512-bit wide vector data and 8 micro-ops, the number of data elements for a single vector instruction may be as high as 512 (when the data element width is 8 bits (ELEN=8)). In such cases, 512-bit mask data is required, which may be referred to as the worst-case scenario for a 512-bit mask register. On the other hand, a vector instruction with a data element width of 32 bits and 1 micro-op (LMUL=1) will only require 16 bits of mask data, which can be called the best case scenario for mask registers. In a mandatory implementation, each entry of the execution queue will be equipped with 512 bits for the possibility of handling 512 bits of mask data, regardless of whether all 512 bits are required by the vector instructions in the execution queue . If the execution queue had 8 entries, a total of 32,768 bits (8x8x512) would be required to handle the mask in the worst case scenario for each entry in the execution queue. This is excessive storage of masks. In an embodiment, a mask queue is used to process the mask of the vector data for all queue entries in the execution queue, rather than reserving 512 bits in each queue entry for processing the mask.

In an embodiment of the 512-bit wide mask register v(0), the 32 mask entries of the mask queue 21 would have the 32 mask entries for the 32-bit wide data elements when LMUL is 1 The ability to mask data for vector instructions, where only the first 16 bits of the mask register are used for the mask data for the vector register (ie, the best case scenario). When the LMUL is 8, the mask queue 21 has the ability to handle 4 vector instructions with 32-bit wide data elements, where the first 128 bits (512*8/32) of the mask register are used for the vector register The mask data of the register. For 16-bit wide data elements, mask queue 21 has processing for 16 vector instructions when LMUL is 1 (i.e., 32-bit mask data) and 2 vector instructions when LMUL is 8 ( That is, 256-bit mask data) mask data capabilities. For 8-bit wide data elements, mask queue 21 has processing for 8 vector instructions when LMUL is 1 (i.e., 64-bit mask data) and 1 vector instruction when LMUL=8 ( That is, 512 bits of masking data) of the masking data capability.

It should be noted that a 512-bit wide mask register is used to demonstrate the concepts of the present invention, mask registers with different width bits such as 32, 63, 128, 1024 bits may also be suitable for handling mask operations. code data. For example, in an embodiment of a 1024-bit wide mask register, the microprocessor may be equipped with a 1024-bit wide mask queue to handle worst-case scenarios (e.g., VLEN = 1024, ELEN = 8, MLUL=8). Furthermore, the width of the data elements and the number of vector length multipliers (LMULs) may also vary without departing from the scope of the present invention. The same algorithm for mask queues as described in the specification can also be adapted to handle data elements with widths of 64 bits, 128 bits, etc.

In an embodiment, the masked queue 21 is accessible by pointers to the write pointer ("wrptr") 211 and the read pointer ("rdptr") 213 of the circular queue. Write pointer 211 is incremented upon allocation of a vector instruction in the execution queue. The fetch indicator 213 is incremented upon completion of a vector instruction. The mask data can be written to the mask queue 21 as a unit of R bits (for example, R=512 bits) at a time, and from the mask queue 21 as M entries (for example, M=32 entries ) for the queue structure read.

In a write operation to the mask queue 21, when the vector instruction is dispatched to the execution queue 19, the entire width of the mask register v(0) can be written to the mask queue 21 as an entry. That is, 512 bits (ie, the total width of the mask register v(0)) can be written to the mask queue 21 starting from the mask entry specified by the location of the write pointer 211 . Specifically, 32 entries of the mask queue are enabled for writing the 512-bit mask data starting from the write pointer 211 . The relocation of the write pointer 211 may be calculated based on the amount of mask data required for the vector data of the issued vector instruction. For example, the first vector instruction has 2 micro-ops (ie, LMUL=2), and the vector data has a data element width (ELEN) of 16 bits. Vector data will have 64 data elements, which require the first 64 bits of mask register v(0) for mask operations. The relocation of the write pointer 211 will be calculated based on the 64-bit (16 x 4) mask data required for the first vector instruction. Specifically, 4 entries of the mask queue 21 are enabled for writing the 64-bit mask data starting from the write pointer 211 . Write mask queue 21 as a single entry for 512-bit mask data but only enable 4 mask entries for writing 64-bit mask data, while blocking 448 bits (512 bits minus 64 bits ) mask data is written into the mask queue 21. Each mask entry may be assigned a write enable bit (not shown) for indicating whether the corresponding mask entry is enabled for write operations. In an example, the write indicator 211 will be incremented by 4 entries. If the first vector instruction is dispatched to the first queue entry 190(0) of the execution queue 19, then the write operation will start from the first mask entry 210(0) and the write pointer 211 will start from the first mask entry Entry 210(0) increments to the fifth mask entry 210(4). When the second vector instruction is dispatched to the second queue entry 190(1), the entire width of the mask register v(0) will be used to write to the mask queue 21 as one entry. The write operation to the mask queue 21 for the mask data of the second vector instruction will start from the new location of the write pointer (ie, the 5th mask entry 210(4)). If the second vector instruction is the worst case scenario requiring the entire width of mask queue 21 (e.g., 512 bits when VLEN = 512, ELEN = 8 bits, and LMUL = 8), then the issue of the second vector instruction Will stall in the decode/issue unit until (micro-ops of) the first vector instruction has all issued to the functional unit 20. In another scenario, if the first vector instruction is the worst case scenario requiring the entire width of the mask queue 21 for the mask operation, then the issue of the second vector instruction following the first vector instruction will stall until The first vector instruction is issued to functional unit 20 . However, in an alternate embodiment of the mask queue 21 that does not depend on the width of the mask register, the size of the mask queue 21 can handle the worst-case scenario of anything but a 512-bit wide vector register. More mask bits than the 512 bit mask data. In such embodiments, the second instruction can still issue after the first vector instruction with the worst-case scenario, as long as the number of available mask entries in mask queue 21 is sufficient to handle the mask corresponding to the second vector instruction. code data. In any case, the vector instruction may stall in decode/issue unit 13 until the number of available mask entries in mask queue 21 is sufficient to hold new mask data for the vector instruction.

The read operation of the mask queue 21 starts with the mask entry pointed to by the read pointer 213 and is incremented when the corresponding vector instruction in the execute queue 19 is issued to the functional unit 20 . A vector instruction may have as many uops as indicated by uop count field 198 , which is decremented by one each time a uop is issued to a functional unit 20 . When all micro-ops of the vector instruction are issued to the functional unit 20, the count value in the micro-op count field 198 is decremented to 0, the valid bit field 191 of the entry in the execution queue 19 is cleared to 0, and The read pointer for mask queue 21 will be incremented. The read pointer 213 points to one of the mask entries corresponding to the first micro-operation of the vector instruction (referred to as the current read mask entry). A read operation may read X consecutive mask entries starting from the current read mask entry, where X is an integer greater than zero. The current read mask entry can be shifted by the order of the micro-operations to read the corresponding mask data stored in the mask queue 21 . For 8-bit elements, the number of mask bits required for each vector uop is 64 bits of mask data (ie, 4 mask entries of mask queue 21). For 16-bit elements, the number of mask bits required per vector uop is 32 bits of mask data (ie, 2 mask entries of mask queue 21). For 32-bit elements, the number of mask bits required per vector uop is 16 bits of mask data (ie, 1 mask entry of mask queue 21). The number of mask entries for each micro-op is referred to herein as the micro-op mask size, namely 4 mask entries for 8-bit elements, 2 mask entries for 16-bit elements, and 1 mask entry for 32-bit elements. In an embodiment, four mask entries are read at a time (i.e., X=4), rather than calculating the number of mask entries read for different element lengths (8-bit, 16-bit, and 32-bit elements) exact number. In the case of 8-bit wide data elements, all 4 entries are used for each micro-operation. In the case of 16-bit wide data elements, the first 2 entries are used for each micro-op. In the case of 32-bit wide data elements, the first entry is used for each micro-op. Accordingly, the read operation of the mask queue 21 is configured to read at least 64 bits, i.e., four 16-bit wide tag entries, for each micro-operation that handles mask data that can be of various widths due to the data element width .

As described above, the current read mask entry may be shifted through the order of micro-operations. If the vector instruction has three micro-ops, then the first micro-op will read 4 consecutive mask entries starting from the mask entry pointed to by read pointer 213 . The second micro-op will read 4 consecutive mask entries starting from the modified read pointer. In an embodiment, the read pointer is modified by adding the micro-op mask size (which depends on the width of the data element) to the read pointer 213 . The third micro-op will read 4 consecutive mask entries starting from the modified read pointer 213 by adding 2 micro-op mask sizes to the read pointer 213 . In the case of a 32-bit wide data element with a micro-op mask size of one mask entry (i.e., 16 mask bits), read pointer 213 points to mask entry 210(0) as the current read mask entry. The first micro-operation reads four consecutive mask entries starting from mask entry 210(0), mask entry 210(0) to mask entry 210(3). The second micro-op reads mask entry 210(1) starting from mask entry 210(1) to mask entry 210(4), where the mask entry pointed to by read pointer 213 is passed by 1 micro-op The mask size is added to the location of the read pointer 213 to modify. The third micro-operation reads mask entry 210(2) starting from mask entry 210(2) to mask entry 210(5), wherein the mask entry pointed to by the read pointer 213 is obtained by combining 2 micro-ops The mask size is added to read the location of pointer 213 to modify, etc. The number of micro-op mask sizes to add depends on the order of the micro-ops. In an embodiment, 64-bit mask data can be read from the mask queue 21 . However, the mask data required for the micro-operations of the vector instructions may vary based on the width of the data elements. In the case of 16-bit wide data elements, each micro-operation of 512-bit wide vector data length requires only 32 bits of mask data, and each mask data read operation will increment 2 mask entries. The micro-op will use the first 32 bits of the 64-bit read mask data (i.e., read mask data[31:0]) and ignore the last 32 bits of the 64-bit read mask data (i.e., read Take Mask Profile [63:32]). It should be noted that a read operation of four consecutive mask entries is not intended to limit the present disclosure. A read operation of mask queue 21 may involve various numbers of mask entries, such as 1, 2, 4, 8, 16, etc., that may be implemented without departing from the scope of the present disclosure. In an alternate embodiment of 1024-bit wide vector data, execute queue 19 may be configured to read eight consecutive tag entries (ie, 128-bit mask data).

6A-6C are diagrams illustrating operations of dispatching vector instructions to execute queue 19 and mask queue 21 according to some embodiments of the present disclosure. Referring to FIG. 6A, a first vector instruction containing 4 micro-ops is received to operate on 512-bit wide vector data with 16-bit wide data elements. The decode/transmit unit 13 checks whether the mask operation is enabled and accesses the scoreboard to check the availability of the corresponding register and the mask register v0. In an embodiment, the mask register v(0) can be directly wired to the decode/transmit unit 13 with a dedicated read port. If mask register v(0) has an outstanding write operation, then the scoreboard entry 150(0) will display the busy information that mask register v(0) could not be read. The busy information in the scoreboard entry 150(0) can be set by setting the unknown field 1511 (or 1521), the count field 1513 (or 1523), or the indication mask register v in the scoreboard entry 150(0) (0) busy extra field to implement.

As an example, the first vector instruction is dispatched and assigned to the first queue entry 190(0) of the execution queue 19, and the mask data corresponding to the first vector instruction will be assigned to the mask queue based on the write pointer 211 The first plurality of mask entries 210(0) through mask entries 210(7) of 21. Mask data is allocated to the mask queue 21 based on the location of the write pointer 211, rather than from the mask register in the first queue entry 190(0) that is part of the first vector instruction in the queue v(0) allocates 512-bit wide mask data. Mask data may be sent directly from mask register v(0) to mask queue 21 via the bus or via decode/transmit unit 13 as part of issuing the first vector instruction. This disclosure is not intended to be limited to mask data transmission path. In an embodiment, the first vector instruction will have 128-bit wide mask data (32×4) due to 16-bit wide data elements and 4 micro-ops, which requires 8 mask entries. After the first vector instruction is allocated, the write pointer 211 is incremented by 8 to indicate the next mask entry for the next vector instruction. In an embodiment, the write enable bits for the first 8 mask entries are set starting at write pointer 211 to allow 128 bits of mask data to be written to mask queue 21 .

Referring to FIG. 6B , the second vector instruction comprising 2 micro-ops is received after the first vector instruction is assigned to the execution queue 19 . The second vector instruction is configured to operate on 512-bit wide vector data having 32-bit wide data elements. Based on the structure of the second vector instruction (ie, ELEN=32, LMUL=2), 32 bits of mask data would be required to perform a mask operation on the second vector instruction, which requires 2 mask entries to store. The 32-bit wide mask data corresponding to the second vector instruction is written to the mask queue 21 starting with the current write mask entry indicated by the current position of the write pointer 211, which Will be mask entry 210(8). As shown in FIG. 6B, mask data ("m-op 2-1") corresponding to the first micro-operation of the second vector instruction is written to mask queue 210(8), and corresponding to the second The mask data for the second micro-op of the vector instruction ("m-op 2-2") is written to mask queue 210(9). After the second vector instruction is allocated, write pointer 211 is incremented by 2 to indicate the next mask entry for the next vector instruction. In an embodiment, write pointer 211 will be relocated to mask queue 210(10) to indicate the next available mask entry for storing the mask data for the vector instruction following the second vector instruction.

Referring to FIG. 6C, the operation of dispatching the first vector instruction in the first queue entry 190(0) is shown. As described above, each micro-operation of the first vector instruction operates on vector data having thirty-two 16-bit wide data elements. Therefore, 32 bits of mask data will be allocated to each micro-op of the first vector instruction. The micro-op mask size is 2 mask entries for each micro-op, where the read pointer 213 is modified to 0, 2, 4, 6 to read the mask data for each micro-op instruction, and each micro-op The read operation of the operation will read 4 consecutive mask entries starting from the modified read pointer 213 . In an embodiment, execution queue 19 accesses mask queue 21 to obtain mask data for the first vector instruction in queue entry 190(0). The first uop of the first vector instruction will be issued to the functional unit 20 together with the mask data stored in the four mask entries 210 ( 0 ) to 210 ( 3 ) of the mask queue 21 . Since vector data is a 16-bit wide data element, functional unit 20 may only use the first 32-bit mask data (e.g., bits[31:0]) and ignore the second 32-bit mask data ( For example, bits[63:32]). For the second micro-operation, the current read mask entry will be shifted by the size of the micro-operation mask. In other words, the second uop of the first vector instruction will read 4 consecutive mask entries 210 ( 2 ) to mask entry 210 ( 5 ) to issue to functional unit 20 . Functional unit 20 may only use the 32-bit mask data stored in two mask entries 210(2) through 210(3) of mask queue 21 and ignore The other 32 bits of the mask entry 210(5). The third uop of the first vector instruction will be issued to the functional unit 20 along with the mask data stored in the four mask entries 210(4) to 210(7) of the mask queue 21 to the functional unit 20. Read pointer 213 modifies two micro-op mask sizes. The fourth uop of the first vector instruction will be issued to functional unit 20 along with the mask data stored in four mask entries 210(6) to 210(9) of mask queue 21 to functional unit 20. Read pointer 213 modifies 3 micro-op mask sizes. When the first vector instruction is fully issued to the functional unit 20, the read pointer 213 is incremented by four micro-op mask sizes, that is, in the case of 16-bit wide data elements, the aforementioned four micro-op mask will be 8 mask entries.

In the case of issuing the second vector instruction to functional unit 20, the micro-op mask size is 1 mask entry due to the 32-bit wide data elements. The first uop of the second vector instruction will issue to functional unit 20 along with the mask data stored in mask entry 210(8) through mask entry 210(11). Since the vector data is a 32-bit wide data element, the functional unit 20 can only use the first 16-bit mask data and ignore the other 48-bit mask data. The second uop of the second vector instruction will be issued to functional unit 20 together with the mask data stored in mask entry 210(9) through mask entry 210(12).

In some embodiments, double-width vector instructions may be dispatched to execution queue 19 . In operations on double-width vector instructions, the result data of the vector operation will be twice the width of the source data. In detail, the first half of the source data (i.e., half the register width) is used to generate the first result data with the full register width, and the second half of the source data is used to generate the first result data with the full register width. 2. Results data. The source scratchpad is read twice when executing each micro-operation of the double-width vector instruction. In an embodiment, mask data is used for result data width and not for source data width. As an example, for a double width instruction, the element data width is 16 bits and the result data width is 32 bits. For example, with LMUL=4, a "single-width" vector instruction with 16-bit elements would have 4 micro-ops and write back to the 4 vector registers of register bank 14, and each Micro-op instructions have 32-bit mask data. A "double wide" vector instruction of 16-bit elements would have 8 micro-ops and write back to the 8 vector registers of register bank 14, with each micro-op having 16-bit mask data. Referring back to FIG. 6C , the first vector instructions are "single-width" vector instructions that have mask 4 micro-operations for encoding data. In the case of "double-width" vector instructions, the double-width vector instruction is logically seen as 8 double-width uops using a single mask entry for each double-width uop, rather than each having 4 micro-ops for 2 mask entries. For example, the mask data in the eight mask entries 210(0) through mask entry 210(7) corresponding to the double-width first vector instruction in the first queue entry 190(0) logically Treated as "m-op 1-0", "m-op 1-1", "m-op 1-2", "m-op 1-3", "m-op 1-4", "m -op 1-4", "m-op 1-5", "m-op 1-6", and "m-op 1-7". In some other embodiments, read operation mask data from mask queue 21 may be delayed by 1 clock cycle because the source operand data elements must be shifted into the correct location for the operation.

In some other embodiments, if the second vector instruction uses the same masked vector register v(0), the same LMUL, and the same ELEN, then the second vector instruction can use the mask queue 21 as the first vector instruction A collection of identically masked entries. Embodiments are not intended to exclude other sizes of LMUL and ELEN, as long as the mask bits can be derived from the same mask entry based on v(0). There is no need to write the same mask data into the mask queue 21 . Same-mask vector register v(0) means that vector register v(0) is not written by any instruction between the first vector instruction and the second vector instruction. A scoreboard bit can be used to indicate the state of the mask vector scratchpad v(0). The LMUL and ELEN values are stored with the read pointer 213 to verify the same LMUL and ELEN for the next vector instruction. The read pointer 213 is used as an identifier for the set of mask entries for the vector instruction. Mask queue 21 may include a vector instruction counter (not shown) to track the number of vector instructions using the same set of mask entries, so that fetch pointer 213 will only be relocated when the vector instruction counter reaches zero. Since each vector instruction uses the same set of mask entries, the vector instruction counter is incremented by one when a vector instruction is dispatched to the execution queue. When all uops of the vector instructions are issued from the execution queue 19 to the functional unit 20, then the vector instruction counter in the mask queue entry is decremented. When the vector instruction counter is zero, then the read pointer 213 is incremented to the number of micro-ops, each micro-op has the size of the micro-op mask. Since the same mask data is not repeatedly written into the mask queue 21, reusing the mask entries in the mask queue 21 (ie, the above description) is a more efficient use of mask data and power consumption .

In the above, mask data is shared by multiple vector instructions in the same execution queue. However, sharing of mask data is not limited to vector instructions in the same queue. In some other embodiments, the mask data of a mask queue can be shared by multiple vector instructions in different execution queues. For example, a first vector instruction may be dispatched to execution queue 19B, with first mask data dispatched to mask queue 21B. If the second vector instruction is dispatched to execution queue 19C and uses the same mask data as the first vector instruction in execution queue 19B (i.e., same masked vector register v(0), same LMUL, and same ELEN) , then the second vector instruction can also share the mask data in the mask queue 21B. A vector instruction counter as described above may also be used to count down the first vector instruction and the second vector instruction. In yet other embodiments, even if the first vector instruction and the second vector instruction do not use the same mask data, a mask queue can be shared between execution queues.

According to the above embodiments, mask data may be handled by the mask queue presented above, rather than reserving 512 bits (or whatever width the mask register is) in each entry of the execute queue. In the present disclosure, mask data for multiple vector instructions can be stored in a mask queue. When a vector instruction is issued from the execution queue to a functional unit for execution, corresponding mask data can be accessed from the mask queue. The decode/issue unit may stop dispatching vector instructions to the execution queue until the mask queue has enough mask entries to write the mask data. In an embodiment, one mask queue may be dedicated to one execution queue. In some other embodiments, mask queue 21 may be shared by more than one execution queue. The same vector mask with the same LMUL and ELEN can be used for multiple vector instructions in different functional units, in which case the mask queue is shared among multiple execution queues to save more area. Embodiments do not limit the sharing of mask queues by multiple execution queues because mask queue entries are shared by vector instructions in different execution queues. In fact, mask queues can be shared even if vector instructions in different execution queues do not share any mask queue entries. Mask queue entries are labeled LMUL and ELEN, and if the second vector instruction uses the same mask vector register, LMUL, and ELEN, then the set of mask queue entries (eg, 210(0) to 210( 7)) for the second vector instruction, otherwise create a new set of mask queue entries if the mask queue has enough entries. The set of mask queue entries includes counters to track the number of vector instructions in the execution queue that use this set of mask queues. The execution queue must track the read pointer 213 of the mask queue 21 to access the mask data for each micro-operation issued to the functional unit 20 . When all micro-ops of the vector instruction are issued from the execution queue 19 to the functional unit 20, then the count of the vector instruction in the mask queue is decremented by one. When the vector instruction count in mask queue 21 is zero, then the set of mask entries is available to accept a new set of mask data from the vector instruction issued from decode/issue unit 13 . In all cases, resources are reserved without additional storage dedicated to handling mask data for vector instructions.

According to one of the embodiments, the microprocessor includes a decode/transmit unit and an execution queue. Execution queues consist of multiple queue entries and mask queues. In an embodiment, the execution queue is configured to assign to the first queue entry a first instruction issued from the decode/issue unit and operating on data having a first plurality of data elements. The mask queue includes a plurality of mask entries, and when the first instruction is assigned to the first queue entry in the execution queue, first mask data corresponding to the first instruction is written to the first number of masks entries, wherein the first number is determined based on the width of the first data element.

According to one of the embodiments, a method of handling masked data of vector instructions comprises at least the steps of: dispatching a first instruction operating on data having a plurality of first data elements to an execution queue comprising a masked queue the step of assigning a first instruction to a first queue entry in the execution queue, and writing first mask data corresponding to the first instruction to a first number of mask entries in the mask queue The step of , wherein the first number is determined based on the width of the first data element.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the following detailed description. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. .

1: Data processing system 10: Microprocessor 11: Instruction cache memory 12: Branch prediction unit 13: decoding/transmitting unit 14: Register group 15: Scoreboard 16: Read/write control unit 17: Load/store unit 18:Data cache memory 19, 19A, 19B, 19C, 19D, 19E: execution queue 20, 20A, 20B, 20C: functional units 21,21A,21B,21C,21E: mask queue 22: label array 24: data array 30: Memory 31: Read the bus 32: Result bus 150(0) to 150(N), 1510(0) to 1510(N), 1520(0) to 1520(N): Scoreboard entries 151: The first scoreboard 152: Second scoreboard 161: Read shifter 163: write shifter 171: Address generation unit 190(0) to 190(Q): Execute queue entries 191: Valid fields 193:Execution Control Data Field 195:Address field 197: Throughput time field 198:Micro operation count field 199: cumulative counter 210(0) to 210(M): mask queue entries 211: Write indicator 213:Read indicators 1511,1521: Unknown field 1513: Write count field 1515: Functional unit field 1523: Read count field v(0) to v(N): vector scratchpad entries

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a block diagram illustrating a data processing system according to some embodiments. Figure 2 is a diagram illustrating a scoreboard and register bank according to some embodiments of the present disclosure. 3A-3B are diagrams illustrating various structures of scoreboard entries according to some embodiments of the present disclosure. FIG. 4 is a diagram illustrating a vector execution queue according to some embodiments of the disclosure. FIG. 5 is a diagram illustrating a mask queue according to some embodiments of the present disclosure. 6A-6C are diagrams illustrating operations of dispatching vector instructions to execute queues and mask queues according to some embodiments of the present disclosure.

21: Mask queue

210(0) to 210(M): mask queue entries

211: Write indicator

213:Read indicators

Claims (20)

A microprocessor comprising: decoding/transmitting unit; and an execution queue comprising a plurality of queue entries and a mask queue, and assigning to the first queue entry a first instruction dispatched from the decode/issue unit, wherein the first instruction has a plurality of first data elements operate on the data, Wherein the mask queue includes a plurality of mask entries, and when the first instruction is dispatched to the first queue entry in the execution queue, the first mask corresponding to the first instruction will be Data is written to a first number of mask entries, wherein the first number is determined based on a width of the first data element. The microprocessor of claim 1, wherein the execution queue further assigns a second instruction dispatched from the decode/issue unit to a second queue entry following the first queue entry, wherein A second instruction operates on data having a plurality of second data elements, and the mask queue writes second mask data corresponding to the second instruction to a second number of mask entries, wherein The second number is determined based on the width of the second data element. The microprocessor of claim 2, wherein the decode/transmit unit is configured to store the mask data for the second instruction in the event that the mask queue does not have sufficient space Stop dispatching the second instruction. The microprocessor of claim 1, wherein the first number of mask entries used to store the first mask data is further determined based on a vector length multiplier of the first instruction. The microprocessor of claim 1, wherein said first number of said mask entries starts from a first write mask entry indicated by a write pointer, and said write pointer is at said first instructions assigned to said first queue entry of said execution queue are relocated by said first number of said mask entries, and second mask data corresponding to a second instruction is at said write pointer The relocation of is followed by writing to the second writemask entry indicated by the write pointer. The microprocessor according to claim 1, wherein the execution queue is further configured to access the first number of the mask entries with The first instruction of the first mask data is issued to a functional unit, and the execution queue reads X number of mask entries per micro-op starting from the current read mask entry, wherein the X is an integer equal to or greater than 1, wherein the read pointer is repositioned upon completion of issuing the first instruction to the functional unit based on the width of the data element and a vector length multiplier corresponding to the first instruction. The microprocessor of claim 6, wherein, for each micro-operation of the first instruction, the current read mask entry shifts the micro-operation mask based on the order of the micro-operations of the first instruction A factor of size, and the micro-op mask size is determined based on the width of the data element corresponding to the first instruction. The microprocessor of claim 7, wherein the first instruction is a double-width instruction, and the micro-op mask size is modified based on the number of double-width micro-ops modified and the mask is read The timing of the data is delayed while shifting the current read mask. The microprocessor of claim 1, wherein the execution queue further assigns a second instruction dispatched from the decode/issue unit and operating on data having a second plurality of data elements to the a second queue entry following a queue entry, and wherein the second instruction is determined to use the same mask entry as the first instruction in the first queue entry, and the first instruction and the second instruction is issued to the same functional unit. In the microprocessor according to claim 9, the mask queue further includes a vector instruction counter configured to count the first instruction and the second instruction, and in the first instruction Or the second command is decremented by one when it is issued to the corresponding functional unit, and the read pointer of the mask queue is reset when the command counter reaches 0. The microprocessor as claimed in claim 1, wherein the execution queues include a first execution queue corresponding to a first functional unit and a second execution queue corresponding to a second functional unit, the decode/transmit unit Further configured to dispatch a second instruction operating on data having a second plurality of data elements to a first queue entry of the second execution queue, a second masked data write corresponding to the second instruction into a second number of mask entries of the mask queue shared with the first instruction in the first entry of the execution queue, wherein the first instruction and the second instruction are respectively Issued to the first functional unit and the second functional unit through the first execution queue and the second execution queue. The microprocessor of claim 11, wherein said first number of said mask entries corresponding to said first instruction, and said second number of said mask entries corresponding to said second instruction A code entry maps to the same mask entry in the mask queue. A method of handling mask data for vector instructions, comprising: dispatching a first instruction operating on data having a plurality of first data elements to an execution queue comprising a mask queue; allocating the first instruction to a first queue entry in the execution queue; and writing first mask data corresponding to the first command to a first number of mask entries in the mask queue, wherein the first number is determined based on a width of the first data element . The method as described in claim item 13, said method further comprising: assigning a second instruction operating on data having a second plurality of data elements to a second queue entry in the execution queue subsequent to the first queue entry; and Writing second mask data corresponding to the second instruction to a second number of mask entries, wherein the second number is determined based on a width of the second data element. The method of claim 14, wherein the first number is further determined based on a first vector length multiplier of the first instruction, and the second number is further based on a second vector length of the second instruction judged by the multiplier. The method as described in claim item 14, said method further comprising: writing the first mask data based on a write index; After the first instruction is allocated to the first queue entry, relocating the write based on the width of the first data element of the first instruction and a vector length multiple of the first instruction input indicators; and Writing the second mask material corresponding to the second instruction starts from a current write mask entry among the mask entries as indicated by the relocated write pointer, wherein the current A mask entry is written immediately after the portion of the mask entry storing said first number of said first masking material. The method as described in claim item 13, said method further comprising: dispatching a second instruction to the execution queue; issuing the first instruction to a first functional unit with the first mask data read from the first number of mask entries; and The second instruction is issued to a first functional unit with the first mask material read from the first number of mask entries. The method as described in claim item 17, said method further comprising: incrementing an instruction count by one when each of the first instruction and the second instruction is dispatched; and decrementing the instruction count by one when each of the first instruction and the second instruction is issued; and When micro-op count reaches 0, relocating by said first number of said first mask data determined based on a multiple of said width and vector length of said first data element of said first instruction Read metrics. The method according to claim 13, wherein the execution queue includes a first execution queue corresponding to the first functional unit and a second execution queue corresponding to the second functional unit, the method further comprising: dispatching the first instruction and the second instruction to the first execution queue and the second execution queue respectively, and assigning the first mask data and the second mask data corresponding to the second instruction code data is written to the same masked queue shared between said first execution queue and said second execution queue; and Issue the first instruction and the second instruction from the first execution queue and the second execution queue to the first functional unit and the second functional unit. The method as described in claim item 13, said method further comprising: reading X number of consecutive mask entries to obtain said first mask material starting from a current read mask entry indicating a read indicator until a micro-operation count reaches 0, wherein said X is equal to or greater than 1; The read pointer is shifted by a factor of a micro-op mask size based on the order of the micro-ops of the first instruction and the width of the data element, wherein the micro-op mask size is based on the determined by the width of the data element of a command; and When the uop count reaches zero, the read pointer is repositioned based on a multiple of the width of the data element of the first instruction and a vector length.

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