以下實施例將伴隨著圖式說明本發明之概念，在圖式或說明中，相似或相同之部分係使用相同之標號，並且在圖式中，元件之形狀、厚度或高度在合理範圍內可擴大或縮小。本發明所列舉之各實施例僅用以說明本發明，並非用以限制本發明之範圍。對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。The following embodiments will illustrate the concept of the present invention along with the drawings. In the drawings or descriptions, similar or identical parts use the same symbols, and in the drawings, the shape, thickness or height of the elements can be changed within a reasonable range. Expand or shrink. The various embodiments listed in the present invention are only used to illustrate the present invention, and are not intended to limit the scope of the present invention. Any obvious modifications or changes made to the present invention do not depart from the spirit and scope of the present invention.
第1A圖為根據本發明一實施例中的一半導體元件陣列1000之上視示意圖。半導體元件陣列1000包含複數個半導體元件1以陣列的方式排列於基板上。半導體元件1可以為發光二極體（Light-Emitting Diode；LED）、雷射二極體（Laser Diode；LD）、或電晶體（Transistor）…等半導體元件。半導體元件陣列1000可以由單一種類或不同種類之半導體元件1所組成。基板10可以為半導體元件1的成長基板，或是移除成長基板後做為半導體元件1的載體。基板10的材料包含但不限於鍺（Ge）、砷化鎵（GaAs）、銦化磷（InP）、藍寶石（Sapphire）、碳化矽（SiC）、矽（Si）、鋁酸鋰（LiAlO
2）、氧化鋅（ZnO）、氮化鎵（GaN）、氮化鋁（AlN）、金屬、玻璃、熱移除膠帶（Thermal Release Tape）、光解膠膜（UV release tape）、化學移除膠帶（Chemical Release Tape）、耐熱膠帶、藍膜（Blue Tape）、或是具有動力釋放層（Dynamic Release Layer；DRL）的膠帶。每一個半導體元件1遠離基板10的一側具有一對導電凸塊2a、2b，用以作為與外部電路（例如：電路板、背板等）的電性與物理連接。於上視圖，導電凸塊的投影形狀大致為矩形，如第1A圖與第3A圖所示。
FIG. 1A is a schematic top view of a semiconductor device array 1000 according to an embodiment of the present invention. The semiconductor device array 1000 includes a plurality of semiconductor devices 1 arranged in an array on a substrate. The semiconductor element 1 may be a light-emitting diode (Light-Emitting Diode; LED), a laser diode (Laser Diode; LD), or a transistor (Transistor) . . . and other semiconductor elements. The semiconductor device array 1000 can be composed of a single type or different types of semiconductor devices 1 . The substrate 10 may be a growth substrate of the semiconductor device 1 , or be used as a carrier of the semiconductor device 1 after the growth substrate is removed. The material of the substrate 10 includes but not limited to germanium (Ge), gallium arsenide (GaAs), indium phosphorus (InP), sapphire (Sapphire), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO 2 ) , zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), metal, glass, thermal release tape (Thermal Release Tape), photolytic film (UV release tape), chemical removal tape ( Chemical Release Tape), heat-resistant tape, blue film (Blue Tape), or tape with a dynamic release layer (Dynamic Release Layer; DRL). Each semiconductor element 1 has a pair of conductive bumps 2a, 2b on the side away from the substrate 10 for electrical and physical connection with external circuits (eg circuit board, backplane, etc.). In the top view, the projected shape of the conductive bump is roughly rectangular, as shown in FIG. 1A and FIG. 3A .
第1B圖為第1A圖 A-A´線段的剖面示意圖。半導體元件1遠離基板10的一側上具有一對電極3a、3b。導電凸塊2a、2b分別直接設置在電極3a、3b上。導電凸塊2a、2b的上表面為圓弧形，且不平行於電極3a、3b的上表面。Figure 1B is a schematic cross-sectional view of the line segment A-A' in Figure 1A. The semiconductor element 1 has a pair of electrodes 3a, 3b on a side remote from the substrate 10 . The conductive bumps 2a, 2b are directly arranged on the electrodes 3a, 3b, respectively. The upper surfaces of the conductive bumps 2a, 2b are arc-shaped and not parallel to the upper surfaces of the electrodes 3a, 3b.
導電凸塊2a、2b與電極3a、3b以選用不同的材料尤佳。電極的材料包括金屬，例如：金（Au）、銀（Ag）、銅（Cu）、鉻（Cr）、鋁（Al）、鉑（Pt）、鎳（Ni）、鈦（Ti）、或其合金、或其疊層組合。導電凸塊2a、2b的材料可以包含低熔點的金屬或低液化熔點（Liquidus Melting Point）的合金，其熔點或液化溫度低於210℃，例如：鉍（Bi）、錫（Sn）、銦（In）、或其合金。在一實施例中，低熔點的金屬的熔點或低液化熔點合金液化溫度低於170℃。低液化熔點合金的材料可以是錫銦合金或錫鉍合金。It is particularly preferable that the conductive bumps 2a, 2b and the electrodes 3a, 3b are made of different materials. Electrode materials include metals such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), or alloys, or their stacked combinations. The material of the conductive bumps 2a, 2b may include metals with low melting points or alloys with low liquidus melting points (Liquidus Melting Point), whose melting point or liquefaction temperature is lower than 210°C, for example: bismuth (Bi), tin (Sn), indium ( In), or its alloys. In one embodiment, the melting point of the low melting point metal or the liquefaction temperature of the low melting point alloy is lower than 170°C. The material of the low melting point alloy may be tin-indium alloy or tin-bismuth alloy.
第1C圖為根據本發明另一實施例中的一半導體元件陣列1001之上視示意圖。半導體元件陣列1001包含複數個半導體元件1以預定的圖案排列於基板10上。基板10具有大致上圓形的外型。基板的材料可以參考前述相關段落。第1D圖為第1C圖 A-A´線段的剖面示意圖。半導體元件1與基板10之間具有一黏著結構4。半導體元件1透過黏著結構4暫時固定於基板10上。半導體元件1遠離基板10的一側上具有一對電極3a、3b。導電凸塊2a、2b分別直接設置在電極3a、3b上。導電凸塊2a、2b的上表面為圓弧形，且不完全平行於電極3a、3b的上表面。黏著結構4可以包含聚合物，例如，聚醯亞胺（Polyimide）或苯并環丁烷（Benzocyclobutane； BCB）。導電凸塊2a、2b與電極3a、3b的材料可以參考前述相關段落。如第1D圖所示，黏著結構4的外側邊42大體上與半導體元件1的最外側邊19齊平。黏著部4具有一厚度H4，大約2～3μm或1～10μm。在另一實施例中，外側邊42不與半導體元件1的最外側邊19齊平，黏著結構4可以相對於半導體元件1的最外側邊19內縮或外凸。黏著結構4具有一最大寬度W5，半導體元件1具有一最大寬度 W6。W5大體上與W6相等。在另一實施例中，W5可以小於或是大於W6。FIG. 1C is a schematic top view of a semiconductor device array 1001 according to another embodiment of the present invention. The semiconductor device array 1001 includes a plurality of semiconductor devices 1 arranged in a predetermined pattern on the substrate 10 . The substrate 10 has a substantially circular shape. For the material of the substrate, reference may be made to the aforementioned relevant paragraphs. Figure 1D is a schematic cross-sectional view of the line segment A-A' in Figure 1C. There is an adhesive structure 4 between the semiconductor element 1 and the substrate 10 . The semiconductor element 1 is temporarily fixed on the substrate 10 through the adhesive structure 4 . The semiconductor element 1 has a pair of electrodes 3a, 3b on a side remote from the substrate 10 . The conductive bumps 2a, 2b are directly arranged on the electrodes 3a, 3b, respectively. The upper surfaces of the conductive bumps 2a, 2b are arc-shaped and not completely parallel to the upper surfaces of the electrodes 3a, 3b. The adhesive structure 4 may include a polymer, for example, polyimide (Polyimide) or benzocyclobutane (Benzocyclobutane; BCB). For the materials of the conductive bumps 2a, 2b and the electrodes 3a, 3b, reference may be made to the aforementioned relevant paragraphs. As shown in FIG. 1D , the outer side 42 of the adhesive structure 4 is substantially flush with the outermost side 19 of the semiconductor device 1 . The adhesive part 4 has a thickness H4 of about 2-3 μm or 1-10 μm. In another embodiment, the outer side 42 is not flush with the outermost side 19 of the semiconductor device 1 , and the adhesive structure 4 may shrink or protrude relative to the outermost side 19 of the semiconductor device 1 . The adhesive structure 4 has a maximum width W5, and the semiconductor device 1 has a maximum width W6. W5 is substantially equal to W6. In another embodiment, W5 may be smaller or larger than W6.
第1E圖為根據本發明另一實施例中的一半導體元件陣列1001´之剖面示意圖。半導體元件陣列1001´包含複數個半導體元件1以預定的圖案排列於基板10上。基板的材料可以參考前述相關段落。半導體元件1與基板10之間具有一黏著結構4。半導體元件1透過黏著結構4暫時固定於基板10上。半導體元件1遠離基板10的一側上具有一對電極3a、3b。導電凸塊2a、2b分別直接設置在電極3a、3b上。黏著結構4的材料、導電凸塊2a、2b與電極3a、3b的結構以及材料可以參考前述相關段落。如第1E圖所示，黏著結構4具有高台部43以及連續部44。連續部44為一個不間斷的結構，並在基板10上連續分佈以穿越所有半導體元件1的下方以及兩相鄰半導體元件1間的區域。每一個高台部43位於半導體元件1與連續部44之間，並自連續部44向上突起並對應單一個半導體元件1。高台部43的外側邊42與半導體元件1的最外側邊19齊平或靠近。黏著部4具有一厚度H4，大約2～3μm。連續部44具有一厚度H5，大於0μm小於1μm。在另一實施例中，外側邊42不與半導體元件1的最外側邊19齊平，高台部43可以相對於半導體元件1的最外側邊19內縮或外凸。高台部43具有一最大寬度W5，半導體元件1具有一最大寬度 W6。W5大體上與W6相等。在另一實施例中，W5可以小於或是大於W6。FIG. 1E is a schematic cross-sectional view of a semiconductor device array 1001′ according to another embodiment of the present invention. The semiconductor device array 1001′ includes a plurality of semiconductor devices 1 arranged in a predetermined pattern on the substrate 10 . For the material of the substrate, reference may be made to the aforementioned relevant paragraphs. There is an adhesive structure 4 between the semiconductor device 1 and the substrate 10 . The semiconductor element 1 is temporarily fixed on the substrate 10 through the adhesive structure 4 . The semiconductor element 1 has a pair of electrodes 3a, 3b on a side remote from the substrate 10 . The conductive bumps 2a, 2b are directly arranged on the electrodes 3a, 3b, respectively. For the materials of the adhesive structure 4 , the structures and materials of the conductive bumps 2 a , 2 b and the electrodes 3 a , 3 b , reference may be made to the relevant paragraphs above. As shown in FIG. 1E , the adhesive structure 4 has a raised portion 43 and a continuous portion 44 . The continuous portion 44 is an uninterrupted structure, and is continuously distributed on the substrate 10 to pass through the areas below all the semiconductor elements 1 and between two adjacent semiconductor elements 1 . Each elevated portion 43 is located between the semiconductor element 1 and the continuous portion 44 , protrudes upward from the continuous portion 44 and corresponds to a single semiconductor element 1 . The outer side 42 of the platform portion 43 is flush with or close to the outermost side 19 of the semiconductor element 1 . The adhesive part 4 has a thickness H4 of about 2-3 μm. The continuous portion 44 has a thickness H5 greater than 0 μm and less than 1 μm. In another embodiment, the outer side 42 is not flush with the outermost side 19 of the semiconductor device 1 , and the elevated portion 43 may shrink or protrude relative to the outermost side 19 of the semiconductor device 1 . The plateau portion 43 has a maximum width W5, and the semiconductor device 1 has a maximum width W6. W5 is substantially equal to W6. In another embodiment, W5 may be smaller or larger than W6.
第2A圖為根據本發明一實施例中的一半導體元件1的立體示意圖。半導體元件1的最大邊長，不大於100 μm、或是50 μm。例如：半導體元件的最大邊長大約40 μm、寬大約20 μm。導電凸塊2a與導電凸塊2b具有相反的極性（正極、負極），且之間的最小水平距離D小於40 μm，例如，半導體元件的最大邊長大約40 μm，D大約為15 μm。導電凸塊2a、2b完整覆蓋電極（如第1B圖中之電極3a/3b），並具有一外凸的圓弧形狀以及一頂部21a、21b。參考第1A圖，頂部21a、21b大約位於導電凸塊2a、2b及/或電極的幾何中心。FIG. 2A is a perspective view of a semiconductor device 1 according to an embodiment of the present invention. The maximum side length of the semiconductor element 1 is not greater than 100 μm or 50 μm. For example: a semiconductor element has a maximum side length of approximately 40 μm and a width of approximately 20 μm. The conductive bump 2a and the conductive bump 2b have opposite polarities (positive and negative), and the minimum horizontal distance D between them is less than 40 μm, for example, the maximum side length of a semiconductor element is about 40 μm, and D is about 15 μm. The conductive bumps 2a, 2b completely cover the electrodes (such as the electrodes 3a/3b in FIG. 1B ), and have a convex arc shape and a top 21a, 21b. Referring to FIG. 1A, the tops 21a, 21b are located approximately at the geometric centers of the conductive bumps 2a, 2b and/or electrodes.
第2B圖為第2A圖中半導體元件沿著BB´線段的剖面示意圖。半導體元件1被放置在基板10上並具有半導體疊層14、保護層15、第一電極3a、第二電極3b、第一導電凸塊2a、以及第二導電凸塊2b。半導體疊層14的最外側邊19為一傾斜面，傾斜於基板10。半導體疊層14包含第一半導體層11、活性層12、以及第二半導體層13。第一半導體層11及第二半導體層13，可分別提供電子、電洞，使電子、電洞於活性層12中復合（Recombination）以發出光線。第一半導體層11、活性層13、及第二半導體層13可包含Ⅲ-Ⅴ族半導體材料，例如Al
xIn
yGa
（ 1-x-y ）N或Al
xIn
yGa
（ 1-x-y ）P，其中0≦x、 y≦1；（x+y）≦1。依據活性層之材料，LED晶粒可發出一峰值介於610 nm及650 nm之間的紅光、峰值介於530 nm及570 nm之間的綠光、峰值介於500nm及485 nm之間的青光（Cyan）、峰值介於450 nm及490 nm之間的藍光、峰值介於400nm及450 nm之間的紫光、或是峰值介於280 nm及400 nm之間的紫外光。半導體疊層14的最大厚度約等於或小於10 μm。在一實施例中，第一半導體層11的下表面17與基板10相接觸且為一粗糙表面。在另一實施例中，第一半導體層11的下表面17為大致平坦的表面（圖未示）。在又一實施例中，基板10為用以磊晶成長（Epitaxially Grow）半導體疊層14的成長基板（Growth Substrate），基板10面對半導體疊層14的全部上表面為一粗糙表面（圖未示），例如，圖形化藍寶石基板（Patterned Sapphire Substrate；PSS）。在一實施例中，半導體元件1包含一載體（圖未示），載體位於半導體疊層14之下並用以支撐半導體疊層14，載體可以為半導體疊層14的磊晶成長基板或非磊晶成長基板，載體的材料可以參考前述基板10的相關段落，為材料的選用應符合理論與實務可行性。
Fig. 2B is a schematic cross-sectional view of the semiconductor element along the line BB' in Fig. 2A. The semiconductor element 1 is placed on a substrate 10 and has a semiconductor stack 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor stack 14 is an inclined surface inclined to the substrate 10 . The semiconductor stack 14 includes a first semiconductor layer 11 , an active layer 12 , and a second semiconductor layer 13 . The first semiconductor layer 11 and the second semiconductor layer 13 can provide electrons and holes respectively, so that the electrons and holes can recombine in the active layer 12 to emit light. The first semiconductor layer 11, the active layer 13 , and the second semiconductor layer 13 may include III-V group semiconductor materials , such as AlxInyGa ( 1-xy ) N or AlxInyGa ( 1-xy ) P, Among them, 0≦x, y≦1; (x+y)≦1. Depending on the material of the active layer, the LED die can emit a red light with a peak between 610 nm and 650 nm, a green light with a peak between 530 nm and 570 nm, and a green light with a peak between 500 nm and 485 nm. Cyan, blue light with a peak between 450 nm and 490 nm, violet light with a peak between 400 nm and 450 nm, or ultraviolet light with a peak between 280 nm and 400 nm. The maximum thickness of the semiconductor stack 14 is approximately equal to or less than 10 μm. In one embodiment, the lower surface 17 of the first semiconductor layer 11 is in contact with the substrate 10 and is a rough surface. In another embodiment, the lower surface 17 of the first semiconductor layer 11 is a substantially flat surface (not shown). In yet another embodiment, the substrate 10 is a growth substrate (Growth Substrate) for epitaxially growing (Epitaxially Grow) the semiconductor stack 14, and the entire upper surface of the substrate 10 facing the semiconductor stack 14 is a rough surface (not shown in the figure). shown), for example, patterned sapphire substrate (Patterned Sapphire Substrate; PSS). In one embodiment, the semiconductor element 1 includes a carrier (not shown in the figure), which is located under the semiconductor stack 14 and is used to support the semiconductor stack 14. The carrier can be the epitaxial growth substrate of the semiconductor stack 14 or a non-epitaxial The material of the growth substrate and the carrier can refer to the relevant paragraphs of the above-mentioned substrate 10, and the selection of the material should conform to the theoretical and practical feasibility.
半導體疊層14具有一平台16，用以暴露第一半導體層11於活性層12與第二半導體層13之外。保護層15覆蓋第二半導體層13的上表面、第一半導體層11的側壁、活性層12的側壁、第二半導體層13的側壁、以及位於平台16中的第一半導體層11的上表面。保護層15可以與基板10直接接觸。在另一實施中，保護層15不與基板10接觸。保護層15於平台16中具有一第一開孔5a以暴露出部分的第一半導體疊層11。保護層15於第二半導體層13上具有一第二開孔5b以暴露出部分的第二半導體層13。第一電極3a位於平台16中，具有一部分形成在保護層15之上，覆蓋位於平台16中的保護層15以及部分位於平台16以外的保護層15。第一電極3a具一第一凹部6a形成在第一開孔5a中，並與第一半導體層11電性連接。第一電極3a於平台16的位置處，具有一階梯狀的外型。第二電極3b具有一部分位於第二開孔5b以外的保護層15上，以及一第二凹部6b形成在第二開孔5b中並與第二半導體層13電性連接。The semiconductor stack 14 has a platform 16 for exposing the first semiconductor layer 11 outside the active layer 12 and the second semiconductor layer 13 . The passivation layer 15 covers the upper surface of the second semiconductor layer 13 , the sidewalls of the first semiconductor layer 11 , the sidewalls of the active layer 12 , the sidewalls of the second semiconductor layer 13 , and the upper surface of the first semiconductor layer 11 located in the platform 16 . The protective layer 15 may directly contact the substrate 10 . In another implementation, the protection layer 15 is not in contact with the substrate 10 . The passivation layer 15 has a first opening 5 a in the platform 16 to expose part of the first semiconductor stack 11 . The passivation layer 15 has a second opening 5 b on the second semiconductor layer 13 to expose part of the second semiconductor layer 13 . The first electrode 3 a is located in the platform 16 , has a part formed on the protective layer 15 , covering the protective layer 15 located in the platform 16 and a part of the protective layer 15 located outside the platform 16 . The first electrode 3 a has a first recess 6 a formed in the first opening 5 a and is electrically connected to the first semiconductor layer 11 . The first electrode 3 a has a stepped shape at the position of the platform 16 . A part of the second electrode 3 b is located on the protective layer 15 outside the second opening 5 b , and a second recess 6 b is formed in the second opening 5 b and electrically connected to the second semiconductor layer 13 .
保護層15可為單層或多層結構，且具有電性絕緣的特性。單層結構的材料可包含氧化物、氮化物、或聚合物（Polymer）。氧化物可包含氧化鋁（Al
2O
3）、氧化矽（SiO
2）、二氧化鈦（TiO
2）、五氧化二鉭（Tantalum Pentoxide, Ta
2O
5）或氧化鋁（AlO
x）。氮化物可包含氮化鋁（AlN）、氮化矽（SiN
x）。聚合物可包含聚醯亞胺（Polyimide）或苯并環丁烷（Benzocyclobutane， BCB）。多層結構的材料可包含氧化鋁（Al
2O
3）、氧化矽（SiO
2）、二氧化鈦（TiO
2）、五氧化二鈮（Nb
2O
5）、氮化矽（SiN
x）、上述材料的組合。多層結構也可以形成一布拉格反射鏡（Distributed Bragg Reflector；DBR）。
The protection layer 15 can be a single-layer or multi-layer structure, and has the property of electrical insulation. The material of the single-layer structure may include oxide, nitride, or polymer. The oxide may include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), titanium dioxide (TiO 2 ), tantalum pentoxide (Tantalum Pentoxide, Ta 2 O 5 ) or aluminum oxide (AlO x ). The nitride may include aluminum nitride (AlN), silicon nitride (SiN x ). The polymer may comprise polyimide (Polyimide) or benzocyclobutane (Benzocyclobutane, BCB). The material of the multilayer structure can include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), titanium dioxide (TiO 2 ), niobium pentoxide (Nb 2 O 5 ), silicon nitride (SiN x ), the above materials combination. The multilayer structure can also form a Bragg reflector (Distributed Bragg Reflector; DBR).
參考第2B圖，第一導電凸塊2a直接形成在第一電極3a的上方。第一導電凸塊2a可以完全地或部分地填滿第一電極3a的第一凹部6a，且其最外表面22a具有一具巨觀上平滑且外凸的圓弧狀。第一導電凸塊2a具有一頂部21a，為第一導電凸塊2a與基板10距離最遠的區域。如圖所示，第一導電凸塊2a的最外表面22a不平行於第一導電凸塊2a的最下表面，也不與第一電極3a的上表面平行。第一半導體層11的下表面17為一粗糙表面，第一導電凸塊2a的最外表面22a的粗糙度較第一半導體層11的下表面17的粗糙度小，也較第一電極3a的上表面的粗糙度小。Referring to FIG. 2B, the first conductive bump 2a is formed directly above the first electrode 3a. The first conductive bump 2a can completely or partially fill the first recess 6a of the first electrode 3a, and its outermost surface 22a has a macroscopically smooth and convex arc shape. The first conductive bump 2 a has a top 21 a , which is the farthest region between the first conductive bump 2 a and the substrate 10 . As shown in the figure, the outermost surface 22a of the first conductive bump 2a is not parallel to the lowermost surface of the first conductive bump 2a, nor is it parallel to the upper surface of the first electrode 3a. The lower surface 17 of the first semiconductor layer 11 is a rough surface, and the roughness of the outermost surface 22a of the first conductive bump 2a is smaller than the roughness of the lower surface 17 of the first semiconductor layer 11, and is also smaller than that of the first electrode 3a. The roughness of the upper surface is small.
參考第2B圖，第二導電凸塊2b直接覆蓋於第二電極3b的上方。第二導電凸塊2b可以完全地或部分地填滿第二電極3b的第二凹部6b，且其最外表面22b具有一具巨觀上平滑且外凸的圓弧狀。第二導電凸塊2b具有一頂部21b，為第二導電凸塊2b與基板10距離最遠的區域。如圖所示，第二導電凸塊2b的最外表面22b不平行於第二導電凸塊2b的最下表面，也不與第二電極3b的上表面平行。第二導電凸塊2b的最外表面22b的粗糙度較第一半導體層11的下表面17的粗糙度小，也較第二電極3b的上表面的粗糙度小。較佳地，第一導電凸塊2a的頂部21a與第二導電凸塊2b的頂部21b大致上位於同一水平高度，有利於半導體元件1後續穩定地固定在基板上。然而，在實務上，在製程工藝的容許下可以存在一定程度的高度差異。第一導電凸塊2a與第二導電凸塊2b的最下表面通常係共形地（Conformally）分別形成在第一電極3a與第二電極3b上，兩者的最低點往往不會位於同一水平高度。參考第2B圖，第一導電凸塊2a從頂部21a到保護層15的最上表面151的垂直距離可以量得一個第一厚度H1，第一導電凸塊2a具有一第一（最大）寬度W1，H1／W1介於0.1～0.4之間，較佳為0.1～0.25。第二導電凸塊2b從頂部21b到保護層15的最上表面151的垂直距離可以量得一個第二厚度H2，第二導電凸塊2b具有一第二（最大）寬度W2，H2／W2介於0.1～0.4之間，較佳為0.1～0.25。H1／W1 以及H2／W2可以相同也可以不同。第二導電凸塊2b的第二厚度 H2 為4～6 μm。Referring to FIG. 2B, the second conductive bump 2b directly covers the second electrode 3b. The second conductive bump 2b can completely or partially fill the second concave portion 6b of the second electrode 3b, and its outermost surface 22b has a macroscopically smooth and convex arc shape. The second conductive bump 2b has a top portion 21b, which is the farthest region between the second conductive bump 2b and the substrate 10 . As shown in the figure, the outermost surface 22b of the second conductive bump 2b is not parallel to the lowermost surface of the second conductive bump 2b, nor is it parallel to the upper surface of the second electrode 3b. The roughness of the outermost surface 22b of the second conductive bump 2b is smaller than the roughness of the lower surface 17 of the first semiconductor layer 11, and is also smaller than the roughness of the upper surface of the second electrode 3b. Preferably, the top 21a of the first conductive bump 2a is substantially at the same level as the top 21b of the second conductive bump 2b, which is beneficial for the subsequent stable fixing of the semiconductor element 1 on the substrate. However, in practice, there may be a certain degree of height difference under the tolerance of the manufacturing process. The lowermost surfaces of the first conductive bump 2a and the second conductive bump 2b are usually conformally formed on the first electrode 3a and the second electrode 3b respectively, and the lowest points of the two are often not at the same level high. Referring to FIG. 2B, the vertical distance from the top 21a of the first conductive bump 2a to the uppermost surface 151 of the protective layer 15 can be measured as a first thickness H1, and the first conductive bump 2a has a first (maximum) width W1, H1/W1 is between 0.1-0.4, preferably 0.1-0.25. The vertical distance of the second conductive bump 2b from the top 21b to the uppermost surface 151 of the protective layer 15 can be measured as a second thickness H2, the second conductive bump 2b has a second (maximum) width W2, and H2/W2 is between Between 0.1 and 0.4, preferably 0.1 to 0.25. H1/W1 and H2/W2 may be the same or different. The second thickness H2 of the second conductive bump 2b is 4-6 μm.
若第一導電凸塊2a越密實地填入第一電極3a的第一凹部6a中，第二導電凸塊2b越密實地填入第二電極3b的第二凹部6b中，可以提高半導體元件1與電路基板（無顯示）間物理與電性連接的可靠度，降低失效情形的發生機率。詳言之，若半導體元件1的結構如第2B圖所示但是無導電凸塊2a/2b，當半導體元件1以焊料固接於電路基板時，位於第一電極3a與電路基板（無顯示）之間的焊料不時會在第ㄧ凹部6a附近產生孔洞；位於第二電極3b與電路基板（無顯示）之間的焊料不時會在第二凹部6b附近產生孔洞。這些孔洞皆會降低半導體元件1與電路基板的固接強度。If the first conductive bump 2a is more densely filled in the first recess 6a of the first electrode 3a, and the second conductive bump 2b is more densely filled in the second recess 6b of the second electrode 3b, the semiconductor element 1 can be improved. The reliability of the physical and electrical connection with the circuit board (no display) reduces the probability of failure. In detail, if the structure of the semiconductor element 1 is as shown in FIG. 2B but without conductive bumps 2a/2b, when the semiconductor element 1 is fixed to the circuit substrate with solder, the first electrode 3a and the circuit substrate (not shown) The solder between them will occasionally produce holes near the first recess 6a; the solder between the second electrode 3b and the circuit substrate (not shown) will occasionally produce holes near the second recess 6b. These holes will reduce the bonding strength between the semiconductor element 1 and the circuit substrate.
若在形成導電凸塊的過程中有熱處理步驟，在特定導電凸塊與電極的材料選用組合下，導電凸塊在熱處理步驟後可能會在其內部形成離散分布的金屬顆粒，如第2C圖顯示。第2C圖為根據本發明另一實施例中的一半導體元件1的剖面示意圖。第2C圖的結構可以參考第2B圖及相關段落的描述。第一導電凸塊2a與第二導電凸塊2b內，具有離散分布、大小不規則、外型不規則的顆粒7散佈其中，顆粒7的材料與導電凸塊2a、2b不同，但與電極3a、3b的部分材料相同，例如金、鉑或前述材料的合金。顆粒7的外型可以為長條狀、多角形、葉片狀、水滴狀。If there is a heat treatment step in the process of forming the conductive bump, under the material selection combination of the conductive bump and the electrode, discrete distribution of metal particles may be formed inside the conductive bump after the heat treatment step, as shown in Figure 2C . FIG. 2C is a schematic cross-sectional view of a semiconductor device 1 according to another embodiment of the present invention. The structure of Figure 2C can refer to the description of Figure 2B and related paragraphs. In the first conductive bump 2a and the second conductive bump 2b, particles 7 with discrete distribution, irregular size, and irregular appearance are scattered therein. , 3b are partly made of the same material, such as gold, platinum or an alloy of the aforementioned materials. The appearance of the particles 7 can be strip-shaped, polygonal, blade-shaped, or drop-shaped.
第2D～2E圖為根據本發明另一實施例中的一半導體元件1´的示意圖。其結構可以參考第2A～2B圖及相關段落的描述。如第2D圖顯示，導電凸塊2a、2b具有一外凸的圓弧形狀，並具有一頂部21a、21b。頂部21a與頂部21b沒有位於同一水平高度。頂部21a略低於頂部21b。第2E圖為第2D圖中半導體元件1´沿著BB´線段的剖面示意圖。導電凸塊2a位於平台16的上方，當導電凸塊2a與導電凸塊2b的體積近似時，因為部分的導電凸塊2a需填補平台16，因此位於導電凸塊2a的頂部21a略低於導電凸塊2b的頂部21b。在一實施例中，第一導電凸塊2a的第一厚度 H1較第一導電凸塊2a的第一厚度 H1小0.4～1μm。2D-2E are schematic diagrams of a semiconductor device 1′ according to another embodiment of the present invention. Its structure can refer to the descriptions in Figures 2A-2B and related paragraphs. As shown in FIG. 2D, the conductive bumps 2a, 2b have a convex arc shape and have a top 21a, 21b. The top 21a is not at the same level as the top 21b. Top 21a is slightly lower than top 21b. FIG. 2E is a schematic cross-sectional view of the semiconductor element 1′ along the line BB′ in FIG. 2D. The conductive bump 2a is located above the platform 16. When the volume of the conductive bump 2a is similar to that of the conductive bump 2b, because part of the conductive bump 2a needs to fill the platform 16, the top 21a of the conductive bump 2a is slightly lower than the conductive bump 2a. The top 21b of the bump 2b. In one embodiment, the first thickness H1 of the first conductive bump 2a is 0.4˜1 μm smaller than the first thickness H1 of the first conductive bump 2a.
第3A圖為根據本發明一實施例中的一半導體元件1的上視示意圖。第3B圖為第3A圖中半導體元件1沿著CC´線段的剖面圖示意圖。第3C圖為第3A圖中半導體元件1沿著DD´線段的剖面圖示意圖。半導體元件1包含半導體疊層14、以及電極3與導電凸塊2位於半導體疊層14上。導電凸塊2與電極3於第3A圖中，投影形狀大致為矩形。導電凸塊2於剖面圖中，最外表面22具有一巨觀上平滑且外凸的圓弧狀。如第3B圖顯示，最外表面22與電極3的上表面相接觸，導電凸塊2在接觸點的切線與電極3的上表面形成一個夾角θ1。夾角θ1近似90度，較佳為70度＜θ1＜90度。如第3C圖顯示，最外表面22與電極3的上表面相接觸，導電凸塊2在接觸點的切線與電極3的上表面形成一個夾角θ2。夾角θ2＜夾角θ1，較佳為30度＜θ2＜70度。換言之，如第3A圖所示，導電凸塊2於平行電極3邊長的方向上的剖面形狀不同於電極3的對角線方向上的剖面形狀。FIG. 3A is a schematic top view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of the semiconductor element 1 along line CC′ in FIG. 3A. FIG. 3C is a schematic cross-sectional view of the semiconductor element 1 along the line DD′ in FIG. 3A. The semiconductor device 1 includes a semiconductor stack 14 , and the electrodes 3 and the conductive bumps 2 are located on the semiconductor stack 14 . The projected shapes of the conductive bumps 2 and the electrodes 3 in FIG. 3A are roughly rectangular. In the cross-sectional view of the conductive bump 2 , the outermost surface 22 has a macroscopically smooth and convex arc shape. As shown in FIG. 3B , the outermost surface 22 is in contact with the upper surface of the electrode 3 , and the tangent line of the conductive bump 2 at the contact point forms an angle θ1 with the upper surface of the electrode 3 . The included angle θ1 is approximately 90 degrees, preferably 70 degrees<θ1<90 degrees. As shown in FIG. 3C , the outermost surface 22 is in contact with the upper surface of the electrode 3 , and the tangent of the conductive bump 2 at the contact point forms an angle θ2 with the upper surface of the electrode 3 . The included angle θ2<the included angle θ1, preferably 30 degrees<θ2<70 degrees. In other words, as shown in FIG. 3A , the cross-sectional shape of the conductive bump 2 in the direction parallel to the side length of the electrode 3 is different from the cross-sectional shape of the electrode 3 in the diagonal direction.
第4A圖為根據本發明一實施例中的一種半導體元件陣列2000。半導體元件陣列2000包含複數個半導體元件1（為簡化起見，圖中僅繪示一個維度上的三個半導體元件1，然而，半導體元件陣列2000可以包含m*n個半導體元件1，m、n為大於或等於0的正整數，且m、n不同時為0）以及載體30。半導體元件1以導電凸塊2朝向載體30的方式（或稱之為覆晶）配置於載體30上。載體30能支撐及固定半導體元件1。載體30包含承載板31與黏著層32，承載板31的材料係可以為玻璃、藍寶石、或高分子材料等，可被發光二極體或雷射二極體發出的特定波長的光線穿透的透光材料。黏著層32可以包含熱移除膠、光解離膠、化學移除膠、耐熱膠、藍膜、或是具有動力釋放層的膠帶。在另一實施例中，黏著層也可以包含聚合物，例如，聚醯亞胺（Polyimide）或苯并環丁烷（Benzocyclobutane， BCB）。當前述的半導體元件1以覆晶方向排列在載體30上時，其導電凸塊2的平滑外凸的最外表面22直接接觸黏著層32。如圖中所示，導電凸塊2會部分陷入黏著層32中，陷入的部分具有一平行黏著層32表面的最大寬度W3，而導電凸塊2本身具有一最大寬度W4，W4＞W3。此外，導電凸塊2的最外表面22為平滑且為圓弧狀，於一選定的投影方向上，導電凸塊2陷入黏著層部分的投影面積（如第4C圖中的壓痕34的面積）小於電極的面積，且黏著力較低，有利於後續將半導體元件1自載體30移轉到他處的移轉製程。關於半導體元件1的移轉製程將於後面段落敘述。FIG. 4A is a semiconductor device array 2000 according to an embodiment of the present invention. The semiconductor element array 2000 includes a plurality of semiconductor elements 1 (for simplicity, only three semiconductor elements 1 in one dimension are shown in the figure, however, the semiconductor element array 2000 may include m*n semiconductor elements 1, m, n is a positive integer greater than or equal to 0, and m and n are not 0 at the same time) and the carrier 30 . The semiconductor element 1 is disposed on the carrier 30 in such a way that the conductive bumps 2 face the carrier 30 (or called flip chip). The carrier 30 can support and fix the semiconductor element 1 . The carrier 30 includes a carrier board 31 and an adhesive layer 32. The material of the carrier board 31 can be glass, sapphire, or polymer materials, etc., which can be penetrated by light of a specific wavelength emitted by a light emitting diode or a laser diode. Light-transmitting material. The adhesive layer 32 may include heat-removable glue, photodissociation glue, chemical-removable glue, heat-resistant glue, blue film, or adhesive tape with a power release layer. In another embodiment, the adhesive layer may also include a polymer, for example, polyimide (Polyimide) or benzocyclobutane (Benzocyclobutane, BCB). When the aforementioned semiconductor elements 1 are arranged on the carrier 30 in the flip-chip direction, the smooth and convex outermost surface 22 of the conductive bump 2 directly contacts the adhesive layer 32 . As shown in the figure, the conductive bump 2 is partially sunk into the adhesive layer 32 , and the sunken portion has a maximum width W3 parallel to the surface of the adhesive layer 32 , and the conductive bump 2 itself has a maximum width W4, W4>W3. In addition, the outermost surface 22 of the conductive bump 2 is smooth and arc-shaped, and in a selected projection direction, the projected area of the portion where the conductive bump 2 sinks into the adhesive layer (such as the area of the indentation 34 in Figure 4C) ) is smaller than the area of the electrode, and the adhesive force is low, which is beneficial to the subsequent transfer process of transferring the semiconductor element 1 from the carrier 30 to another place. The transfer process of the semiconductor element 1 will be described in the following paragraphs.
第4B及第4C圖顯示為第4A圖半導體元件陣列2000移除一顆半導體元件1的側視圖及上視圖。參考第4C圖，由上視圖觀之，載體30上表面可定義一移除區域33（如虛線處），代表半導體元件1被移除後在載體30上暴露出來的區域，即半導體元件1在上視圖中的投影面積。移除區域33中包含壓痕34。壓痕34為黏著層32被導電凸塊2壓入的區域，壓痕34在上視圖中有一投影面積。根據實驗結果，當導電凸塊的壓痕34的投影面積與半導體元件1的投影面積的比值小於0.2時，半導體元件1較容易自載體30被抓起並移動到其他位置。4B and 4C show a side view and a top view with one semiconductor device 1 removed from the semiconductor device array 2000 in FIG. 4A . Referring to FIG. 4C, from the top view, the upper surface of the carrier 30 can define a removal area 33 (such as the dotted line), which represents the area exposed on the carrier 30 after the semiconductor element 1 is removed, that is, the semiconductor element 1 is in the Projected area in top view. Indentation 34 is contained in removal area 33 . The indentation 34 is the area where the adhesive layer 32 is pressed into by the conductive bump 2 , and the indentation 34 has a projected area in the top view. According to the experimental results, when the ratio of the projected area of the indentation 34 of the conductive bump to the projected area of the semiconductor device 1 is less than 0.2, the semiconductor device 1 is easier to be picked up from the carrier 30 and moved to other positions.
第4D～4E圖為根據本發明另一實施例中的一種半導體元件陣列。第4D圖顯示一半導體元件陣列3000，其可以參考第4A圖及相關段落的描述。半導體元件陣列3000包含複數個半導體元件1以及載體30。載體30包含承載板31與一個黏著層32。半導體元件1以導電凸塊2朝向載體30的方式配置於載體30上。導電凸塊2以及電極3會完全陷入黏著層32中並被黏著層32完整包覆。黏著層32並覆蓋半導體元件1未被電極3覆蓋的下表面。藉由被暫時固定在黏著層32上，複數個半導體元件1之間的相對位置得以維持，較不會因為後續製程而發生變化。第4E圖顯示一半導體元件陣列3001，其可以參考第4D圖及相關段落的描述。半導體元件陣列3001包含複數個半導體元件1以及載體30。載體30包含承載板31與複數個彼此分離的黏著層32，一個黏著層32在水平位置與寬度上對應一個半導體元件1。兩相鄰黏著層32間具有一大於0的走道33。複數個半導體元件1以導電凸塊2朝向載體30的方式配置於載體30上。導電凸塊2以及電極3會完全陷入黏著層32中並被黏著層32完整包覆。黏著層32並覆蓋半導體元件1未被電極3覆蓋的下表面。4D-4E are a semiconductor device array according to another embodiment of the present invention. FIG. 4D shows a semiconductor device array 3000, which can refer to the description of FIG. 4A and related paragraphs. The semiconductor element array 3000 includes a plurality of semiconductor elements 1 and a carrier 30 . The carrier 30 includes a carrier board 31 and an adhesive layer 32 . The semiconductor element 1 is disposed on the carrier 30 with the conductive bump 2 facing the carrier 30 . The conductive bumps 2 and the electrodes 3 are completely immersed in the adhesive layer 32 and completely covered by the adhesive layer 32 . The adhesive layer 32 also covers the lower surface of the semiconductor element 1 not covered by the electrode 3 . By being temporarily fixed on the adhesive layer 32 , the relative positions of the plurality of semiconductor elements 1 can be maintained and will not change due to subsequent manufacturing processes. FIG. 4E shows a semiconductor element array 3001, which can refer to the description of FIG. 4D and related paragraphs. The semiconductor element array 3001 includes a plurality of semiconductor elements 1 and a carrier 30 . The carrier 30 includes a carrier board 31 and a plurality of adhesive layers 32 separated from each other, and one adhesive layer 32 corresponds to one semiconductor element 1 in horizontal position and width. There is a channel 33 greater than 0 between two adjacent adhesive layers 32 . A plurality of semiconductor elements 1 are disposed on the carrier 30 with the conductive bumps 2 facing the carrier 30 . The conductive bumps 2 and the electrodes 3 are completely immersed in the adhesive layer 32 and completely covered by the adhesive layer 32 . The adhesive layer 32 also covers the lower surface of the semiconductor element 1 not covered by the electrode 3 .
第5A～5D圖為根據本發明一實施例中移轉半導體元件1之步驟示意圖。第5A圖顯示，複數個半導體元件1以陣列的形式排列於載體30上。每一個半導體元件1藉由導電凸塊2的部分表面與載體30的黏著層32接觸，並暫時地被固定在載體30上。提供一抓取工具40以將半導體元件1自載體30移動至他處。抓取工具40具有複數個抓取部41，每一個抓取部41與待抓取的半導體元件1的位置相對應。如第5B圖所示，抓取工具40移動靠近複數個半導體元件1，使抓取部41與半導體元件1接觸後，向上移動使被抓取部41抓取的半導體元件1離開載體30。值得注意的是，抓取部41與半導體元件1之間的黏性在進行抓取步驟的當下必須大於半導體元件1與載體30之間的黏性。未被抓取部41接觸的半導體元件1仍留在載體30上。如第5C圖所示，抓取工具40與暫時被固定在抓取部41上的半導體元件1一同移動至目標基板50的預設位置上方。在此預設位置上，半導體元件1可以直接地或間接地接觸目標基板50，並最終地被直接地放置或固定於目標基板50上。如第5D圖所示，半導體元件1自抓取工具40離開並停留在目標基板50上，而抓取工具40則可以移動至同一或不同的載體30抓取其他的半導體元件1。移轉後的半導體元件1以導電凸塊2朝向目標基板50的方式配置於目標基板50上。目標基板50可以為應用於顯示器的電路板、TFT基板、具有重佈線路層（Redistribution Layer；RDL）的基板、或是封裝體的次基板（Sub-mount）。另一實施例中，目標基板50可以與前述載體30相似的暫時載體。其中，第5A～5D圖中，半導體元件1與載體30的接觸方式不限於第4A圖所示的態樣，也可以是第4D、4E圖所示的態樣。5A-5D are schematic diagrams of the steps of transferring the semiconductor device 1 according to an embodiment of the present invention. FIG. 5A shows that a plurality of semiconductor elements 1 are arranged on the carrier 30 in the form of an array. Each semiconductor device 1 is temporarily fixed on the carrier 30 through contact with the adhesive layer 32 of the carrier 30 by a part of the surface of the conductive bump 2 . A grabbing tool 40 is provided to move the semiconductor device 1 from the carrier 30 to another place. The grasping tool 40 has a plurality of grasping parts 41, and each grasping part 41 corresponds to the position of the semiconductor element 1 to be grasped. As shown in FIG. 5B , the gripping tool 40 moves close to a plurality of semiconductor elements 1 , makes the gripping portion 41 contact the semiconductor elements 1 , and then moves upward to make the semiconductor element 1 gripped by the gripping portion 41 leave the carrier 30 . It should be noted that the viscosity between the gripping part 41 and the semiconductor element 1 must be greater than the viscosity between the semiconductor element 1 and the carrier 30 at the moment of the gripping step. The semiconductor components 1 not touched by the gripper 41 remain on the carrier 30 . As shown in FIG. 5C , the pick tool 40 moves above the preset position of the target substrate 50 together with the semiconductor device 1 temporarily fixed on the pick portion 41 . At this predetermined position, the semiconductor device 1 can directly or indirectly contact the target substrate 50 , and finally be directly placed or fixed on the target substrate 50 . As shown in FIG. 5D , the semiconductor device 1 leaves the grabbing tool 40 and stays on the target substrate 50 , and the grabbing tool 40 can move to the same or different carrier 30 to grab other semiconductor devices 1 . The transferred semiconductor element 1 is disposed on the target substrate 50 with the conductive bumps 2 facing the target substrate 50 . The target substrate 50 may be a circuit board applied to a display, a TFT substrate, a substrate with a redistribution layer (Redistribution Layer; RDL), or a sub-mount of a package. In another embodiment, the target substrate 50 may be a temporary carrier similar to the aforementioned carrier 30 . In FIGS. 5A to 5D , the contact method between the semiconductor element 1 and the carrier 30 is not limited to that shown in FIG. 4A , and may also be the ones shown in FIGS. 4D and 4E .
第6A～6C圖為根據本發明另一實施例的移轉半導體元件1之步驟示意圖。第6A圖顯示複數個半導體元件1以陣列的形式被放置於載體30上。每一個半導體元件1藉由導電凸塊2的部分表面與載體30的黏著層32接觸，併暫時地被固定在載體30上。接著，將第6A圖的結構翻轉或移動目標基板50使半導體元件1位於載體30與目標基板50之間，但半導體元件1並不與目標基板50直接接觸，例如，如第6B圖所示，半導體元件1懸置在目標基板50上方。提供一雷射能量L1，自承載板31這側照射黏著層32的特定位置，此特定位置對應於需被移轉的一個半導體元件1。雷射能量L1可以是單發雷射（Single-Shot Laser）或是多發雷射（Multi-Shot Laser）。在一個實施例中，一個半導體元件1或一個黏著層32的單一個位置在一個照射過程中可以被照射一發雷射或多發雷射。在另一個實施例中，一個半導體元件1或一個黏著層32的多個位置在一個照射過程中可以分別被照射一發雷射或多發雷射。如第6C圖所示，被雷射能量L1照射過的黏著層32會造成半導體元件1與黏著層32之間的黏性降低或使半導體元件1向下移動的力量大於黏著層3對半導體元件1的黏性，使半導體元件1自載體30掉落至目標基板50。移轉後的半導體元件1以導電凸塊2遠離目標基板50的方式，配置於目標基板50上。在另一實施例中，於第6B圖的步驟中，半導體元件1可以先與目標基板50直接接觸，再被照射雷射能量L1，如此半導體元件1可以更精準地與目標基板50對位。在第6C圖步驟後，一移除步驟可以選擇性地施加在半導體元件1上以清除殘餘在半導體元件1上的黏著層32。移除步驟可以包含乾蝕刻或是濕蝕刻，乾蝕刻可以為氧氣電漿蝕刻製程。其中，第6A～6C圖中，半導體元件1與載體30的接觸方式不限於第4A圖所示的態樣，也可以是第4D、4E圖所示的態樣。6A-6C are schematic diagrams of the steps of transferring the semiconductor device 1 according to another embodiment of the present invention. FIG. 6A shows that a plurality of semiconductor devices 1 are placed on a carrier 30 in the form of an array. Each semiconductor device 1 is temporarily fixed on the carrier 30 through contact with the adhesive layer 32 of the carrier 30 by a part of the surface of the conductive bump 2 . Next, the structure in FIG. 6A is turned over or the target substrate 50 is moved so that the semiconductor element 1 is positioned between the carrier 30 and the target substrate 50, but the semiconductor element 1 is not in direct contact with the target substrate 50. For example, as shown in FIG. 6B, The semiconductor element 1 is suspended above the target substrate 50 . A laser energy L1 is provided to irradiate a specific position of the adhesive layer 32 from the side of the carrier plate 31 , and the specific position corresponds to a semiconductor element 1 to be transferred. The laser energy L1 can be a single-shot laser (Single-Shot Laser) or a multi-shot laser (Multi-Shot Laser). In one embodiment, a single location of a semiconductor element 1 or an adhesive layer 32 can be irradiated with one laser shot or multiple laser shots during one irradiation process. In another embodiment, multiple positions of a semiconductor element 1 or an adhesive layer 32 may be irradiated with one shot of laser or multiple shots of laser respectively in one irradiation process. As shown in FIG. 6C, the adhesive layer 32 irradiated by the laser energy L1 will cause the adhesion between the semiconductor element 1 and the adhesive layer 32 to decrease or the force of the semiconductor element 1 to move downward is greater than that of the adhesive layer 3 to the semiconductor element. 1 viscosity, the semiconductor element 1 falls from the carrier 30 to the target substrate 50 . The transferred semiconductor element 1 is disposed on the target substrate 50 in such a way that the conductive bumps 2 are away from the target substrate 50 . In another embodiment, in the step of FIG. 6B , the semiconductor device 1 can be in direct contact with the target substrate 50 first, and then irradiated with laser energy L1 , so that the semiconductor device 1 can be more accurately aligned with the target substrate 50 . After the step in FIG. 6C , a removal step can be selectively applied on the semiconductor device 1 to remove the adhesive layer 32 remaining on the semiconductor device 1 . The removing step may include dry etching or wet etching, and the dry etching may be an oxygen plasma etching process. In FIGS. 6A-6C , the contact method between the semiconductor element 1 and the carrier 30 is not limited to that shown in FIG. 4A , and may also be the ones shown in FIGS. 4D and 4E .
第7A～7D圖為根據本發明一實施例的製作半導體元件1之步驟示意圖。如第7A圖顯示，設置複數個半導體單元100於基板10之上。半導體單元100包含半導體疊層14、保護層15、第一電極3a、以及第二電極3b。半導體單元100以第一電極3a與第二電極3b遠離基板10的方式設置於基板10之上。第一電極3a以及第二電極3b各自具有凹部，相關的結構描述可以參考前述相關段落。接著，於第一電極3a以及第二電極3b之上分別形成彼此分開的兩團膠料80。膠料80包含樹脂81以及分散在樹脂81中的複數個導電粒子82。在一實施例中，形成膠料80的方式可以透過印刷（Printing）、塗佈（Coating）、噴塗（Spraying）、點膠（Dispensing）。其中，印刷的方式可以包含氣溶膠噴印（Aerosol Jet Printing）、或噴墨印刷（Ink-Jet Printing）。樹脂81的材料包含熱固性塑料以及助焊劑。熱固性塑料可以是環氧樹脂（Epoxy）、矽氧樹脂（Silicone）、聚甲基丙烯酸甲酯、以及環硫化物（Episulfide）。導電粒子82的熔點低於樹脂81的固化溫度。在一實施例中，導電粒子82的材料可以是金、銀、銅。在另一實施例中，導電粒子82的材料可以是低熔點的金屬或低液化熔點（Liquidus Melting Point ）的合金。在一實施例中，低熔點的金屬或低液化熔點的合金的熔點或液化溫度低於210℃。在另一實施例中，低熔點的金屬或低液化熔點的合金的熔點或液化溫度低於170℃。低液化熔點的合金的材料可以是錫合金，例如：錫銦合金、錫鉍合金。7A-7D are schematic diagrams of the steps of manufacturing the semiconductor device 1 according to an embodiment of the present invention. As shown in FIG. 7A , a plurality of semiconductor units 100 are disposed on the substrate 10 . The semiconductor unit 100 includes a semiconductor stack 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor unit 100 is disposed on the substrate 10 in such a way that the first electrode 3 a and the second electrode 3 b are away from the substrate 10 . Each of the first electrode 3 a and the second electrode 3 b has a concave portion, and related structure descriptions can refer to the relevant paragraphs above. Next, two groups of glue 80 separated from each other are formed on the first electrode 3 a and the second electrode 3 b respectively. The glue 80 includes a resin 81 and a plurality of conductive particles 82 dispersed in the resin 81 . In one embodiment, the method of forming the glue 80 may be through printing, coating, spraying, or dispensing. Wherein, the printing method may include aerosol jet printing (Aerosol Jet Printing) or ink-jet printing (Ink-Jet Printing). The material of the resin 81 includes thermosetting plastics and flux. The thermosetting plastic can be epoxy resin (Epoxy), silicone resin (Silicone), polymethyl methacrylate, and episulfide (Episulfide). The melting point of the conductive particles 82 is lower than the curing temperature of the resin 81 . In an embodiment, the material of the conductive particles 82 may be gold, silver, or copper. In another embodiment, the material of the conductive particles 82 may be a metal with a low melting point or an alloy with a low liquidus melting point (Liquidus Melting Point ). In one embodiment, the melting point or liquefaction temperature of the low melting point metal or low melting point alloy is lower than 210°C. In another embodiment, the low melting point metal or low melting point alloy has a melting point or liquefaction temperature below 170°C. The material of the alloy with a low liquefaction melting point may be tin alloy, for example: tin-indium alloy, tin-bismuth alloy.
如第7B圖所示，利用一雷射能量L2照射膠料80或其鄰近的區域，用以加熱膠料80。雷射能量L2可以包含紫外光（UV）雷射光束、可見光雷射光束或紅外光（IR）雷射光束。在一實施例中，雷射能量L2為紅外光的脈衝（Pulse Mode）雷射光束，其波長介於750 nm ~ 2,000 nm的範圍內，光斑大小（Spot Size）為0.004～0.002 cm
2，光束直徑（Beam Diameter）為100～500 μm，脈衝寬度（Duration）小於20毫秒（ms），重複頻率（Frequency）為500～4000 Hz，工作週期（Duty Cycle）為1 %～10 %，功率（Laser Power）為100 W，雷射能量（Laser Energy）為595～850 J／cm
2。如第7C圖顯示，在加熱過程中，導電粒子82會聚集在第一電極3a以及第二電極3b之上，形成外凸具有圓弧外表面的第一導電凸塊2a與第二導電凸塊2b。樹脂81則移動至第一導電凸塊2a、第二導電凸塊2b、以及第一電極3a以及第二電極3b之間的區域18之上。加熱後，第一導電凸塊2a以及第二導電凸塊2b會固化，而覆蓋在其上的樹脂81也會升溫但尚未完全固化（Uncured），為液態或是半液態的狀態。接著，如第7D圖顯示，進行一清洗步驟，移除未固化的樹脂81，使第一導電凸塊2a以及第二導電凸塊2b暴露於外界環境中，供後續移轉與載板相接觸。清洗步驟可以利用溶劑進行清洗，溶劑可以包含N-甲基吡咯烷酮（N-Methylpyrrolidinone；NMP）、丁酮（Methyl Ethyl Ketone；MEK）、丙酮（Acetone； ACE）、或異丙醇（Isopropyl Alcohol；ACE）。
As shown in FIG. 7B , a laser energy L2 is used to irradiate the glue 80 or its adjacent area to heat the glue 80 . The laser energy L2 may comprise an ultraviolet (UV) laser beam, a visible laser beam or an infrared (IR) laser beam. In one embodiment, the laser energy L2 is a pulsed (Pulse Mode) laser beam of infrared light, the wavelength of which is in the range of 750 nm to 2,000 nm, and the spot size (Spot Size) is 0.004 to 0.002 cm 2 , the beam The diameter (Beam Diameter) is 100-500 μm, the pulse width (Duration) is less than 20 milliseconds (ms), the repetition frequency (Frequency) is 500-4000 Hz, the duty cycle (Duty Cycle) is 1%-10%, and the power (Laser Power) is 100 W, and laser energy (Laser Energy) is 595-850 J/cm 2 . As shown in FIG. 7C, during the heating process, the conductive particles 82 will gather on the first electrode 3a and the second electrode 3b, forming the first conductive bump 2a and the second conductive bump with a circular arc outer surface. 2b. The resin 81 moves to the first conductive bump 2a, the second conductive bump 2b, and the region 18 between the first electrode 3a and the second electrode 3b. After heating, the first conductive bump 2a and the second conductive bump 2b will be solidified, and the resin 81 covering them will also heat up but not yet fully cured (Uncured), and is in a liquid or semi-liquid state. Next, as shown in FIG. 7D, a cleaning step is performed to remove the uncured resin 81, so that the first conductive bump 2a and the second conductive bump 2b are exposed to the external environment for subsequent transfer and contact with the carrier. . The cleaning step can be cleaned with a solvent, and the solvent can include N-Methylpyrrolidinone (N-Methylpyrrolidinone; NMP), methyl ethyl ketone (Methyl Ethyl Ketone; MEK), acetone (Acetone; ACE), or isopropyl alcohol (Isopropyl Alcohol; ACE ).
第8A～8D圖為根據本發明另一實施例的製作半導體元件1之步驟示意圖。如第8A圖顯示，設置複數個半導體單元100於基板10之上。半導體單元100包含半導體疊層14、保護層15、第一電極3a、以及第二電極3b。半導體單元100以第一電極3a與第二電極3b遠離基板10的方式設置於基板10之上。第一電極3a以及第二電極3b各自具有一凹部，相關的結構描述可以參考前述相關段落。利用電鍍、化鍍、或是蒸鍍的方式分別形成第一接合墊23a與第二接合墊23b於第一電極3a與第二電極3b上。第一接合墊23a的上表面24a與第二接合墊23b的上表面24b大致與第一電極3a與第二電極3b的上表面共形（Conformal），亦即兩者的輪廓相近，並具有凹部及/或粗糙的紋理。形成單一團膠料83於半導體單元100、第一接合墊23a、與第二接合墊23b之上。膠料83在此例中僅包含樹脂。在另一實施例中，膠料83包含樹脂以及較低濃度的導電粒子（相較於第7A圖中的導電粒子而言）。在一實施例中，形成膠料80的方式可以透過印刷、塗佈、噴塗、點膠。其中，印刷的方式可以包含氣溶膠噴印、或噴墨印刷。第一接合墊23a與第二接合墊23b的材料可以參考前述有關導電凸塊2a、2b的相關段落。樹脂的材料可以參考前述相關段落。8A-8D are schematic diagrams of the steps of manufacturing the semiconductor device 1 according to another embodiment of the present invention. As shown in FIG. 8A , a plurality of semiconductor units 100 are disposed on the substrate 10 . The semiconductor unit 100 includes a semiconductor stack 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor unit 100 is disposed on the substrate 10 in such a way that the first electrode 3 a and the second electrode 3 b are away from the substrate 10 . Each of the first electrode 3 a and the second electrode 3 b has a concave portion, and related structure descriptions can refer to the relevant paragraphs above. The first bonding pad 23a and the second bonding pad 23b are respectively formed on the first electrode 3a and the second electrode 3b by means of electroplating, electroless plating, or vapor deposition. The upper surface 24a of the first bonding pad 23a and the upper surface 24b of the second bonding pad 23b are approximately conformal to the upper surfaces of the first electrode 3a and the second electrode 3b (Conformal), that is, the contours of the two are similar and have a concave portion. and/or rough texture. A single ball of glue 83 is formed on the semiconductor unit 100, the first bonding pad 23a, and the second bonding pad 23b. The size 83 in this case only contains resin. In another embodiment, the paste 83 includes a resin and a lower concentration of conductive particles (compared to the conductive particles in FIG. 7A ). In one embodiment, the way of forming the adhesive material 80 may be through printing, coating, spraying, or dispensing. Wherein, the printing method may include aerosol jet printing or inkjet printing. For materials of the first bonding pad 23 a and the second bonding pad 23 b , reference may be made to relevant paragraphs about the conductive bumps 2 a and 2 b mentioned above. For resin materials, please refer to the relevant paragraphs above.
如第8B圖所示，利用一雷射能量L3照射第一接合墊23a與第二接合墊23b的位置，用以加熱膠料83、第一接合墊23a與第二接合墊23b。雷射能量L3可以包含紫外光（UV）雷射光束、可見光雷射光束或紅外光（IR）雷射光束。在一實施例中，雷射能量L3為紅外光雷射光束，其波長介於750 nm ~ 2,000 nm的範圍內。如第8C圖顯示，在加熱過程中，第一接合墊23a與第二接合墊23b受熱熔融於膠料83中，並聚集在第一電極3a以及第二電極3b之上（若樹脂含有導電粒子，導電粒子受熱後也會部分或全部朝第一電極3a以及第二電極3b移動），形成外凸具有圓弧外表面的第一導電凸塊2a與第二導電凸塊2b。膠料83則移動至第一導電凸塊2a、第二導電凸塊2b、以及第一電極3a以及第二電極3b之間的區域18之上。加熱後，第一導電凸塊2a以及第二導電凸塊2b會固化，而覆蓋在其上的膠料83（或樹脂）也會升溫但尚未完全固化，為液態或是半液態的狀態。接著，如第8D圖顯示，進行一清洗步驟，移除未固化膠料83（或樹脂），使第一導電凸塊2a以及第二導電凸塊2b暴露於外界環境中，供後續移轉與載板相接觸。清洗步驟可以參考前述第7D圖的相關段落說明。As shown in FIG. 8B, a laser energy L3 is used to irradiate the positions of the first bonding pad 23a and the second bonding pad 23b to heat the glue 83, the first bonding pad 23a and the second bonding pad 23b. The laser energy L3 may comprise an ultraviolet (UV) laser beam, a visible laser beam or an infrared (IR) laser beam. In one embodiment, the laser energy L3 is an infrared laser beam with a wavelength in the range of 750 nm to 2,000 nm. As shown in Figure 8C, during the heating process, the first bonding pad 23a and the second bonding pad 23b are heated and melted in the glue 83, and gather on the first electrode 3a and the second electrode 3b (if the resin contains conductive particles , the conductive particles will also partially or completely move toward the first electrode 3a and the second electrode 3b after being heated), forming the first conductive bump 2a and the second conductive bump 2b with a circular arc outer surface. The glue 83 moves onto the first conductive bump 2a, the second conductive bump 2b, and the area 18 between the first electrode 3a and the second electrode 3b. After heating, the first conductive bump 2a and the second conductive bump 2b will be solidified, and the glue 83 (or resin) covering them will also heat up but not fully cured, and is in a liquid or semi-liquid state. Next, as shown in FIG. 8D, a cleaning step is performed to remove the uncured glue 83 (or resin), so that the first conductive bump 2a and the second conductive bump 2b are exposed to the external environment for subsequent transfer and The substrate is in contact. The cleaning steps can be described with reference to the relevant paragraphs of the aforementioned Figure 7D.
在另一實施例中，前述第7D、8D圖的清洗步驟中，若導電凸塊2a、2b間的膠料未完全被清除乾淨而殘留在半導體元件100上。為不影響後續移轉以及固晶的製程，殘留的膠料的最大水平高度較佳地不高於導電凸塊2a、2b。第9A圖為根據本發明另一實施例的一半導體元件20的立體示意圖。第9B圖為第9A圖中半導體元件20，沿著BB´線段的剖面示意圖。參考第9A圖，半導體元件20的上側具有兩個彼此分離的第一導電凸塊2a與第二導電凸塊2b。於第一導電凸塊2a與第二導電凸塊2b之間，具有至少一團殘餘的膠料84覆蓋在半導體元件20上。於上視圖中，殘留的膠料84具有不規則的形狀，且具有不固定的面積。參考第9B圖，半導體元件20具有半導體疊層14、保護層15、第一電極3a、第二電極3b、第一導電凸塊2a、以及第二導電凸塊2b。半導體疊層14的最外側邊19為一傾斜面，傾斜於基板10。半導體疊層14包含第一半導體層11、活性層12、以及第二半導體層13。殘留的膠料84位於第一導電凸塊2a與第二導電凸塊2b之間的保護層15之上。殘留的膠料84的最上表面不高於第一導電凸塊2a與第二導電凸塊2b的最高水平高度，且具有粗糙的外表面。因為殘餘膠料84的高度不超出導電凸塊2a、2b，所以不會影響後續的移轉以及固晶製程。In another embodiment, in the cleaning steps of FIGS. 7D and 8D , if the glue between the conductive bumps 2 a and 2 b is not completely removed, it remains on the semiconductor device 100 . In order not to affect the subsequent transfer and die-bonding processes, the maximum level of the residual glue is preferably not higher than the conductive bumps 2a, 2b. FIG. 9A is a perspective view of a semiconductor device 20 according to another embodiment of the present invention. FIG. 9B is a schematic cross-sectional view of the semiconductor element 20 in FIG. 9A along the line BB′. Referring to FIG. 9A, the upper side of the semiconductor device 20 has two first conductive bumps 2a and second conductive bumps 2b separated from each other. Between the first conductive bump 2 a and the second conductive bump 2 b, there is at least one group of residual glue 84 covering the semiconductor device 20 . In the top view, the remaining glue 84 has an irregular shape and an unfixed area. Referring to FIG. 9B, the semiconductor element 20 has a semiconductor stack 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor stack 14 is an inclined surface inclined to the substrate 10 . The semiconductor stack 14 includes a first semiconductor layer 11 , an active layer 12 , and a second semiconductor layer 13 . The remaining glue 84 is located on the protective layer 15 between the first conductive bump 2a and the second conductive bump 2b. The uppermost surface of the remaining glue 84 is not higher than the highest level of the first conductive bump 2 a and the second conductive bump 2 b, and has a rough outer surface. Because the height of the residual glue 84 does not exceed the conductive bumps 2a, 2b, it will not affect the subsequent transfer and die-bonding processes.
第10A圖為根據本發明一實施例的一半導體元件1固晶於目標基板51之示意圖。目標基板51可以為應用於顯示器中具有導電線路的電路板、TFT基板、具有重佈線路層（Redistribution Layer；RDL）基板、或是封裝體的次基板。目標基板51上具有複數個導電連接墊52。半導體元件1可以為前述的任一個結構。導電凸塊被加熱熔融並固化形成接合層53以連接半導體元件1與導電連接墊52。半導體元件1可以透過導墊連接墊52與接合層53接收電力及/或驅動訊號。接合層53可以選擇性地覆蓋導墊連接墊52的側表面521。在加熱導電凸塊形成接合層53的過程中，因為加熱溫度、加熱時間等製程參數的調整，接合層53內可能出現分散的金屬顆粒。第10B圖為根據本發明另一實施例中的一半導體元件1固晶於目標基板51之示意圖。當接合層53固化後，接合層53中出現不規則的顆粒8。換言之，接合層53中，具有離散分布、外型不規則的顆粒8散佈其中，其顆粒8的材料與接合層53不同，但與半導體元件1的電極3a、3b、及／或導墊連接墊52的部分材料相同，例如金、鉑或前述材料的合金。在一實施例中，加熱固化的方式可以施以一雷射能量，雷射能量可以包含紫外（UV）雷射光束、可見光雷射光束或紅外（IR）雷射光束。在一實施例中，紅外雷射光束，其波長介於750 nm ~ 2,000 nm的範圍內。FIG. 10A is a schematic diagram of a semiconductor device 1 die-bonded on a target substrate 51 according to an embodiment of the present invention. The target substrate 51 may be a circuit board with conductive lines applied in a display, a TFT substrate, a substrate with a redistribution layer (Redistribution Layer; RDL), or a sub-substrate of a package. The target substrate 51 has a plurality of conductive connection pads 52 . The semiconductor element 1 may have any of the aforementioned structures. The conductive bumps are heated and melted and solidified to form the bonding layer 53 to connect the semiconductor element 1 and the conductive connection pads 52 . The semiconductor device 1 can receive power and/or driving signals through the pad connection pad 52 and the bonding layer 53 . The bonding layer 53 may selectively cover the side surface 521 of the pad connection pad 52 . During the process of heating the conductive bumps to form the bonding layer 53 , due to the adjustment of process parameters such as heating temperature and heating time, dispersed metal particles may appear in the bonding layer 53 . FIG. 10B is a schematic diagram of a semiconductor device 1 die-bonded on a target substrate 51 according to another embodiment of the present invention. After the bonding layer 53 is cured, irregular particles 8 appear in the bonding layer 53 . In other words, in the bonding layer 53, particles 8 with discrete distribution and irregular appearance are scattered therein, and the material of the particles 8 is different from that of the bonding layer 53, but it is compatible with the electrodes 3a, 3b, and/or the conductive pads of the semiconductor element 1. Some of the materials of 52 are the same, such as gold, platinum or alloys of the aforementioned materials. In one embodiment, the heating and curing method may apply a laser energy, and the laser energy may include ultraviolet (UV) laser beams, visible light laser beams or infrared (IR) laser beams. In one embodiment, the wavelength of the infrared laser beam is in the range of 750 nm to 2,000 nm.
以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。The above-described embodiments are only to illustrate the technical ideas and characteristics of the present invention, and its purpose is to enable those skilled in this art to understand the content of the present invention and implement it accordingly, and should not limit the patent scope of the present invention. That is to say, all equivalent changes or modifications made according to the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.
