TW202315076A - Three-dimensional flash memory and method of forming the same - Google Patents

Abstract

Provided is a three-dimensional flash memory including a substrate, a stack structure, a stop layer, two slit trenches, a plurality of vertical channel structures, and a plurality of slit holes. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The stop layer is disposed between the substrate and the stack structure. The two slit trenches penetrate through the stack structure to expose the stop layer. The vertical channel structures are disposed between the two slit trenches and penetrate through the stack structure and the stop layer. The slit holes are discretely disposed between the vertical channel structures, and penetrate through the stack structure to expose the stop layer. A method of forming the three-dimensional flash memory is also provided.

Description

Three-dimensional flash memory and method of forming the same

The present invention relates to a memory and its forming method, and in particular to a three-dimensional flash memory and its forming method.

Non-volatile memory (such as flash memory) has the advantage that the stored data will not disappear after power failure, so it has become a type of memory widely used in personal computers and other electronic devices.

Currently, the 3D flash memory commonly used in the industry includes a negative-or (NOR) flash memory and a negative-and-type (NAND) flash memory. In addition, another type of 3D flash memory is AND flash memory, which can be applied in a multi-dimensional flash memory array and has high integration and high area utilization, and has fast operation speed. The advantages. Therefore, the development of 3D flash memory has gradually become the current trend.

The invention provides a three-dimensional flash memory including: a base, a stack structure, two adjacent slit trenches, multiple vertical channel structures and multiple slit openings. The stack structure is configured on the base. The stack structure includes a plurality of dielectric layers and a plurality of conductor layers stacked alternately. Two adjacent slit ditches run through the stacked structure. Two adjacent slit trenches have an average width of 30w. Multiple vertical channel structures are arranged between two adjacent slit trenches and run through the stacked structure. A plurality of slit openings are discretely arranged between the plurality of vertical channel structures and run through the stacked structure. The average width W of the plurality of slit openings is greater than or equal to the average width 30w of two adjacent slit trenches.

The invention provides a method for forming a three-dimensional flash memory, comprising: forming a stop layer and a stack structure on a substrate, wherein the stack structure includes a plurality of dielectric layers and a plurality of sacrificial layers stacked alternately; in the stack structure and the stop layer forming a plurality of first openings; forming a plurality of vertical channel structures in the plurality of first openings; forming a plurality of second openings exposing the stop layer in the stacked structure, wherein the plurality of second openings at least include an average width of 30w Two adjacent slit trenches and a plurality of slit openings with an average width W, a plurality of vertical channel structures are formed between the two slit trenches, and a plurality of slit openings are discretely formed in the plurality of vertical channels Between the structures, the average width W of the plurality of slit openings is greater than or equal to the average width 30w of two adjacent slit trenches; and a gate replacement process is performed through the plurality of second openings to replace the plurality of sacrificial layers for multiple conductor layers.

Based on the above, in this embodiment, a plurality of slit openings are discretely formed between the plurality of vertical channel structures, so as to increase the removal efficiency of the sacrificial layer and the filling efficiency of the conductor layer in the gate replacement process, thereby improving the three-dimensional Yield of flash memory. In this case, this embodiment can not only solve the bottleneck of the existing memory manufacturing process, but also increase the number of memory units per unit chip area, thereby improving the integration degree and area utilization rate of the memory.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar component numbers represent the same or similar components, and the following paragraphs will not repeat them one by one.

FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4A and FIG. 5 are schematic cross-sectional views of a manufacturing process of a three-dimensional AND (AND) flash memory according to an embodiment of the present invention. Fig. 4B is a schematic plan view along the line A-A of Fig. 4A. Although the following embodiments are described by taking the three-dimensional flash memory as an example, the present invention is not limited thereto. In other embodiments, the obtained memory structure can also be a three-dimensional inverting-or (NAND) flash memory or a three-dimensional inverting-or (NOR) flash memory.

Referring to FIG. 1 , first, an initial structure 10 is provided. Specifically, the initial structure 10 may include a substrate 100 , a cap layer 106 , a stop layer 108 , a stack structure 110 and a vertical channel structure 130 . In one embodiment, the substrate 100 includes a dielectric substrate. The dielectric substrate may be a dielectric layer formed on a silicon substrate, such as a silicon oxide layer. In one embodiment, the material of the capping layer 106 includes a dielectric material, such as silicon oxide. In one embodiment, the material of the stop layer 108 includes doped polysilicon material. For example, the stop layer 108 can be a P-type doped (P+) polysilicon layer.

The stack structure 110 may include a plurality of dielectric layers 112 and a plurality of sacrificial layers 114 stacked alternately. In one embodiment, the dielectric layer 112 and the sacrificial layer 114 may be different dielectric materials. For example, the dielectric layer 112 can be a silicon oxide layer; the sacrificial layer 114 can be a silicon nitride layer. The quantities of the dielectric layer 112 and the sacrificial layer 114 can be adjusted according to requirements, and the present invention is not limited thereto.

A vertical channel structure 130 may be formed in the opening 20 . As shown in FIG. 1 , the opening 20 (also referred to as the first opening) may penetrate through the stack structure 110 , the stopper layer 108 , the cover layer 106 and partially extend into the substrate 100 . Specifically, the vertical channel structure 130 may include a channel layer 132 , an insulating pillar 134 , a dielectric material 135 , a first source/drain pillar 136 and a second source/drain pillar 138 . The first source/drain column 136 and the second source/drain column 138 penetrate the dielectric material 135 and partially extend into the substrate 100 . In this embodiment, the polysilicon material 142 , 144 has the same material as the polysilicon layer 102 , 104 , such as N-type doped (N+) polysilicon material. In this case, the first source/drain column 136 may include a polysilicon layer 102 (also referred to as a first portion) embedded in the substrate 100 and a polysilicon material 142 (also referred to as a first portion) disposed on the polysilicon layer 102 (also referred to as a first portion). the second part). Similarly, the second source/drain column 138 may also include a polysilicon layer 104 embedded in the substrate 100 (also referred to as a first portion) and a polysilicon material 144 disposed on the polysilicon layer 104 (also referred to as a second portion). part two). In this embodiment, the cross-sectional area of the polysilicon layer 102 , 104 may be smaller than the cross-sectional area of the polysilicon material 142 , 144 . That is, the perimeter of the polysilicon layers 102, 104 may lie within the confines of the polysilicon material 142, 144, as shown in FIG. 4B. The insulating column 134 is disposed between the first source/drain column 136 and the second source/drain column 138 to separate the first source/drain column 136 and the second source/drain column 138 . In addition, the channel layer 132 is located on the sidewall of the opening 20 and can laterally surround the insulating pillar 134 , the dielectric material 135 , the first source/drain pillar 136 and the second source/drain pillar 138 .

As shown in FIG. 1 , the initial structure 10 may optionally include a plurality of oxide layers 124 , 128 . The oxide layer 124 can be disposed between the sacrificial layer 114 and the channel layer 132 , and the oxide layer 128 can be disposed between the stop layer 108 and the channel layer 132 . The oxide layer 124 may be formed by oxidizing the sidewall of the sacrificial layer 114 , and the oxide layer 128 may be formed by oxidizing the sidewall of the stop layer 108 . In one embodiment, the oxide layer 124 and the oxide layer 128 have different materials. For example, the oxide layer 124 may be a silicon oxynitride layer, and the oxide layer 128 may be a silicon oxide layer. In one embodiment, the oxidation treatment includes thermal oxidation, wet oxidation or a combination thereof. It should be noted that since the oxidation rate of the stop layer 108 is faster than that of the sacrificial layer 114 , the thickness of the oxide layer 128 may be greater than the thickness of the oxide layer 124 .

After the vertical channel structure 130 is formed, a gate replacement process may be performed to replace the sacrificial layer 114 in the stacked structure 110 with the conductor layer 154 , as shown in FIGS. 2 to 4B .

First, please refer to FIG. 2 , an opening 30 (also referred to as a second opening) is formed in the stack structure 110 next to the vertical channel structure 130 . The opening 30 penetrates the stack structure 110 to stop on and expose the stop layer 108 . Although the bottom surface of the opening 30 is flush with the top surface of the stop layer 108 as shown in FIG. 2 , the invention is not limited thereto. In other embodiments, the bottom surface of the opening 30 may also be higher or lower than the top surface of the stop layer 108 .

It should be noted that, in this embodiment, the opening 30 includes at least two slit trenches 30T and a plurality of slit openings 30H, as shown in FIG. 8A . Specifically, from a cross-sectional perspective, the slit trench 30T can penetrate through the stack structure 110 and expose the stop layer 108 , as shown by reference numeral 30 in FIG. 2 . From the top view of FIG. 8A , the slit trenches 30T may extend along the X direction and be arranged along the Y direction, so as to separate the plurality of vertical channel structures 130 into a plurality of array regions AR arranged along the Y direction. In this embodiment, the vertical channel structure 130 is formed between two slit trenches 30T. On the other hand, the slit openings 30H may be discretely formed between the vertical channel structures 130 of each array region AR. In this embodiment, the shape of the slit opening 30H may be a dot shape. In this case, the average diameter 30d of the slit opening 30H may be greater than or equal to the average width 30w of the slit trench 30T, that is, 30d≧30w. The average diameter 30d of the slit opening 30H may be greater than or equal to the average diameter 130d of the vertical channel structure 130 , ie, 30d≧130d. In one embodiment, the average diameter 130d of the vertical channel structure 130 may be between 100 nm and 350 nm.

Referring back to FIG. 8A , in general, if there is no slit opening 30H, the distance 35 between two adjacent slit trenches 30T may be between 1 μm and 20 μm, or less than the average of the vertical channel structure 130 200 times the diameter of 130d. When the distance 35 between two adjacent slit trenches 30T is too large, the subsequent etching process may not completely remove the sacrificial layer 114 in the middle region of the array region AR. In this case, the residual silicon nitride problem will appear in the middle region of the array region AR, which will lead to poor filling of the subsequent conductor layer (or gate). Therefore, in the conventional method, the distance 35 between two adjacent slit trenches 30T cannot be increased to accommodate more vertical channel structures 130 , and thus the accumulation degree of memory elements cannot be improved.

On the other hand, when the height of the stacked structure 110 in FIG. 2 is higher, the upper width of the opening 20 is larger than the lower width due to the high aspect ratio. When the upper width of the opening 20 is too large, the upper spacing 130s (as shown in FIG. 8A ) between two adjacent vertical channel structures 130 (or two adjacent openings 20 ) will become too small, which may cause Subsequent etching processes cannot completely remove the sacrificial layer 114 here. In this case, the residual silicon nitride problem will also appear in the area between two adjacent vertical channel structures 130 , which will lead to poor filling of subsequent conductor layers (or gate electrodes).

In order to solve the above problems, in this embodiment, a plurality of slit openings 30H are discretely formed between the plurality of vertical channel structures 130, so as to increase the removal efficiency of the sacrificial layer 114 and the conductor layer 154 in the gate replacement process ( FIG. 4A ). Fill efficiency, thereby improving the yield of memory components. In this case, the distance 35 between two adjacent slit trenches 30T may be greater than or equal to 20 μm, thereby accommodating more vertical channel structures 130 . Therefore, this embodiment can also improve the integration of memory elements.

Next, referring to FIG. 3 , an etching process is performed through the opening 30 to remove the sacrificial layer 114 to form a plurality of gaps 34 between the dielectric layers 112 . Void 34 laterally exposes oxide layer 124 . That is, the void 34 is defined by the dielectric layer 112 and the oxide layer 124 . It should be noted that the oxide layer 124 can be regarded as an etch stop layer for removing the sacrificial layer 114 in the above etching process, so as to avoid excessive etching and thus damage the channel layer 132 . In one embodiment, the etching process may be a wet etching process. For example, when the sacrificial layer 114 is silicon nitride, the etching process may be to use an etching solution containing phosphoric acid, and pour the etching solution into the opening 30 (which includes the slit trench 30T and the slit opening 30H ), thereby removing the sacrificial layer 114. Since the etchant has high etch selectivity to the sacrificial layer 114 , the sacrificial layer 114 can be completely removed, while the dielectric layer 112 , the stop layer 108 and the capping layer 106 are not removed or only slightly removed.

FIG. 8B shows an enlarged schematic view of the region 40 in FIG. 8A . In one embodiment, as shown in FIG. 8B , the first portion of the plurality of slit openings 30H in which the sacrificial layer 114 is removed in the gate replacement process has a first removal limit area A1 having a removal limit length K1 . The second removal limit area A2 of the second portion of the plurality of slit openings 30H for removing the sacrificial layer 114 in the gate replacement process has a removal limit length K2 . The first removal limited area A1 partially overlaps the second removal limited area A2. That is to say, the sum of the removal limit lengths of two adjacent slit openings 30H in the gate replacement process for removing the sacrificial layer 114 (that is, equivalent to the total removal limit diameter 2 (K1+K2)) can be It is greater than the distance D1 between two adjacent slit openings 30H, that is, 2(K1+K2)>D1. In this case, this embodiment can ensure that the sacrificial layer 114 located in the middle region of the array region AR is completely removed through the slit opening 30H.

FIG. 8C shows an enlarged schematic view of the region 50 in FIG. 8A . In one embodiment, as shown in FIG. 8B and FIG. 8C , one of the plurality of slit openings 30H removes the removal limit area A1/A2 of the sacrificial layer 114 and two slits during the gate replacement process. One of the trenches 30T partially overlaps the removal limit area A3 of the sacrificial layer 114 during the gate replacement process. That is to say, the sum (K1+K3) of the removal limit length of the sacrificial layer 114 from the slit opening 30H to the slit trench 30T in the gate replacement process may be greater than that of the slit opening 30H and the slit trench 30T. The distance D2 between 30T, that is, K1+K3>D2.

It can be seen from FIG. 8A to FIG. 8C that, in this embodiment, the slit openings 30H discretely arranged between two adjacent slit trenches 30T can be used to remove the sacrificial layer 114 located in the middle region of the array region AR, and The slit trench 30T is used to remove the sacrificial layer 114 located in the peripheral area of the array area AR. In the case of the slit opening 30H and the slit trench 30T, this embodiment can ensure that all the sacrificial layers 114 in the array area AR are completely removed through the slit opening 30H and the slit trench 30T. Therefore, this embodiment can not only solve the conventional silicon nitride residue problem, but also increase the number of vertical channel structures 130 in the array region AR, thereby improving the density and area utilization of the memory.

9 to 12 illustrate the layout of the arrangement of slit openings according to various embodiments of the present invention.

Although FIG. 8A shows that the slit openings 30H are staggered along the X direction, the present invention is not limited thereto. In other embodiments, the slit holes 30H may also be arranged in a single line along the X direction, as shown in FIG. 9 . In an alternative embodiment, the slit openings 30H may also be arranged in double lines or multi-lines along the X direction, as shown in FIG. 10 .

Although FIG. 8A to FIG. 10 illustrate that the shape of the slit opening 30H is dot-like, the present invention is not limited thereto. In other embodiments, the shape of the slit opening 30S may also be a strip shape. Specifically, as shown in FIG. 11 , the average length L of the plurality of slit openings 30S is greater than three times the average width W of the plurality of slit openings 30S, ie L>3W. The average width W of the slit opening 30S may be greater than or equal to the average width 30w of the slit trench 30T, that is, W≧30w. The average width W of the slit opening 30S may be greater than or equal to the average diameter 130d of the vertical channel structure 130 , ie W≧130d. In this embodiment, the strip-shaped slit openings 30S can be regarded as short slit trenches. Therefore, when performing the step of forming the opening 30 as shown in FIG. on the stop layer 108 . That is to say, the slit opening 30S and the slit trench 30T may have the same depth and cross-sectional profile.

In addition, although FIG. 11 shows that the slit openings 30S are arranged in a single line along the X direction, the present invention is not limited thereto. In other embodiments, the slit openings 30S may also be staggered along the X direction, as shown in FIG. 12 . In an alternative embodiment, the slit openings 30S may also be arranged in double lines or multi-lines along the X direction. In another embodiment, the dot-shaped slit trenches 30T and the strip-shaped slit openings 30S can also adopt the same arrangement of the slit-openings as shown in FIG. 11 .

Referring back to FIG. 4A and FIG. 4B , the charge storage layer 120 and the conductor layer 154 are sequentially formed in the gap 34 , thereby completing the three-dimensional flash memory 1 of the present invention. Specifically, as shown in FIG. 4A , the charge storage layer 120 conformally covers the void 34 to surround the conductive layer 154 . In an embodiment, the charge storage layer 120 may be a composite layer composed of a tunneling layer, a charge storage layer and a blocking layer. The tunneling layer, charge storage layer and blocking layer can be regarded as oxide/nitride/oxide (ONO), respectively. In one embodiment, the material of the conductive layer 154 is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide ( _WSix ) or cobalt silicide ( _CoSix ). In addition, after forming the charge storage layer 120 and before forming the conductor layer 154 , a buffer layer and a barrier layer may be sequentially formed between the charge storage layer 120 and the conductor layer 154 . The material of the buffer layer is, for example, a material with a high dielectric constant greater than 7, such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxide, Lanthanide oxides or combinations thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

In this embodiment, the three-dimensional flash memory 1 has a plurality of memory units 160 . In detail, as shown in FIG. 4A , in the three-dimensional flash memory 1 , there are four memory cells 160 stacked on top of each other. But the present invention is not limited thereto. In other embodiments, the number of memory units 160 can be adjusted along with the number of conductor layers 154 in the stacked structure 210 . In addition, although FIG. 4A and FIG. 4B only show a single vertical channel structure 130 , the present invention is not limited thereto. In an alternative embodiment, the three-dimensional flash memory 1 may include a plurality of vertical channel structures 130 , and these vertical channel structures 130 may be arranged in an array in a top view, as shown in FIG. 8A .

In order to operate the 3D flash memory 1, after manufacturing the 3D flash memory 1, conductive wires will be formed on the 3D flash memory 1 to electrically connect to the 3D flash memory Body 1. In this embodiment, some conductive lines formed above and electrically connected to the first source/drain column 136 as the source are used as source lines, and some conductive lines are formed on the second source/drain column 138 as the drain. The other conductive lines formed above and electrically connected thereto serve as bit lines, and these source lines and the bit lines are arranged parallel to each other without contacting each other.

The operation of the memory unit 160 in the three-dimensional flash memory 1 will be described below.

For the three-dimensional flash memory 1, each memory unit 160 can be operated individually. An operating voltage can be applied to the first source/drain column 136, the second source/drain column 138, and the corresponding conductor layer 154 (which can be regarded as a gate or a word line) of the memory cell 160 to perform writing ( programming) operation, read operation or erase operation. During a read operation, as shown in FIG. 4B , a voltage is applied to a selected conductor layer 154 (which may be considered a gate or word line). When the applied voltage is higher than the threshold voltage (Vth) of the corresponding memory cell 160 , the channel region in the channel layer 132 of the vertical channel structure 130 intersecting the selected conductor layer 154 will be turned on. In this case, the current will enter the second source/drain column 138 (which can be regarded as the drain column) from the bit line and flow to the first source through the conduction channel region (such as the direction indicated by the arrows E1 and E2). pole/drain post 136 (which can be considered a source post), and finally flows to the source line. Each memory unit 160 on the same vertical channel structure 130 is electrically connected in parallel.

Referring to FIG. 5 , after the gate replacement process is performed, a dielectric material may be formed to fill the opening 30 and extend to cover the top surface of the stack structure 210 . Next, a planarization process (such as a CMP process) is performed to remove excess dielectric material on the top surface of the stack structure 210 , so as to form a dielectric layer 230 in the opening 30 . In this case, the top surface of the dielectric layer 230 may be coplanar with the top surface of the stack structure 210 . In one embodiment, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.

In another embodiment, after the gate replacement process is performed, a dielectric material can be conformally formed to fill the opening 30 and extend to cover the top surface of the stack structure 210 . Thereafter, a conductive material is formed on the dielectric material. Next, a planarization process (such as a CMP process) is performed to remove excess dielectric material and conductive material on the top surface of the stacked structure 210 , so as to form a composite structure 330 in the opening 30 . In this case, the top surface of the composite structure 330 may be coplanar with the top surface of the stacked structure 210 . As shown in FIG. 6 , composite structure 330 includes conductive features 334 and dielectric layer 332 covering conductive features 334 . In one embodiment, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, and the conductive material includes polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), silicide Tungsten ( _WSix ) or Cobalt Silicide ( _CoSix ). In this embodiment, the dielectric layer 332 can be used to electrically isolate the conductor feature 334 from the conductor layer 154 (or the stop layer 108 ).

The three-dimensional flash memory 1 of the above-mentioned embodiment uses an oxide/nitride/oxide last (ONO last) process to form the charge storage layer 120 . But the present invention is not limited thereto. In other embodiments, the three-dimensional flash memory 2 can also form the charge storage layer 220 through an ONO first (ONO first) process. Please refer to the following paragraphs for details.

7A and 7B are a schematic cross-sectional view and a schematic plan view of a three-dimensional NAND flash memory according to other embodiments of the present invention.

Referring to FIG. 7A , a three-dimensional NAND flash memory 2 is provided. The 3D NAND flash memory 2 includes a substrate 500 . A stop layer 508 is formed on the substrate 500 . The stop layer 508 includes a polysilicon layer, which can be used as a common source plane (or a common source line) of the 3D NAND flash memory 2 . A stack structure 510 is formed over the stop layer 508 . The stack structure 510 includes a plurality of dielectric layers 512 and a plurality of conductive layers 554 stacked alternately. The conductive layer 554 can be regarded as a gate or a word line. The vertical channel structure 530 may include a charge storage layer 520 , a channel layer 532 and insulating pillars 534 . Referring to FIG. 7A , the insulating post 534 may penetrate the cap layer 516 , the stack structure 510 and the stop layer 508 and partially extend into the substrate 500 . The channel layer 532 is in physical contact with the conductive plug 531 . The channel layer 532 can cover the sidewall and the bottom surface of the insulating pillar 534 , and the conductive plug 531 can seal the top surface of the insulating pillar 534 . In this case, the channel layer 532 can completely cover all surfaces of the insulating pillars 534 . The charge storage layer 520 can be disposed between the channel layer 532 and the stack structure 510 . The charge storage layer 520 between the channel layer 532 and the stop layer 508 is removed. The charge storage layer 520 directly contacts the stop layer 508 .

Fig. 7B is a schematic plan view along the line B-B in Fig. 7A. The channel layer 532 laterally surrounds the insulating post 534 . The charge storage layer 520 laterally surrounds the channel layer 532 . The materials of the insulating pillars 534 , the channel layer 532 and the charge storage layer 520 are the same as those of the insulating pillars 134 , the channel layer 132 and the charge storage layer 120 described in the preceding paragraphs.

To sum up, in this embodiment of the present invention, a plurality of slit openings are discretely formed between the plurality of vertical channel structures, so as to increase the removal efficiency of the sacrificial layer and the filling efficiency of the conductor layer in the gate replacement process. , thereby improving the yield rate of the three-dimensional flash memory. In this case, this embodiment can not only solve the bottleneck of the existing memory manufacturing process, but also increase the number of memory units per unit chip area, thereby improving the integration degree and area utilization rate of the memory.

1: Three-dimensional and type (AND) flash memory 2: Three-dimensional NAND flash memory 10: Initial structure 20, 30: opening 30d: average diameter 30H, 30S: slit opening 30T: slot trench 30w: average width 34: Gap 35, D1, D2: distance 100, 500: Base 102, 104: polysilicon layer 106, 516: cover layer 108, 508: stop layer 110, 210, 510: stacked structure 112, 512: dielectric layer 114: sacrificial layer 120, 220, 520: charge storage layer 124, 128: oxide layer 130, 530: vertical channel structure 130d: average diameter 130s: upper spacing 132, 532: channel layer 134, 534: insulating column 135: Dielectric material 136: The first source/drain column 138: Second source/drain column 142, 144: polysilicon material 154, 554: conductor layer 160: memory unit 230, 332: dielectric layer 330: Composite structure 334: Conductor Characteristics 531: Conductive plug A1, A2, A3: remove limit area AR: array area E1: the first electrical path E2: Second electrical path L: average length K1, K2, K3: remove limit length W: average width X, Y: direction

FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4A and FIG. 5 are schematic cross-sectional views of a manufacturing process of a three-dimensional AND (AND) flash memory according to an embodiment of the present invention. Fig. 4B is a schematic plan view along the line A-A of Fig. 4A. FIG. 6 is a schematic cross-sectional view of a three-dimensional flash memory according to another embodiment of the present invention. 7A is a schematic cross-sectional view of a three-dimensional NAND flash memory according to another embodiment of the present invention. Fig. 7B is a schematic plan view along the line B-B in Fig. 7A. FIG. 8A illustrates a layout of an arrangement of slit openings according to an embodiment of the present invention. FIG. 8B and FIG. 8C are enlarged schematic diagrams of the regions in FIG. 8A , respectively. 9 to 12 illustrate the layout of the arrangement of slit openings according to various embodiments of the present invention.

30: opening

30d: average diameter

30H: Slit opening

30T: slot trench

30w: average width

35: Distance

130: Vertical channel structure

130d: average diameter

130s: upper spacing

AR: array area

X, Y: direction

Claims (10)

A three-dimensional flash memory, comprising: base; a stack structure configured on the substrate, wherein the stack structure includes a plurality of dielectric layers and a plurality of conductor layers stacked alternately; Two adjacent slit trenches run through the stacked structure, wherein the two adjacent slit trenches have an average width of 30w; A plurality of vertical channel structures arranged between the two adjacent slit trenches and running through the stacked structure; and A plurality of slit openings are discretely arranged between the plurality of vertical channel structures and run through the stacked structure, wherein the average width W of the plurality of slit openings is greater than or equal to that of the two adjacent slits The average width of the seam trench is 30w. The three-dimensional flash memory according to claim 1, wherein the two adjacent slit trenches extend along a first direction, and the plurality of slit openings are arranged along the first direction. The three-dimensional flash memory according to claim 1, wherein the plurality of slit openings are strip-shaped, and the average length of the plurality of slit openings is greater than the average length of the plurality of slit openings three times the width. The three-dimensional flash memory according to claim 3, wherein the distance between two adjacent slit trenches is between 1 μm and 20 μm. The three-dimensional flash memory according to claim 1, wherein each vertical channel structure includes a first source/drain column and a second source/drain column surrounded by a channel layer. The three-dimensional flash memory according to claim 1, wherein the shapes of the plurality of slit openings include dots, stripes or a combination thereof in a top viewing angle. The three-dimensional flash memory according to claim 1, wherein when the shape of the plurality of slit openings is point-like, the average diameter of the plurality of slit openings is greater than or equal to the two slits The average width of the trench, and the average diameter of the plurality of slit openings is greater than or equal to the average diameter of the plurality of vertical channel structures. The three-dimensional flash memory according to claim 1, wherein the average width of the plurality of slit openings is greater than or equal to an average diameter of the plurality of vertical channel structures. A method for forming a three-dimensional flash memory, comprising: forming a stop layer and a stack structure on the substrate, wherein the stack structure includes a plurality of dielectric layers and a plurality of sacrificial layers stacked alternately; forming a plurality of first openings in the stack structure and the stop layer; forming a plurality of vertical channel structures in the plurality of first openings; A plurality of second openings exposing the stop layer are formed in the stacked structure, wherein the plurality of second openings at least include two adjacent slit trenches with an average width 30w and a plurality of slit trenches with an average width W Slit openings, the plurality of vertical channel structures are formed between the two slit trenches, and the plurality of slit openings are discretely formed between the plurality of vertical channel structures, wherein the plurality of The average width W of each slit opening is greater than or equal to the average width 30w of the two adjacent slit trenches; and A gate replacement process is performed through the plurality of second openings to replace the plurality of sacrificial layers with a plurality of conductor layers. The method for forming a three-dimensional flash memory according to claim 9, wherein the average width of the plurality of slit openings is greater than or equal to the average diameter of the plurality of vertical channel structures.

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