TW202314965A - Self-aligned wide backside power rail contacts to multiple transistor sources - Google Patents

Abstract

Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

Description

Self-aligning wide-back power rail contacts to multiple transistor sources

Embodiments of the present disclosure relate generally to semiconductor devices. More specifically, embodiments of the present disclosure are directed to power rail structures, 3D packaging, and methods of manufacturing semiconductor elements.

The semiconductor process industry continues to strive to increase throughput while improving the uniformity of layers deposited on substrates with large surface areas. These factors, combined with new materials, also provide a higher degree of circuit integration per unit area of the substrate. As the level of circuit integration increases, so does the need for greater process control of uniformity and layer thickness. Accordingly, various techniques have been developed to deposit layers on substrates in a cost-effective manner while maintaining control over the properties of the layers.

Semiconductor elements are usually deposited on a semiconductor substrate by sequentially depositing an insulating layer or dielectric layer, a conductive layer, and a semiconductor material layer, and using lithography to pattern the various material layers to form circuit components and elements thereon. Conductive layers facilitate the electrical routing of various electrical components, including transistors, amplifiers, inverters, control logic, memory, power management circuits, buffers, filters, resonators, capacitors, inductors, resistors, and more.

Transistors are key components of most integrated circuits. Since the drive current (ie, speed) of a transistor is directly proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Consequently, there is a compromise between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to resolve the conflicting goals of having the largest drive current and smallest transistor size. FinFETs, which feature finned channel regions that greatly increase the size of transistors without significantly increasing the transistor's footprint, are now being used in many integrated circuits. However, finFETs also have their own drawbacks.

As the feature size of transistor components continues to shrink to achieve greater circuit density and higher performance, it is necessary to improve the structure of transistor components to improve electrostatic coupling and reduce negative effects, such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, Fin Field Effect Transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA element structure consists of several lattice-matched channels suspended in a stacked fashion and connected by source/drain regions. The hGAA structure provides good electrostatic control and can be widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

Connecting the semiconductors to the power rails is usually done on the front side of the battery, which requires a lot of battery area. Therefore, there is a need to connect semiconductor components to power rails using less battery area.

One or more embodiments of the disclosure are directed to methods of forming semiconductor devices. In one or more embodiments, the method for forming a semiconductor element includes: forming a superlattice structure on the top surface of the substrate, the superlattice structure includes a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of Stacking pairs; forming a plurality of source trenches and a plurality of drain trenches near the superlattice structure on the substrate; expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form source and drain cavities; depositing sacrificial material in the source and drain cavities; forming source and drain regions; forming CT and CG electrically connected to the source and drain regions; forming a damascene trench through the substrate; at least partially removing the sacrificial material to form at least one opening extending to the damascene trench; and depositing metal in the at least one opening and the damascene trench.

Additional embodiments of the disclosure are directed to methods of forming semiconductor devices. In one or more embodiments, the method for forming a semiconductor element includes: forming a superlattice structure on the top surface of the substrate, the superlattice structure includes a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of Stacking pairs; forming a gate structure on the top surface of the superlattice structure; forming a plurality of source trenches and a plurality of drain trenches near the superlattice structure on the substrate; expanding at least one of the plurality of source trenches or at least one of a plurality of drain trenches to form a source cavity and a drain cavity; a sacrificial material is deposited in the source cavity and the drain cavity; each horizontal channel layer of the plurality of horizontal channel layers forming an inner spacer layer; forming a source region and a drain region; forming an interlayer dielectric layer on the substrate; forming a replacement metal gate; forming CT and CG electrically connected to the source region and the drain region; forming a first metal lines; rotate semiconductor element 180 degrees; planarize substrate; planarize substrate; deposit interlayer dielectric material on substrate; form backside power rail vias in substrate; enlarge backside power rail vias to form damascene trenches ; removing the sacrificial material to form at least one opening; and depositing metal in the at least one opening and the damascene trench.

Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the structural details or process steps described below. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

In this specification and the appended claims, the term "substrate" refers to a surface or a portion of a surface on which a process is applied. Those skilled in the art will also understand that reference to a substrate may also refer to only a portion of a substrate, unless the context clearly dictates otherwise. Additionally, references to depositing on a substrate can refer to a bare substrate as well as a substrate having one or more films or features deposited or formed thereon.

As used herein, "substrate" refers to any substrate on which a film process is performed or the surface of a material formed on a substrate during a manufacturing process. Examples of processable substrate surfaces include silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and Any other materials such as metals, metal nitrides, metal alloys and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft target chemical groups to impart chemical functionality), anneal, and/or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in this disclosure, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate, as disclosed in detail below, whereas the term "substrate surface" It is intended to include such an underlying layer, as the context indicates. Thus, for example, when a film/layer or part of a film/layer is deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface. What a given substrate surface consists of will depend on the film being deposited, as well as the specific chemical composition used.

In this specification and the appended claims, the terms "precursor", "reactant", and "reactive gas" are used interchangeably to refer to any gaseous species that can react with the surface of the substrate.

Transistors are circuit components or elements usually formed on semiconductor components. Transistors are formed on semiconductor components in addition to capacitors, inductors, resistors, diodes, conductive lines or other elements depending on the circuit design. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions comprise doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric layer interposed between the gate electrode and the channel region in the substrate.

As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement mode field effect transistors usually exhibit very high input impedance at low temperatures. The conductivity between the drain and source is controlled by the electric field in the element, which is created by the voltage difference between the body and gate of the element. The three terminals of the FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), the terminal that regulates the channel's conductivity. Traditionally, the current entering a channel at the source (S) is called I _S , while the current entering the channel at the drain (D) is called I _D . The drain-to-source voltage is referred to as V _DS . By applying a voltage to the gate (G), the current entering the channel at the drain (ie, I _D ) can be controlled.

A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate whose voltage determines the conductivity of the element. This ability to change conductivity with the magnitude of the applied voltage is used to amplify or switch electronic signals. The basis of the MOSFET is the regulation of the charge concentration by means of a metal-oxide-semiconductor (MOS) capacitance between the body electrode and the gate electrode above the body, and is insulated from all other component areas by the gate dielectric layer . Compared to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to respective highly doped regions separated by the body region. These regions can be p-type or n-type, but they are all of the same type and the opposite type of the bulk region. The source and drain (unlike the body) are highly doped, indicated by a "+" after the doping type.

If the MOSFET is an n-channel or nMOS FET, then the source and drain are n+ regions and the body is p region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are p+ regions and the body is n region. The source is called the source because it is the source of the charge carriers (electrons for n-channels and holes for p-channels) flowing through the channel; similarly, the drain is where the charge carriers leave the channel.

The term "Fin Field Effect Transistor (FinFET)" as used herein refers to a MOSFET transistor built on a substrate in which the gates are placed on two or three sides of the channel, forming a double-gate or triple-gate structure . The FinFET component has been given the generic name of FinFET because the channel region forms the "fin" on the substrate. FinFET components have fast switching times and high current densities.

As used herein, the term "gate all around (GAA)" refers to an electronic component (eg, transistor) in which the gate material surrounds the channel region on all sides. The channel region of the GAA transistor may include nanowires or nanoplates or nanosheets, strip channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of the GAA element has a plurality of vertically spaced horizontal nanowires or bars, making the GAA transistor a stacked horizontal wraparound gate (hGAA) transistor.

The term "nanowire" as used herein refers to a nanostructure with a diameter on the order of nanometers (10 ⁻⁹ meters). Nanowires can also be defined as having a length to width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is constrained to a few tens of nanometers or less, but not limited in length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, the nanowires are made of semiconductor, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (eg, DRAM) and non-volatile (eg, NAND) components. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure with a thickness ranging from about 0.1 nm to about 1000 nm.

Embodiments of the disclosure are described with reference to drawings illustrating elements (eg, transistors) and processes for forming the transistors in accordance with one or more embodiments of the disclosure. The processes shown are only illustrative of possible uses of the disclosed processes, and skilled artisans will recognize that the disclosed processes are not limited to the illustrated applications.

One or more embodiments of the disclosure are described with reference to the drawings. In the method of one or more embodiments, a transistor, such as a wraparound gate transistor, is fabricated using standard process flows. In some embodiments, a silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. An epitaxial layer (eg, epitaxial silicon) is deposited. The wafer is then subjected to components and front-end processes. After front-end processing, the wafer undergoes hybrid bonding, such as bonding to copper or oxide, and the wafer is then advantageously thinned. Thinning the wafer provides the required flatness and bonding to enable power rails on the backside. To thin the wafer, the silicon substrate layer having an initial first thickness is ground to a second thickness, the second thickness being less than the first thickness. After grinding, in some embodiments, the silicon wafer is subjected to chemical mechanical polishing (CMP) followed by etching and CMP polishing to reduce the thickness of the silicon to a third thickness that is less than the second thickness. In one or more embodiments, the etch stop is at a buried etch stop layer. The contacts are then pre-filled with metal and metallized.

In an alternative embodiment, standard process flows are used to fabricate transistors, such as wraparound gate transistors. In some embodiments, a silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. An epitaxial layer (eg, epitaxial silicon) is deposited. The wafer is then subjected to components and front-end processes. After front-end processing, the wafer undergoes hybrid bonding, such as bonding to copper or oxide, and the wafer is then advantageously thinned. Thinning the wafer provides the required flatness and bonding to enable power rails on the backside. To thin the wafer, the silicon substrate layer having an initial first thickness is ground to a second thickness, the second thickness being less than the first thickness. After grinding, a large mask is deposited and vias are formed in the mask. The wafer is then etched through the vias to the buried etch stop layer, which is then selectively removed and liftoff occurs.

In the method of one or more embodiments, a transistor, such as a wraparound gate transistor, is fabricated using standard process flows. After the source/drain cavity is recessed, the size of the source/drain cavity is enlarged and a sacrificial fill material is deposited. During fabrication, inner spacers are formed, source/drain epitaxy, interlayer dielectric formation, replacement gate formation, CT and CG formation, and front metal line formation. The substrate is then flipped and planarized. The ILD is deposited on the backside, the backside power system vias are patterned, and the ILD is etched. A damascene trench is formed, and the sacrificial fill is removed to form an opening. Metal is deposited in the openings and then backside metal lines are formed. In one or more embodiments, the sacrificial fill material has good selectivity to form self-aligned trenches and/or vias when etched to avoid dislocations.

In the method of one or more embodiments, a transistor, such as a wraparound gate transistor, is fabricated using standard process flows. Deep holes are etched with a separate mask, or with a conventional contact or via mask. After etching the regular vias, a mask is placed, and then the power rail vias are etched to a depth below the component for backside connections. Both standard holes and deep holes/contacts are simultaneously filled with titanium nitride/tungsten (TiN/W) or titanium nitride/ruthenium (TiN/Ru) or molybdenum (Mo) contacts and then planarized. Wafers can be selectively thinned. On the backside, vias are etched to connect to the deep holes. Metallization is then performed.

FIG. 1A depicts a process flow diagram of a method 6 of forming a semiconductor device according to certain embodiments of the present disclosure. FIG. 1B is a continuation of the process flow diagram of FIG. 1A depicting method 6 according to one or more embodiments. 2A-2U depict stages in the fabrication of semiconductor structures according to certain embodiments of the disclosure. Method 6 will be described below with reference to FIGS. 2A-2U . 2A-2U are cross-sectional views of an electronic component, such as a GAA, according to one or more embodiments. Method 6 may be part of a multi-step manufacturing process for a semiconductor device. Accordingly, Method 6 may be performed in any suitable process chamber coupled to a cluster tool. A cluster tool may include a process chamber for fabricating semiconductor elements, such as a chamber configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other chamber for fabricating semiconductor elements appropriate chamber.

2A-2U are fabrication steps for operations 8 through 54 in FIGS. 1A-1B . Referring to FIG. 1A , method 6 of forming component 100 begins with operation 8 , providing substrate 102 . In some embodiments, substrate 102 may be a bulk semiconductor substrate. As used herein, the term "semiconductor substrate bulk" refers to a substrate that is composed entirely of semiconductor materials. The bulk of the semiconductor substrate may comprise any suitable semiconductor material and/or combination of semiconductor materials to form a semiconductor structure. For example, the semiconductor layer may comprise one or more materials such as crystalline silicon (eg, Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped Doped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide or other suitable semiconducting materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 includes a semiconductor material such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination. In one or more embodiments, the substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials from which substrates can be formed are described herein, it is within the spirit and scope of this disclosure to use any material upon which passive and active electronic components (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronics, or any other electronic components).

In some embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor that is created by doping an electron-donating element into an intrinsic semiconductor during fabrication. The term n-type comes from the negative charge of electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. The term "p-type" as used herein refers to the positive charge of the well (or hole). In contrast to n-type semiconductors, p-type semiconductors have a greater concentration of holes than electrons. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

Referring to FIG. 1A , in some not-illustrated embodiments, at operation 10 an etch stop layer may be formed on the top surface of the substrate. The etch stop layer may comprise any suitable material known to those skilled in the art. In one or more embodiments, the etch stop layer includes silicon germanium (SiGe). In one or more embodiments, the etch stop layer has a high germanium (Ge) content. In one or more embodiments, the germanium content is in the range of 30% to 50%, including the range of 35% to 45%. Without intending to be bound by theory, applicants believe that a germanium content in the range of 30% to 50% increases the selectivity of the etch stop layer and minimizes stress defects. In one or more embodiments, the thickness of the etch stop layer is in the range of 5 nm to 30 nm. The etch stop layer can be used as an etch stop for planarization (eg, CMP), dry or wet etch during the backside process.

In one or more non-illustrated embodiments, at operation 12 an epitaxial layer (eg, epitaxial silicon) may be deposited on the etch stop layer. The thickness of the epitaxial layer may be in the range of 20 nm to 100 nm.

Referring to FIGS. 1A and 2A , in one or more embodiments, at operation 14 at least one superlattice structure 101 is formed on the top surface of the substrate 102 or on top of the etch stop layer and the epitaxial layer. The superlattice structure 101 includes a plurality of semiconductor material layers 106 and a corresponding plurality of horizontal channel layers 104 alternately arranged in a plurality of stacked pairs. In some embodiments, the plurality of stacked layer sets includes silicon (Si) and silicon germanium (SiGe) sets. In some embodiments, the plurality of semiconductor material layers 106 includes silicon germanium (SiGe), and the plurality of horizontal channel layers 104 includes silicon (Si). In other embodiments, the plurality of horizontal channel layers 104 includes silicon germanium (SiGe), and the plurality of semiconductor material layers 106 includes silicon (Si).

In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 may include any number of lattice-matched material pairs suitable for forming the superlattice structure 204 . In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 include about 2 to about 50 pairs of lattice matching materials.

In one or more embodiments, the thickness of the plurality of semiconductor material layers 106 and the plurality of horizontal channel layers 104 is in the range of about 2 nm to about 50 nm, and in the range of about 3 nm to about 20 nm. within, or within the range of about 2 nm to about 15 nm.

Referring to FIGS. 1A and 2B , in one or more embodiments, at operation 16 the superlattice structure 101 is patterned to form openings 108 between adjacent stacks 105 . Patterning can be accomplished by any suitable means known to those skilled in the art. The term "opening" as used in this context refers to any intentional surface irregularity. Suitable examples of openings include, but are not limited to, trenches having a top, two sidewalls, and a bottom. The openings may have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1. 1.

Referring to FIGS. 1A and 2C , at operation 18 , shallow trench isolation (STI) 110 is formed. As used herein, the term "shallow trench isolation (STI)" refers to an integrated circuit feature that prevents current leakage. In one or more embodiments, STI is achieved by depositing one or more dielectric materials, such as silicon dioxide, to fill the trenches or openings 108, and removing the excess dielectric using techniques such as chemical mechanical planarization. Forming.

Referring to FIGS. 1A and 2D , in some embodiments, an alternate gate structure 113 (eg, a dummy gate structure) is formed over and adjacent to the superlattice structure 101 . The dummy gate structure 113 defines the channel region of the transistor device. The dummy gate structure 113 may be formed using any suitable conventional deposition and patterning process known in the art.

In one or more embodiments, the dummy gate structure includes one or more of gate 114 and polysilicon layer 112 . In one or more embodiments, the pseudo-gate structure includes tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium One or more of aluminum (TiAl) and N-type doped polysilicon.

Referring to FIGS. 1A and 2E , in some embodiments, at operation 22 , sidewall spacers 116 are formed along the outer sidewalls of the dummy gate structure 113 and on the superlattice 101 . The sidewall spacers 116 may include any suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and the like. In some embodiments, the sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma assisted atomic layer deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, phase deposition or isotropic deposition.

Referring to FIGS. 1A and 2F , at operation 24 , in one or more embodiments, source/drain trenches 118 are formed adjacent to (ie, on both sides of) superlattice structure 101 .

Referring to FIGS. 1A and 2G , at operation 26 , in one or more embodiments, source/drain trenches 118 are deepened and enlarged to form cavities 119 under superlattice structure 101 . Cavity 119 may have any suitable depth and width. In one or more embodiments, cavity 119 extends through shallow trench isolation 110 to substrate 102 . In one or more embodiments, the cavity 119 etch and dummy fill extend below the shallow trench isolation 110 and maximally to the silicon germanium (SiGe) etch stop layer, thereby enabling self-aligned contacts without bumping. touch element.

Cavity 119 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, a hard mask 117 is deposited to block non-V _ss /V _dd sources/drains. In one or more embodiments, hard mask 117 may comprise suitable materials known to those skilled in the art. In some embodiments, hard mask 117 is a resist. Once the hard mask 117 is formed, the cavity 119 is formed by etching.

The etch process of operation 26 may include any suitable etch process that is selective to the source-drain trench 118 . In some embodiments, the etching process of operation 26 includes one or more of a wet etching process or a dry etching process. The etch process may be a directional etch.

In some embodiments, the dry etch process may include conventional plasma etch or a remote plasma assisted dry etch process, such as the SiCoNi ^™ etch process, available from Applied Materials, Inc. of Santa Clara, CA. In the SiCoNi ^™ etch process, the device is exposed to _H2 , _NF3 and/or _NH3 plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, components may be simultaneously exposed to _H2 , _NF3 , and _NH3 plasmas. The SiCoNi ^TM etch process can be performed in a SiCoNi ^TM Preclean chamber that can be integrated into a variety of multi-process platforms, including the Centura ^® , Dual ACP, Producer ^® GT and Endura ^® platforms, available from Applied Materials ^® . The wet etch process may include a hydrofluoric acid (HF) final process, the so-called "HF final" process, in which the surface is hydrogen-terminated by HF etching. Alternatively, any other liquid-based pre-epitaxy pre-cleaning process can also be used. In some embodiments, the process includes sublimation etching to remove native oxide. Etching processes can be plasma-based or thermal. The plasma process can be any suitable plasma (eg, conductively coupled plasma, inductively coupled plasma, microwave plasma).

Referring to FIGS. 1A and 2H , at operation 28 , sacrificial material 120 is deposited in cavity 119 . The sacrificial material may comprise any suitable material known to those skilled in the art. In some embodiments, the sacrificial material 120 includes silicon germanium (SiGe). In one or more embodiments, sacrificial material 120 has a high germanium (Ge) content. In one or more embodiments, the germanium content is in the range of 30% to 50%, including the range of 35% to 45%. Without intending to be bound by theory, applicants believe that a germanium content in the range of 30% to 50% results in increased selectivity of the sacrificial material and minimizes stress defects.

In one or more embodiments, the sacrificial material 120 is doped with dopants for reducing contact resistance. In some embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In a specific embodiment, the sacrificial material 120 is silicon germanium with a germanium content in the range of 30% to 50% and doped with a material selected from the group consisting of boron (B), gallium (Ga), phosphorus (P) and arsenic (As). A dopant of one or more of them.

Referring to FIGS. 1A and 2I , at operation 30 , an inner spacer layer 121 is formed on each horizontal channel layer 104 . The inner spacer layer 121 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the inner spacer layer 121 includes a nitride material. In a specific embodiment, the inner spacer layer 121 includes silicon nitride.

Referring to FIGS. 2J and 1A , at operation 32 , embedded source/drain regions 122 are formed in source/drain trenches 118 in some embodiments. In some embodiments, source region 122 is formed adjacent to a first end of superlattice structure 101 , and drain region 122 is formed adjacent to a second, opposite end of superlattice structure 101 . In some embodiments, the source and/or drain regions 122 are formed of any suitable semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphorus (SiP), Silicon arsenic (SiAs), etc. In some embodiments, the source/drain regions 122 may be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the source/drain regions 122 are independently doped with one or more of phosphorus (P), arsenic (As), boron (B) and gallium (Ga).

In some embodiments, referring to FIGS. 1A and 2K , at operation 34 , an interlayer dielectric (ILD) layer 124 is blanket deposited on the substrate 102 , including source/drain regions 122 , dummy gate structures 113 and sidewall spacers 116 . ILD layer 124 may be deposited using conventional chemical vapor deposition methods (eg, plasma assisted chemical vapor deposition and low pressure chemical vapor deposition). In one or more embodiments, the ILD layer 124 is formed of any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (eg, BPSG, PSG), silicon nitride, and Silicon oxynitride. In one or more embodiments, the ILD layer 124 is then polished using conventional chemical mechanical planarization methods to expose the tops of the dummy gate structures 113 . In some embodiments, the ILD layer 124 is polished to expose the tops of the dummy gate structures 113 and the tops of the sidewall spacers 116 .

The dummy gate structure 101 can be removed to expose the channel region 108 of the superlattice structure 101 . The ILD layer 124 protects the source/drain region 122 during the removal of the dummy gate structure 113 . The dummy gate structure 113 can be removed using any conventional etching method (eg, plasma dry etching or wet etching). In some embodiments, the dummy gate structure 113 includes polysilicon, and the dummy gate structure 113 is removed by a selective etching process. In some embodiments, the dummy gate structure 113 includes polysilicon, and the superlattice structure 101 includes alternating layers of silicon (Si) and silicon germanium (SiGe).

Referring to FIG. 1B and FIG. 2L , at operation 38 , the formation of the semiconductor element (eg, GAA) continues in the conventional flow with nanosheet release and replacement metal gate formation. Specifically, in one or more non-illustrated embodiments, the plurality of semiconductor material layers 106 are selectively etched between the plurality of horizontal channel layers 104 in the superlattice structure 101 . For example, when the superlattice structure 101 is composed of a silicon (Si) layer and a silicon germanium (SiGe) layer, the silicon germanium (SiGe) is selectively etched to form channel nanowires. A plurality of semiconductor material layers 106, such as silicon germanium (SiGe), can be removed using any known etchant, and the etchant is selective to the plurality of horizontal channel layers 104, wherein the etching rate of the etchant for the plurality of semiconductor material layers 106 is Significantly higher than the plurality of horizontal channel layers 104 . In some embodiments, a selective dry etch or wet etch process may be used. In some embodiments, when the plurality of horizontal channel layers 104 are silicon (Si) and the plurality of semiconductor material layers 106 are silicon germanium (SiGe), a wet etchant may be used to selectively remove the silicon germanium layer, wet etching Agents such as but not limited to carboxylic acid/nitric acid/HF aqueous solution and citric acid/nitric acid/HF aqueous solution. The removal of the semiconductor material layers 106 leaves gaps between the horizontal channel layers 104 . The gap between the plurality of horizontal channel layers 104 has a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layer 104 forms a vertical array of channel nanowires coupled to source/drain regions 122 . The channel nanowires are parallel to the top surface of the substrate 102 and aligned with each other to form a single row of channel nanowires.

In one or more embodiments, a high-k dielectric is formed. The high-k dielectric can be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. The high-k dielectric of some embodiments includes hafnium oxide. In some embodiments, a conductive material such as titanium nitride (TiN), tungsten (W), cobalt (Co), aluminum (Al), etc. is deposited on the high-k dielectric to form the replacement metal gate 128 . The conductive material may be formed using any suitable deposition process, such as but not limited to atomic layer deposition (ALD), to ensure formation of a layer of uniform thickness surrounding each of the plurality of channel layers.

Referring to FIGS. 1B and 2M , at operation 38 , a contact to the transistor (CT) 132 and a contact to the gate (CG) 134 are formed.

Referring to FIGS. 1B and 2N , at operation 40 , a metal ( M0 ) line 142 is formed and electrically connected to a via ( V1 ) 144 . This is similar to the traditional process, except that the M0 line has no power rail, thus creating ample space for the signal line.

Referring to FIG. 2O, at operation 42, the component 100 is rotated or flipped 180 degrees so that the substrate 102 is now at the top of the drawing. Additionally, in one or more embodiments, the substrate 102 is planarized. Planarization may be any suitable planarization process known to those skilled in the art, including but not limited to chemical mechanical planarization (CMP). In one or more embodiments, the front side is bonded with copper (Cu) metallization on the last layer prior to spinning, with hybrid bonding (oxide-to-oxide, Cu-to-Cu) or electrostatic pseudo-wafer bonding.

Referring to FIGS. 1B and 2P , at operation 44 an interlayer dielectric 146 / 148 is deposited on the backside. ILD material 146/148 may be deposited by any suitable means known to those skilled in the art. The interlayer dielectric material 146/148 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the ILD material 146/148 includes one or more of silicon nitride (SiN), carbide, or boron carbide to enable high aspect ratio etching and metallization.

As shown in FIG. 2Q , at operation 46 , in one or more embodiments, backside power rail vias 152 are formed. The via hole 152 can be formed by any suitable means known to those skilled in the art. In one or more embodiments, via 152 may be formed by patterning and etching ILD material 146/148.

Referring to FIGS. 1B and 2R , at operation 48 , damascene trenches 154 are formed by enlarging vias 152 to contacts 120 , 122 . Enlarging via 152 to form trench 154 at least doubles the size of the opening allows self-alignment. In one or more embodiments, via 152 starts with dimensions of approximately 16 nm by 26 nm and expands to form trench 154 having dimensions of approximately 90 nm by 74 nm.

The damascene trench 154 stops at the contacts 120 , 122 . The damascene trenches 154 may have any suitable aspect ratio known to those skilled in the art. In some embodiments, the aspect ratio is greater than or equal to about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1. 1. In one or more embodiments, the critical dimension of the damascene trench 154 is about 16 nm by 26 nm, or about 10 nm by 30 nm, or about 15 nm by 30 nm. In one or more embodiments, the height of the backside via depends on the thickness of the original epitaxial layer deposited on the etch stop layer.

At operation 50 , as shown in FIG. 2S , sacrificial layer 120 is selectively removed to form opening 156 on source/drain 122 . In one or more embodiments, if the sacrificial layer 120 is doped with one or more of Ga, B, P, it may be partially removed leaving some sacrificial layer 120 . Partial removal of the sacrificial layer 120 may form a low-resistivity contact to the remaining sacrificial layer 120 (eg, SiGe).

At operation 52 , as shown in FIG. 2T , a metal fill 156 is deposited in opening 156 formed after removal of sacrificial layer 120 . Metal fill 156 may comprise any suitable material known to those skilled in the art. In one or more embodiments, metal filler 156 is selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt One or more of (Co), copper (Cu), ruthenium (Ru), and the like.

Referring to FIGS. 1B and 2U , at operation 54 , a backside metal line ( M0 ) 160 is formed. Without intending to be bound by theory, applicants believe that placing the power rails on the backside can result in cell area gains in the range of 20% to 30%.

FIG. 3 illustrates a process flow diagram of a method 60 for thinning a semiconductor wafer according to some embodiments of the present disclosure. 4A-4E depict wafer thinning stages according to some embodiments of the present disclosure. Method 60 will be described below in conjunction with FIGS. 4A-4E . 4A-4E are cross-sectional views of an electronic component, such as a GAA, according to one or more embodiments. Method 60 may be part of a multi-step manufacturing process for a semiconductor device. Accordingly, method 60 may be performed in any suitable process chamber coupled to a cluster tool. A cluster tool may include a process chamber for fabricating semiconductor elements, such as a chamber configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other appropriate chambers.

4A-4E are fabrication steps of operations 62 through 76 in FIG. 3 . Referring to FIG. 3 , method 60 of thinning element 400 begins at operation 62 . Referring to Figures 3 and 4A-4E, in the method of one or more embodiments, a transistor, such as a wraparound gate transistor, is fabricated using standard process flows.

In some embodiments, a silicon wafer 402 is provided and at operation 62 a buried etch stop layer 404 is formed on the silicon wafer. Buried etch stop layer 404 may comprise any suitable material known to those skilled in the art. In one or more embodiments, buried etch stop layer 404 includes silicon germanium (SiGe). In one or more embodiments, buried etch stop layer 404 has a high germanium (Ge) content. In one or more embodiments, the germanium content is in the range of 30% to 50%, including the range of 35% to 45%. Without intending to be bound by theory, applicants believe that a germanium content in the range of 30% to 50% results in increased selectivity of the buried etch layer 404 and minimizes stress defects.

In one or more non-illustrated embodiments, at operation 64 an epitaxial layer (eg, epitaxial silicon) is deposited. The wafer is then placed in component and front-end processing at operation 66 . The front-end process may be the process described above with respect to method 6 illustrated in FIGS. 1A-1B and the cross-sectional views in FIGS. 2A-2U .

3 and 4B, at operation 68, in one or more embodiments, after front-end processing, wafer 400 undergoes hybrid bonding (e.g., to copper or to oxide), and the wafer is then advantageously Thinned. Without intending to be bound by theory, applicants believe that thinning the wafer is beneficial in providing the required flatness and bonding to enable backside power rails.

In one or more embodiments, referring to FIGS. 3 and 4C , to thin the wafer, at operation 70 , the silicon substrate layer 402 having an initial first thickness t ₁ is ground to a second thickness, the second The thickness _t2 is smaller than the first thickness. The silicon substrate layer 402 may be ground by any suitable means known to those skilled in the art. In some embodiments, the silicon substrate layer 402 is subjected to chemical mechanical planarization (CMP), followed by etching and CMP polishing. The thickness of the silicon substrate layer 402 is reduced to a third thickness t ₃ , the third thickness being smaller than the second thickness. In one or more embodiments, the first thickness is in the range of 500 microns to 1000 microns. In one or more embodiments, the second thickness is in the range of 20 microns to 100 microns. In one or more embodiments, the third thickness is in the range of 1 micron to 20 microns.

Referring to FIGS. 3 and 4D , at operation 72 , the buried etch stop layer 404 is selectively removed to expose the source/drain 408 . At operation 74, the contacts 410 are then pre-filled with metal and metallized, as shown in FIG. 4E. In one or more embodiments, the contact 410 is pre-filled with a metal selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum ( One or more of Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

5A-5E illustrate alternative fabrication steps for operations 78-80 of FIG. 3 . Referring to Figure 3, the method 60 of thinning a component 400 begins at operation 62 and proceeds to operation 70, as detailed and illustrated in Figures 4A-4C.

After thinning the silicon substrate 402 by silicon grinding at operation 70 , the method may proceed to operation 78 where a large mask 502 is formed over the buried etch stop layer 404 . Mask 502 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the mask 502 is selected from one or more of carbide, boron carbide, and silicon nitride.

At operation 80 , mask 502 is etched to form a plurality of through silicon vias (TSVs) 508 extending to buried etch stop layer 404 . Vias 508 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, vias 508 are formed by etching. TSVs with dimensions on the nanometer scale allow high-density packaging of this formed component or other wafers connected to this component, without the need for conventional large TSVs, which increase cost and space in conventional 3D packaging.

At operation 82 , referring to FIGS. 3 and 5C , the buried etch stop layer 404 is selectively removed to form the opening 510 . The buried etch stop layer 404 can be selectively removed by any suitable means known to those skilled in the art. In one or more embodiments, the buried etch stop layer 404 is selectively removed by etching the sides of the device.

Referring to Figures 3 and 5D, at operation 84, the shroud 508 with the through holes 508 is lifted off the component. Lift-off may occur by any suitable means known to those skilled in the art. In one or more embodiments, lift-off allows the wafer to be thinned to a thickness in the range of 50nm to 100nm. In one or more embodiments, the lift-off results in a thinned wafer that is substantially free of defects and scratches in the component 500 . In one or more embodiments, lift-off requires lateral (isotropic etching) of the sacrificial layer 120 on the wafer, which can be achieved by Selectra® etching.

FIG. 6 illustrates a process flow diagram of a method 600 of manufacturing a semiconductor device according to some embodiments of the present disclosure. 7A-7D depict the stages of forming deep vias and backside contacts according to some embodiments of the present disclosure. Method 600 will be described below in conjunction with FIGS. 7A-7D . 7A-7D are cross-sectional views of an electronic component (eg, GAA) 700 according to one or more embodiments. Method 600 may be part of a multi-step manufacturing process for a semiconductor device. Accordingly, method 600 may be performed in any suitable process chamber coupled to a cluster tool. A cluster tool may include a process chamber for fabricating semiconductor elements, such as a chamber configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other appropriate chambers.

7A-7D are fabrication steps of operations 602 to 614 in FIG. 6 . Referring to FIG. 6 , a method 600 of forming deep vias and backside contacts begins at operation 602 . Referring to Figures 6 and 7A-7D, in method 600 of one or more embodiments, at operation 602, a transistor, such as a wraparound gate transistor, is fabricated using standard process flows. Component 700 may be formed according to the methods described with respect to FIGS. 1A-1B and 2A-2Q.

At operation 604, at least one deep via 702 is formed on the front side as shown in FIG. 7A. Deep vias 702 may be of any suitable size or shape. The deep via 702 may have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1. 1. In one or more embodiments, deep via 702 has a critical dimension of about 16 nm x 16 nm, or about 10 nm x 10 nm, or about 15 nm x 15 nm, or about 20 nm m x 20 nm.

Referring to FIGS. 6 and 7B , at operation 606 , deep via 702 may be filled with metal 704 . Metal 704 may be any suitable metal known to those skilled in the art. In one or more embodiments, metal 704 is selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co ), copper (Cu), ruthenium (Ru) and the like.

Referring to FIGS. 6 and 7C , at operation 608 bonded wafer 706 is bonded to the front side. At operation 610 , the substrate 708 may optionally be thinned according to the method described above with respect to FIG. 3 . At operation 612 , as shown in FIG. 7D , contacts 710 are then formed to electrically connect with the metal 704 in the deep via 702 . Contact 710 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the contacts 710 comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt One or more metals of (Co), copper (Cu), ruthenium (Ru) and the like. At operation 614, as shown in Figure 7D, metallization then occurs.

In some embodiments, these methods are integrated so that there is no vacuum break. In one or more embodiments, via etch (operation 80), buried sacrificial layer removal (operation 82), and substrate release lift-off (operation 84) may be integrated without vacuum breaks between operations.

Other embodiments of the disclosure are directed to a process tool 300 for forming GAA devices and methods, as shown in FIG. 8 . A variety of multi-process platforms can be used, including the Reflexion® CMP, Selectra® Etch, ^Centura® , Dual ACP, Producer® ^GT , and ^Endura® platforms available from Applied ^Materials® , as well as other process systems. Cluster tool 300 includes at least one central transfer station 314 having a plurality of sides. A robot 316 is positioned within the central transfer station 314 and is configured to move the robot blade and wafer to each of the plurality of sides.

The cluster tool 300 includes a plurality of process chambers 308, 310, and 312, also referred to as process stations, connected to a central transfer station. A variety of process chambers provide independent process areas isolated from adjacent process stations. The process chamber may be any suitable chamber, including but not limited to a pre-clean chamber, a deposition chamber, an anneal chamber, an etch chamber, and the like. The specific configuration of process chambers and components may vary from cluster tool to cluster tool and should not be considered as limiting the scope of this disclosure.

In the embodiment shown in FIG. 8 , factory interface 318 is connected to the front of cluster tool 300 . The factory interface 318 includes a chamber 302 for loading and unloading on the front 319 of the factory interface 318 .

The size and shape of the load and unload chambers 302 may vary depending on, for example, the substrates being processed in the cluster tool 300 . In the illustrated embodiment, the load and unload chamber 302 is sized to accommodate a cassette in which a plurality of wafers are placed.

Robot 304 is within factory interface 318 and is movable between loading and unloading chamber 302 . The robot 304 can transfer the wafers in the load chamber 302 to the load lock chamber 320 through the factory interface 318 . The robot 304 is also capable of transferring wafers from the load lock chamber 320 to the cassettes of the unload chamber 302 via the factory interface 318 .

Robot 316 of some embodiments is a multi-armed robot capable of independently moving more than one wafer simultaneously. Robot 316 is configured to move wafers between chambers around transfer chamber 314 . A single wafer is handled onto a wafer transport blade located at the distal end of the first robotic mechanism.

The system controller 357 communicates with the robot 316 and the plurality of process chambers 308 , 310 and 312 . The system controller 357 can be any suitable component that can control the process chamber and the robot. For example, system controller 357 may be a computer including a central processing unit (CPU) 392, memory 394, input/output 396, appropriate circuitry 398, and storage devices.

The recipes may generally be stored in the memory of the system controller 357 as software routines that, when executed by the processor, cause the process chamber to execute the processes of the present disclosure. Software routines may also be stored and/or executed by a second processor (not shown) remote from hardware controlled by the processor. Some or all of the methods of this disclosure may also be implemented in hardware. Thus, a process may be implemented in software and executed using a computer system, in hardware such as an application specific integrated circuit or other type of hardware, or as a combination of software and hardware. The software programs, when executed by the processor, turn the general-purpose computer into a special-purpose computer (the controller) that controls the operation of the chamber to execute the process.

In some embodiments, the system controller 357 is configured to control the RTP chamber to crystallize the template material.

In one or more embodiments, the process tool includes: a central transfer station, including a robot configured to move wafers; a plurality of process stations, each process station is connected to the central transfer station and provides communication with adjacent processing stations process area separated processing area, a plurality of process stations including a template deposition chamber and a template crystallization chamber; a controller, connected to a central transfer station and a plurality of process stations, the controller is configured to activate a robot to move between the process stations wafers, and control the processes that occur in each process station.

In the context of describing the materials and methods discussed herein (particularly in the context of the claims below), the use of the terms "a" and "the" and similarly designated pronouns should be construed to encompass both the singular and the plural, except herein otherwise stated or clearly contradicted by the context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. Same. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (eg, "such as") provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating that any non-claimed element is essential to the practice of the disclosed materials and methods.

Reference throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment includes In at least one embodiment of the present disclosure. Thus, appearances of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" throughout this specification do not necessarily mean refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made in the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure may include modifications and changes within the scope of the appended claims and its equivalents.

6,60,600: method 8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,62, 64,66,68,70,72,74,76,78,80,82,84,602,604,606,608,610,612,614: Operation 100,400,500,700: components 101: Superlattice Structures 102,708: substrate 104: Horizontal channel layer 105:Stacking 106: Semiconductor material layer 108: opening 110: shallow trench isolation 112: Multi-silicon layer 113: Pseudo gate structure 114: Gate 116: side wall spacer 117: Hard mask 118: Source/drain trench 119: cavity 120: Sacrificial material 121: inner spacer layer 122: Source/drain area 124: interlayer dielectric layer 128: Replace metal gate 132: Contact to transistor 134: Contact to gate 142: Metal (M0) wire 144: Through hole (V1) 146,148: interlayer dielectric 152: Through hole 154: mosaic groove 156: opening 160: Back side metal wire (M0) 300: Cluster Tools 302: Loading and unloading chamber 304,316: Robots 308,310,312: process chambers 314:Central Transfer Station 318: Factory interface 320:Loading lock chamber 355: Gas Disposal System 357: System Controller 392: central processing unit 394: memory 396: Input/Output 398: circuit 402: Silicon wafer 404: Buried etch stop layer 408: source/sink 410,710: contacts 502: mask 508: Through hole 510: opening 702: deep through hole 704: metal 706: Wafer Bonding

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

Figure 1A is a process flow diagram of a method according to one or more embodiments;

FIG. 1B is a continuation of the process flow diagram of FIG. 1A depicting a method according to one or more embodiments;

Figure 2A depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2B depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2C depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2D depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2E depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2F depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2G depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2H depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2I depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2J depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2K depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2L depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2M depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2N depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2O depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2P depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2Q depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2R depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2S depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2T depicts a cross-sectional view of an element according to one or more embodiments;

Figure 2U depicts a cross-sectional view of an element according to one or more embodiments;

Figure 3 depicts a process flow diagram of a method according to one or more embodiments;

Figure 4A depicts a cross-sectional view of an element according to one or more embodiments;

Figure 4B depicts a cross-sectional view of an element according to one or more embodiments;

Figure 4C depicts a cross-sectional view of an element according to one or more embodiments;

Figure 4D depicts a cross-sectional view of an element according to one or more embodiments;

Figure 4E depicts a cross-sectional view of an element according to one or more embodiments;

Figure 5A depicts a cross-sectional view of an element according to one or more embodiments;

Figure 5B depicts a cross-sectional view of an element according to one or more embodiments;

Figure 5C depicts a cross-sectional view of an element according to one or more embodiments;

Figure 5D depicts a cross-sectional view of an element according to one or more embodiments;

Figure 6 depicts a process flow diagram of a method according to one or more embodiments;

Figure 7A depicts a cross-sectional view of an element according to one or more embodiments;

Figure 7B depicts a cross-sectional view of an element according to one or more embodiments;

Figure 7C depicts a cross-sectional view of an element according to one or more embodiments;

Figure 7D depicts a cross-sectional view of an element according to one or more embodiments; and

Figure 8 depicts a clustering tool in accordance with one or more embodiments.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the various figures. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100: components

102: Substrate

104: Horizontal channel layer

106: Semiconductor material layer

110: shallow trench isolation

114: Gate

116: side wall spacer

117: Hard mask

119: cavity

Claims (20)

A method of forming a semiconductor device, the method comprising the steps of: A superlattice structure is formed on a top surface of a substrate, and the superlattice structure includes a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternately arranged in a plurality of stacked pairs; forming a plurality of source trenches and a plurality of drain trenches near the superlattice structure on the substrate; expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial material in the source cavity and the drain cavity; forming a source region and a drain region; forming a CT and CG electrically connected to the source region and the drain region; forming a damascene trench through the substrate; at least partially removing the sacrificial material to form at least one opening extending to the damascene trench; and A metal is deposited in the at least one opening and in the damascene trench. The method as described in claim 1, wherein the step of enlarging at least one of the plurality of source trenches and at least one of the plurality of drain trenches comprises the following steps: at least one of the plurality of source trenches depositing a hard mask over one and at least one of the plurality of drain trenches, and not depositing the hard mask over at least one of the plurality of source trenches and at least one of the plurality of drain trenches masking, and etching the unmasked source trench and the unmasked drain trench to form a source cavity and a drain cavity. The method of claim 1, wherein the sacrificial material is completely removed. The method of claim 1, wherein the sacrificial material comprises silicon germanium (SiGe). The method according to claim 4, wherein a germanium (Ge) content of the silicon germanium (SiGe) is in a range from 30% to 50%. The method as described in claim 4, wherein the silicon germanium (SiGe) is doped with a dopant selected from boron (B), gallium (Ga), phosphorus (P), arsenic (As) and The group formed by the combination of . The method of claim 1, wherein the step of forming the damascene trench comprises the steps of: etching at least one via hole into the substrate and enlarging the via hole to form the damascene trench. The method of claim 1, wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently comprise one or more of silicon germanium (SiGe) and silicon (Si). The method as claimed in claim 1, wherein the step of forming the source region and the drain region comprises the step of: growing an epitaxial layer thereon. The method according to claim 1, wherein the source region and the drain region are independently doped with one or more of phosphorus (P), arsenic (As), boron (B) and gallium (Ga). The method as claimed in claim 1, further comprising the step of: forming a gate structure on a top surface of the superlattice structure. The method as claimed in claim 11, further comprising the step of: forming a dielectric layer on the gate structure and the superlattice structure. The method as claimed in claim 12, wherein the gate structure comprises tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium One or more of aluminum (TiAl) and N-type doped polysilicon. The method as claimed in claim 1, wherein the metal comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co ), copper (Cu), ruthenium (Ru) in one or more. A method of forming a semiconductor device, the method comprising the steps of: A superlattice structure is formed on a top surface of a substrate, and the superlattice structure includes a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternately arranged in a plurality of stacked pairs; forming a gate structure on a top surface of the superlattice structure; forming a plurality of source trenches and a plurality of drain trenches near the superlattice structure on the substrate; expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial material in the source cavity and the drain cavity; forming an inner spacer layer on each of the plurality of horizontal channel layers; forming a source region and a drain region; forming an interlayer dielectric layer on the substrate; forming a replacement metal gate; forming a CT and CG electrically connected to the source region and the drain region; forming a first metal line; rotate the semiconductor element 180 degrees; planarizing the substrate; planarizing the substrate; depositing a layer of inter-dielectric material on the substrate; forming a backside power rail via in the substrate; enlarging the backside power rail via to form a damascene trench; removing the sacrificial material to form at least one opening; and A metal is deposited in the at least one opening and in the damascene trench. The method according to claim 15, wherein the step of enlarging at least one of the plurality of source trenches and at least one of the plurality of drain trenches comprises the following steps: at least one of the plurality of source trenches depositing a hard mask over one and at least one of the plurality of drain trenches, and not depositing the hard mask over at least one of the plurality of source trenches and at least one of the plurality of drain trenches masking, and etching the unmasked source trench and the unmasked drain trench to form a source cavity and a drain cavity. The method of claim 15, wherein the sacrificial material comprises silicon germanium (SiGe). The method of claim 17, wherein a germanium (Ge) content of the silicon germanium (SiGe) is in a range from 30% to 50%. The method as described in claim 17, wherein the silicon germanium (SiGe) is doped with a dopant selected from boron (B), gallium (Ga), phosphorus (P), arsenic (As) and The group formed by the combination of . The method as claimed in claim 15, wherein the step of forming the source region and the drain region comprises the step of: growing an epitaxial layer thereon.

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