TW202314710A - Self-repair for sequential sram - Google Patents

Abstract

In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

Description

Self-healing for Sequential Static Random Access Memory (SRAM)

This application relates to self-healing for sequential static random access memory (SRAM). Cross-references to related applications

This application claims priority under 35 U.S.C. § 119 to U.S. Provisional Patent Application No. 63/239,687, filed September 1, 2021, and U.S. Nonprovisional Patent Application No. 17/658,740, filed April 11, 2022 , the contents of which are hereby incorporated by reference in their entirety for all purposes.

Systems on a Chip (SOC) for virtual reality and augmented reality usually require low power and high performance static random-access memory (SRAM). Performing memory access operations on SRAM devices is a delicate process that can result in a functional failure in which one or more of the bit cell arrays fails; or a parametric failure in which one or more of the bit cell arrays fail The grid is slow or weak, thereby slowing down memory access. However, many conventional repair techniques result in additional device burden and/or power consumption, which is problematic for many use cases.

The present disclosure generally relates to self-healing of sequential SRAMs. According to some embodiments, a system can include a SRAM device and a controller. The SRAM device may comprise: an array of bit cells comprising a plurality of bit cells arranged in a plurality of columns and a plurality of rows, each row of the plurality of rows being operatively coupled to a pair of bit lines, wherein the plurality of rows is configured as a plurality of row groups each comprising a plurality of partial rows; a column decoder configured to operatively couple the word lines based at least in part on a column address provided to the column decoder; a column of the plurality of columns connected to the plurality of bit cells; and a plurality of row decoders, each associated with a row group of the plurality of row groups, wherein each row decoder is configured to operate the data line Ground is coupled to a local row of a plurality of local rows corresponding to a row group of a plurality of row groups associated with the row decoder. The controller can be configured to sense for a row group of the plurality of row groups by a reconfigured sequential order for a given partial row that is different from the physical sequential order of the plurality of partial rows of the row group A partial row of the plurality of partial rows included in the row group is read by measuring the voltage difference on the corresponding bit line pair.

In some examples, the reconfigured sequential order is determined based at least in part on reordering signals obtained by the controller. In some examples, the reordering signal is a binary signal. In some examples, the reconfigured sequential order is the opposite of the entity sequential order. In some examples, the reconfigured sequential order is determined based on an exclusive OR (XOR) operation of the reordering signal with bits of the row address associated with the local row.

In some examples, sensing the voltage difference on the corresponding pair of bit lines in a sequential order other than the physical sequential order of the plurality of local rows includes sensing the bit associated with the local row having the second access time. Before the voltage difference of the bit line pair, the voltage difference of the bit line pair associated with the local row having the first access time is sensed, the second access time being longer than the first access time.

In some examples, the controller is further configured to provide the column address to the column decoder such that a word line corresponding to a column of the plurality of columns associated with the column address is read during the reading of the plurality of local rows Part of the line is asserted before. In some examples, the controller is further configured to deassert wordlines after the partial rows have been read in the reconfigured sequential order.

In some examples, the signal indicative of the reconfigured sequential order is used by the row multiplexer to select a partial row of the plurality of partial rows in the reconfigured sequential order.

According to some embodiments, a system includes a SRAM device and a controller. The SRAM device may comprise: an array of bit cells comprising a plurality of bit cells arranged in a plurality of columns and a plurality of rows, each row of the plurality of rows being operatively coupled to a pair of bit lines, wherein the plurality of rows is configured as a plurality of row groups each comprising a plurality of partial rows, and wherein the plurality of rows comprises one or more redundant rows; a column decoder configured to decode, at least in part, based on providing to a column operatively coupling the word line to columns of a plurality of columns of the plurality of bit cells; and a plurality of row decoders, each associated with a row group of the plurality of row groups, Wherein each row decoder is configured to operatively couple a data line to a partial row of a plurality of partial rows corresponding to a row group of a plurality of row groups associated with the row decoder. The controller can be configured to: obtain an address of a bit cell in the bit cell array to perform a sequential memory access operation, wherein the address includes a column address, a row group identifier, and a local row address; mapping the column address, the row group identifier, and the local row address to a repair address corresponding to a repair bit cell, wherein the repair address corresponds to a redundant row of one or more redundant rows; address is provided to the column decoder such that word lines corresponding to columns of the plurality of columns associated with the column address are asserted; and performed at the repair address by selecting the redundant row corresponding to the repair address Sequential memory access operations.

In some examples, a first cell of a redundant row corresponds to a faulty cell of a first partial row, and a second cell of a redundant row corresponds to a faulty cell of a second partial row different from the first partial row. Faulty bit cell. In some examples, the column of the first cell of the redundant row is the same as the column of the failed cell of the first partial row.

In some examples, mapping the column address, row group identifier, and local row address to the repair address includes self-lookup by providing the column address, row group identifier, and local row address to a lookup table. The table gets the repair address. In some examples, the look-up table is pre-configured based on testing of the SRAM device. In some examples, the lookup table is operatively coupled to a multiplexer configured to select the redundant row corresponding to the repair address.

In some examples, the one or more redundant rows include at least two redundant rows, and wherein the at least two redundant rows are associated with different row groups of the plurality of row groups.

In some examples, the controller is further configured to precharge a set of bit lines corresponding to a plurality of local rows included in a row group corresponding to the row group identifier, and wherein Mapping the column address, row group identifier, and local row address to the repair address occurs simultaneously with precharging the set of bit lines.

In some examples, mapping the column address, row group identifier, and local row address to the repair address occurs concurrently with asserting the word line.

In some examples, at least one partial row of the row group associated with the row group identifier does not have a corresponding redundant row included in the one or more redundant rows.

According to some embodiments, a system includes a SRAM device and a controller. The SRAM device may comprise: an array of bit cells comprising a plurality of bit cells arranged in a plurality of columns and a plurality of rows, each row of the plurality of rows being operatively coupled to a pair of bit lines, wherein the plurality of rows is configured as a plurality of row groups each comprising a plurality of partial rows; a column decoder configured to operatively couple the word lines based at least in part on a column address provided to the column decoder a plurality of columns connected to the plurality of bit cells; and a plurality of row decoders, each associated with a row group of the plurality of row groups, wherein each row decoder is configured to operatively connect the data line Coupled to a local row of a plurality of local rows corresponding to a row group of a plurality of row groups associated with the row decoder. The controller may be configured to, for a row group of the plurality of row groups: provide a column address to a column decoder such that a word line corresponding to a column of the plurality of columns associated with the column address Asserted; responsive to a determination that a sequential memory access operation in a series of memory access operations is to be performed on a slow bit line of one or more bit lines having a length longer than one or more bit lines an access time of an access time associated with at least one other bit line of a bit line, thereby causing a delay in at least a subset of memory access operations of the series of memory access operations; and during a period associated with the delay At least a subset of memory access operations are performed after elapsed.

In some examples, causing a delay of at least a subset of memory access operations is in response to enabling a stall signal, and wherein performing at least a subset of memory access operations after a period associated with the delay has elapsed is in response to stalling Use the stall signal. In some examples, enabling the stall signal and disabling the stall signal is performed using a handshake protocol associated with performing the series of memory access operations. In some examples, a handshake protocol is associated with a column stride and/or a row stride for performing the series of memory access operations.

In some examples, the series of memory access operations includes a series of read operations. In some examples, the precharge of one or more bit lines is extended during a time period. In some examples, at least one subset of memory access operations includes all memory access operations in the series of memory access operations.

In some examples, the series of memory access operations includes a series of write operations. In some examples, slow bit lines are driven during periods. In some examples, at least a subset of memory access operations includes memory access operations subsequent to accessing the local row associated with the slow bit line.

In some examples, the time period corresponds to a clock cycle.

Devices, methods and techniques for self-healing of static random access memory (SRAM) devices used in sequential SRAM configurations are disclosed herein. SRAM devices configured for sequential memory access operations perform memory access operations on rows associated with a column by asserting the word line associated with the column and performing memory access operations sequentially on the row during the assertion of the word line Memory access operations (eg, read operations and/or write operations) are performed sequentially. In other words, unlike conventional SRAM memory access operations, where a word line remains in the asserted state during a series of bit cell accesses, each bit cell access is associated with a row, rather than being asserted and asserted for each access. Undo assertions with character lines. The techniques described herein utilize sequential burst accesses of rows within a column implemented in a sequential SRAM to repair bit cells that are malfunctioning (herein generally referred to as "failures") and and/or associated with bit lines that are relatively slow (eg, relative to other bit lines of the SRAM device), eg, to create a voltage difference (generally referred to herein as "parametric failure"). An overview of sequential SRAM operation is described below in conjunction with FIGS. 1A and 1B .

In some embodiments, the order of accessing the local rows is reconfigured to allow the local row associated with the relatively slower bit line to be accessed last in a sequential read operation, as described below in conjunction with FIGS. 2, 3A, 3B and as shown and described in FIG. 4 . In some embodiments, a repair address corresponding to a redundant row is identified such that the redundant row is selected during a consecutive series of operations, as shown and described below in connection with FIGS. 5-7 . Identification of repair addresses may be performed during the time initialization operations are performed for sequential SRAM operations. In some embodiments, memory access operations are delayed and/or the latency of memory access operations is extended to allow time for slower bit lines to generate voltage differences and/or drive currents.

A static random access memory (SRAM) device includes an array of cells configured as a set of columns and a set of rows. The set of rows may be configured as a set of row groups, where each row group includes a set of partial rows. Each cell is operatively coupled to a pair of bit lines (generally referred to herein as lbl and lblb ). Each column is operatively coupled to the word lines. When accessing (whether as part of a read operation or as part of a write operation) a particular cell of the array, the column address is provided to the column decoder and can be configured to activate (e.g., assert ) corresponds to the word line of the column address. During operation, a row decoder associated with a particular row group can be configured to use a row multiplexer to select a particular partial row within the row group. The row multiplexer can select a local bit line pair, which is then operatively coupled to the data line pair for performing an operation. For example, in a read operation, the read/write circuitry of the row multiplexer can sense voltages on the bit line pairs that can then be transmitted to one or more interface circuits. As another example, in a write operation, the read/write circuit drives a pair of bit lines to store a data value in a corresponding bit cell.

1A shows a schematic diagram of an implementation of a SRAM device 100 according to some embodiments. As illustrated, the SRAM device 100 has a bit cell array 102 . The bit cell array 102 includes 16 columns. The columns of the bit cell array 102 are accessible by a column decoder 103 . For example, column decoder 103 may use as input a 4-bit column address identifying one of 16 columns. The bit cell array 102 additionally includes five row groups 104 , 106 , 108 , 110 and 112 . Each row group is associated with a row decoder. For example, row group 104 is associated with row decoder 114 , row group 106 is associated with row decoder 116 , row group 108 is associated with row decoder 118 , and row group 110 is associated with row decoder 120 and row group 112 is associated with row decoder 122 . Each row group of bitcell array 102 includes four partial rows. Each row decoder may include a row multiplexer (not shown) that selects a particular partial row of a group of rows. A row multiplexer can operatively couple bit line pairs of a selected local row to a data line (eg, one of data lines 124, 126, 128, 130, or 132) associated with a row decoder. For the bit cell array 102 of FIG. 1A, a row decoder may use as input a 2-bit row address identifying one of the four partial rows.

With conventional SRAM devices, word lines corresponding to a particular column are asserted and deasserted within a single clock cycle. In other words, when multiple bit cells associated with different rows and the same column are accessed sequentially, word lines are asserted and deasserted for each access within the same column. The switching of word lines consumes power, which is problematic for devices requiring low power. Furthermore, due to the switching transitions, additional time is required for the switching of the word lines, thus requiring a slower clock period.

Sequential SRAM utilizes sequential access to cells within the same column to reduce power and minimize switching transitions. In the case of sequential SRAM, a word line associated with a particular column is asserted and remains in the asserted state during accesses to that column's multiple bit cells (eg, corresponding to different local rows). Additionally, bit lines associated with a plurality of bit cells are precharged and maintained in the precharged state for a plurality of clock cycles corresponding to a plurality of accesses.

FIG. 1B shows an example timing diagram utilizing the SRAM device shown in FIG. 1A with sequential SRAM. As illustrated, during the first clock cycle 150, the bit lines associated with a local row of a particular row group are precharged. Additionally, during the first clock cycle 150, the word line associated with a particular column is asserted. During the second clock cycle 152, a voltage difference is generated on the bit lines. During the third, fourth, fifth and sixth clock cycles (clock cycles 154-160, respectively), blocks (eg, bit cells) are accessed from local rows 0-3, respectively. During each block access, the word line remains asserted and remains precharged. After the last bit cell of the row group has been accessed (eg, after the last row of the row group has been selected), the word line is deasserted and the precharge state is disabled.

Sequential SRAM allocates memory accesses over more clock cycles than conventional SRAM. For example, in conventional SRAM, each clock cycle may be associated with a memory access, and with reference to the example shown and described above in connection with FIG. 1B , four memory accesses occur within six clock cycles. . In particular, two clock cycles are used for initialization prior to a memory access (eg, asserting a word line and precharging a bit line of a local row to be selected). Although the effective data accessed per cycle using sequential SRAM is lower than using conventional SRAM, since sequential SRAM operation does not need to switch every clock cycle (e.g., assert and deassert a word line for each memory access ), the overall device speed using sequential SRAM is faster than conventional SRAM due to the reduced switching burden. Furthermore, in some embodiments, the slower data accesses per cycle of sequential SRAM can be advantageously used to implement the repair techniques described herein. For example, in some implementations, the initialization phase may be used to identify the location of a replacement failed cell by allowing time to identify the address of the repaired cell (eg, by accessing a look up table (LUT)). The bit cells are repaired (eg, stored in redundant rows), as described below in conjunction with FIGS. 5-7 . As another example, in some embodiments, a handshake protocol used in sequential SRAMs to coordinate the timing of memory accesses and implement row strides and/or row strides when sequentially accessing bit cells may be used to coordinate The latency of a memory operation in a series of sequential memory access operations. More specifically, the delay can allow slower bit line times to create voltage differences without slowing down the operation of the overall SRAM device, as shown and described below in conjunction with FIGS. 8A, 8B and 9 .

In some cases, bit lines may discharge slowly and/or take longer to generate a voltage difference, eg, due to manufacturing variations. In conventional sequential SRAM operation, the entire SRAM device is operated at a slower clock speed to accommodate the slow bit lines. As described herein, in some embodiments, local rows can be selected in an order based at least in part on speed information associated with one or more bit lines. In other words, in some embodiments, the partial rows are selected in a reconfigured sequential order that differs from a physical sequential order of the partial rows, where the reconfigured sequential order is based at least in part on velocity information. For example, in some embodiments, local rows associated with relatively faster bit lines may be selected before local rows associated with relatively slower bit lines, allowing time for relatively slower bit lines to discharge and/or create a voltage difference. By reconfiguring the row selection order, an overall faster SRAM device speed can be achieved relative to conventional sequential SRAM technology, thereby improving parametric failure of the SRAM device. Reordering the row selection order can address parametric failures associated with slower bit lines, and by allowing overall faster SRAM device speed while addressing parametric failures, the overall parametric yield of SRAM devices can be increased. It should be noted that the slower bit lines (sometimes referred to herein as "high variation lines") can be identified during testing of SRAM devices so that the configuration reconfigures the row selection order after testing and during operation of the SRAM device be usable.

2 shows an example timing diagram for reordering row selection based on bit line speed, according to some embodiments. At point in time 202, a wordline associated with a particular column is asserted. By time point 204, the bit lines associated with local rows 1, 2, and 3 have developed sufficient voltage differences to be accessed. However, the bit lines associated with local row 0 have not developed enough voltage difference. In other words, the bitline associated with local row 0 may be considered "weak" or "slow." As illustrated by access order 206, the partial row will typically be selected in sequential order of "0," "1," "2," and "3" (eg, the physical sequential order of the partial row). However, as illustrated by access order 208, in response to information indicating that the bit line associated with local row 0 is weak or slow, the local rows may be selected in an order that places local row 0 last, such as "3," "2," "1," and "0," allowing extra time for the bit line associated with local row 0 to discharge.

In some embodiments, a row decoder associated with a row group is configured to modify the order of the local rows used to select the row group. The group of rows can be modified in order based at least in part on a repair signal generated based on information indicative of the speed of the bit lines associated with the local row. For example, the repair signal can be a binary signal indicating whether a row group includes slow or weak bit lines. In some embodiments, the row decoder may provide an order to a row multiplexer configured to select the local rows in the order indicated by the row decoder.

Figure 3A shows a schematic diagram of implementing a row decoder with row remapping. As illustrated, the bit cell array 302 is accessed using a column decoder 304 and one or more row multiplexers 306, each column decoder and row multiplexer selecting a partial row of a particular row group. For example, column decoder 304 may be configured to receive a column address (eg, N bits identifying one of 2 ^N columns) and assert the word line corresponding to the column address. Row multiplexer 306 is associated with row decoder 308 . For example, the row multiplexer 306 is operatively coupled to the row decoder 308 and/or the row decoder 308 receives signals. As illustrated, row decoder 308 may take as input a pre-repair row address (eg, M bits identifying one of 2 ^M partial rows). Row decoder 308 may additionally use as input a repair signal indicating whether the order used to select the local rows is to be modified. Row decoder 308 may then generate a repaired row address based at least in part on the repair signal. For example, post-repair row addresses may be the same as pre-repair row addresses in instances where the repair signal indicates that row selection reordering is not required. Conversely, in instances where the repair signal indicates that row select reordering is to be performed, the post-repair row address may be different from the pre-repair row address. Effectively, row decoder 308 can remap logical and physical row addresses based on the repair signal such that physical row addresses associated with relatively slower bit lines map to logical row addresses selected earlier in the sequence.

In some embodiments, the order in which the local rows are selected can be reversed in response to velocity information associated with the bit lines of the local rows. For example, in instances where the speed information indicates that local rows that are typically selected in the first half of the sequential order are associated with relatively slower bit lines, the speed information can be used to generate a fix that reverses the selection order of the local rows Signal. By way of example, in instances where the partial rows are generally selected in the order "0," "1," "2," and "3," the order can be reversed such that the partial rows are in the order "3," "2" , "1" and "0" order selection. In some embodiments, an exclusive OR (XOR) operation can be performed on a binary repair signal that indicates whether row reordering is to be performed using the bits of the row address. For example, in an instance where the repair signal is 1 and the 3-bit row address (which identifies one of the 8 partial rows) is 000, an XOR operation can be used to generate a repair address of 111 such that the first row address is selected Eight partial lines instead of the first partial line.

3B shows a schematic diagram of implementing an implementation for sequential row remapping according to some implementations. As illustrated, the row repair signal 352 indicates whether the selection order of the local rows is to be reversed. An XOR of the row repair signal 352 is then performed with the bits of the local row address to be accessed. For example, XOR gate 360 performs an XOR operation using first bit 354 and row repair signal 352 . As another example, XOR gate 362 performs an XOR operation using second bit 356 and row repair signal 362 . As yet another example, XOR gate 364 performs an XOR operation using third bit 358 and row repair signal 352 . The output of XOR gates 360-364 is provided to row decoder 366, which generates a high signal on one of row select lines 368 corresponding to the local row to be selected. By way of example, in the case where the pre-repair order of the local rows is: 000, 001, 010, 011, 100, 101, 110, and 111 and the repair signal is 1, the post-repair order of the local rows is: 111, 110, 101, 100, 011, 010, 001 and 000. It should be noted that XOR gates 360-364 perform row remapping, and row decoder 366 performs row decoding based on the remapped rows.

FIG. 4 shows an example of a process 400 for sequential remapping of local row accesses according to some specific examples. In some embodiments, the blocks of process 400 may be performed in an order other than that shown in FIG. 4 . In some embodiments, two or more blocks of process 400 may be performed substantially in parallel. In some embodiments, one or more blocks of process 400 may be omitted. In some embodiments, blocks of process 400 may be performed by a controller, such as a controller (eg, a microcontroller) of a system-on-chip (SOC) device including a SRAM device.

Process 400 may begin at block 402 by providing a pre-repair local row address and a repair signal to a repair block. The pre-repair local row address may be M bits identifying a local row in the 2 ^M local rows of a row group. In some embodiments, the repair signal may be a binary signal indicating whether the pre-repair local row address is to be mapped to the post-repair row address. In some embodiments, the repair signal can be generated based at least in part on information indicative of the relative velocity of the bit lines associated with the local row. For example, information may indicate that a particular local row is associated with a relatively slow or weak bit line. In some embodiments, the repair signal may be set in response to an indication that local rows associated with relatively slower or weaker bit lines are generally selected earlier (eg, earlier than most other local rows) information is enabled. In some embodiments, the repair block can include a series of XOR gates each corresponding to one of the bits of the pre-repair local row address.

At block 404, process 400 may obtain a post-repair local row address from the repair block. For example, the post-repair local row address may be a pre-repair local row address where the bits of the address are flipped. As a more specific example, in the case where the pre-repair local row address is 000, the post-repair local row address may be 111.

At block 406, process 400 may select the local row corresponding to the repaired local row address. Process 400 may then loop back to block 402 and repeat blocks 402-406 until all partial rows of the row group have been selected. Thus, based on the repair signal, pre-repair local row addresses have been remapped to post-repair local row addresses such that local rows are selected based on information indicative of bit line velocity (eg, discharge and/or generated voltage difference).

Conventional SRAM repair techniques include effectively replacing the entire redundant row group with a partial row group with a faulty cell or by including a redundant row that effectively replaces an entire partial row with a faulty cell to resolve a malfunction of a single faulty bit cell associated with a particular partial row. In other words, non-faulty bit cells (eg, by inclusion in redundant rows and/or groups of redundant rows) are replaced using known functional repair techniques. Conventional techniques result in increased device size. For example, using known techniques, redundant rows are used for each failed bit cell. Increasing device size can itself be problematic (for example, by requiring extra area on the SOC), as well as increasing dissipated power.

As described herein, in some embodiments, the above SRAM device implementing sequential SRAM can have one or more redundant rows, where the bit cells of the redundant rows can correspond to different partial rows. The redundant row of cells can be used to repair defective cells of the primary array of cells, thereby improving malfunction at reduced device size and reduced power dissipation relative to prior art. Furthermore, given a fixed SRAM device size (eg, a fixed size dictated by the space constraints of an SOC that includes an SRAM device), more faulty bit cells can be repaired. In some embodiments, redundant rows may replace partial rows of a particular group of rows. In some specific examples, a repair multiplexer can be used to select one of the redundant rows. In some embodiments, addresses (e.g., column identifiers, row group identifiers, and local row addresses) may be provided to the LUT to identify the addresses corresponding to the ones to be repaired (e.g., associated with faulty bit cells) A redundant row of one or more redundant rows. The output of the LUT can then be used by the repair multiplexer to select redundant rows during memory accesses, rather than partial rows that include faulty cells. It should be noted that in some embodiments, the LUT may be configured during testing of the SRAM device (eg, during factory testing) after faulty cells have been identified, and then utilized during operation.

5 shows a schematic diagram of an example implementation of redundant data rows. As illustrated in FIG. 5 , a SRAM device may have two row groups 502 and 504 . In the example shown in Figure 5, each row group includes four partial rows. Partial rows within a row group may be selected by the row multiplexer. For example, row multiplexer 506 selects partial rows within row group 502 , while row multiplexer 508 selects partial rows within row group 504 . Row multiplexers 506 and 508 are operatively coupled to read/write circuits 510 and 512, respectively. The SRAM device additionally includes redundant rows 514 . Redundant row 514 is operatively coupled to read/write circuitry 516 to allow access to the bit cells of the redundant row (eg, to perform read operations and/or write operations). Redundant row 514 includes a bit cell that replaces a failed bit cell in any partial row in row group 502 or row group 504 . For example, the first repair bit cell at the first column of redundant row 514 may replace the first failed bit cell in the first column of any partial row of row group 502 or row group 504 . Continuing with the example, the second repair bit cell at the second column of redundant row 514 may replace the second failed bit cell in the second column of any partial row of row group 502 or row group 504 . Continuing with the example, in some embodiments, the first failed bit cell may be associated with a different local row than the second failed bit cell.

6 shows a schematic diagram of an example SRAM device 600 utilizing a LUT to address bit cells of redundant rows, according to some embodiments. As illustrated, SRAM device 600 includes four row groups 602 , 604 , 606 and 608 . Although not shown in FIG. 6, each row group includes a set of partial rows that can be selected by the corresponding row decoder. Read and write operations may be performed by read/write circuitry associated with each row group. Additionally, each row group is associated with a redundant row. For example, row group 602 is associated with redundant row 610, row group 604 is associated with redundant row 612, row group 606 is associated with redundant row 614, and row group 608 is associated with redundant row 616. couplet. The redundant row may include repair bit cells, each repair bit cell corresponding to a faulty bit cell. Repair bit cells within a particular redundant row may correspond to different partial rows. In some embodiments, the columns associated with the repaired bit cell are the same as the columns associated with the corresponding failed bit cell. A column decoder is used to select the column associated with the column address (eg, by asserting the word line corresponding to the selected column).

In some embodiments, the address is provided to LUT 618 that maps the address to a repair address. For example, an address may include a column address, a row group identifier, and a local row identifier, and LUT 618 then identifies the row corresponding to the column address, row group identifier, and local row identifier. As a more specific example, in instances where the address provided to LUT 618 corresponds to a failed bit cell, LUT 618 identifies the repair address associated with the redundant row that includes the repaired bit cell corresponding to the failed cell. . In some embodiments, the repair address is associated with the same row as the row of faulty cells. The output of LUT 618 (eg, repair address) is then provided to repair multiplexer 620, which selects redundant rows during memory access operations (eg, read operations or write operations). Data can be stored and/or provided via the corresponding interface 622 . It should be noted that, as used herein, a repair address may refer to a control signal used by a repair multiplexer (e.g., repair multiplexer 620) to select a particular redundant row that includes replacing a corresponding faulty bit Grid repair bit grid.

FIG. 7 shows an example of a process 700 of exploiting redundancy, according to some embodiments. In some embodiments, blocks of process 700 may be performed by a controller that controls the operation of the SRAM device, such as a controller that also includes the SRAM device's SOC. In some embodiments, the blocks of process 700 may be performed in an order other than that shown in FIG. 7 . In some embodiments, one or more blocks of process 700 may be omitted. In some embodiments, two or more blocks of process 700 may be performed substantially in parallel.

At block 702, process 700 may obtain addresses of groups of bit cells in the bit cell array on which sequential memory access operations are to be performed. The address information may include a column address corresponding to a particular column of the bitcell array, a row group identifier identifying a particular row group of the bitcell array, and a specific row group identifier identifying the row group corresponding to the row group identifier. The partial row identifier for the partial row. It should be noted that the array of cells may include one or more redundant rows each configured to store one or more repair cells to replace a corresponding failed cell. In some embodiments, within a redundant row, repair bit cells may correspond to different partial rows and/or different row groups. For example, a first repair cell of a redundant row may be associated with a first faulty cell of a first partial row, and a second repair cell of a redundant row may be associated with a second repair cell of a second partial row. The faulty bit cells are associated, wherein the first partial row and the second row are different. Additionally, the first partial row and the second partial row may be associated with different row groups. In some embodiments, the repaired bit cell can be associated with the same column as the corresponding failed bit cell. For example, in an instance where the faulty cell is in column 1, the repaired cell may be in the redundant row at column 1.

At block 704, process 700 may precharge the local bit lines associated with the row group corresponding to the row group identifier. As described above, precharging local bit lines may allow local rows of a row group to be adjusted prior to sequential memory access operations. Precharging a local bit line can be considered as part of an initialization phase of a series of sequential memory access operations, where the initialization phase is unique with respect to sequential SRAM operations of conventional SRAM operations, as described above in connection with FIG. 2 .

At block 706, process 700 may assert the wordline. A word line may correspond to a column associated with a column address. The assertion of word lines may be considered part of the initialization phase of the series of sequential memory access operations, where the initialization phase is unique to sequential SRAM operations relative to conventional SRAM operations, as described above in connection with FIG. 2 .

Identification of a repair address corresponding to the address obtained at block 702 occurs at blocks 708 and 710 . It should be noted that blocks 708 and 710 may be performed substantially in parallel with blocks 702 and 704 . That is, blocks 708 and/or 710 may occur concurrently with precharging a local bit line at block 704 and/or asserting a word line at block 710 . In other words, blocks 708 and 710 may occur during an initialization phase that is unique relative to sequential SRAM operations of conventional SRAM operations, thereby allowing identification of repair addresses to occur during the initialization phase.

At block 708, process 700 may provide the address of the bitcell to the LUT to identify the repair address corresponding to the redundant row of the bitcell array. The repair address may indicate the row address of the redundant row selected to address the repair address. In some embodiments, the repair address may be a control signal that causes the redundant row to be selected instead of the local row corresponding to the local row identifier. In some embodiments, the LUT may be stored in memory associated with a controller performing process 700 .

At block 710, process 700 can address redundant rows. For example, process 700 may use a repair multiplexer to select redundant rows rather than select local rows associated with addresses obtained at block 702 (eg, pre-repair addresses).

At block 712, process 700 may perform a memory access operation at the repair address. For example, in instances where the sequential memory access operation is a read operation, process 700 may activate a sense circuit of the read/write circuit that causes the bit line associated with the redundant row to The voltage difference across the pair is sensed and/or recorded as a data value. As another example, in instances where the sequential memory access operation is a write operation, the process 700 may activate driver circuitry that drives bit line pairs associated with redundant rows to store values in and repair in the repair bit cell associated with the address.

In some embodiments, process 700 may then proceed to perform subsequent sequential memory access operations by accessing bit cells associated with the same column and different partial rows of the row group. Process 700 may then loop through the partial rows of the row group. After looping through the local rows of the row group, process 700 may cause the word line to be deasserted. By way of example, in an instance where column 1 is accessed and the faulty bit cell is located at column 1, row 3, process 700 may assert the word line corresponding to column 1, and then access row 1, row 2, using The LUT identifies redundant rows and row 4, and then deasserts the word line corresponding to column 1 . It should be noted that in some specific examples, a redundant row may only be selected once for a particular column access. In other words, in some embodiments, when a redundant row can store a repair cell corresponding to a faulty cell of a different local row, a column bit 0 between the faulty cell and the corresponding repair cell can be reserved site.

It should be noted that by performing blocks 708 and 710 substantially in parallel with blocks 704 and 706, process 700 can take advantage of the time required to precharge a local bit line (at block 704) and cause the word line to pass through Asserted (at block 706) to identify the repair address and address the redundant row associated with the repair address. In other words, since precharging local bit lines during bursts of sequential memory access operations requires additional time when utilizing sequential SRAM devices relative to conventional SRAM devices, using a lookup table to identify specific redundant rows can Utilize the extra time required, thereby reducing the load on the SRAM device. By allowing time to identify redundant rows, individual faulty cells can be replaced from multiple different partial rows rather than replacing an entire row due to one faulty cell, thereby resolving functional failures while reducing device burden.

In some embodiments, the parametric yield of SRAM devices can be achieved by modifying the latency of performing memory access operations on local rows associated with slow access times while maintaining memory execution on local rows with faster access times To improve the latency of bank access operations. In other words, additional latency may be provided for the slowest local row to perform memory access operations, which may allow an overall increase in the speed of the SRAM device, rather than slowing down sequential memory access operations across the entire SRAM device to accommodate the slowest local row . It should be noted that slower local rows may be identified during SRAM device testing (eg, factory testing). Using delay periods for identified slower local rows may then be hardwired or hard-coded for use during operation of the SRAM device. In other words, slower local rows need not be identified during operation of the SRAM device.

It should be noted that sequential SRAM operations generally require a handshake protocol to coordinate the timing of sequential memory access operations. For example, the handshake protocol can be used to accommodate various column strides and/or row strides in which not contiguous columns or rows are selected, but every Nth column or row is selected. Techniques described herein for increasing the latency of performing certain memory access operations (eg, for memory access operations associated with relatively slower bit lines) may utilize handshaking protocols. For example, in some embodiments, a handshake protocol may be used to coordinate the latency of certain memory access operations. As a more specific example, in some embodiments, a handshake protocol may be used to enable and/or disable stall signals that cause delays. By utilizing the handshaking protocol required by sequential SRAM, the parametric yield of SRAM devices can be improved with relatively little overhead.

In some embodiments, additional time may be provided for local rows associated with bit lines that generate voltage differences relatively slowly to generate Voltage difference. In particular, bit lines corresponding to local rows may be precharged for an additional duration (eg, one or more additional clock cycles) to allow additional time for slower bit lines to generate voltage differences. A series of sequential read operations can then be performed by selecting partial rows in sequential order. In some embodiments, one or more additional clock cycles of the initialization phase may be triggered by a stall signal. The stall signal may be generated in response to determining that at least one bit line is relatively slow to generate a voltage difference (eg, slow relative to other bit lines of the SRAM device).

8A shows an example timing diagram for performing a read operation with extended latency, according to some embodiments. As illustrated, the first initialization phase 802 begins at time 804 . The first initialization phase may correspond to precharging bitlines associated with a set of local rows and/or asserting wordlines of a particular column. At time 806, a stall signal 808 is set to an enabled state. The stall signal 808 may be set to an enabled state in response to information indicating that a particular bit line associated with the set of partial rows is associated with a relatively longer time required to generate a voltage difference than other bit lines of the RAM device (e.g., Other partial rows associated with other partial row groups than the row group associated with this set of partial rows). The enabled state of the stall signal 808 triggers a second initialization stage 810 . The second initialization phase 810 may correspond to precharging the bit lines for an extended duration (eg, for one or more additional clock cycles). At 811 , the stall signal 808 is deactivated. In response to the disable stall signal 808, at 812, 814, 816, and 818, a series of read operations are performed by sequentially selecting rows 0, 1, 2, and 3, respectively. It should be noted that, as illustrated in FIG. 8 , the entire series of read operations for the set of local rows is delayed due to the activation of the stall signal 808 . In some specific examples, the delay may correspond to one cycle.

In some embodiments, relatively slower bit lines may be associated during a write operation by causing the bit line to be driven for an additional period of time (eg, one or more additional clock cycles) during the write operation. Linked cells provide additional time. In some embodiments, one or more additional clock cycles may be triggered by the stall signal. The stall signal may be generated in response to determining that at least one bit line is relatively slow to generate a voltage difference (eg, slow relative to other bit lines of the SRAM device).

8B shows an example timing diagram for performing a write operation with extended latency, according to some embodiments. In the example shown in FIG. 8B , the relatively slower bit line is the bit line corresponding to local row 2 . An initialization phase 852 occurs. The initialization phase 852 may include precharging the bit lines corresponding to the local rows of the row group and/or asserting the word lines corresponding to the columns for which the write operation is to be performed. At time 854, a series of write operations begins. At 856, local row 0 is selected and a write operation is performed on the bit cell corresponding to local row 0. Similarly, at 858, local row 1 is selected and a write operation is performed on the bit cell corresponding to local row 1 . At 860, a write operation is performed on the bit cell corresponding to local row 2 . Concurrently with the write operation at 864, stall signal 862 is enabled in response to information indicating that a local row (eg, local row 2) is associated with a relatively slower bit line. At time 866, the stall signal is deactivated. However, in response to the stall signal having been enabled during the write operation at 864 , an additional write cycle is performed at 868 for the bit cell corresponding to local row 2 . In other words, the row driver is driven for an additional period (corresponding to the number of clock cycles for which the stall signal is enabled) during which local row 2 is selected. At 870, a write operation is performed on the bit cell corresponding to local row 3 . It should be noted that only the write operation associated with local row 3 is delayed due to the stall signal.

9 shows an example of a process 900 of performing sequential memory access operations with extended latency, according to some embodiments. Blocks of process 900 may be performed by a controller that controls the timing and other operations of the SRAM device. In some embodiments, the blocks of process 900 may be performed in an order other than that shown in FIG. 9 . In some embodiments, two or more blocks of process 900 may be performed substantially in parallel. In some embodiments, one or more blocks of process 900 may be omitted. In some embodiments, blocks of process 900 may be performed by a controller, such as a controller of an SOC including SRAM devices.

At 902, process 900 can obtain information indicative of a speed of one or more bit lines. The information may indicate that a particular bit line generates a voltage difference more slowly than other bit lines of the SRAM device (eg, bit lines associated with other row groups). The information may indicate the specific row address associated with the slower bit line. It should be noted that the obtained information may not directly indicate the speed of one or more bit lines. Instead, the obtained information may indicate that a particular bit line is to be accessed in conjunction with delay, as described below in connection with blocks 904 and 906 .

At block 904, in response to determining based at least in part on the obtained information that a memory access operation in a series of sequential memory access operations is to be performed on the slow bit line, the process 900 may cause the series of memory access operations The delay of at least a subset of . The delay may correspond to a period of one or more clock cycles. In some embodiments, process 900 may cause a delay by enabling a stall signal. For example, in instances where the series of memory access operations is a series of read operations, the stall signal may be generated at the end of a first initialization phase in which a set of bit lines associated with a row group is pre-set. Charging and/or asserting the word lines of a particular column is illustrated in Figure 8A. Continuing with the example, the stall signal can delay the entire series of read operations by causing the initialization phase to be extended by one or more additional clock cycles.

As another example, in instances where the series of memory access operations is a series of write operations, the stall signal may be generated concurrently with the write operation as indicated in the information obtained at block 902 The slower bit lines are associated, as illustrated in FIG. 8B. Continuing with the example, the stall signal can delay the remaining subset of memory write operations until the slower bit lines are driven an additional clock cycle or cycles. By way of example, in an instance where the slow bit line corresponds to local row 2 and the sequential order of the local row is selected among 0, 1, 2, 3, the selection of local rows 0 and 1 may not be delayed, while the selection of local row 3 Selection may be delayed due to extended write operations associated with local row 2 .

At block 906, process 900 may perform the remaining series of memory access operations after the period associated with the delay has elapsed. In some embodiments, process 900 may perform the remaining series of memory access operations in response to disabling the stall signal. For example, in the instance where the memory access operation is a read operation, disabling the stall signal may cause the initialization phase to end, and the remaining series of read operations may include sequentially performing a read memory operation on all local rows of a row group. Pick. As another example, in instances where the memory access operation is a write operation, disabling the stall signal may end the extra write cycle associated with the slow bit line and allow the write operation to proceed to row The next partial row in the group. In some implementations, the process 900 can deassert the wordline after performing the remaining series of memory access operations.

It should be noted that in some specific examples, any of the restoration techniques described above in conjunction with FIGS. can be combined. For example, the order used to select partial rows including one or more redundant rows can be modified, thereby combining the sequential row remapping techniques described above in connection with FIGS. 2-4 with those described above in connection with FIG. 5 The combination of address-dependent repair techniques described in FIG. 7 . As another example, the order used to select the partial rows can be modified, where operations are performed with extended latency in conjunction with one of the partial rows, combining the sequential row remapping techniques described above in connection with FIGS. The extended delay repair technology combination described in conjunction with FIG. 8A , FIG. 8B and FIG. 9 . As yet another example, memory access operations can be performed with extended latency in conjunction with the use of redundant rows, thereby combining the address-dependent repair techniques described above in connection with FIGS. 5-7 with those described above in connection with FIGS. 8B and the extended delay repair technology combination described in FIG. 9 . As yet another example, in some embodiments, sequential row remapping repair techniques, address-dependent repair techniques, and extended latency repair techniques may all be combined.

The integrated circuits described herein may be used in conjunction with various technologies, such as artificial reality systems. Artificial reality systems, such as head-mounted display (HMD) or heads-up display (HUD) systems, generally include displays configured to present artificial images depicting objects in a virtual environment. Displays can present virtual objects or combine images of real objects with virtual objects, such as in virtual reality (VR), augmented reality (AR) or mixed reality (MR) applications . For example, in an AR system, a user can view a virtual reality through, for example, see-through transparent display glasses or lenses (often referred to as optical see-through) or by viewing a displayed image of the surrounding environment captured by a camera (often referred to as video see-through). Both the displayed image of the object (eg, computer-generated image (CGI)) and the displayed image of the surrounding environment. In some AR systems, an LED-based display subsystem may be used to present artificial images to the user.

In some embodiments, the integrated circuits or integrated circuit packages described herein can be integrated into an HMD. For example, such HMDs may include one or more light emitters and/or one or more light sensors incorporated into a portion of the HMD's frame so that light may be emitted toward the tissue of the wearer of the HMD , the portion of the tissue adjacent to or touching the frame of the HMD. Example locations for this portion of the HMD's frame may include configurations to be adjacent to the wearer's ear (e.g., adjacent to the upper tragus, adjacent to the upper pinna, adjacent to the posterior pinna, adjacent to the lower pinna, or the like) or), adjacent to the wearer's forehead, or the like. It should be noted that multiple sets of light emitters and light sensors can be incorporated into the frame of the HMD so that photoplethysmography (PPG) can be determined from measurements associated with multiple body positions of the wearer of the HMD .

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of examples of the present disclosure. It may be evident, however, that various examples may be practiced without these specific details. For example, devices, systems, structures, assemblies, methods, and other components may be shown as components in block diagram form in order not to obscure the examples with unnecessary detail. In other instances, well-known devices, procedures, systems, structures and techniques may be shown without unnecessary detail in order not to obscure the examples. The drawings and descriptions are not intended to be limiting. The terms and expressions which have been used in this disclosure are terms of description and not of limitation, and in the use of such terms and expressions it is not intended to exclude any equivalents or parts thereof of the features shown and described. The word "example" is used herein to mean "serving as an example, instance, or illustration." Any particular example or design described herein as an "example" is not necessarily to be construed as being better than or superior to other particular examples or designs.

Embodiments disclosed herein may be used to implement components of an artificial reality system or may be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been modified in some way before being presented to the user, which may include, for example, virtual reality, augmented reality, mixed reality, hybrid reality, or some combination and/or derivative thereof things. Artificial reality content may include fully generated content or generated content combined with captured (eg, real world) content. Artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of these may be presented in a single channel or in multiple channels, such as stereoscopic video that creates a three-dimensional effect on the viewer. In addition, in some embodiments, an artificial reality may also be used in conjunction with, for example, applications that generate content in an artificial reality and/or are otherwise used in an artificial reality (e.g., to perform activities in an artificial reality), products, accessories, services or a combination thereof. AR systems that provide AR content can be implemented on a variety of platforms, including HMDs connected to a host computer system, standalone HMDs, mobile devices or computing systems, or capable of delivering AR content to one or more viewers any other hardware platform.

The methods, systems, and devices discussed above are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For example, in alternative configurations, the methods described may be performed in an order different from that described, and/or various stages may be added, omitted, and/or combined. Furthermore, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments can be combined in a similar manner. In addition, technology evolves, and thus many of the elements are examples that do not limit the scope of the disclosure to their specific examples.

Specific details are given in the description to provide a thorough understanding of specific examples. However, specific examples may be practiced without such specific details. For example, well-known circuits, processes, systems, structures and techniques have been shown without unnecessary detail in order not to obscure the particular example. This description provides illustrative specific examples only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the foregoing descriptions of the specific examples will provide those of ordinary skill in the art with a description that can enable the various specific examples to be practiced. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the invention.

Additionally, some specific examples are described as processes depicted as flowcharts or block diagrams. Although each may describe operations as sequential processes, many operations may be performed in parallel or simultaneously. Additionally, the order of operations can be reconfigured. Processes may have additional steps not included in the figures. Furthermore, embodiments of the methods may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform associated tasks may be stored in a computer-readable medium such as a storage medium. The processor can perform associated tasks.

It will be apparent to those of ordinary skill in the art that substantial changes may be made according to particular requirements. For example, custom or dedicated hardware may also be used, and/or particular elements may be implemented in hardware, software (including portable software, such as applets, etc.), or both. Additionally, connections to other computing devices, such as network input/output devices, may be used.

Referring to the figures, a component that may include memory may include a non-transitory machine-readable medium. The terms "machine-readable medium" and "computer-readable medium" may refer to any storage medium that participates in providing data that causes a machine to operate in a specific manner. In the specific examples provided above, various machine-readable media may be involved in providing instructions/code to a processing unit and/or other device for execution. Additionally or alternatively, a machine-readable medium may be used to store and/or carry such instructions/code. In many implementations, the computer-readable medium is a physical and/or tangible storage medium. Such media may take many forms including, but not limited to, non-volatile media, volatile media, and transmission media. Common forms of computer readable media include, for example, magnetic and/or optical media such as compact disks (CDs) or digital versatile disks (DVDs); punched cards; paper tape; any other Physical media; RAM; programmable read-only memory (PROM); erasable programmable read-only memory (EPROM); FLASH-EPROM; any other memory a physical chip or cartridge; a carrier wave as described below; or any other medium from which a computer can read instructions and/or code. A computer program product may include code and/or machine-executable instructions which may represent a program, function, subroutine, program, routine, application, subroutine, module , package, class, or any combination of instructions, data structures, or program statements.

Those of ordinary skill in the art will appreciate that information and signals used to convey the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or particles, or combinations thereof.

As used herein, the terms "and" and "or" may include a variety of meanings which are also expected to depend, at least in part, on the context in which such terms are used. Typically, "or" when used in relation to a list such as A, B, or C is intended to mean A, B, and C (herein used inclusively), and A, B, or C (herein used in an exclusive sense) . In addition, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe some combination of features, structures or characteristics. It should be noted, however, that this is merely an illustrative example and that claimed subject matter is not limited to this example. Furthermore, the term "at least one of" if used in connection with a list such as A, B or C may be interpreted to mean any combination of A, B and/or C such as A, AB, AC, BC, AA , ABC, AABBCCC, etc.

Furthermore, although certain embodiments have been described using specific combinations of hardware and software, it should be recognized that other combinations of hardware and software are possible. Certain embodiments may be implemented in hardware only, or only software, or a combination thereof. In one example, the software can be implemented by a computer program product containing computer code or instructions executable by one or more processors for performing the steps, operations or processes described in this disclosure. Any or all of the processes in which the computer program may be stored on a non-transitory computer readable medium. The various processes described herein may be implemented in any combination on the same processor or on different processors.

Where a device, system, component, or module is described as being configured to perform certain operations or functions, such configuration may be achieved, for example, by designing electronic circuits to perform the operations, by programming programmable electronic circuits such as microprocessor) to perform operations (such as by executing computer instructions or code, or a processor or core programmed to execute code or instructions stored on a non-transitory memory medium), or any combination thereof . Processes may communicate using a variety of techniques, including but not limited to well-known techniques for inter-process communication, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense. It will be evident, however, that additions, subtractions, deletions and other modifications and changes may be made thereto without departing from the broader spirit and scope as set forth in the claims. Thus, although certain embodiments have been described, such embodiments are not intended to be limiting. Various modifications and equivalents are within the scope of the following claims.

100: SRAM device 102: bit cell array 103: column decoder 104: row group 106: row group 108: row group 110: row group 112: row group 114: row decoder 116: row decoder 118: row decoder 120: row decoder 122: row decoder 124: data line 126: data line 128: data line 130: data line 132: data line 150: The first clock cycle 152: The second clock cycle 154: clock cycle 156: clock cycle 158: clock cycle 160: clock cycle 202: time point 204: time point 206: Access sequence 208: Access sequence 302: bit cell array 304: column decoder 306: row multiplexer 308: row decoder 352: line repair signal 354: the first bit 356: second bit 358: the third bit 360: XOR Gate 362: XOR gate 364: XOR gate 366: row decoder 368: Row selection line 400: process 402: block 404: block 406: block 502: row group 504: row group 506: row multiplexer 508: row multiplexer 510: read/write circuit 512: read/write circuit 514: Redundant line 516: read/write circuit 600: SRAM device 602: row group 604: row group 606: row group 608: row group 610: Redundant row 612: Redundant line 614: redundant line 616: redundant line 618:LUT 620: Repair multiplexer 622: interface 700: process 702: block 704: block 706: block 708: block 710: block 712: block 802: Initialization phase 804: time 806: time 808: Stall signal 810: the second initialization stage 811: time 812: Read operation 814: Read operation 816: Read operation 818: Read operation 852:Initialization phase 854: time 856: Write operation 858: Write operation 860: time 862: Stall signal 864: Write operation 866: time 868: Write operation 870: Write operation 900: process 902: block 904: block 906: block

Illustrative specific examples are described in detail below with reference to the following figures. [FIG. 1A] is a schematic diagram showing an example implementation of a static random access memory (SRAM) device according to some embodiments. [ FIG. 1B ] An example timing diagram illustrating sequential memory operation using a sequential SRAM device according to some embodiments. [FIG. 2] is an example timing diagram illustrating sequential row remapping according to some embodiments. [FIG. 3A] and [FIG. 3B] are schematic diagrams illustrating an example implementation of sequential row remapping according to some embodiments. [FIG. 4] is a flowchart depicting an example process for sequential row remapping according to some embodiments. [ FIG. 5 ] is a schematic diagram illustrating the use of redundant rows with sequential SRAM devices according to some embodiments. [ FIG. 6 ] is a schematic diagram of a system for implementing address-dependent repair according to some embodiments. [FIG. 7] is a flowchart depicting an example process of address dependent repair according to some embodiments. [FIG. 8A] and [FIG. 8B] are example timing diagrams of multi-cycle repair operations according to some embodiments. [FIG. 9] is a flowchart depicting an example process of a multi-cycle repair operation according to some embodiments. The drawings depict specific examples of the disclosure for purposes of illustration only. Those of ordinary skill in the art will readily recognize from the following description that alternative embodiments of the illustrated structures and methods may be used without departing from the principles of the disclosure or the rights claimed. In the drawings, similar components and/or features may have the same reference number. Furthermore, various components of the same type may be distinguished by the use of a dash after the reference label and a second label that distinguishes among similar components. If only a first element number is used in the specification, the description applies to any of similar components having the same first element number regardless of the second element number.

100: SRAM device

102: bit cell array

103: column decoder

104: row group

106: row group

108: row group

110: row group

112: row group

114: row decoder

116: row decoder

118: row decoder

120: row decoder

122: row decoder

124: data line

126: data line

128: data line

130: data line

132: data line

Claims (30)

A system comprising: A static random access memory (SRAM) device comprising: A bit cell array comprising a plurality of bit cells configured into a plurality of columns and a plurality of rows, each row of the plurality of rows being operatively coupled to a pair of bit lines, wherein the plurality of rows are configured as a plurality of row groups, and each row group contains a plurality of partial rows, a column decoder configured to operatively couple word lines to columns of the plurality of columns of the plurality of bit cells based at least in part on a column address provided to the column decoder, and a plurality of row decoders, each row decoder associated with a row group of the plurality of row groups, wherein each row decoder is configured to operatively couple a data line to a partial row of the plurality of partial rows , the partial row corresponds to a row group of the plurality of row groups associated with the row decoder; and a controller configured, for a row group of the plurality of row groups, by resetting for a given partial row in a physical sequential order different from that of the plurality of partial rows in the row group A sequential order is configured to sense a voltage difference on corresponding bit line pairs to read the partial row of the plurality of partial rows included in the row group. The system of claim 1, wherein the reconfigured sequential order is determined based at least in part on a reordering signal obtained by the controller. The system according to claim 2, wherein the reordering signal is a binary signal. The system of claim 3, wherein the reconfigured sequence is an inverse sequence to the physical sequence. The system of claim 4, wherein the reordered sequential order is determined based on an exclusive OR (XOR) operation of the reordering signal with bits of row addresses associated with the plurality of partial rows. The system of claim 1, wherein sensing the voltage difference on the corresponding bit line pair in the reconfigured sequential order that is different from the physical sequential order of the plurality of local rows includes sensing and having a second Before the voltage difference of the bit line pair associated with the local row of the access time, the voltage difference of the bit line pair associated with the local row having a first access time is sensed, the second access time is longer than the first access time an access time. The system of claim 1, wherein the controller is further configured to provide a column address to the column decoder such that the word corresponding to the column of the plurality of columns associated with the column address The metaline is asserted prior to reading the local row of the plurality of local rows. The system of claim 7, wherein the controller is further configured to deassert the wordline after the plurality of partial rows have been read in the reconfigured sequential order. The system of claim 1, wherein the signal indicative of the reconfigured sequential order is used by a row multiplexer to select a partial row of the plurality of partial rows in the reconfigured sequential order. A system comprising: a static random access memory (SRAM) device comprising: A bit cell array comprising a plurality of bit cells configured into a plurality of columns and a plurality of rows, each row of the plurality of rows being operatively coupled to a pair of bit lines, wherein the plurality of The rows are configured as a plurality of row groups, each row group includes a plurality of partial rows, and wherein the plurality of rows includes one or more redundant rows; a column decoder configured to operatively couple a word line to a column of the plurality of columns of the plurality of bit cells based at least in part on a column address provided to the column decoder; and a plurality of row decoders, each row decoder associated with a row group of the plurality of row groups, wherein each row decoder is configured to operatively couple a data line to a partial row of the plurality of partial rows , the partial row corresponds to a row group of the plurality of row groups associated with the row decoder; and A controller configured to: Obtaining an address of a bit cell in the bit cell array to be performed a sequential memory access operation, wherein the address includes a column address, a row group identifier, and a local row address; mapping the column address, the row group identifier and the local row address to a repair address corresponding to a repair bit cell, wherein the repair address corresponds to a redundant row in the one or more redundant rows OK; providing the column address to the column decoder which asserts the word line corresponding to the column of the plurality of columns associated with the column address; and The sequential memory access operation is performed at the repair address by selecting the redundant row corresponding to the repair address. The system according to claim 10, wherein the first cell of the redundant row corresponds to the faulty cell of the first partial row, and the second cell of the redundant row corresponds to a fault cell different from the first partial row The faulty bit cell of the second partial row. The system of claim 11, wherein the column of the first cell of the redundant row is the same as the column of the faulty cell of the first partial row. The system of claim 10, wherein mapping the column address, the row group identifier, and the local row address to the repair address includes by using the column address, the row group identifier, and the local The row address is provided to a lookup table from which the repair address is obtained. The system of claim 13, wherein the look-up table is preconfigured based on testing of the SRAM device. The system of claim 13, wherein the look-up table is operatively coupled to a multiplexer configured to select the redundant row corresponding to the repair address. The system of claim 10, wherein the one or more redundant rows comprise at least two redundant rows, and wherein the at least two redundant rows are associated with different row groups of the plurality of row groups. The system of claim 10, wherein the controller is further configured to precharge a set of bit lines corresponding to a plurality of partial rows included in the row group corresponding to the row group identifier group, and wherein mapping the column address, the row group identifier, and the local row address to the repair address occurs simultaneously with precharging the group of bit lines. The system of claim 10, wherein mapping the column address, the row group identifier, and the local row address to the repair address occurs concurrently with asserting the word line. The system of claim 10, wherein at least one partial row of the row group associated with the row group identifier does not have a corresponding redundant row included in the one or more redundant rows. A system comprising: a static random access memory (SRAM) device comprising: A bit cell array comprising a plurality of bit cells configured into a plurality of columns and a plurality of rows, each row of the plurality of rows being operatively coupled to a pair of bit lines, wherein the plurality of The rows are configured as a plurality of row groups, and each row group includes a plurality of partial rows; a column decoder configured to operatively couple a word line to a column of the plurality of columns of the plurality of bit cells based at least in part on a column address provided to the column decoder; and a plurality of row decoders, each row decoder associated with a row group of the plurality of row groups, wherein each row decoder is configured to operatively couple a data line to a partial row of the plurality of partial rows , the partial row corresponds to a row group of the plurality of row groups associated with the row decoder; and a controller configured for the row group of the plurality of row groups: providing a column address to the column decoder such that the word line corresponding to the column of the plurality of columns associated with the column address is asserted; A sequential memory access operation responsive to determining that a series of memory access operations will be performed on a slow bit line of one or more bit lines having a length longer than that of the one or more bit lines an access time of an access time associated with at least one other bit line, thereby causing a delay in at least a subset of memory access operations in the series of memory access operations; and The at least one subset of memory access operations is performed after a period of time associated with the delay has elapsed. The system of claim 20, wherein the delay causing the at least one subset of memory access operations is in response to an enabling stall signal, and wherein the at least one memory access operation is performed after the time period associated with the delay has elapsed Fetching the subset of operations is responsive to disabling the stall signal. The system of claim 21, wherein enabling the stall signal and deactivating the stall signal is performed using a handshake protocol associated with performing the series of memory access operations. The system of claim 22, wherein the handshake protocol is associated with a row stride and/or a row stride for performing the series of memory access operations. The system of claim 20, wherein the series of memory access operations includes a series of read operations. The system of claim 24, wherein the precharging of the one or more bit lines is extended during the time period. The system of claim 24, wherein the at least one subset of memory access operations includes all memory access operations in the series of memory access operations. The system of claim 20, wherein the series of memory access operations includes a series of write operations. The system of claim 27, wherein the slow bit line is driven during the time period. The system of claim 27, wherein the at least one subset of memory access operations includes memory access operations subsequent to accessing the local row associated with the slow bit line. The system of claim 20, wherein the time period corresponds to a clock cycle.

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