TW202307647A - Floating point multiply-add, accumulate unit with carry-save accumulator - Google Patents

Abstract

Floating point Multiply-Add, Accumulate Unit, supporting BF16 format for Multiply-Accumulate operations, and FP32 Single-Precision Addition complying with the IEEE 754 Standard. The Multiply-Accumulate unit uses higher radix and longer internal 2's complement significand representation to facilitate precision as well as comparison and operation with negative numbers. The addition can be performed using Carry-Save format to avoid long carry propagation and speed up the operation. The circuit uses early exponent comparison to shorten the accumulate pipeline stage. Operations including overflow detection, zero detection and sign extension are adopted for 2s complement and Carry-Save format.

Description

Floating-point multiply-accumulate unit with carry-save accumulator

The field of the present disclosure is the implementation of arithmetic logic circuits, including floating-point multiply-accumulate circuits, sometimes referred to as multiply-and-accumulate circuits, for high-speed processors, including processors configured to efficiently perform training and inference. References to Priority Applications

This application claims priority to: U.S. Patent Application No. 17/534,376, filed November 23, 2021; U.S. Patent Application No. 17/465,558, filed September 2, 2021; U.S. Patent Application No. 17/397,241 filed May 19, 2021 U.S. Provisional Patent Application No. 63/190,749 filed May 19, 2021 U.S. Provisional Patent Application No. 63/174,460 filed April 13, 2021, U.S. Provisional Patent Application No. 63/166,221, filed March 25, 2021, U.S. Provisional Patent Application No. 63/165,073, filed March 23, 2021, and U.S. Provisional Patent Application, filed August 31, 2021 Case No. 63/239,384. All eight of the aforementioned applications are hereby incorporated by reference.

Arithmetic logic circuits including floating point, multiply and accumulate units as implemented in high performance processors are relatively complex logic circuits. Multiply and accumulate circuits are used for matrix multiplication and other complex mathematical operations, which are used in machine learning and inference engines.

In essence, the multiply-and-accumulate circuit generates the sum S(i) of a sequence of terms A(i)*B(i), usually expressed as follows:

Here, the sum S(i) at period (i) is equal to adding the term A(i)*B(i) to the sum S(i-1), i.e. the term A(0)*B(0) to A Accumulation of (i-1)*B(i-1). The final sum S(N-1) is the sum output of multiplication and accumulation operations for N cycles (from 0 to N-1).

In a floating-point implementation, two input floating-point operands A(i) and B(i) including exponent and rms values are multiplied each cycle to produce a multiplier output term A(i)*B(i ), then calculate the accumulator output sum S(i) by adding the multiplier output term A(i)*B(i) of the current cycle to the accumulator output sum S(i−1) of the previous cycle.

In the floating-point encoding format used to encode floating-point numbers in computing, the number can be normalized so that the significand includes an integer bit to the left of the binary point (always "1" in binary), and A decimal represented by bits to the right of the binary point, and the number in question is encoded using only the decimal. The binary 1 integer is omitted from the encoding because it can be implied by the normalized form. Operations on floating point encoded format numbers encoded in this way take into account the integers to the left of the binary point, known as "implicit 1".

Multiplication of floating-point numbers can be accomplished by adding the exponents, multiplying by the significand, and then normalizing the result by shifting the resulting significand on the output and adjusting the output exponent to accommodate this shift.

Addition of floating-point numbers can be accomplished by first identifying the larger exponent, and the difference between the exponents of the operands, and then shifting the significand of the operand with the smallest exponent to align with the larger exponent. Finally, the result is normalized, which may involve additional shifting of the significand and adjustment of the exponent.

Calculations with numbers that result in formats not supported, such as floating-point encoding formats, result in exception signals. In dataflow architectures and other architectures that implement complex algorithms such as machine learning algorithms, these anomalies can cause the algorithm to stall or fail. Anomalies in real-time systems that cause algorithms to stall or fail can lead to system failures or other performance problems.

There is a need to provide an exception handling system that can be applied to complex data processing settings.

and

A detailed description of techniques for implementing an arithmetic unit of a configurable and reconfigurable dataflow architecture with exception handling is provided. An example reconfigurable dataflow architecture is described in US Patent No. 10,831,507 issued November 10, 2020 to Shah et al., which is incorporated by reference as if fully set forth herein. The arithmetic unit can perform a plurality of floating-point arithmetic operations using input operands and generate at least one output operand, where the source of the input operands, the destination of the output operands, and the operation are configurable and can be operated on through the data stream The configuration data remains static during reconfiguration.

During the execution of at least one floating-point arithmetic operation, anomalies related to illegal operations and to the generation of results not normally represented by the floating-point encoding format used are detected, and the result of the operation is made available during the operation Values for further processing that do not require special interrupt handling by, for example, the runtime processor. As a result, dataflow operations can be completed without interruption due to at least some exceptions.

In some embodiments, the arithmetic operations and arithmetic units used on the control flow architecture may implement the exception handling techniques described herein. Floating-point carry-save MAC (FP-CS-MAC)

Describes the FP-CS-MAC that can operate in three operation modes, such as: input A (BF16) x input B (BF16) + accumulation loop input A (BF16) x input B (BF16) + input C (FP32) or A single 32-bit floating-point addition, such as: input A (FP32) + input C (FP32) operand A can be in any format, and in this implementation it is one of the following two formats: BF16 or FP32, where BF16 It is a format that contains 8-bit exponent, 1 sign bit, and 7-bit significand, in which 1 integer bit is implied, and there are 8 significand bits in total. FP32 is known as the single-precision 32-bit, IEEE floating-point 754 standard.

Other encoding formats may be used and appropriate adaptations of the described implementations may be made.

A triple-mode floating-point carry-save MAC (FP-CS-MAC) unit is described that includes circuitry implemented as a pipeline that operates in response to a pipeline clock. In some implementations, the pipeline clock can be on the order of gigahertz (GHz) or faster. When the pipeline clock is running, each cycle of the clock corresponds to a pipeline cycle. Thus, in some embodiments, the pipeline cycle time may be less than one nanosecond. In a pipeline, stages of the pipeline include input registers or data stores that hold input data at the stage of the first pipeline clock pulse (e.g., the leading edge of the clock pulse), and hold input data at the stage of the next pipeline The leading edge of a clock pulse, defining a pipeline clock period) of the register stage outputs data to an output register or data store. When the first pipeline clock pulse starts a pipeline cycle (i), the output register of the stage holds the stage output data of the previous pipeline cycle (i-1), and the stage output data of a stage in the pipeline is at least Part of the stage input data for the next stage. The circuitry at each stage must settle reliably within the pipeline cycle, so fast pipeline clocks pose significant difficulties for timing-critical stages.

One implementation of a triple-mode floating-point carry-save MAC (FP-CS-MAC) unit contains 6 pipeline stages. Speed can be further increased by increasing the number of pipeline stages. Power can be further reduced by reducing the number of pipeline stages. In general, the optimal number of pipeline stages depends on the specific technology and design requirements. The first main unit is the BF16 multiplier, which in this example is implemented in two pipeline stages and includes a conversion unit for converting the multiplier result to a 16-bit 2's complement significand and exponent. The third pipeline stage is the carry-save-accumulate stage. The next two stages convert the result in carry-sum format back to a traditional normalized signed-numeric format, such as BF16 or FP32 as required for the output encoding format.

|a|＜2之間，因為它們在十進制點左側包含隱含的1，並且僅包括有效數的小數部分。所述單元不支援非正規化數字並將它們截斷為零。因此，使用BF16或FP32，輸入運算元的範圍為±2−126到(2−2−7)×2127。如果小於±2−126，則超出此範圍的數字截斷為零，或者如果大於±(2−2−7)×2127，則轉換為±無窮大。 浮點編碼格式 The last pipeline stage performs normalization and rounding to produce the result. In this case the final format is BF16 or FP32 format. Input operand valid number is between 1

|a|<2 because they include an implied 1 to the left of the decimal point and only the fractional part of the significand. The unit in question does not support denormalized numbers and truncates them to zero. Therefore, with BF16 or FP32, the range of input operands is ±2−126 to (2−2−7)×2127. Numbers outside this range are truncated to zero if less than ±2−126, or converted to ±infinity if greater than ±(2−2−7)×2127. floating point encoding format

Figure 1 illustrates the bit patterns for the two encoding formats. The first example diagram of the first bit format illustrates Bfloat16 110 . The Bfloat16 floating-point encoding format (sometimes "BF16") is a 16-bit numeric format. BF16 preserves the approximate dynamic range of IEEE single-degree precision. The BF16 format described consists of 7 bits of fraction, an "implicit bit" or "hidden bit" to complete the significand, 8 bits of exponent, and a sign bit.

The second figure illustrates the IEEE 754 single-precision 32-bit floating-point (FP32) 130 encoding format. The illustrated IEEE 754 single-precision 32-bit floating point 130 includes 23 bits of fraction, an "implicit bit" or "hidden bit" to complete the significand, an 8-bit exponent, and a sign bit. A feature of these two encoding formats is that numbers in FP32 format can be converted to BF16 format by discarding the 16 less significant digits of the 23-bit portion, and in some embodiments rounding is performed to select the lower order bits. System Block Diagram

Figure 2 is a high-level block diagram of a floating-point multiply-accumulate unit with a carry-save accumulator in BF16 and FP32 formats. Operand A 213 is illustrated as BF16 format or FP32 format 217 . Operand B 214 is in BF16 format and is the first input to multiplier circuit 202 . The second input is the BF16 operand A 213 . When both the operand A and the operand B are in the BF16 format, the operand A and the operand B can occupy a single 32-bit temporary register, and each uses 16 bits to represent the multiplier and the multiplicand input of the multiplier. The product (A*B) output of the multiplier circuit 210 is produced in Carry-Sum form on line 218 , which is the input to the final adder in block 220 . Block 220 also converts the result to 2's complement form and includes base-8 converter circuitry to support base-8 arithmetic.

When the pipeline operates with a single 32-bit addition, (one operand) operand A can bypass the multiplier circuit 202 , while the second operand C for addition comes from line 216 .

In this example, operand C 216 is a 32-bit operand that is input to base-8 converter 215 , which outputs the result on line 219 to the first input of one of multiplexers 210 and 211 . The second input to multiplexers 210 and 211 are two buses for the carry and sum value C/S-ACC (and exponent not shown) on lines 224 and 226 fed back from the output of accumulator 240 . The multiplexers 211 and 212 output the exponent and the significand as two values of the bus 223 .

Carry-save adder 230 receives the output of block 220 on line 221 and the outputs of multiplexers 211 , 212 on bus 223 . Carry save adder 230 outputs the exponent and C/S value of the sum on dual bus 222 into accumulator 240 . Accumulator 240 provides the C/S-ACC exponent and significand in carry-save form on output buses 224 and 225 which feed back to multiplexer 211, multiplexer 212, and on bus 226 The C/S-ACC exponent and significand-to-carry-save-to-sign value conversion block 250 is provided in carry-save form, which performs the carry-out of the significand on bus 226 and the final addition of the sum value on bus 227 The above converts the resulting significand to signed numeric format. Buses 252 and 251 carry data from accumulator 240 to carry save to sign value conversion block 250 .

The base 8 to base 2 conversion and normalization block 260 has an input on bus 227 and outputs the normalized result on bus 228 for post normalization, rounding and conversion to FP32 or BF16 block 270, which is on bus 228 Line 229 converts the output to FP32 or BF16 format. The operation outputs the result "Z" on bus 229 in 32-bit FP32 format or 16-bit BF16 format.

Accordingly, FIG. 2 illustrates an example of a circuit that may be implemented as a multi-stage pipeline configured to perform in three modes, including multiply and accumulate operations for input sequences of floating-point operands. In this example, the circuit can be configured as a pipeline comprising a first stage comprising a floating point multiplier with a sum and carry output, a multiplier output adder comprising a sum and carry output for the multiplier, and a The second stage of the circuit that converts the adder output to base-8 format with a 2's complement significand, the third stage of the exponent circuit including the significand circuit and the accumulator adder, the accumulator sign bit, the accumulator exponent A fourth stage that converts the sum-accumulator significand and carry value to signed numeric significand format, a fifth stage that converts signed numeric significand format from base-8 alignment to base 2 alignment and produces a normalized exponent and significand, and a sixth level to perform rounding and conversion to standard floating-point representation.

The technique described herein provides a multiply-accumulate method to compute a sum S(i) of terms A(i)*B(i), where (i) ranges from 0 to N-1, where N is the number of terms in the sum. The method may comprise receiving a sequence of operands A(i) and operands B(i) in floating-point encoded format, where (i) ranges from 0 to N-1; combining operands A(i) and operands B( i) multiply to produce terms A(i)*B(i) in the format containing the multiplier output exponent and the multiplier output significand, and convert the multiplier output significand to 2's complement format; use carry-save addition Adds the 2's complement significand of the term A(i)*B(i) to the significand of the sum S(i-1) and produces a sum and carry value for the sum S(i); from A( Select the index of the sum S(i) from the multiplier output index of *B(i) and the index of the sum S(i-1) to generate the index of the sum S(i); and combine the sum and the carry value with the sum The exponent of S(i) is converted to normalized floating-point encoding format.

Additionally, the method may include providing the multiplier output exponent and the multiplier output significand of the term A(i)*B(i) in base 8 format, and prior to converting to a normalized floating point encoding format which may be base 2 Generates the sum and carry value and the exponent of the sum S(i) in base-8 format.

The alignment required for the accumulate-add phase depends on a number of conditions, including sum S(i-1) sign-extended, sum S(i-1) sign-extended, and addends: term A(i)*B(i) and sum The difference between the indices of S(i-1). These conditions can be determined and combined for alignment within the same pipeline cycle (eg, third stage in a six-stage example), resulting in fast execution and faster pipeline clocks. In the example provided herein, the unit performs a method of computing a sum S(i) of terms A(i)*B(i), where (i) ranges from 0 to N-1, and N is the number of terms of the sum , the method contains: Receive a sequence of operands A(i) and operands B(i) in floating-point encoding format, where (i) is from 0 to N-1; Multiply operand A(i) and operand B(i) to produce term A(i)*B(i) during the first pipeline cycle in a format that includes the term A(i)*B(i) The multiplier output exponent and the multiplier output significand of the term A(i)*B(i) and the sum S( The accumulator output indices of i-1) are compared to generate a comparison signal for the sum S(i); Adds the term A(i)*B(i) to the sum S(i-1) to produce the sum S(i) during the next pipeline cycle in a format including the accumulator output index of the sum S(i) and the sum S The accumulator of (i) outputs a significand, wherein the addition includes Determine the accumulator output exponent of the sum S(i) and assign either or both of the accumulator output significand of the sum S(i-1) and the multiplier output significand of the term A(i)*B(i) or shifted as a result of the comparison signal of the sum S(i).

The step of comparing the multiplier output exponent of the term A(i)*B(i) with the accumulator output exponent of the sum S(i-1) during the first pipeline cycle is performed to produce a sum for the sum S(i ) while performing adjustments to operands in the next pipeline cycle (early exponent compare) enables the use of pipelines with accumulator stages that have shorter critical timing paths and can operate at higher clock speeds. floating point multiplier

The floating-point multiplier includes an exponent circuit and a significand circuit. The exponent section performs addition of the operands' exponents, and the significand section performs binary multiplication of the operands' significands. The operands that go into the multiplier are "normalized" floating point numbers, where the first bit is 1. Therefore, the effective number (m) of the operand is between 1≤m<2, that is, greater than or equal to 1 and less than 2. Therefore, the product of the significands of the two operands is in the range 1≤p<4, and can never be equal to or greater than 4.

If the product p as a result of significand multiplication is in the range 2 ≤ p < 4, the exponent will be incremented and the significand shifted right by one binary position for normalization.

The first pipeline stage performs addition of exponents and multiplication of operand significands using 8x8-bit integer multipliers, including a carry-save adder for partial products. After summing all the partial products using the carry-save adders, the result of the multiplier array can consist of two parts: the 8-bit sum of the carry-save adders of the partial products in the most significant part of the multiplier array and the 9-bit carry, and the 8-bit product of the least significant part of the multiplier array. In this example, the 8-bit partial product in the least significant part is added using a ripple-carry adder, since these bits come from the partial product reduction tree. This summation can be done using a ripple-carry adder, because the time-arrival distribution from the least significant part of the multiplier is the part that arrives in time from the least significant bit (LSB) to the most significant bit (MSB), enough to do Ripple carry adder. Applying a ripple-carry adder (RCA) significantly reduces the complexity of the multiplier (Figure 4a).

The stage includes a multiplier circuit that provides multiplier significand and multiplier exponent values prior to the pipeline clock in response to the first and second input operands being buffered at the pipeline clock. The multiplier circuit includes a significand multiplier circuit and an exponent adder circuit, the significand multiplier circuit having a carry-save adder for generating a partial product of the carry and sum values to produce the high-order bits of the multiplier output significand, and a ripple-carry adder to generate the partial product of the significand carry and low-order bits of the sum output. In addition, the multiplier circuit includes a base-8 conversion circuit for converting the multiplier significand and multiplier exponent values into a base-8 format for the multiplier output exponent and significand; and a 2's complement conversion circuit for converting the multiplier The significand value of the multiplier is converted to the 2's complement representation of the multiplier output significand.

Exponents are added individually. Both exponents are positive numbers greater than zero. When the addition result is a number greater than 256, the indication is the carry output signal from the exponent adder. If the resulting exponent is equal to 255, then a positive infinity indication is determined. If the exponent is equal to 0, the significand is set to zero according to the IEEE 754 standard rules. In this implementation, if the exponent of the product is 0, the significand of the result is forced to 0, thus representing a +/- zero float (Figure 4b). In other embodiments, subnormal numbers may be treated differently.

Exponential addition requires subtracting 127 from the result, because in BF16 and FP32 encoding formats, both operands include a 127 offset. Adding 129 to the result speeds up the conversion process by inverting the MSB of the exponent on one of the inputs and introducing a 1 to the adder's carry input. This greatly simplifies the circuit and can reduce the time required for pipeline stages (Figure 4b).

We prove the correctness of this procedure in the following way: The addition causes the two offsets of 127 to add, making the offset 254. However, since the carry out of the adder (ie 256) is ignored, the resulting bias will be -2. We can get 127 by adding 129 to the result of the operation. This is accomplished by inverting the MSB of the operand, which is equivalent to adding 128 in the case of a negative operand, since the MSB position contains a zero. In the case of positive operands with MSB equal to 1, this is also equivalent to adding 128. The extra 1 at the carry input biases the result: -2+129, which equals the desired bias of 127.

The same pipeline stage converts the result to a base-8 number with a 5-bit exponent and a significand shifted right by 7 positions appropriately. For the quantity represented by the value of the remaining 3 exponent bits, conversion to a 5-bit exponent requires a left shift from the 7th position. This requires the significand to pass through a left shifter which will shift the significand left from the 0 bit to the 7 bit position as required by the 3-LSB bits of the 8 bit exponent. (Figure 5b)

The multiplier saves computation time by identifying uneven arrival distributions of signals originating from Partial Product Reduction Trees (PPRTs). The LSB bit arrives first, followed by the next bit, and so on for the first 8 least significant bit bits (LSB) of the PPRT. Due to the unequal arrival distribution, the addition of the LSB part can be masked ("hidden") at the delay of the multiplier array, thereby providing savings for pipeline stages (e.g., the second pipeline stage in the example outlined above) ( in time). Adding the LSB part uses an 8-bit ripple-carry adder (RCA) to reduce the size of the carry-propagate adder (CPA) from 17 bits to 9 bits using a carry-save adder for partial products . For the MSB part of the next pipeline stage, including the final adder which is only 9 bits long. The significand of the product is formed in the pipeline stage by summing the most significant 9 bits of the final adder and augmenting it with the least significant 8 bits previously formed using the ripple-carry adder of the previous pipeline stage (Fig. 4a).

3 is a simplified block diagram 300 of a multiplier circuit 202 with two inputs (operator A on line 213 and operand B on line 214). Multiplier circuit 202 includes two blocks (multiplier and adder block 210a and exponent block 210b).

Figure 4a illustrates an example of a multiplier and adder block 210a showing an 8x8 multiplier partial product reduction tree with carry-save adders for partial products for higher significant digits and no carry for lower significant digits The final 16-bit adder of the 7-LSB ripple-carry adder block for partial product addition (provided in the next stage). Operand A 213 is stored in register 420 which includes three fields: Sa, Ea and Fa. Sa is the sign bit. Ea is the eight exponent bits, and Fa is the fractional part of the significand. The Fa field is applied to the first input of the 8×8 BF16 multiplier circuit 410 on line 422 . The operand B 214 is stored in the register 421, and the register 421 includes three fields: Sb, Eb and Fb. Sb is the sign bit. Eb is the eight exponent bits, and Fb is the fractional part of the significand. The Fb field is applied to the second input of the 8×8 BF16 multiplier circuit 410 on line 423 . On line 440, the input to the multiplier circuit 410 is a forced zero bit which, when zero, forces the 8X8 BF16 multiplier circuit to produce a zero output.

8×8 BF16 multiplier circuit 410 outputs two 7-bit LSB buses 428 and 429 , which are inputs to 7-bit ripple-carry adder 430 . In addition, the 8×8 BF16 multiplier circuit 410 outputs 8 sum bits S8 426 and 9 carry bits C9 427 . On line 424 , the 7-bit ripple carry adder 430 outputs 7 bits, and on line 425 , the carry-out bit COUT is output to register 450 . Scratchpad 450 has the following mappings: Line 424 maps to PL[6:0], COUT on line 425 maps to C7, S8 on line 426 maps to Sp[14:7], C9 on line 427 maps to Cp [14:6].

FIG. 4b illustrates an example index unit (eg, 210b of FIG. 3 ) with a special index detection block 467 . The operand A 213 in FIG. 4 a is in the register 420 , while the operand B in FIG. 4 a is in the register 421 . Ea on line 465 is an input to the special exponent detection block and exponent adder circuit 464 . Eb on line 462 is the second input to the special index detection block. The 7 least significant digit bits of Eb on line 462 are input to exponent adder circuit 464 and the 8th bit is inverted by inverter 461 before entering exponent adder circuit 464 at the 8th bit position. The carry value of the exponent adder circuit 464 is set to "1".

Exponential adder circuit 464 operates on Ea 465 and Eb 462 , adding them together and subtracting an offset value of 127. The output is a 10-bit value 466 to scratchpad 470 . Two extra bits, beyond the 8 bits required to encode the exponent, are used to detect an exponent overflow condition. These 10 bits are further checked in exponent exception handling circuit 524, as shown in Figure 5C.

The input index signal is checked in special index detection block 467 to be zero, as indicated by the signal on line 468, or invalid, as indicated by the signal on line 469. The sign bits Sa and Sb from the registers 420 and 421 are input to the exclusive OR gate 471a, and the output thereof is applied to the exclusive OR gate 471b. Additionally, an invalid signal on line 469 is input to an exclusive OR gate 471c. If the null signal is zero, the resulting sign is an exclusive OR function of Sa and Sb. If Invalid is true (equal to "1"), the product sign Sp is set to "zero", as specified in the encoding standard. base 8 conversion

FIG. 5A is a simplified diagram showing a substrate 8 converter block 592 (eg, block 220 of FIG. 2 ). The base 8 converter block 592 consists of two sub-blocks, in this example the final addition significand selection and base 8 conversion sub-block 592a and the exponent exception handling sub-block 592b. converted to base -8 , 2 's complement significand

The external input operand A is converted to base-8 encoding in the second pipeline stage. The operand A significand is converted to a 2's complement significand. The significand is extended to 34 bits, including two significand sign bits. As shown in FIG. 5b, the resulting pipeline register 520 contains a 5-bit exponent, a 34-bit significand, and two additional status bits, for a total of 41 bits.

The conversion to base-8 is implemented using the last 3 bits of the exponent to align the 24-bit operand significand from the scratchpad 450 of FIG. The LSB of the significand is aligned if the 3-LSB of the exponent equals 0 (shifted right by 8 positions from the binary point). Any value represented by the 3-LSBs of the exponent is the amount by which the significand is shifted left (from the 8th bit position) to compensate for those bits that were truncated from the exponent. The remaining bits up to the binary point, and the two bits beyond, are filled with sign extension bits. In the case where all three exponent LSBs are b'1, that is, equal to decimal 7, the first significand bit of the 32-bit significand will be a nonzero bit, that is, the normalized significand. Since the significand is represented as 2's complement, the two extra bits to the left of the significand point will be used to store the sign bit (including the extended sign bit). An extra second sign bit is used instead of one in order to preserve the sign since a possible overflow condition would cause the 2-bit integer to overwrite the lower sign bit (Fig. 5b).

Depending on the sign of the product, the significand is crossed or inverted to create a 2's complement negative representation of the significand. This implementation differs from IEEE 754, where the significand can be positive or negative. This operation is performed by adding a sign bit to the 24-bit significand and inverting these bits when the sign is equal to 1 (negative number).

Check for values with exponent between -126 and 126. If it is greater than 126, it is treated as infinity; if it is less than -126, it is treated as a denormalized number (less than -126) and converted to zero (Fig. 5c).

In some implementations, the final scratchpad at this stage of the pipeline contains a normalized floating-point product with a 5-bit exponent and a 34-bit 2's complement significand, (containing the repeated sign of the product, and no Implicit 1) and three exponent status bits.

FIG. 5B illustrates an exemplary schematic diagram of the final partial product addition, significand selection, and base-8 conversion sub-block 592a. Register 450 (FIG. 4a) contains fields for PL[6:0], C7, Sp[14:7] and Cp[14:6]. Register 470 (FIG. 4b) contains a field for a 10-bit product exponent (Ep) value. The register 504 includes status bits.

In cases where the pipeline runs in FP32 add mode, operand A is in FP32 format and the multiplier is bypassed. In this case, operand A originates from register 460 and occupies two combined 16-bit registers 420 and 421 . The add_op control signal on line 511 indicates when the pipeline mode is set to add (single precision floating point in this example) or accumulate.

Significant final adder circuit 502 receives Sp[14:7] on line 503, Cp[14:6] on line 501, and carry bit C7 on line 507 as inputs, and outputs overflow signal 519 to overflow selection circuit 506. Overflow select circuit 506 has an input bus 523 which is a combination of PL[6:0] on line 509 and the significand final adder circuit 502 output on line 521 . Inverse OR gate 522 has an input exponent overflow bit on line 525 and a zero force bit on line 468 and outputs a signal on line 527 . The signal on line 527 and bus 529 output by overflow select circuit 506 is routed to AND gate 544 which sets the significand to all zeros in the event of exponent overflow and in the event the significand is forced to zero. In addition, the valid number selection circuit 512 uses the add_op control signal on line 511 to select between the bypass valid number Fa[22:0] on bus 515 or the output of AND gate 544 on bus 553 .

The exponent selection circuit 510 selects between the 8 exponent bits, Ep[7:0] on line 517, or the bypass exponent bits Ea[30:23] bits on line 513, and selects the selected exponent on line 533 The exponent is output to the E_mult field of register 520 . The sign bit selection circuit 508 receives as input the Sp sign bit on line 473 ( FIG. 4 b ) and the bypass sign bit Sa, and outputs the sign bit 531 to the S_mult field in the register 520 .

The add_op control signal on line 511 is routed to significand select circuit 512, exponent select circuit 510, and sign bit select circuit 508 as their control inputs.

The output of significand select circuit 512 enters 8-bit left shifter circuit 514 . The lower three bits [2:0] from the line 533 of the index select circuit 510 are output on line 533 to control the 8-bit left shifter circuit 514. The output bus 537 of the 8-bit left shifter circuit 514 feeds Input multiplexer circuit 518 that selects between the input on line 537 (if the significand is positive) and the input on line 539 (if the significand is negative). This is selected by sign bit 531 . 2's complement inverted add 1 circuit 516 builds the 2's complement output of the shifter on line 537 and outputs the complement value on line 539 . The output of the multiplexer circuit 518 on line 541 enters the pipeline register 520 as a 34-bit F_mult significand. The program converts the selected significand into a 2's complement significand, which is 32 bits long with 2 sign bits, stored in pipeline register 520 .

Figure 5C illustrates a block diagram of the exponential exception handling sub-block 592b. Significant final adder circuit 502 receives inputs Sp[14:7] 503 , Cp[14:6] 501 and carry bit C7 507 from scratchpad 450 as described with reference to FIG. 5 b . The overflow output of significand final adder circuit 502 is connected to exponent exception handling circuit 524 . Upon detection of an overflow condition, significand final adder circuit 502 asserts overflow signal 519 as a first input to exponent exception handling circuit 524 . The second input of the exponent exception handling circuit 524 is the exponent bits Ep[9:0] (sum of input operand exponents) from the register 470 on the bus 517 . The third input is the output signal of the exponent overflow detection circuit 522 on line 523 . The output of exponent anomaly processing circuit 524 is then input on line 549 to exponent anomaly detection circuit 526 and exponent selection circuit 510 (described with reference to Figure 5b).

The exponent bits Ep[9:0] on the bus 517 are input to the exponent overflow detection circuit 522, which detects an overflow condition: exp_ovf=Ec[8], indicates that if bit 8 is 1, an exponent overflow is detected, exp_povf=~Ec[9]&Ec[8]: If bit 9 is 0 and bit 8 is 1; positive overflow, exp_novf=Ec[9] & Ec[8]: If bit 9 and bit 8 are both 1; negative overflow. The first output on line 523 of circuit 522 is routed to exponential exception processing circuit 524, the second output on line 543 is routed to output exception control signal generation circuit 528, and the third output is included on line 525 of gate 522 in FIG. 5B The exponent overflow bits of .

The index anomaly detection circuit 526 outputs an anomaly including the following three bits to the register 532 via the bus 547 : of (overflow); uf (underbit); and nv (invalid). This happens when the following conditions are detected: of(overflow) - means if Ec is 11111111, and infinity is not detected, it is interpreted as overflow. uf (underbit) - means if Ec is 00000000 and zero (significant) is not signaled, then an underbit condition. nv (invalid) "1" - means the result is invalid.

The output abnormality control signal generating circuit 528 has four inputs. The first input is the add_op control signal on line 511, which indicates accumulate or bypass add mode, the second input is the status bit (infinity, zero, or invalid) on line 509, and the third input on line 545 is from The multiplexed exponent select circuit 510 routes between the Ea[30:23] bits of register 460 or the output of exponent exception handling circuit 524, while the fourth input comes from the second output on line 543 of exponent overflow detection circuit 522 . The output exception control signal generating circuit 528 outputs five bits on line 551 , representing exp_mul_zero, exp_mul_inf, exp_zero_en, exp_inf_en and f_zero_en stored in the register 530 . exp_mul_zero means: the multiplier product exponent is zero, exp_mul_inf means: the multiplier product exponent is infinity exp_zero_en means: when (one of the multiplier input exponents is zero, and none of the multiplier input exponents are zero) or the multiplier product exponent has negative Enable on overflow, exp_inf_en Meaning: enable when one of the input exponents of the multiplier is infinite or the multiplier product exponent has a positive overflow. ) or enabled when the multiplier product exponent is zero. carry-save accumulator unit

FIG. 6 illustrates a block diagram 600 of a carry-save accumulator (eg, 240 of FIG. 2 ) for a significand. Base-8 converter 215 receives operand C as input and outputs operand C in base-8 format on line 219 to multiplexer 210 and multiplexer 211 . Two additional inputs to multiplexers 210 and 211 are busses 224 and 225 fed back from accumulator sum register 242 and accumulator carry register 241 . The outputs of multiplexer 210 and multiplexer 211 are routed to shifter circuits 609 and 610, which perform a right shift by 8/16/24 bits or a left shift by 8 bits. The outputs of the shifter circuits 609 and 610 are routed to a carry-save adder circuit (CSA) 614 . The carry save adder circuit 614 has a third input from the right shift circuit of the 8/16/24 circuit 608 whose input is the product 602 of A*B(BF16) or A(FP32) operands alone. The output of the carry save adder circuit 614 on lines 667 and 669 is routed to the LZA circuit 606 which provides an output to the S bit register 636, and to the overflow detect block 605 which provides an output to the O bit register 634 .

The carry-save-accumulate unit includes the significand of the multiplier output receiving the term A(i)*B(i) at the first pipeline clock of cycle (i) and the feedback representing the previous accumulator output of the sum value S(i-1) Significant circuit for sum and carry values. The significand circuit includes a 2's complement, carry-save adder for generating a sum and a carry accumulator to output a significand value for the sum S(i) at the second pipeline clock. a carry save accumulator unit comprising an exponent circuit receiving at a first pipeline clock the multiplier output exponent of the term A(i)*B(i) and the feedback exponent value representing the previous accumulator output of the sum value S(i-1), The accumulator output index value is generated on the second pipeline clock for the sum value S(i). The significand circuit includes a significand shifter responsive to an exponent comparison signal stored at the first pipeline clock to align the multiplier output significand and a feedback sum and carry value for addition. The exponential circuit generates an accumulator output exponential value in response to the exponential comparison signal stored at the first pipeline clock. The pipeline includes exponent comparison circuitry to compare the multiplier output exponent of term A(i)*B(i) with the feedback exponent value of sum S(i-1) prior to the first pipeline clock to generate the value stored at An exponential comparison signal at a pipeline clock.

The carry-save-accumulate unit in this embodiment includes an overflow detector circuit to generate a first condition signal indicating an overflow condition for at least one of the sum and the carry value fed back at the first pipeline clock, and a leading sign bit and a meta detector circuit to generate a second condition signal indicating that at least one of the fed back sum and carry values has more than or equal to a number of eight extended sign bits at the first pipeline clock. The exponent circuit and the significand circuit are also responsive to the first condition signal and the second condition signal. Overflow and leading sign bit adjustment and exponent compare adjustment are combined to be implemented by the shifter in the same pipeline cycle as described with reference to Table 1: CSA unit control below.

Additionally, this stage of the pipeline features accumulator mode and sum mode and includes selectors to provide the fed back accumulator output in accumulator mode and a third floating-point input operand in sum mode to an active Number circuit and index circuit. The significand circuit may include a significand shifter responsive to the exponent compare signal stored at the first pipeline clock to align the sum and carry values of the multiplier output significand and feedback for addition in accumulator mode, and Aligns the multiplier output significand and the significand of the third input operand for addition in sum mode. The exponential circuit generates an accumulator output exponential value in response to the exponential comparison signal stored in the first pipeline clock. The pipeline includes exponent compare circuitry to compare the multiplier output exponent with the fed back exponent value in accumulator mode prior to the first pipeline clock, and to compare the multiplier output exponent with the value of the third input operand in sum mode The indices are compared to generate an index comparison signal stored in the first pipeline clock. Significant number circuit:

The carry-save adder (CSA) significand stage has two paths: the accumulator path, where operands from the accumulator can be shifted right by 8, 16, or 24 bits, and can be shifted left by 8 bits, and Multiplier path, where operands from the multiplier can be shifted right by 8, 16, or 24 bits. When using base-8 exponents, a right shift of 8, 16, or 24 bits corresponds to an exponent difference of 1, 2, or 3 between the operands. An 8-bit left shift is done when the carry-save adder outputs a sign-extended number beyond 8 bits.

If the difference between the operand exponents is greater than 3, it means that one of the operands has been shifted to the right by more than 24 bits, which makes the operand too far right aligned to be within the bounds of the larger operand. This case is equivalent to adding zero to the larger operand, or using a bypass multiplexer to simply pass the larger operand unchanged to the accumulator (Figure 7c).

This implementation eliminates the bypass multiplexer by adding CSA to zero when the exponent difference is greater than 3, equivalent to bypassing the operand. The input to the CSA comes from the multiplier and accumulator, and is gated by an AND gate. The shifter and exponent control unit detects this condition and sets the appropriate operands to zero. This implementation saves a multiplexer stage in each path.

The detection of sign extension occurs after the 3:2 carry-save adder stage. If this condition is detected, the sign extension bit S and the overflow bit O are set and processed on subsequent pipeline clocks. In order not to lose the sign bit due to overflow, the calculation carries repeated signs. Additional complexity is introduced to improve accuracy. This involves extending the accumulator to 36 or 40 bits. In another implementation, the introduction of detection logic improves timing and accuracy. The detection logic takes the inputs of the carry-save adder circuit (CSA) 614 from three inputs 683, 685, 689 instead of the two outputs of the carry-save adder circuit (CSA) 614 and is the subject of another related disclosure. Exponent circuit:

An "exponent control unit" compares the exponent difference between the first exponent operand from the multiplier and the second exponent operand from the accumulator. The index control unit checks the conditions generated by comparing the multiplier and accumulator indices and selects the operand path according to Table 1. At the same time, a new accumulator index is determined and stored in the index accumulator (Eacc) register 654 (FIG. 7b).

The exponential part has two branches: the left branch and the right branch. The left branch consists of inputs 671 and 673 (Entry OR gate), selects the larger of the two indices, then becomes the resulting index. Select this condition according to Table 1. The right branch consisting of inputs 675 and 677 (into the exponential output or gate) will select either Ea+1 or Ea-1 according to the conditions described in Table 1. If significand overflow is signaled, the accumulator significand shall be shifted right by 8 bits (SHR_8), and the exponent shall be incremented by 1.

Overflow (O) detection is performed during CS addition. If an overflow is detected, the O bit is latched into the output pipeline register. The overflow condition will be corrected according to Table 1 in the next cycle. Implementation of CS-cumulative

The functions of the exponent path and the significand path are interdependent, depending on the exponent generated by the significand part and the state of the "sign extend" (SE) and "overflow" (O) signals. There are two accumulators, one for carry and one for sum. They are added to the product using a 3:2 carry-save adder (CSA) and threaded through two separate paths, one for the carry and the other for the sum.

The target register of the pipeline stage is an accumulator containing the carry and sum (two registers). The conversion to legacy format is performed in the next pipeline stages (Pipeline 4 and Pipeline 5). The carry save phase can be a timing critical phase. Therefore, pay special attention to the timing and regions described in this section to guide design decisions. The critical path of the pipeline stage contains: exponent control, three 2:1 multiplexers, a 5-bit subtractor, a 5-bit subtractor and compare unit, in the exponent part, and in the significand part, the exponent control , 5-bit incrementer, 3:2 carry-save adder (CSA) and an AND gate. The critical path can traverse both the exponential path and the significand path, as is the case in this design. accumulator design

7A illustrates a simplified block diagram 610 of accumulator 240, which includes three circuit blocks: exponent control unit 240A, exponent comparator unit 240B, and significand portion 240C.

*其中： emult：        是乘積指數 eaccu：        是累加器指數 emmp           含義：emult大3以上 eamp           含義：eaccu大4以上 還有其它控制訊號： accum_ld  -含義：累加器接收輸入C值。 exp_zero_en-含義：將乘積指數設置為零。 f_zero_en -含義：如果Exponent=0，則將乘積有效數設置為0(因為不允許非正規) e_cin_zero -含義：輸入C指數等於零 FIG. 7B illustrates an exemplary hierarchical block diagram and schematic diagram of the exponent control unit 240A and the exponent comparator unit 240B. Shifter exponent control signal generation/bypass control circuit 630 receives inputs from: accum_ld, exp_zero_en, f_zero_en, e_cin_zero, 551, csa_ovf bit 634 O and Signext which is S bit 636 and 16 bit multiplier exponent compare The output of circuit 652, which is stored in the 16-bit status register 650, sixteen exponent comparison bits*:

* Among them: emult: is the product exponent eaccu: is the accumulator exponent emmp Meaning: emult greater than 3 eamp Meaning: eaccu greater than 4 There are other control signals: accum_ld - Meaning: the accumulator receives the input C value. exp_zero_en - Meaning: Set the product exponent to zero. f_zero_en - meaning: if Exponent=0, set product significand to 0 (since denormals are not allowed) e_cin_zero - meaning: input C exponent equal to zero

The outputs of the shifter index control signal generation/bypass control circuit 630 are control signals: accumulation shifter control on line 638, accumulation bypass control on line 636, multiplier bypass control on line 634, and Multiplier Shifter Control on 632 , Ea_sel on line 646 , Ea1m_sel on line 642 , Em_sel on line 648 , Ea1p_sel on line 645 .

Comparator circuit 652 compares the exponents of the two operands from: (1) the multiplier exponent E_mult on line 521 and the accumulator exponent on line 679; (2) or input A (in bypass mode from (3) or input A (from exponent E_mult on line 521 in bypass mode) and input C (from exponent Ec on line 460). Comparator circuit 652 generates the following status bits stored in 16-bit status register 650: emult: multiplier index; eaccu: accumulator index; z_diff - emult is the same as eaccu; mgrt - emult is greater than eaccu; agrt - eaccu is greater than em1p - emult big 1; em2p - emult big 2; em3p - emult big 3; emmp - emult big 3; ea1p - eaccu big 1; ea2p - eaccu big 2; ea3p - eaccu big 3; ea4p - eaccu big 4; eamp - eaccu is greater than 4; emz - emult is zero; eaz - eaccu is zero; eminf - emult is infinity; and eainf - eaccu is infinity. The 16-bit status register 650 interfaces with the shift bit index control signal generation/bypass control circuit 630 through the bus 621 . The 16-bit status register 650 stores the comparison result of Eacc from the sum S(i-1), and during generation of Eacc for the sum S(i), the E_mult register 520 stores the term A(i) in accumulate mode *B(i).

The input to compare circuit 652 on line 647 is from subtractor circuit 646 . Subtractor circuit 646 receives E_mult from pipeline register 520 on line 521 and the output of multiplexer 642, which performs a process between Ec from register 460 and the new exponent output on line 679 of OR gate 670. Select, where the multiplexer 642 is controlled by the accum_en signal on line 665 indicating the mode. (Figure 7b)

Exp_Zero_En on line 618 is applied to inverter 619 whose output is used as input to AND gate 617 . The E_mult exponent bit from pipeline register 520 is also input to AND gate 617, whose output on line 681 feeds AND gate 668, where the Em_sal bit on line 648 comes from the shifter exponent control signal generation/bypass Control circuit 630 to pass or block E_mult. The output on line 671 of AND gate 668 is connected to a four-input OR gate 670 . OR gate 670 has three other inputs, including the output of AND gate 615, which is selected by signal Ea_sel to pass through or block Eaccum, while the output of incrementer 660 on line 616 and the output of decrementer 661 on line 663 are each output from Ea1p_sel and Ea1m_sel are controlled at AND gates 664 and 665, respectively. According to the selection signal (only one of which can be 1), 648, 646, 645, 642, the appropriate index is selected as the output of the OR gate 670. This output is the Eacc signal, also known as the new exponent, which is the input of the exponent accumulator (Eacc) register 654 and the input of the multiplexer 642 .

The output of the multiplexer 665 ("the new index of the sum S(i), or the index of the operand C, depending on the mode) is also recorded in this embodiment in the scratchpad 460, which is on line 644 The upper connection is the input of the incrementer 660 and the decrementer 661 .

Thus, when the new index on line 679 represents the sum S(i) using the comparison bits produced by the sum S(i-1), the new index will be in the entry A(i-1)*B( The E-mult values of i-1) are compared to generate a comparison signal that will be latched with the sum S(i) and used for shifter control during generation of the sum S(i+1).

FIG. 7C is a schematic diagram of the significand portion 240C. A shifter index control signal generation/bypass control circuit 630 is illustrated showing four output control signals. The first control signal is the accumulator shifter control on line 638 , which is the select signal for shifter circuits SHR8/16/24/SHL8 609 and 610 . Two shifter circuits: SHR8/16/24/SHL8 609 and 610 receive inputs from a set of multiplexers 210 and 211 on lines 682 and 683 . The accum_en signal on line 665 controls multiplexer 210 and multiplexer 211 to select between the sum on line 224, the carry on line 225, or the value on line 219, derived from register Fcin 560 or logic " 0" as another input of the multiplexer 211. Multiplexers 210 and 211 output the selected values on bus 682 and bus 683 to shifter circuits SHR8/16/24/SHL8 609 and 610 . Shifter circuits 609 and 610 output the shifted values on buses 692 and 693 . Bus 692 may interface directly to bus 613 or may traverse optional carry rounding block 604 which adds the rounded bit amount to bus 613 . Bus 693 may interface directly to bus 611 or may traverse optional sum rounding block 612 and add round bits to 693 . Buses 611 and 613 are inputs to AND gates 687 and 688, whose outputs are used as inputs to carry-save adder circuit 614 on lines 689 and 685 (the AND symbols indicate the diversity of AND gates for each signal line on the bus: 613 , 611 and 607. The inputs of the AND gate 688 and the AND gate 686 are selected by the control signals on the line 633 and the line 634 respectively.

The F_mult value in pipeline register 520 is input to simple product rounding block 684 , which is input directly to shift register SHR 8/16/24 circuit 608 on line 603 . The select signal for SHR 8/16/24 circuit 608 is a multi-shifter control on line 632 that selects between the F_mult input on line 601 and the rounded product on line 603 . The output is the product on bus 607 containing 42 bits (34+8), which is applied to the input of AND gate 686 , whose output is the input to carry save adder circuit 614 .

The 42-bit 3:2 carry-save adder circuit 614 has three inputs including the output 683 of the AND gate 686, the output 689 of the AND gate 687, and the output 685 of the AND gate 688. The 42-bit 3:2 carry-save adder circuit The output of 614 is two buses: a sum bus 669 and a carry bus 667. The two outputs 669 and 667 respectively enter the 42-bit fractional sum register 242 through the bus 669 and enter the 42-bit fractional carry register 241 through the bus 667 . Bus 669 and bus 667 are also inputs to overflow detection block 605 and sign extension detection unit 662 . Two blocks, the overflow detection block 605 and the sign extension detection unit 662, provide outputs to the O bit 634, the csa_ovf signal and the S-bit 636 which is the sign extension signal. Sign extension detection unit 662 has an enable bit accum_en signal on line 665 which is set to logic "1" when the operation is accumulation. The sign extension detection module can only operate when the "accum_en" signal is enabled. There are three operation modes to choose from, which are: input A(BF16) x input B (BF16) + input C (FP32), input A (BF16) x input B (BF16) + cumulative loop (sum), input A (FP32) + input C(FP32). The "accum_en" signal is only enabled during the second mode condition (accumulation). In additive mode, sign extension detection is not required. Required only in accumulate mode, since the gradual increment of the sign-extended bits can only occur during the accumulate operation. Sign extension detection unit 662 :

According to some aspects, sign extension detection unit 662 is attached to the accumulator output of both the sum and the carry. When a 10-bit sign is detected (including two sign bits, and an extra 8 bits in the first byte of the sum or carry), the output will be shifted left in the next cycle (SHL_8) to hold the operand accuracy. Without sign-extension detection, during normal operation, the significand bits of operands are gradually shifted to the right until they are replaced by sign-extended bits, resulting in a loss of precision. In the implementation, each time one of the operands detects at least 10 leading sign bits, the justification performs a left shift of the operands by 8 bit positions. The index is adjusted accordingly by subtracting one from the index value, which is performed in the same cycle. When S is detected in the carry or sum portion of the accumulator, the S bit is latched in the output pipeline register 636 for correction in the next cycle. The correction operation shifts the accumulator left by 8 bit positions (SHL_8). Sometimes this condition may cancel itself on the next action (requires SHR_8), and usually remains unchanged, as shown in Table 1. Normalization and conversion to symbolic numeric format

FIG. 8A illustrates a normalized conversion to signed numeric format block 270, which contains two sub-blocks, the first sub-block is the conversion from carry-save to signed numeric format block 270a, and the second sub-block is the conversion from base-8 to base-2 float Points block 270b.

FIG. 8B illustrates an exemplary schematic diagram of the convert from carry-save to signed value format block 270a. Two temporary registers, the 42-bit decimal sum temporary register 242 and the 42-bit decimal carry temporary register 241 output shift carry [42:0] bus 704 and sign extension sum [42:0] bus 702 as Input to 43-bit adder circuit 708. Second circuit LZA/LOA 710 receives input bus 702 and bus 704 . The second circuit LZA/LOA 710 outputs two bus bars POS_P[5:0] on line 711 and POS_N[5:0] on line 712 to the third LZA POS selection circuit 714 . The output of LZA POS select circuit 714, eg, via bus 715, is POS[5:0], which maps to register 730 as a 6-bit location specifying the amount of left shift required to normalize the significand.

43-bit adder circuit 708 outputs signal SIGN on line 719 to control LZA POS select circuit 714, routes bus 716 to significand select multiplexer circuit 720 on the "0" branch input, and routes bus 716 to Negative input: inverting and adding 1 circuit 718. The "1" branch of 2's significand selection multiplexer circuit 720 receives bus 717, which represents a negative significand, which is converted to a positive one. Symbol 719 controls the significand select multiplexer so that output 738 always contains a positive significand. The output of 2's complement select multiplexer circuit 720 is bus 738 , which maps to register 730 as a 41-bit positive significand. The 5-bit exponent on line 706 maps directly to register 730 and sign bit 726 . This step completes the conversion of the accumulator significand in carry-save format to signed numeric base-8 format.

At this stage, the two values on sum bus 702 and carry bus 704 (representing the significand in carry-save format) are summed in 43-bit adder circuit 708 to produce the sign-valued format of the significand. The leading zero/leading one predictor (second LZA/LOA circuit) 710 will calculate two numbers: the number 711 of leading zeros (in case the significand 716 is positive) and the number 712 of leading ones (in case the significand 716 is positive). negative case). According to the significand sign bit 719 , the multiplexer LZA POS selection circuit 714 will select the correct position and store it in the register 730 . Both LZ and LO positions POS_P and POS_N are 6-bit long numbers, expected to contain 32 cases of leading zeros or ones.

If the significand of the output of the 43-bit adder circuit 708 is negative, the negative number is converted to a positive number (since IEEE 754 uses signed value representation, that is, a positive significand). For this purpose, a 2's complement converter 718 is used. The sign bit 719 controls the multiplexer circuit 720 so that if the number is positive, it is stored directly into the 41-bit significand register 730 . If the output is negative, the output on line 717 , the value on 716 converted to a positive value, will be passed to scratchpad 730 on line 738 .

The predicted 6-bit position of the significand will be added to the 5-bit exponent to produce a new 8-bit exponent conforming to the standard floating-point representation, and the significand will be aligned relative to the floating-point significand, using the same 6-bit Predicted location (Fig. 8c).

FIG. 8C illustrates an exemplary schematic diagram of block 270b from base 8 to base 2 floating point conversion. The register 730 is connected to the SHL left shifter circuit 735 through a 41-bit bus 731 . The register 730 is connected to the effective zero detection circuit 728 through the 41-bit bus 734 . The 6-bit position field of register 730 provides Pos[5:0] on line 723 to control SHL left shifter circuit 735 . Pos[5:0] on line 723 is also an input to exponent adder circuit 740 . The exponent 5-bit field of register 730 is the second input to exponent adder circuit 740 on line 721 . Exponent adder circuit 740 adjusts (increases) the exponent of the significand indicated by POS[5:0] shifted left by the number of positions and provides an output on line 736 to register 748 . However, since the predictor may be wrong in one position, the output of the shifter is passed to the overflow/under detection circuit 752, which will signal the error by issuing signal 739, which is applied to the exponent adder circuit 740 The carry input is the control input of the under detection multiplexer 760 . Under detect multiplexer 760 has an input on line 746, where the valid number on line 742 from shifter circuit 735 is in the same position (no error detected), and an input on line 747, where the valid number on line 742 The number is shifted left by one bit (error detected). If signal 739 indicates an underdetection, the correct output will be latched into register 770 via bus 745 . Errors in exponent adjustment are corrected by inputting 1 to the adder via the carry input. Symbolic values are copied from scratchpad 730 to scratchpad 747 .

The sign bit in register 730 is passed to register 747 via line 744 .

Exception control (8-bit) register 750 passes its value to exception control register 751 on line 724 . The meanings of the exception control register bits are as follows: exp_inf_en: operand A is infinity or operand B is infinity z_diff accumulator index equals product index s_mult: product sign s_cin: Enter the C symbol e_mul_zero: Product index = 0 e_cin_zero: Enter C Index = 0 e_mul_inf: The product exponent equals infinity. e_cin_inf: Enter C exponent equal to infinity. Bit six 726 of the exception control (8-bit) register 750 is "z_diff", indicating the result of the exponent comparison between the accumulator and the product exponent. When equal to 1, the accumulator's exponent is equal to the product's exponent. When "z_diff"=0, it means that the accumulator index is less than or equal to the product index. Bit [6] "z_diff" is the first input on line 726 to significant zero detect circuit 728 . Significant zero detection circuit 728 outputs a 1-bit signal on line 753, which replaces bit [6] "z_diff", which now becomes "pos_zero" 753 in exception control register 751, indicating that the resulting significand is zero. Once the accumulation operation is complete and the operation proceeds to normalization, the second output of significant zero detection circuit 728 provides a signal on line 755 to fractional zero register 756 .

FIG. 9A illustrates performing 700 the final conversion to BF16 or IEEE 754 32-bit single-precision format block 270, including performing rounding and converting to BF16 or IEEE 754 32-bit single-precision format signed numeric format block 270a and executing Sub-block 270b for index and exception handling. Round and convert to FP32 format

According to certain aspects, the final stage is pipeline 6, which performs rounding of the result to a standard floating-point sign/value number, which has the following: sign bit, 8-bit exponent, 23 bits, normalized significand (+ 1 implies an integer bit). During conversion of the 31-bit significand to the 24-bit normalized significand with an implied bit, the result is rounded from 31-bit to 24-bit. In this implementation, two rounding modes are implemented: round towards zero (RTZ) truncate, round to nearest even (RNE). However, any other rounding mode, eg, round to nearest odd (RNO), can easily be incorporated.

According to some aspects, the rounding logic checks the last 15 LSB bits of the 39 significand bits from scratchpad 770 (not counting the GRS bits that make up the total 42 bits (39+3 GRS bits)) , and determine whether the remaining 24 bits need to be rounded (according to the rules imposed: RNE or RTZ). The incrementers required by the RNE are included in the rounding box. The three bits GRS carried from the accumulator (CSA) operation are ignored in this implementation. They can be incorporated into the final rounding of other possible implementations. Rounding is done in one of several ways: (a) apply round-to-nearest-odd (RNO) during CS accumulation operations, - For sum signals, only if the round bit is inserted into the carry LSB on position, - For each sum signal and carry signal respectively, (b) during CS accumulation, and at the pipeline 6 stage (final rounding), and (c) Only in pipeline 6 stage, and CSA is disabled. Each rounding mode is imposed according to the precision and specific requirements imposed by the particular application.

The output of line 6 is FP32 or BF16 as desired. Therefore, the significand length is 24 (23+implied bits) or 8 bits (7+implied bits). This is controlled by the "Out_FP32" signal applied to the first multiplexer. If rounding results in a 25-bit significand, the significand will be shifted right by one position and the exponent will be incremented by 1.

The properly normalized and rounded result is stored in the output register of pipeline 6 as a BF16 number consisting of a 1-bit sign, 8-bit exponent, and 7-bit fractional significand, or a 1-bit sign, An FP32 number consisting of an 8-bit exponent and a 23-bit fractional significand.

FIG. 9B illustrates an exemplary schematic diagram showing rounding and conversion to BF16 or IEEE 754 32-bit SP format. The 39-bit significand scratchpad 770 bus fpst_l[38:0] 837 provides fpst_l[32:0] 819 or fpst_l[16:0] 819 to include protection bits, rounding bits, and sticky bits The rounding circuit 830. Control Out_FP32 selects the portion of the significand on line 819 to be rounded by rounding circuit 830 . In case the 32-bit SP format is selected, 3 rounding bits are added to the upper 24 bits [38:16]. Multiplexer 840 selects between a "0" input on line 835 or the output of round circuit 830 on line 825 , where multiplexer 840 is controlled by round-to-zero select line 823 . This happens when the exponent exceeds -126 and the significand becomes denormal, causing rounding to zero in this implementation. The output on line 827 routes 23 bits (one implied) and 3 round bits to first round increment circuit 860 so that the significand is properly rounded on line 819 in IEEE 754 SP 32 bit format.

When the BF16 output format is selected, the second round increment circuit 850 is used for rounding to BF-16 format. The conversion of the 39-bit significand from fpst_l[38:0] 817 to the BF-16 output on line 817 is done in round-increment circuit 850, resulting in 7 bits (one implied), plus 1 rounding decision bit element, and an extra 16 zeros. This represents the significand at the output on line 821 as one of the inputs to multiplexer 802 .

The first multiplexer 802 uses the control line signal Out_FP32 801 to select FP-32 or BF16 output. When Out_FP32 801 is active, it outputs FP-32 format valid numbers on line 805 . When the Out_FP32 801 control signal is inactive, the output on line 805 is a valid number in BF-16 format. The output of the first multiplexer 802 is a bus 805 , which splits into a bus 807 and a bus 809 , entering the second multiplexer 810 . Multiplexer 810 is controlled by bit 24 of the output bus on line 805 and the frnd[23] signal on line 803 . Where rounding produces a 25-bit significand, as described in [0093], the 24th bit will be 1. In this case, the signal frnd[23] bit on line 803 selects input bus 807, which shifts bus 805 to the right by one bit position. (The frnd[23] signal also increments the exponent of the result by 1 to adjust for the right shift. If frnd[23] is equal to 0, no right shift is required and bus 805 will go directly across line 831 through the selected input bus 809 .

A third multiplexer (zero) 820 selects between all "0"s on line 829 input or fnorm[22:0] on line 831 . If the output exponent is infinite or denormal, the output significand is forced to zero, which is done by control signal Zero_Sel on line 788 , which selects all "0" inputs 829 . If there are no exceptions, normalized significand bus 831 is routed as bus 833 and mapped to 23-bit significand (IEEE 754) scratchpad 930 .

FIG. 9C illustrates an exemplary schematic diagram showing index and exception handling block 270b. The 8-bit exponent 748 provides the EPST_L[9:0] 964 bus and is incremented by 1 if frnd[23]=1. This is accomplished by routing frnd[23] to the carry position of incrementer 982. The output of the exponent incrementer 982 is the 9-bit Enorm[8:0] bus 968 which is the first input to the first multiplexer (zero) 974 . The second input of the first multiplexer (zero) 974 is the all "0" bus 829 . The purpose of the first multiplexer (zero) 974 is to set the exponent to all "0"s in case an exception is required, indicated by the exception control (8-bit) register 750 through the zero control logic 970 .

The exception control (8-bit) register 750 operates on the following eight conditions 953: exp_inf_en, pos_zero, s_mult, s_cin, e_mul_zero, e_cin_zero, e_mul_zero, and e_cin_inf.

Zero control logic 970 has three inputs: sign_diff from exclusive OR gate on line 961 and e_cin_zero on line 959, e_mul_zero from exception control (8-bit) scratchpad 750 on line 957, and output on line 972 The first multiplexer (zero) 974 is controlled. The output on line 975 of the first multiplexer (zero) 974 passes through multiplexer 976 to provide an index signal bus 979 stored in index register 980 . If infinity control 962 signals infinity on line 963, an all "1" input on line 907 passes through multiplexer 976, setting all exponent bits to "1", as recommended by the IEEE 754 standard. The meaning of the signal is: (explained in paragraph 089) exp_inf_en operand A is infinity or operand B is infinity pos_zero The result significand is zero s_mult product sign s_cin Enter the C symbol e_mul_zero Product index = 0 e_cin_zero Enter C Index = 0 e_mul_inf The product exponent equals infinity. e_cin_inf Enter C exponent equal to infinity. Furthermore, the signal "sign_diff" indicates that the sign of the product "s_mult" is different from the sign of the input C "s_cin". The signals are obtained by applying a mutex or function to the s_mult and s_cin signals taken from the exception control (8-bit) register 750 .

Exception control (8-bit) register 750 provides the following signals on bus 965 to sign generation and exception handling circuit 988 and under/overflow detection and exponent anomaly detection circuit 986: s_cin, s_mult, exp_inf_en, e_cin_inf, e_mul_inf , pos_zero, sign_diff. The control signals for circuit 986 are norm_en 758 on line 969 and fractional zero register 756 on line 971 . The outputs of circuit 986 are three signals ov (overflow), uf (underflow) and (invalid) nv. A fourth output on line 991 is sent from infinity detection circuit 992 to sign generation and exception handling circuit 988 to indicate overflow.

The signals have the following abbreviations, as follows: s_cin (enter C symbol), s_mult (multiply sign), e_mul_zero (multiply exponent zero), e_cin_zero (enter C exponent zero), e_mul_inf (multiply exponent infinite), and e_cin_inf (enter C exponent infinity).

Two related events cause an underbit. One is to create a tiny non-zero result between ±2-126 [where -126 is the minimum exponent value], since it is so small that it might later cause some other anomaly, such as overflow in division. Another incident is the unusual loss of accuracy during approximations to such small numbers. Loss of precision may be detected when the passed result differs from the result computed with the exponent range and precision unbounded. IEEE Std 754 does not track precision other than requiring single and double precision. In this disclosed implementation, no "denormal" numbers are used, and any value with an exponent of -126 and a significand less than 1 will be converted to zero. Zero is represented by setting all significands to zero and the exponent value to zero, which is handled by the exception handling circuitry in our disclosed implementation.

Symbol generation and exception handling circuit 988 receives input from exception control (8-bit) register 750 via bus 965 and infinity detection circuit 992 . The output of sign generation and exception handling circuit 988 is a sign bit, which is stored to register 990 via signal line 983 .

The infinity detection circuit 992 operates on the exponential signal bus 979 input and if it detects that all exponent bits are 1, it will provide a "1" to the OR gate 987 which in turn sets its output 788 to a "1" . This sets the ZERO-SEL signal 788, which sets the significand to all zeros (Mux 820, FIG. 9B).

When the index value on index signal bus 979 is out of range, denormal circuit 994 detects this condition and signals an underbit condition on signal line 967 . This condition is also signaled to OR gate 987 which generates signal ZERO-SEL on line 788 . The ZERO-SEL signal on line 788 (FIG. 9B) will instruct the multiplexer 820 to insert all '0's into the significand, thereby creating the correct IEEE 754 representation of 'zero' (both exponent and significand contain all '0's).

A floating-point multiply-accumulate unit using carry-save add and accumulate with base-8 exponents is described. This balances critical timing for exponential units with critical timing for significand units. Also, unlike the signed numerical representation proposed in the floating-point IEEE-754 standard, the 2's complement number system is used to represent positive and negative significands that also have operand signs. This avoids unnecessary significand subtraction when exponents are equal to determine the greater of the two as specified by the IEEE-754 standard. The introduction of 2's complement representation requires a novel leading zero (leading one) detector (predictor) suitable for both positive and negative numbers. The same applies to overflow (OV) detection. Furthermore, it is necessary to determine when adding the carry and sum results in a long sign extension (SE), which requires the introduction of novel design features.

Describes the floating-point multiply-accumulate unit, supporting BF16 format for multiply-accumulate operations, and FP32 single-precision add in accordance with the IEEE 754 standard. The multiply-accumulate unit uses a higher internal precision and longer accumulator to facilitate precision and comparisons and operations with negative numbers by converting the operands to a higher base and longer internal 2's complement significand representation . Addition is performed using a carry-save format to avoid long carry propagation and speed up operations. The 2's complement and carry-save formats employ operations such as overflow detection, zero detection, and sign extension. Handling of overflow and sign extension allows fast operations relatively independent of the size of the accumulator. The rounding suitable for machine learning is introduced in the accumulation operation that does not affect the time, which greatly improves the accuracy of the calculation. exception handling

10 to 21 relate to exception handling in the circuits and methods described above. Depending on the particular encoding format used to represent the significand and exponent, floating-point numbers can take on special-case values such as: positive or negative infinity, zero, and denormal numbers.

FIG. 10 illustrates the range of floating point numbers 1000 shown in block 1010 as a horizontal number line divided into regions of interest by a number of terms. Definitions of terms are defined in Table 1. floating point special number

The following list shown in Table 1 contains three rows. The first line lists the definitions of special floating-point numbers. The second line lists the values in BF16 floating point encoding format. The third line shows the value in floating point encoded FP32 format.

In the Note column of Table 1, the term (+)Nan includes the value 7F81 in BF16 and the value 7F800001 in FP32 as two conventions for expressing NaN. The term (+) norm (Norm) is listed as (+)Pi, (3.14...) and the term (-) norm is listed as (-)Pi for testing purposes. The terms (+) non-norm and (-) non-norm are the smallest representable values. (+)Zero and (-)Zero have two representations, the difference lies in the most significant sign bit. The same is true for all other terms related to sign bits.

The BFloat16 floating-point format, also known as the brain floating-point format, (sometimes referred to as "BF16") is a 16-bit numeric encoding format. BF16 preserves the approximate dynamic range of IEEE single-degree precision. The BF16 format includes a 7-bit fraction (also known as a mantissa or significand), an "implicit bit" or "hidden bit", an 8-bit exponent, and a sign bit. Single precision floating point values can be converted to BF16 to speed up machine learning. Dynamic range is the same as single-precision FP32 (8-bit exponent) using 8-bit precision instead of 24-bit fractional. BFloat16 can reduce memory requirements, reduce storage requirements, and increase the calculation speed of machine learning algorithms. BF16 is a truncated 16-bit version of the 32-bit single-precision IEEE 754 format, which is intended to speed up machine learning.

The second number format is IEEE 754 single precision 32-bit floating point (FP32). IEEE 754 single-precision 32-bit floating point includes a 23-bit fraction, an "implicit" or "hidden bit," an 8-bit exponent, and a sign bit.

The following content of Table 2 lists BFloat16 terms and their numerical definitions.

The following in Table 3 lists additional BFloat16 terms and their numerical definitions in binary format. Positive infinity and negative infinity are defined when all exponent bits are equal to one and when all scale bits are equal to zero. A positive or negative NaN (not a number) is defined as when all exponent bits are equal to one and when not all scale bits are equal to zero. Positive or negative non-norm is defined when all exponent bits are equal to zero and when not all scale bits are equal to zero. Positive or negative infinity, NaN or non-norm depending on the sign bit.

In some embodiments, the exception handling unit for machine learning operations does not support denormal or NaN operations. Denormal numbers are treated as zero, and NaN numbers are treated as infinity. abnormal

Chapter 7 of the IEEE Std 754-2019 specification describes the five classes of floating-point exceptions listed below. According to one embodiment, three of the following categories are implemented: (1) invalid operation, (3) overflow, and (4) underbit. This embodiment does not support division by zero and inexact. 1) invalid operation 2) divide by zero 3) Overflow 4) Underbit 5) Imprecise

According to some other embodiments, four categories are implemented: (1) invalid operation, (2) division by zero, (3) overflow, and (4) underbit. According to other embodiments, all five categories are implemented. invalid operation

The IEEE Std 754-2019 specification describes the following as invalid operations: a) Any general calculation operation on signaling NaN; b) Multiplication: multiplication (0, ∞) or multiplication (∞, 0); c) fusedMultiplyAdd (fusedMultiplyAdd): fusedMultiplyAdd(0, ∞, c) or fusedMultiplyAdd(∞, 0, c); d) Addition or subtraction or product and fusion addition: infinite amplitude subtraction, such as addition (+∞, -∞); e) Division: division (0, 0) or division (∞, ∞); f) Remainder: Remainder (x, y), when y is zero or x is infinite, and neither of them is NaN; g) if the operand is negative, the square root; and h) Quantization when the result does not fit in the target format or when one operand is finite and the other is infinite.

According to one embodiment, exception handling in the carry-save-accumulate unit implements the invalid operations a/b/c/d listed above. According to another embodiment, any combination of categories (a) to (h) is possible. invalid operation exception

The following in Table 4 lists invalid operations that produce exceptions. Table 4 action first operand second operand note result multiplier (±) infinity (±)0 vice versa positive infinity Adder Norm/Rounding (+) infinity (-)gigantic vice versa positive infinity overflow exception

The following content of Table 5 lists the overflow exception of an example of multiplying the maximum norm (max-norm) of two operands by the max-norm. These overflow exceptions produce the result "Signed Infinity". This overflow exception occurs when the result is greater than the signed maximum norm (Signed maximum norm) and only if there are no infinite values present on the operand's inputs. table 5 action first operand second operand note result multiplier maximum norm maximum norm vice versa sign infinity Adder Norm/Rounding maximum norm maximum norm vice versa sign infinity Under bit exception

In one embodiment, there are several cases where the result is less than the signed minimum norm. This exception occurs when there is no exact zero value on the operand input. When adder norm/rounding: (+) norm + (-) norm occurs, the result is a denormal (denormal) value (but not exactly zero), but the actual result will be a "signed zero". See Table 6, which shows an example of minimum norm (min-norm) multiplication of two operands by min-norm. Table 6 action first operand second operand note result multiplier minimum norm minimum norm vice versa sign zero Adder Norm/Rounding (+) norm (-) norm vice versa sign zero

In some embodiments, exception handling can be divided into "exception flag generation" and "exception result generation". Exceptions are handled, for example, at floating point multiplier block 1110 and floating point carry save adder block 1130 of FIG. 12A. exception flag generation

In some embodiments, floating point multiplier exception flags are provided for: (1) overflow, (2) underbit, and (3) invalid.

In some embodiments, the following floating point adder exception flags are provided: (1) overflow, (2) underrun, and (3) invalid. abnormal result generation

The operation of exception handling is explained in Chapter 6 of IEEE Std 754-2019. The following two tables summarize one embodiment and implementation of the multiply and add operations. multiplier operation

According to one embodiment, the contents of Table 7 lists multiplication operations with annotations for invalid, underbit, and overflow operations. Table 7 operation Operand #1 Operand #2 result note multiplication (+) zero (+) zero (+) zero multiplication (+) zero (-)zero (-)zero multiplication (+) zero (+) infinity (+) infinity invalid multiplication (+) zero (-)gigantic (+) infinity invalid multiplication (+) zero (+) norm (+) zero multiplication (+) zero (-) norm (-)zero multiplication (-)zero (-)zero (+) zero multiplication (-)zero (+) infinity (+) infinity invalid multiplication (-)zero (-)gigantic (+) infinity invalid multiplication (-)zero (+) norm (-)zero multiplication (-)zero (-) norm (+) zero multiplication (+) infinity (+) infinity (+) infinity multiplication (+) infinity (-)gigantic (-)gigantic multiplication (+) infinity (+) norm (+) infinity multiplication (+) infinity (-) norm (-)gigantic multiplication (-)gigantic (-)gigantic (+) infinity multiplication (-)gigantic (+) norm (-)gigantic multiplication (-)gigantic (-) norm (+) infinity multiplication (+) norm (-) norm (-) norm multiplication (+) norm (+) norm (+) norm multiplication (-) norm (-) norm (+) norm multiplication (+) maximum norm (+) maximum norm (+) infinity overflow multiplication (+) maximum norm (-) maximum norm (-)gigantic overflow multiplication (+) maximum norm (+) minimum norm (+) norm multiplication (+) maximum norm (-) minimum norm (-) norm multiplication (+) maximum norm (+) non-norm (+) zero multiplication (+) maximum norm (-) non-norm (-)zero multiplication (-) maximum norm (-) maximum norm (+) infinity overflow multiplication (-) maximum norm (+) maximum norm (-)gigantic multiplication (-) maximum norm (-) maximum norm (+) infinity multiplication (-) maximum norm (+) non-norm (-)zero multiplication (-) maximum norm (-) non-norm (+) zero multiplication (+) minimum norm (+) minimum norm (+) zero owe multiplication (+) minimum norm (-) minimum norm (-)zero owe multiplication (+) minimum norm (+) non-norm (+) zero multiplication (+) minimum norm (-) non-norm (-)zero multiplication (-) minimum norm (-) minimum norm (+) zero owe multiplication (-) minimum norm (+) non-norm (-)zero multiplication (-) minimum norm (-) non-norm (+) zero multiplication (+) non-norm (+) non-norm (+) zero multiplication (+) non-norm (-) non-norm (-)zero multiplication (-) non-norm (-) non-norm (+) zero Addition

According to one embodiment, the contents of the list of adder operations of Table 8 have annotations for invalid and overflow operations. Table 8 operation Operand #1 Operand #2 result note adder (+) zero (+) zero (+) zero adder (+) zero (-)zero (+) zero adder (+) zero (+) infinity (+) infinity adder (+) zero (-)gigantic (-)gigantic adder (+) zero (+) norm (+) norm adder (+) zero (-) norm (-) norm adder (-)zero (-)zero (-)zero adder (-)zero (+) infinity (+) infinity adder (-)zero (-)gigantic (-)gigantic adder (-)zero (+) norm (+) norm adder (-)zero (-) norm (-) norm adder (+) infinity (+) infinity (+) infinity adder (+) infinity (-)gigantic (+) infinity invalid adder (+) infinity (+) norm (+) infinity adder (+) infinity (-) norm (+) infinity adder (-)gigantic (-)gigantic (-)gigantic adder (-)gigantic (+) norm (-)gigantic adder (-)gigantic (-) norm (-)gigantic adder (+) norm (-) norm (+) norm adder (+) norm (+) norm (+) norm adder (-) norm (-) norm (-) norm adder (+) maximum norm (+) maximum norm (+) infinity overflow adder (+) maximum norm (-) maximum norm (+) zero adder (+) maximum norm (+) minimum norm (+) maximum norm adder (+) maximum norm (-) minimum norm (+) maximum norm adder (+) maximum norm (+) non-norm (+) maximum norm adder (+) maximum norm (-) non-norm (+) maximum norm adder (-) maximum norm (-) maximum norm (-)gigantic overflow adder (-) maximum norm (+) minimum norm (-) maximum norm adder (-) maximum norm (-) minimum norm (-) maximum norm adder (-) maximum norm (+) non-norm (-) maximum norm adder (-) maximum norm (-) non-norm (-) maximum norm adder (+) minimum norm (+) minimum norm (+) norm adder (+) minimum norm (-) minimum norm (+) zero adder (+) minimum norm (+) non-norm (+) minimum norm adder (+) minimum norm (-) non-norm (+) minimum norm adder (-) minimum norm (-) minimum norm (-) norm adder (-) minimum norm (+) non-norm (-) minimum norm adder (-) minimum norm (-) non-norm (-) minimum norm adder (+) non-norm (+) non-norm (+) zero adder (+) non-norm (-) non-norm (+) zero adder (-) non-norm (-) non-norm (-)zero This article describes an exception handling circuit for detecting at least one invalid operation or result in a multiplier and at least one invalid operation or result in an adder according to a floating-point encoding format, and setting the output operand of the multiplier or adder to A value that can be used for further processing. high level architecture

FIG. 11 illustrates an example high-level architectural block diagram 1100 depicting elements of exception handling in a carry-save-accumulate unit for machine learning.

In one embodiment, the exception handling in the carry-save-accumulation unit design involves three different input signals. These are operand A 1113 , operand B 1114 and operand C 1116 . Operand A 1113 may be in BF16 and FP32 formats. Operand B 1114 is in BF16 format, and operand C 1116 is in FP32 format. Operands are also called inputs.

The multiplier exception handling block 1102 feeds into operand A 1113 and operand B 1114 . The output of multiplier exception handling block 1102 is connected to: (1) via bus 1106 to multiplier exception flag 1104, (2) via bus multiplier exception condition signal 1108 to exception output control signal generation 1126, and (3 ) multiplier abnormal result 1115.

The operand C 1116 in FP32 format enters the operand C basic conversion block 1118 and outputs to: (1) via the operand C abnormal condition signal bus 1120 to the abnormal output control signal generation 1126, and (2) via the bus 1122 to the carry Adder block 1130 is saved.

Carry save adder (CSA) block 1130 processes two inputs via bus 1122 : (1) the multiplier exception result 1115 , and (2) the output from operand C primitive conversion block 1118 . In one embodiment, the CSA block 1130 has an accumulator loop 1124 that will only output data at the end of the loop. The CSA module 1130 outputs through the bus 1132 .

Adder normalization exception handling block 1134 takes two inputs. The first input is the CSA block 1130 output via bus 1132 . The second input is the exception control 1128 from the exception output control signal generation 1126 block.

The output of adder normalized exception handling block 1134 is adder exception result 1139 and bus 1138 routed to adder exception flags block 1140 .

Operand A is a 32-bit bus and provides BF16 inputs for multiplication and FP32 inputs for addition. Operand B is used for multiplication only and always has the BF16 16-bit input format. Operand C is used for addition or accumulator initialization and always has FP32 32-bit input format. The multiplier section has separate output flags (overflow, underbit, and invalid), while multiplier exception results become direct inputs to the adder. The abnormal condition signal of the adder is generated by the multiplier and connected to the "exception control signal generation" block, and has the abnormal condition signal from the operand C and the accumulator, and generates the "exception control" signal for the normalization block of the adder for use in Adder exception handling. operation mode

According to one embodiment, the exception handling in the carry-save-accumulation unit design supports three different operation modes.

FIG. 12A illustrates a first mode of operation 1200 according to the high-level block diagram architecture of FIG. 11 . The multiply-accumulate operation shows operand A 1113 in BF16 format, which is first multiplied with operand B 1114 in BF16 format, and then the product is added to operand C 1116 in FP32 format. Multiply and add operations are done in a single operation. This operation produces multiplication and addition exception flags and results.

The multiplier block 1110 feeds into operand A 1113 and operand B 1114 . The output of the multiplier block 1110 is connected (1) via bus 1106 to the multiplier exception flag 1104 block, and (2) to the multiplier exception result 1115 to the carry save adder (CSA) block 1130 . In some embodiments, the first mode of operation uses the multiplier exception flag 1104 for statistical purposes.

Carry save adder (CSA) block 1130 processes two inputs: (1) multiplier exception result 1115 and (2) operand C 1116 . CSA block 1130 has two outputs. The first output is adder exception result 1139 which is routed to output block 1129 in BF16 or FP32 format. The second output is bus 1138 routed to adder exception flag block 1140 .

FIG. 12B illustrates a second mode of operation 1202 according to the high-level block diagram architecture of FIG. 11 . The multiply-accumulate operation is shown as operand A 1113 in BF16 format multiplying operand B 1114 in BF16 in a single operation. It produces output at the end of the accumulation loop. During accumulation, the adder output and adder exceptions are disabled. This operation produces multiplication and addition exception flags and results.

The multiplier block 1110 feeds into operand A 1113 and operand B 1114 . The output of multiplier block 1110 is connected to (1) via bus 1106 to multiplier exception flag 1104 and (2) via multiplier exception result 1115 to carry save adder (CSA) 1130 . In some embodiments, the second mode of operation uses the multiplier exception flag 1104 for statistical purposes.

Carry save adder (CSA) block 1130 processes the following two inputs: (1) Multiplier exception result 1115 and accumulator wrap 1124 . CSA block 1130 has two outputs. The first output is the adder exception result 1139 , which is routed to the output block 1131 in BF16 or FP32 format only at the end of the accumulator loop 1124 . The second output is bus 1138 , which is routed to adder exception flag block 1140 .

FIG. 12C illustrates a third mode of operation 1203 according to the high-level block diagram architecture of FIG. 11 . The addition operation is shown as operand A 1113 in FP32 format added to operand C 1116 in FP32 format. This operation only produces an additive exception flag and result. Multiplier exception handling is disabled.

A carry save adder (CSA) block 1130 adds the two inputs. Operand A 1113 in FP32 format is added to operand C 1116 in FP32 format. CSA block 1130 has two outputs. The first output is adder exception result 1139 which is routed to output block 1129 in BF16 or FP32 format. The second output is bus 1138 routed to adder exception flag block 1140 . exception handling structure

According to some embodiments, exception handling is divided into "exception flag generation" and "exception result generation", which can also be divided into multiplier exception and adder exception.

Multiplier and adder flag generation generates overflow, underbit, and invalid flags. These flags are shown as a set of circuit implementations in the application below.

The multiplier and adder abnormal result generation includes three states: (1) sign generation, (2) exponent generation, and (3) decimal generation. The symbols have positive or negative outputs. When abnormal conditions occur, the index can have all "0" and all "1" conditions, and when abnormal conditions do not occur, the index can have normal output. Fractional values can have two states; for all abnormal cases, it is "0", and for non-exceptional cases, it is normal.

FIG. 13 illustrates an exception handling structure 1300 depicted in a high-level block diagram. Floating point multiply accumulator exception block 1308 outputs a flag to exception flag generation block 1304 and outputs the result to exception result generation block 1312 . Flags contain status information or data for handling by dedicated exception handling blocks, as described further below.

Exception flag generation block 1304 may output a flag to multiplier exception flag generation block 1302 or adder exception flag generation block 1306 . Multiplier exception flag generation block 1302 drives multiplier overflow flag condition block 1381 , multiplier underbit flag condition block 1382 , and multiplier invalid flag condition block 1383 .

Adder exception flag generation block 1306 drives adder overflow flag condition block 1387 , adder underbit flag condition block 1388 , and adder invalid flag condition block 1389 .

Exception result generation block 1312 provides results to multiplier exception result generation block 1310 and adder exception result generation block 1314 .

Multiplier exception result generation block 1310 outputs results to: (1) multiplier sign generation status block 1320A, (2) multiplier exponent generation status block 1322A, and (3) multiplication decimal generation status block 1324A.

Adder exception result generation block 1314 outputs results to: (1) Adder sign generation status block 1326A, (2) Adder exponent generation status block 1328A, and (3) Adder decimal generation status block 1330A.

The multiplier symbol generation status block 1320A outputs the status to blocks 1320B and 1320C. The multiplier index generation status block 1322A outputs the status to blocks 1322B, 1322C, and 1322D. The multiplication decimal generation status block 1324A outputs the status to blocks 1324B and 1324C.

Adder symbol generation status block 1326A outputs the status to blocks 1326B and 1326C. The adder index generation status block 1328A outputs the status to blocks 1328B, 1328C, and 1328D. Adder fraction generation status block 1330A outputs the status to blocks 1330B and 1330C.

The following diagrams from FIG. 14A to FIG. 21B illustrate a schematic implementation of the high-level blocks shown in FIG. 13 . For example, block 1381 in Figure 13 is implemented in Figure 14A, and block 1382 is implemented in Figure 14B. The figure titles below correspond to the block names in Figure 13. status circuit

FIG. 14A depicts one implementation 1400 of multiplier overflow flag condition circuit 1381 . The diagram shows that the multiplier overflow flag condition 1446 is active on the high order output from the multiplier overflow AND gate 1444 . AND gate 1444 has the following three inputs: (1) multiply operation enable 1414, (2) the output of inverse OR gate 1445, and (3) 1442, which is the output of product exponent AND gate 1440, also referred to as Ep (exponent product) and the multiplier product exponent.

The NOR gate 1445 has two inputs eainf and ebinf. If the input A is infinity, the signal exponent A infinity (eainf) occurs and is detected when the exponent is equal to 0xFF (meaning all "1s"). If input B is infinity, the signal exponent B infinity (ebinf) occurs and is detected when the exponent is equal to 0xFF (meaning all "1"). Table 2 shown above defines the BFloat16 terms and their numerical definitions. Eainf is the output of AND gate 1420 . The input to AND gate 1420 is the exponent of operand A and is shown with least significant bit (LSB) 1402 and most significant bit (MSB) 1404 comprising eight exponent bits.

Ebinf is the output of AND gate 1430 . The input to AND gate 1430 is the exponent of operand B and is shown with least significant bit (LSB) 1406 and most significant bit (MSB) 1408 comprising eight exponent bits.

The inputs to the product exponent sum gate 1440 are least significant bit (LSB) 1410 and most significant bit (MSB) 1412, comprising eight exponent bits.

FIG. 14B depicts one implementation 1400 of the multiplier under flag condition circuit 1382 . The multiplier underbit flag condition 1482 is asserted on the high order output from the multiplier underbit AND gate 1480 . AND gate 1480 has the following three inputs: (1) multiplication enable 1418 , (2) the output of NOR gate 1475 , and (3) 1472 which is the output of NOR gate 1470 .

Inverse OR gate 1475 has two inputs, eaz (input A index is zero) and ebz (input B index is zero). Eaz is the output of the NOR gate 1450 . The input to NOR gate 1450 is the exponent of operand A and is shown with least significant bit (LSB) 1422 and most significant bit (MSB) 1424 comprising eight exponent bits.

Ebz is the output of the NOR gate 1460 . The input to NOR gate 1460 is the exponent of operand B and is shown with least significant bit (LSB) 1426 and most significant bit (MSB) 1428 comprising eight exponent bits.

The inputs to product exponent OR gate 1470 are least significant bit (LSB) 1432 and most significant bit (MSB) 1434 , comprising eight exponent bits.

The assertion of the multiplier underbit flag occurs when the multiplication operation is enabled, Ep (product exponent) is 0x00, and any multiplier exponent input is non-zero. A non-zero multiplier exponent input means that neither operand A nor operand B has any exponent other than 0x00.

The determination of the multiplier invalid flag occurs according to the following two conditions: (1) the multiplication operation is enabled and (2) invalid is "1". Invalid "1" is defined as when the exponent of operand A is infinity (0xFF) and the exponent of operand B is zero (0x00) or when the exponent of operand B is infinity (0xFF) and the exponent of operand A is zero (0x00) status.

FIG. 15 depicts one implementation 1500 of the multiplier invalid flag condition circuit in block 1383. The multiplier invalid flag condition 1582 is asserted on the high order output from the multiplier invalid AND gate 1580 . AND gate 1580 has the following two inputs: (1) multiplication enable 1501 , and (2) 1572 , the output of OR gate 1570 .

OR gate 1570 has two inputs, the first input is 1552 derived from AND gate 1550 : the second input is 1562 derived from AND gate 1560 .

And gate 1550 has two inputs: eainf and ebz. Signal ebz occurs when input B is zero, ie (+) zero or (-) zero, and the case is when the exponent is 0x00 (meaning all "0"). Eainf is the output of AND gate 1510 . The input to AND gate 1510 is the exponent of operand A and is shown with least significant bit (LSB) 1502 and most significant bit (MSB) octet 1504 . Ebz is the output of the NOR gate 1520 . The input to NOR gate 1520 is the octet exponent of operand B and is shown with least significant bit (LSB) 1506 and most significant bit (MSB) 1508 .

And gate 1560 has two inputs: ebinf and eaz. Ebinf is the output of AND gate 1530 . The input to AND gate 1530 is the octet exponent of operand B and is shown with least significant bit (LSB) 1506 and most significant bit (MSB) 1508 . Eaz is the output of the NOR gate 1540 . Signal eaz occurs when input A is zero, ie (+) zero or (-) zero), and the exponent is 0x00 (meaning all "0s"). The input to NOR gate 1540 is the exponent of operand A, and is illustrated with least significant bit (LSB) 1502 and most significant bit (MSB) octet 1504, containing eight exponent bits.

FIG. 16 depicts one implementation 1600 of multiplier symbol generation condition circuit 1320 . A multiplier flag condition 1632 is generated by AND gate 1630 . The multiplier invalid flag condition 682 of FIG. 15 is the first input to the AND gate 1630 . The second input of AND gate 1630 is derived 1632 from the output of EX-OR gate 1620 . Symbol A 1618 and Symbol B 1622 comprise inputs to EX-OR gate 1620 .

FIG. 17A shows an implementation 1700 of the multiplier exponent generation condition circuit 1322 . The multiplier index 1752 is generated from three conditions. These are: (1) all '0' (0x00=zero), (2) all '1' (0xFF=infinity), and (3) normal exponent.

The first situation is that the index is all "0". The first condition may arise if any exponent of operand A or any exponent of operand B is zero. The first condition can also occur if the multiplier exponent evaluates to a negative overflow, which means that the multiplier exponent evaluates to less than -126.

The second condition is all "1". The second condition may arise if any exponent of operand A or any exponent of operand B is infinity. If the calculation result of the multiplier exponent is a positive overflow, the second situation may also occur, that is, the calculation result of the multiplier exponent is greater than Emax (+127).

The third condition is a normal output, defined as neither the first condition nor the second condition is occurring. This is defined as anything other than all '0's or all '1's.

Eight-bit wide multiplexer 1750 has three 8-bit buses as inputs. These are all '0's, all '1's, and other buses. The output of multiplexer 1750 is controlled using the control gates of OR gate 1710 , and gate 1720 , OR gate 1730 and inverse OR gate 1740 .

One implementation 1700 of the multiplier fraction generation condition circuit 1324 is shown in FIG. 17B . The multiplier fractional bus 1772 is 16 bits wide and is generated according to two conditions: (1) abnormal, (2) normal fractional. The two multiplexer inputs are: (1) the all '0' state (0x00=zero), and (2) the normal fractional state.

Multiplexer 1770 has two 16-bit input buses. These are all "0" and decimal buses. The OR gate 1760 controls the gating of the multiplexed 16-bit wide multiplexed output of the 1770.

Signals exp_overflow and zero are two inputs of OR gate 1760 . Signal exp_overflow is the logical OR of positive overflow or negative overflow, where overflow is described above in Figure 17A. In some embodiments, a status bit is provided after exponent calculation to detect exponent overflow. The term zero is defined as eaz (input A index is zero) or ebz (input B index is zero). The output of OR gate 1760 is 1762, which is a control that selects between two 16-bit wide multiplexer 1770 input buses. All "0"s occur when (1) the product exponent is positive overflow, or (2) there is negative overflow, or (3) the exponent of operand A is zero, or (4) the exponent of operand B is zero.

In some embodiments, the exception handling in the carry save accumulation unit does not support denormal or NaN operations. In this case, denormal numbers are treated as zero, and NaN numbers are treated as infinity. When any of these exceptions occur, the fractional output will be all "0". Otherwise, the output of multiplexer 1770 is a normalized decimal.

FIG. 18A illustrates an exemplary implementation 1800 of the adder overflow flag condition circuit in block 1387. A signal named adder overflow 1832 demonstrates an overflow flag condition and is the output of AND gate 1830 . The adder overflow flag condition occurs when AND gate 1830 has the following three inputs: (1) normalize_enable, (2) AND gate 1810 output named overflow, and (3) NOR gate 1820 output Named non-input exponent infinity 1822. The input to AND gate 1810 is eight normalized exponent bits. The input to the NOR gate 1820 is the product exponent infinity and the input C exponent infinity. In summary, during normalization, if the normalization exponent is equal to 0xFF and there is no input with an exponent infinity condition, an adder overflow 1832 flag condition may occur.

FIG. 18B shows an implementation 1800 of the adder underbit flag condition circuit in block 1388. Adder Underbit 1892 is active on the higher order output of AND Gate 1890 with the following three inputs: (1) Normalize_Enable, (2) AND Gate 1850 output named Underbit, and (3) Inverse OR Gate 1880 output Named Non-Input Exact Zero 1882. The input to AND gate 1850 is eight normalized exponent bits and a fractional output of zero. In summary, an adder under-flag condition typically occurs during normalization when the normalization exponent is 0x00 (equal to 0) and the input inexact is zero. The following paragraphs will describe one implementation of a circuit that can check for non-input exact zero 1882 conditions.

Further describing the circuit of FIG. 18B , the non-input exact-zero signal 1882 is generated through the three inputs of the NOR gate 1880 . These three inputs are: (1) multiplier product exponent zero, (2) input C exponent zero, and (3) output exact zero 1872 , derived from the output of AND gate 1870 . AND gate 1870 has two inputs. The first input is an EX- or 1860 gate output named sign_diff. EX- or 1860 gates operate on two inputs (multiplier product sign and input C sign). The second input of the AND gate 1870 is (+) zero, where (+) zero is the logical AND of the input C index greater than or equal to the multiplier product index and the fractional zero signal.

An adder underbit is a combination of the following conditions, as shown in the circuit. The first condition; (1) is enabled at the time of final normalization. The second condition; (2) is when the final addition exponent result, that is, when the normalized exponent is equal to 0x00 and the final addition decimal result (decimal output zero signal) is not completely zero. The third condition; (3) is when the multiplier product index zero, input C index zero and output non-exact zero are all disabled, which means one of them is zero. If any of the three conditions is zero, no adder underbit occurs.

One implementation 1900 of the adder invalid flag condition circuit in block 1389 is shown in FIG. 19A. Referring to Table 8, an invalid condition occurs when adding (+) infinity and (-) infinity. Adding (+) infinity and (+) infinity or adding (-) infinity and (-) infinity does not cause invalid flag condition 1389. The circuit checks for two operands of infinity with opposite signs. The adder invalid 1932 flag is the output of the AND gate 1930 . AND gate 1930 has the following three inputs: (1) normalize enable, (2) OR gate 1910 output named 1912 , and (3) sign_diff output from EX-OR gate 1920 .

The two inputs to the adder inactive OR gate 1910 are the multiplier product exponent infinity and the input C exponent infinity. EX-OR gate 1920 operates on two inputs, the multiplier product sign and the input C sign.

To summarize the circuit function, when (1) final normalization is enabled, (2) if the inputs from input A (or multiplier product) and input C are of different signs (positive and negative, or negative and positive), and (3) If the exponents of both inputs are infinity (0xFF), an adder invalid flag condition occurs. Adder symbol generation circuit

Figure 19B shows one implementation 1900 of adder sign positive condition circuit 810A for generating the adder sign positive output. As before, exception result generation has three parts: sign generation; exponent generation; and decimal generation. The resulting signed output can be positive or negative. One implementation of the symbolic output has two circuits that combine to provide the correct symbolic output for abnormal result generation. The first circuit is adder sign positive condition circuit 810A. The adder sign output has a positive status (+) when the adder sign positive 1992 bit is equal to "1".

The sign output function forces the positive case to zero according to the addition of: (1) (+) Zero + (-) Zero, (2) (+) non-norm + (-) non-norm (and vice versa), (3 ) are different signs and one of the exponent inputs is infinity ((+)Inf+(-)Inf and vice versa), (4) are different signs and the multiplier product is positive and the exponent is infinity ((+)zero x(+)Inf = (+)Inf), (5) the sign is different and the operand C exponent is greater than the operand A (or multiplier product) exponent, (6) the equation and decimal output is zero, and (7) when the multiplier product sign and input The C symbols are all positive.

One implementation of the first circuit for generating a sign bit forced to "0" for a positive condition is shown in FIG. And gate 1990 has two inputs. The first input is the OR gate 1980 output named 1982 and the second input is sign_diff from the EX-OR gate 1960 . The EX-OR gate 1960 operates on two inputs, the multiplier product sign and the input C sign. The OR gate 1980 has four inputs. These are underbits 1967, 1972 and add zero and fractional output zero.

The output of the AND gate 1950 is called an underbit, which is a combination of the output 1942 of the NOR gate 1940 and the AND fractional output zero. The input to NOR gate 1940 is an 8-bit normalized exponent vector. The two inputs to OR gate 1965 are the multiplier product exponent infinity and the input C exponent infinity. AND gate 1970 has a first input multiplier exponent infinitely capable, while a second input is the output of inverting gate 1968 whose input is the sign of the multiplier product.

FIG. 20A depicts one implementation 2000 of an additive sign negative condition circuit block 1326C for generating an additive sign negative (-) condition output. This is the second circuit used to generate the symbolic output as described above. The sign output consists of two circuits that combine to generate either a positive (+) condition or a negative (-) condition. Add sign negative condition circuit 810B generates a negative (-) condition when adder sign negative condition 2042 bit is equal to "1". The second circuit is first described as a schematic implementation and the described functions are summarized in the following paragraphs.

One implementation of a circuit that produces a sign output bit that is forced to 1' for a negative (-) condition is shown in FIG. 20A. OR gate 2040 outputs adder sign negative condition 2042 . The two inputs of the OR gate 2040 are the output 2022 of the AND gate 2020 and the output 2032 of the AND gate 2030 . When AND gate 2020 is asserted, a first sum sign negative condition may occur. The AND gate 2020 operates on the input multiplier product sign and the input C index, and if both signs are negative, the output is judged.

The decision of the AND gate 2030 may result in a negative sign condition of the second adder. This will happen when the following AND gate 2030 inputs are asserted: multiplier exponent infinite power, multiplier product sign sum 2012. The output of the NAND gate 2010 is 2012 enabled by the multiplier product exponent infinite and the output of the NAND gate 2005 with the symbol of the operand C as the input.

Summarizing the adder signed negative condition, the signed output is forced to a logic "1" for the negative condition (-) according to the following conditions: (1) When operand A (or multiplier product) and operand C are both signed "1" (both negative numbers); (2) or when the operand A (or multiplier product) is negative infinity and the operand C is not positive infinity. Adding Exponent Circuit

The adder exponential output is generated using three conditions. The first condition is all "0"s (0x00=zero). The second condition is all "1", where 0xFF will equal the infinity condition. The third state is the regular index.

FIG. 20B illustrates an implementation 2000 of adder index generation in the all '0' condition circuit block 1328B. Adder index all "0" select 2082 is the output of OR gate 2080 with three inputs. Each input represents a separate condition.

When the multiplier product index zero or the input C index zero enters the OR gate 2050, the first adder index all "0" condition is generated. The status decision 2052 selects 2082 with trigger adder index all "0".

When AND gate 2060 has (+) zero and sign_diff inputs, the second adder exponent all "0" condition is generated, where (+) zero is the input C index is greater than or equal to the multiplier product exponent logically ANDed with the fractional output zero signal . EX-OR gate 2070 operates on the multiplier product sign and the input C sign to generate sign_diff. When AND gate 2060 is asserted, 2062 can operate to trigger adder exponent all "0" selection 2082 .

The third adder exponent all "0" condition is generated by the fractional output zero input to OR gate 2080 to trigger adder exponent all "0" select 2082.

FIG. 21A illustrates an exemplary implementation 2100 of adder index generation for all "1" condition circuit block 1328B. An OR output function with three input conditions determines an all "1" output condition and is described in the following paragraphs. Status circuit 81 IB presents adder exponent all "1" select 2122 as the output of OR gate 2120 comprising three inputs. Each input represents a separate condition.

The first all "1" condition is generated when the multiplier product exponent infinity or input C exponent infinity is a valid input to OR gate 2110. The situation is determined 2112 .

A second all "1" condition is generated when the 8th bit of the normalized exponent [8] of the adder has an overflow result.

The third all "1" condition can be generated approximately by the multiplier exponent being infinite, where the multiplier output exponent is infinite or has a positive overflow.

In summary, when either the input A (or the multiplier product) or any exponent of the input C is infinity, or the final adder normalized exponent overflows, or the multiplier output exponent is infinity or positive overflow ((+) zero x(+) Inf=(+)Inf), generate all "1" situations.

FIG. 21B shows an exemplary implementation 2100 of adder fraction generation condition circuit 1330A. The circuit routes actual normalized fractional values or 23-bit zeros depending on the condition of the three selectors controlling the multiplexer. The three conditions that force the first 23-bit bus to zero are: (1) overflow of any normalized exponent; (2) underflow of the normalized exponent; or (3) either the multiplier output exponent is infinite or positively overflows otherwise , this condition is normal, and the second bus containing the 23-bit normalized fractional bus is routed to the adder fractional 2132 output.

The schematic diagram of circuit 812A shows the adder fractional 2132 output as a 23-bit bus provided by multiplexer 2150 . The OR gate 2130 output selector controls 2131 to select between the two 23-bit input buses of the multiplexer 2150 . Multiplexer 2150 has two 23-bit buses as inputs. The first input bus is a 23 all zero bit bus. The second input bus is a 23-bit normalized fractional bus. OR gate 2130 outputs control 2131 to multiplexer 2150 according to the three input conditions described in the paragraph above.

The output of the adder decimal 2132 has two states, that is, all "0" (0x00=zero) and normal decimal. In one embodiment, the exception handling in the carry save accumulation unit does not support denormal or NaN operations, treating denormal numbers as zero and NaN numbers as infinity. When any of these exceptions occur, the fractional output will be all "0".

When an overflow or underbit exception occurs, or the output exponent of the multiplier is infinity or a positive overflow ((+) zero multiplied by (+)Inf=(+)Inf), all "0"s appear. Multiplier Adder Operation Case Considerations

In the next paragraph, x is the multiplication operator, while + is the sum operator, and = is the equality operator. [value 1 x value 2] + value 3 = result [(+)zero x (+) infinity] + (-)gigantic = (+) infinity [(+)zero x (+) infinity] + (-) norm = (+) infinity [(+) infinity x (-)gigantic] + (+) zero = (-)gigantic [(+) infinity x (-)gigantic] + (+) infinity = (+) infinity [(+)zero x (+) infinity] + (+) zero = (+) infinity [(+)max-norm x (+) maximum norm] + (+) maximum norm = (+) infinity [(+)max-norm x (+) non-norm] + (+) minimum norm = (+) minimum norm

While the invention has been disclosed by reference to various embodiments and examples detailed above, it should be understood that these examples are intended to be illustrative and not restrictive. It is expected that those skilled in the art will readily devise modifications and combinations which will be within the spirit of the invention and scope of the appended claims.

110:Bfloat16 130: IEEE754 single-precision 32-bit floating point (FP32) 202: Multiplier circuit 210a: Multiplier and adder blocks 210b: Index block 210: multiplexer 211: multiplexer 212: multiplexer 213: Operand A 214:Operator B 215: base 8 converter 216: Operator C; line 217: BF16 format or FP32 format 218: line 219: line 220: block 221: line 222: double busbar 223: busbar 224: output bus 225: output bus 226: busbar 227: busbar 228: busbar 229: busbar 230: Carry save adder 240: accumulator 240A: Index control unit 240B: Exponent comparator unit 240C: Significant part 241: 42-bit decimal carry register 242: 42-bit fractional sum register 250: Carry reserved to sign value conversion box 251: busbar 252: busbar 260:Base-8 to base-2 conversion and normalizing squares 270: FP32 or BF16 block 300:Simplified Block Diagram 410:8X8 BF16 multiplier circuit 420: scratchpad 421: scratchpad 422: line 423: line 424: line 425: line 426: line 427: line 428: 7-bit LSB bus 429: 7-bit LSB bus 430: 7-bit ripple-carry adder 440: line 450: scratchpad 460: scratchpad 461: Inverter 462: line 464:Exponent adder circuit 465: line 466: 10-bit value 467:Special index detection block 468: line 469: line 470: scratchpad 471a: Anti-Mutual Exclusion OR Gate 471b: Anti-mutex OR gate 471c: Anti-Mutual Exclusion OR Gate 473: line 501: line 502: Effective number final adder circuit 503: line 504: scratchpad 506: overflow selection circuit 507: line 508: Sign bit selection circuit 509: line 510: Index selection circuit 511: line 512: Significant number selection circuit 513: line 514: 8-bit left shifter circuit 515: busbar 516:2's complement inverting plus 1 circuit 517: busbar 518:Multiplexer circuit 519: overflow signal 520: scratchpad 521: line 522: Exponent overflow detection circuit 523: input bus; line 524: Index exception processing circuit 525: line 526: Index anomaly detection circuit 527: line 528: Output abnormal control signal generation circuit 529: busbar 530: scratchpad 531: sign bit 532: scratchpad 533: line 537: output bus bar; line 539: line 541: line 543: line 544: and gate 545: line 547: busbar 549: line 551: line 553: busbar 560: Register Fcin 592: Base 8 Converter Block 592a: Final addition significand selection and base-8 conversion sub-block 592b: Exponential exception handling sub-block 602: product 604: Carry rounding box 605: Overflow detection block 606: LZA circuit 607: busbar 608: Shift register SHR8/16/24 circuit 609: Shifter circuit 610: Shifter circuit 611: busbar 612:Sum rounding box 613: busbar 614: Carry save adder circuit 617: and gate 619: Inverter 630: Shifter index control signal generation/bypass control circuit 633: line 634: line 636:Output pipeline register 644: line 646: line 647: line 648: line 650: 16-bit status register 652: 16-bit multiplier exponent comparison circuit 654: Index accumulator (Eacc) scratchpad 660: incrementer 661:Decrementer 662: sign extension detection unit 664: and gate 665: and gate 667: carry bus 668: and gate 669: sum bus 670: OR gate 671: line; input 673:Input 675:Enter 677:Input 679: line 681: line 682: line 683: line 684: Simple Product Rounding Blocks 685:Output 686: and gate 687: and gate 688: and gate 689:Output 692: busbar 693: busbar 700: final conversion 270:Normalize Convert to Symbolic Numeric Format Box 270a: Convert from Carry-Saving to Signed Numeric Format Block 270b: Converting from base-8 to base-2 floating point squares 702: Bus 704: busbar 706: line 708: 43-bit adder circuit 710: second circuit LZA/LOA 711: line 712: line 714: LZA POS selection circuit 715: busbar 716: busbar 717: busbar 718: Inverting plus 1 circuit 719: line 720: Valid number selection multiplexer circuit 726: sign bit 728: Significant zero detection circuit 730: scratchpad 735:SHL left shifter circuit 736: line 738: busbar 739:Signal 740:Exponent adder circuit 742: line 744: line 745: Bus 746: line 747: line 748: scratchpad 750: exception control (8-bit) scratchpad 751: Exception control register 752: Overflow/under detection circuit 753: line 755: line 756: Decimal zero register 758: norm_en 760: under detection multiplexer 770: 39-bit significant number 788: line 801: Control line signal Out_FP32 802: The first multiplexer 803: line 805: Bus 807: Bus 809: Bus 810A: Adder Sign Positive Condition Circuit 811B: Status circuit 812A: circuit 817: line 819: line 820: multiplexer 821: line 823: Round to zero selection line 825: line 827: line 829: line 830: Rounding circuit 831: line 833: busbar 835: line 837: 39-bit significand register 770 bus fpst_l[38:0] 840: multiplexer 850: second rounding increment circuit 860: first round increment circuit 907: line 930: 23-bit significand (IEEE 754) register 953: eight conditions 957: line 959: line 961: line 962: infinite control 963: line 964: EPST_L[9:0] bus 965: busbar 967: signal line 968: 9-bit Enorm[8:0] bus 969: line 970: Zero control logic 971: line 972: line 974: first multiplexer (zero) 975: line 976: multiplexer 979: index signal bus 980: index register 982: incrementer 983: signal line 986: Under/overflow detection and exponent anomaly detection circuit 987: OR gate 988:Symbol generation and exception handling circuits 990: scratchpad 991: line 992: Infinity detection circuit 994: informal circuit 1000: range of floating point numbers 1010: block 1100:Example High-Level Architecture Block Diagram 1102: Multiplier exception handling block 1104: Multiplier exception flag 1106: busbar 1108: Bus multiplier abnormal condition signal 1110: Multiplier block 1113: Operand A 1114:Operator B 1115: Abnormal multiplier result 1116:Operator C 1118:Operator C basic conversion block 1120: Operation element C abnormal condition signal bus 1122: busbar 1124: accumulator loop 1126: Abnormal output control signal generation block 1128: Abnormal control 1129: output block 1130: Carry save adder (CSA) block 1131: output block 1132: busbar 1134: Adder normalization exception handling block 1138: busbar 1139: Abnormal adder result 1140: Adder exception flag block 1300: exception handling structure 1302: Multiplier exception flag generation block 1304: Abnormal flag generation block 1306: Adder exception flag generation block 1308: Floating-point multiplication accumulator exception block 1310: The abnormal result of the multiplier generates a block 1312: Abnormal result generation block 1314: The abnormal result of the adder generates a block 1320A: Multiplier Symbol Generation Status Block 1320B: block 1320C: block 1322A: Multiplier Exponent Generation Status Block 1322B: block 1322C: block 1322D: block 1324A: Multiplication decimal generation status block 1324B: block 1324C: block 1326A: Adder Symbol Generation Status Block 1326B: block 1326C: block 1328A: Adder Exponent Generation Status Block 1328B: block 1328C: block 1328D: block 1330A: Adder decimal generation status block 1330B: block 1330C: block 1381: Multiplier overflow flag status block 1382:Multiplier underbit flag status box 1383: Multiplier invalid flag status block 1387: Adder overflow flag status block 1388: Adder underbit flag status block 1389: Adder invalid flag status block 1400: Implementation 1402: Least Significant Bit (LSB) 1404: most significant bit (MSB) 1406: least significant bit (LSB) 1408: Most significant bit (MSB) 1410: least significant bit (LSB) 1412: Most significant bit (MSB) 1414: Enable multiplication operation 1418: Enable multiplication operation 1420: and gate 1430: and gate 1440: Product index and gate 1442: output 1444: and gate 1445: Inverse OR gate 1446: Multiplier overflow flag status 1450: Inverse OR gate 1460: Inverse OR gate 1470: product index inverse OR gate 1472: output 1475: Inverse OR gate 1480: Multiplier underbit and gate 1482: Multiplier underbit flag status 1500: Achieved 1501: Enable multiplication operation 1502: Least Significant Bit (LSB) 1504: Most significant bit (MSB) octet 1506: Least Significant Bit (LSB) 1508: Most significant bit (MSB) 1510: and gate 1520: reverse OR gate 1530: and gate 1540: Inverse OR gate 1550: and gate 1560: and gate 1570: OR gate 1580: Multiplier invalid and gate 1552: first input 1562: second input 1572: output 1582: Multiplier invalid flag condition 1600: Achieved 1618: Symbol A 1620: EX-OR gate 1622: Symbol B 1630: and gate 1632: second input 1700: Achieved 1710: OR gate 1720: and gate 1730: OR gate 1740: Inverse OR gate 1750: multiplexer 1760: OR gate 1770: multiplexer 1752: Multiplier exponent 1762: output 1772: Multiplier Fractional Bus 1800: Schematic implementation 1810: and gate 1820: Inverse OR gate 1830: and gate 1822: Non-input exponent is infinity 1832: Adder overflow 1850: and gate 1860:EX-OR gate 1870: and gate 1880: Inverse OR gate 1890: and gate 1872: Output exact zero 1882: Non-input exact zero 1892: Adder underbit 1900: Implementation 1910: OR gate 1920: EX-OR gate 1930: and gate 1912: output 1932: Adder invalid flag 1940: Inverse OR gate 1942: Export 1950: and gate 1960: EX-OR gate 1965: OR gate 1967: Underbit 1968: Inverting gate 1970: And gate 1972: Underbit 1980: OR gate 1990: And gate 1982: Export 1992: Sign positive bit of signal adder 2000: realized 2005: Reversing gate 2010: Reverse and gate 2020: and gate 2030: and gate 2040: OR gate 2050: OR gate 2060: and gate 2070: EX-OR gate 2080: OR gate 2012: Output 2022: Export 2032: output 2042: adder sign negative status bit 2052: Judgment 2082: Adder index all "0" selection 2100: Schematic implementation 2110: OR gate 2120: OR gate 2112: Judgment 2122: Adder exponent all "1" selection 2130: OR gate 2131: selector control 2132: adder decimal output 2150: multiplexer

[Figure 1] illustrates the encoding format of BFloat16 and floating-point IEEE-754 standards.

[Fig. 2] A high-level block diagram illustrating a floating-point multiply-accumulate unit with a carry-save accumulator in BF16 and FP32 formats.

[ Fig. 3 ] A hierarchical block diagram illustrating a multiplier circuit having two inputs (operator A and operand B).

[FIG. 4a] illustrates an example multiplier and adder block comprising a partial product reduction tree of 8x8 multipliers.

[FIG. 4b] illustrates an example index unit with a special index detection block.

[FIG. 5A] illustrates a hierarchical block diagram showing a base-8 converter including example final addition, significand selection, and base-8 conversion blocks and example exponent exception handling blocks.

[FIG. 5B] An exemplary schematic representation illustrating final partial product addition, significand selection, and base-8 conversion blocks.

[FIG. 5C] illustrates an exemplary schematic representation of an exception handling block.

[FIG. 6] A high-level hierarchical block diagram illustrating a carry-save-accumulate unit.

[FIG. 7A] A high-level hierarchical block diagram illustrating an accumulator comprising two hierarchical blocks: an exponent control unit and a significand unit.

[FIG. 7B] An exemplary hierarchical block diagram and schematic diagram illustrating an index control unit.

[FIG. 7C] Exemplary hierarchical block and schematic diagrams illustrating significand units.

[FIG. 8A] illustrates an exemplary hierarchical block showing a normalized conversion to signed value format block containing two sub-blocks, a first conversion from carry-save to signed value sub-block and base 8 to base 2 The second transformation of the floating-point subsquare.

[FIG. 8B] An exemplary diagram illustrating conversion from carry-save to signed value blocks.

[ FIG. 8C ] An exemplary diagram illustrating conversion of a floating-point number block from base 8 to base 2 .

[FIG. 9A] illustrates an exemplary hierarchical block showing rounding and conversion to BF16 or IEEE 754 32-bit single precision format sub-blocks and exponent and exception handling sub-blocks.

[FIG. 9B] illustrates an exemplary diagram showing rounding and conversion to BF16 or IEEE 754 32-bit SP format blocks.

[FIG. 9C] illustrates an exemplary schematic diagram showing indices and exception handling blocks.

[Fig. 10] illustrates the range of floating-point numbers handled by exception handling in the carry-save accumulation unit for machine learning.

[FIG. 11] shows a high-level architectural block diagram depicting exception handling elements in a carry-save-accumulate unit for machine learning.

[FIG. 12A] illustrates a first mode of operation high-level block diagram architecture comprising input A in BF16 format, input B in BF16 format, and input C in FP32 format, where BF16 specifies a 16-bit machine learning floating-point encoding format called " B-float", or developed by Google (Brain Floating Point (Brain Floating Point)), and FP32 specifies a 32-bit single-precision IEEE 754 standard representation.

[ FIG. 12B ] illustrates a high-level block diagram architecture of the second operation mode including input A in BF16 format, input B in BF16 format, and performing accumulation.

[ FIG. 12C ] illustrates the high-level block diagram architecture of the third operation mode including input A in FP32 format and input C in FP32 format.

[Fig. 13] A high-level block diagram illustrating the exception handling structure.

[FIG. 14A] depicts the multiplier overflow flag condition circuit.

[FIG. 14B] shows the multiplier under-bit flag condition circuit.

[Fig. 15] illustrates the multiplier invalid flag condition circuit.

[ Fig. 16 ] depicts a multiplication sign generation condition circuit.

[FIG. 17A] shows a multiplication index generating condition circuit.

[FIG. 17B] The multiplication decimal number generation condition circuit is depicted.

[FIG. 18A] illustrates the adder overflow flag condition circuit.

[FIG. 18B] shows the adder underbit flag condition circuit.

[FIG. 19A] shows the adder invalid flag condition circuit.

[ Fig. 19B ] The adder sign positive condition circuit is depicted.

[ Fig. 20A ] An adder sign negative circuit is depicted.

[FIG. 20B] illustrates the adder index generating all "0" condition circuit.

[FIG. 21A] illustrates the adder index generating all "1" state circuit.

[FIG. 21B] shows the additive decimal generation condition circuit.

210: multiplexer

211: multiplexer

212: multiplexer

213: Operand A

214:Operator B

215: base 8 converter

216: Operator C; line

217: BF16 format or FP32 format

218: line

219: line

220: block

221: line

222: double busbar

223: busbar

224: output bus

225: output bus

226: busbar

227: busbar

228: busbar

229: busbar

230: Carry save adder

240: accumulator

250: Carry reserved to sign value conversion box

251: busbar

252: busbar

260:Base-8 to base-2 conversion and normalizing squares

270: FP32 or BF16 block

Claims (22)

A multiply-accumulate unit comprising: a pipeline configured to perform a multiply-accumulate operation on a sequence of input floating-point operands, the pipeline comprising: Significant number circuit, it receives the multiplier output significand of 2's complement format in the pipeline cycle and feeds back the sum and the carry value of feedback accumulator output, and described significand number circuit comprises 2's complement number, carry save adder, to generate the sum of the accumulator output and the carry accumulator output valid value; and an exponent circuit receiving, in said pipeline cycle, a multiplier output exponent in base 8 format and a feedback exponent value of said feedback accumulator output in said base 8 format to generate an accumulator output exponent value of said accumulator output . A multiply-accumulate unit as claimed in claim 1, wherein: The significand circuit includes a significand shifter responsive to an exponent comparison signal to align the multiplier output significand with the feedback sum and carry value for addition; the exponent circuit responds to the exponent comparison signal to generate the accumulator output exponent value; and The pipeline includes an exponent compare circuit for comparing the multiplier output exponent with the feedback exponent value prior to the pipeline cycle to generate the exponent compare signal. The multiply-accumulate unit of claim 2, wherein the pipeline comprises: an overflow detector circuit for generating an overflow signal indicative of an overflow condition for at least one of a sum and a carry value of the feedback; and The exponent circuit and the significand circuit are also responsive to the overflow signal. The multiply-accumulate unit of claim 2, wherein the pipeline comprises: an overflow detector circuit for generating a first condition signal indicative of an overflow condition of at least one of said fed back sum and carry values; a preamble bit detector circuit for generating a second status signal indicating that at least one of said fed back sum and carry values has greater than or equal to 8 spreading sign bits; and The exponent circuit and the significand circuit are also responsive to the first condition signal and the second condition signal. The multiply-accumulate unit according to any one of claims 1 to 4, wherein said pipeline comprises: a multiplier circuit responsive to a first input operand and a second input operand, providing a multiplier significand and a multiplier exponent prior to said pipeline cycle; base-8 conversion circuitry for converting the multiplier significand value and the multiplier exponent value to base-8 format for the multiplier output exponent and significand; and A 2's complement conversion circuit, which is used to convert the effective value of the multiplier into a 2's complement representation of the effective number output by the multiplier. The multiply-accumulate unit according to any one of claims 1 to 4, wherein said pipeline comprises: a multiplier circuit for providing a multiplier significand value and a multiplier exponent value prior to said pipeline cycle in response to a first input operand and a second input operand, wherein said multiplier circuit comprises a significand multiplier circuit and an exponent adder circuit having a carry save adder for generating a partial product of a carry value and a sum value to generate the high order bits of the multiplier output significand, and for A ripple-carry adder for generating partial products of the significand carry-out and the low-order bits of the sum output. The multiply-accumulate unit according to any one of claims 1 to 4, wherein said pipeline comprises: a multiplier circuit comprising a significand multiplier circuit and an exponent adder circuit responsive to a first input operand and a second input operand to provide a multiplier significand and a multiplier exponent prior to said pipeline cycle , and wherein said first input operand and said second input operand are in floating-point format including a shift amount, so negative exponents are represented by positive binary numbers, and a circuit for correcting said shift amount, which Inverting the most significant digit of one of the first operand and the second operand and adding 1 to a carry input of the exponent adder circuit. The multiply-accumulate unit according to any one of claim items 1 to 4, wherein the pipeline has an accumulator mode and a totalization mode, and includes: a selector to provide the fed back accumulator output in the accumulator mode and to provide a third floating point input operation to the significand circuit and the exponent circuit in the sum mode Yuan. The multiply-accumulate unit of claim 1, wherein the pipeline comprises: A first stage comprising a floating point multiplier with sum and carry out; A second stage comprising a multiplier output adder for the sum output and the carry output of the multiplier, and a multiplier adder output to convert the multiplier adder output into a 2's complement significand Circuits in base 8 format; a third stage comprising said significand circuit and said exponent circuit; The fourth stage, which is used to convert the sign bit of the accumulator, the accumulator index, the sum of the accumulator significand and the carry value into a sign value significand format; a fifth stage for converting the sign value significand format from base 8 alignment to base 2 alignment and producing a normalized exponent and significand; and The sixth level, which is used to perform rounding and conversion to standard floating point representation. A multiply-accumulate method for computing a sum S(i) of terms A(i)*B(i), where (i) ranges from 0 to N-1, and N is the number of terms in said sum, said Methods include: Receive a series of operands A(i) and operands B(i) in floating-point format, (i) from 1 to N in the multiply-accumulate unit; The multiplier pipeline stage of the multiply-accumulate unit that multiplies operands A(i) and operands B(i) to produce terms in the format A(i)*B(i ) and the multiplier output significand, and the multiplier output significand is converted to 2's complement format; Using a carry-save adder in the accumulator pipeline stage of the multiply-accumulate unit, the multiplier output significand of the term A(i)*B(i) in 2's complement format is added to the sum S(i- 1), and generate a sum and a carry value for the sum S(i); Selecting the index of the sum S(i) from the multiplier output exponent of the A(i)*B(i) and the index of the sum S(i-1) through the exponent circuit of the multiply-accumulate unit to generate the the exponent of the sum S(i) in base 8 format; and Converting the sum and carry values of the sum S(i) and the exponent in the base-8 format to a normalized floating point format. The multiply-accumulate method of claim 10, comprising comparing the exponent of said sum S(i-1) with the multiplier output exponent of said term A(i)*B(i) to generate an exponent comparison signal; and aligning the sum and carry value of said sum S(i-1) with the significand of said term A(i)*B(i) for addition in said carry-save adder in response to an exponent compare signal . The multiply-accumulate method of claim 11, comprising generating an overflow signal indicating an overflow condition for at least one of a sum and a carry value of the sum S(i−1); and aligning the sum and carry value and exponent of the sum S(i−1) with the multiplier output exponent and the multiplier output significand of the term A(i)*B(i) in response to the overflow signal , for addition in the carry-save adder. The multiplication and accumulation method of claim item 11, comprising: generating a first condition signal indicating an overflow condition of at least one of a sum and a carry value of said sum S(i−1); generating a second status signal indicating that at least one of the sum and carry values of the sum S(i-1) has greater than or equal to 8 spread sign bits; and Responsive to said first status signal and said second status signal, combining the sum and carry value and exponent of said sum S(i-1) with said multiplier output exponent sum term A(i)*B(i ) multiplier output significand aligned for addition in the carry-save adder. The multiply-accumulate method of any one of claims 10 to 13, wherein multiplying operand A(i) by operand B(i) to produce term A(i)*B(i) comprises using a method for a carry-save adder that generates a partial product of a carry value and a sum value to generate the high order bits of the multiplier output significand, and uses the low order bits used to generate the significand carry and sum output Ripple-carry adder for partial product. The multiply-accumulate method according to any one of claims 10 to 13, wherein operand A(i) and operand B(i) are in floating-point format including a shift amount such that negative exponents are represented by positive binary numbers, and correct The shift amount includes inverting the most significant bit of one of the operands A(i) and B(i) and adding 1 to the carry input of the exponent adder circuit. A multiply-accumulate unit comprising: a pipeline configured to perform a floating-point multiply-accumulate operation on a sum S(i) of terms A(i)*B(i), where (i) ranges from 0 to N-1, and N is the number of terms in said sum , the pipeline includes: a multiplier pipeline stage comprising a multiplier circuit to provide a multiplier significand and a multiplier exponent value for a term A(i)*B(i) in response to a first input operand and a second input operand, a base-8 conversion circuit for converting the multiplier significand and multiplier exponent values of the term A(i)*B(i) into base-8 format, and for converting the multiplier significand into the term A( i) The multiplier of *B(i) outputs the 2's complement conversion circuit of the 2's complement representation of the significand; an accumulator stage comprising a significand circuit that adds the multiplier output significand of the term A(i)*B(i) to the feedback sum and carry value of the sum S(i-1), And generate the sum and the carry value of the sum S (i), the effective number circuit includes a 2's complement carry save adder, to generate the sum value of the sum S (i) and the carry accumulator output effective value; and an exponent circuit that receives said multiplier exponent value of said term A(i)*B(i) and a feedback exponent value of sum S(i-1) to produce an accumulator output for sum S(i) index value. The multiply-accumulate unit of claim 16, wherein: the significand circuit of the accumulator stage includes a significand shifter responsive to an exponent compare signal; the index circuit is responsive to the index comparison signal; and The pipeline includes an exponent comparison circuit to compare the multiplier exponent value of the term A(i)*B(i) with the feedback exponent of the sum S(i-1) to generate the sum S(i-1) used to generate the sum S( The index comparison signal of i). The multiply-accumulate unit of claim 17, wherein said accumulator stage comprises: an overflow detector circuit for generating a first condition signal indicative of an overflow condition of at least one of a sum and a carry value of the feedback of said sum S(i−1); a preamble bit detector circuit for generating a second status signal indicating that at least one of the sum and carry values of the feedback of said sum S(i−1) has greater than or equal to 8 spread sign bits; and The exponent circuit and the significand circuit are also responsive to the first condition signal and the second condition signal. An accumulation unit comprising: a pipeline configured to perform an accumulation operation on a sequence of input floating point operands, the pipeline comprising: A significand circuit, which receives an input significand in 2's complement format in a pipeline cycle and feeds back the sum and the carry value output by the feedback accumulator, the significand circuit includes a 2's complement, carry-save adder to generate the sum of the accumulator output and the carry accumulator output significand; and an exponent circuit that receives an input exponent in base-8 format and a feedback exponent value of the feedback accumulator output in base-8 format in the pipeline cycle to generate an accumulator output exponent value of the accumulator output. The accumulation unit of claim 19, wherein: the significand circuit includes a significand shifter responsive to an exponent compare signal to align the input significand with the feedback sum and carry value for addition; the exponent circuit responds to the exponent comparison signal to generate the accumulator output exponent value; and The pipeline includes an exponent compare circuit for comparing the input exponent with the feedback exponent value prior to the pipeline cycle to generate the exponent compare signal. The accumulation unit of claim 20, wherein the pipeline comprises: an overflow detector circuit for generating an overflow signal indicative of an overflow condition for at least one of a sum and a carry value of the feedback; and The exponent circuit and the significand circuit are also responsive to the overflow signal. The accumulation unit of claim 20, wherein the pipeline comprises: an overflow detector circuit for generating a first condition signal indicative of an overflow condition of at least one of said fed back sum and carry values; a preamble bit detector circuit for generating a second status signal indicating that at least one of said fed back sum and carry values has greater than or equal to 8 spreading sign bits; and The exponent circuit and the significand circuit are also responsive to the first condition signal and the second condition signal.

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