TW202306131A - Ferroelectric tunnel junction with multilevel switching - Google Patents

Ferroelectric tunnel junction with multilevel switching Download PDF

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TW202306131A
TW202306131A TW111127494A TW111127494A TW202306131A TW 202306131 A TW202306131 A TW 202306131A TW 111127494 A TW111127494 A TW 111127494A TW 111127494 A TW111127494 A TW 111127494A TW 202306131 A TW202306131 A TW 202306131A
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ferroelectric
electrode
tunnel junction
precursor
crystalline material
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黎索爾 伊斯蘭
馬利歐 勞達托
魯本 沃爾德曼
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美商英特摩庫勒公司
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Abstract

The disclosed and claimed subject matter relates to a ferroelectric tunnel junction that is BEOL compatible having a film comprising crystalline ferroelectric materials that include a mixture of hafnium oxide and zirconium oxide having a substantial (i.e., approximately 40% or more) or majority portion of the material in a ferroelectric phase as deposited (i.e., without the need for further processing, such as a subsequent capping or annealing) and methods for preparing and depositing these materials. An interfacial layer is formed by oxidizing one or more of a first electrode and a second electrode. The FTJ has a memory window of between about 2X and 10X and is stable over 4 resistance states for at least 10<SP>3</SP>s. The FTJ is produced at temperatures less than or equal to 400 degrees Celsius.

Description

具有多階開關的鐵電穿隧接面Ferroelectric Tunneling Junction with Multilevel Switching

相關申請案之相互參照Cross-reference to related applications

本案請求2021年7月23日申請的美國臨時專利申請案序號第63/225,400號之優先權,在此以引用的方式將其併入本文。This case claims priority to U.S. Provisional Patent Application Serial No. 63/225,400, filed July 23, 2021, which is hereby incorporated by reference.

本文揭示並請求保護的標的大體上關於使用包括原子層沉積(ALD)在內的氣相技術沉積的鐵電材料。更明確地說,本文揭示並請求保護的標的關於具有薄膜結晶性鐵電材料的鐵電穿隧接面(FTJs),該薄膜結晶性鐵電材料包括具有實質部分(即,約40%或更多)鐵電相材料之氧化鉿和氧化鋯的混合物;以及製備及沉積這些材料的方法。很顯然地,這些材料顯現出無需進一步處理,例如後繼的護面(capping)或退火,的鐵電性質。The subject matter disclosed and claimed herein relates generally to ferroelectric materials deposited using vapor phase techniques including atomic layer deposition (ALD). More specifically, subject matter disclosed and claimed herein pertains to ferroelectric tunneling junctions (FTJs) having thin-film crystalline ferroelectric materials comprising a substantial portion (i.e., about 40% or more Multiple) mixtures of hafnium oxide and zirconium oxide as ferroelectric phase materials; and methods of preparing and depositing these materials. Apparently, these materials exhibit ferroelectric properties without further treatment, such as subsequent capping or annealing.

基於氧化鉿和氧化鋯的鐵電材料由於其很強的非線性電容及剩磁極化(remanent polarization)而能用於包括非揮發性記憶體及節能邏輯裝置的各種電腦裝置。這些材料也可用於各種其他熱和磁應用。含有氧化鉿和氧化鋯的材料因為其與許多CMOS裝配製程及材料的相容性而非常適合這些應用。其也是可取的,因為其能夠從氣相沉積為薄膜,包括藉由涉及逐步引入及去除前驅物,緊接著引入及去除反應氣體的ALD製程及其他已知製程(例如,化學氣相沉積(CVD)或脈衝CVD。基於氧化鉿和氧化鋯的材料是多晶形的。因此,其原子可排列成幾種晶體結構(即,不同的有序原子排列)。眾所周知的是基於氧化鉿和氧化鋯的材料的最穩定整體結構係單斜晶相;但是,此相卻不支持鐵電性。其他多晶形物(例如,一些斜方晶相及菱面體相)具有支持鐵電開關行為所需的對稱性,而其他多晶形物(例如,氧化鋯薄膜中常見的四方相)可為反鐵電類。本文所附的相關技藝列表確定了更詳細地描述該技藝的這些一般特徵及態樣的參考資料。Ferroelectric materials based on hafnium oxide and zirconium oxide can be used in various computer devices including non-volatile memory and power-saving logic devices due to their strong nonlinear capacitance and remanent polarization. These materials can also be used in a variety of other thermal and magnetic applications. Materials containing hafnium oxide and zirconium oxide are well suited for these applications due to their compatibility with many CMOS assembly processes and materials. It is also desirable because it can be deposited into thin films from the vapor phase, including by ALD processes and other known processes (e.g., chemical vapor deposition (CVD) ) or pulsed CVD. Materials based on hafnium oxide and zirconium oxide are polymorphic. Therefore, their atoms can be arranged in several crystal structures (i.e., different ordered atomic arrangements). Well-known is the The most stable overall structure of the material is the monoclinic phase; however, this phase does not support ferroelectricity. Other polymorphs (e.g., some orthorhombic and rhombohedral phases) have the required symmetry, while other polymorphs (e.g., the tetragonal phase commonly found in zirconia thin films) can be of the antiferroelectric type. The list of related arts appended hereto identifies the principles that describe these general features and aspects of the art in more detail. reference materials.

於用於混合氧化鉿和氧化鋯材料的許多氣相和原子層沉積製程中,該材料原沉積時為非晶形的。In many vapor phase and atomic layer deposition processes for mixed hafnium oxide and zirconium oxide materials, the material is amorphous as deposited.

即使經過熱處理,結晶成單斜晶相或其他非鐵電相也是常見的,從而降低了能夠產生鐵電行為的材料的比例。已經有人開發出幾種技術來抑制單斜晶相,有利於能支持鐵電性的相。舉例來說,據報導藉由將其他元素的前驅物依次或同時引入該氣相中,將其他元素(包括但不限於Si、Al、Gd、La及Y)結合到該材料中作為抑制單斜晶相的手段。Even after thermal treatment, crystallization into the monoclinic or other non-ferroelectric phases is common, reducing the proportion of material capable of ferroelectric behavior. Several techniques have been developed to suppress the monoclinic phase in favor of a phase that can support ferroelectricity. For example, it has been reported that other elements, including but not limited to Si, Al, Gd, La, and Y, are incorporated into the material as suppressed monoclinic elements by sequentially or simultaneously introducing their precursors into the gas phase. crystalline means.

有一項研究顯示氧化鉿和氧化鋯的厚膜(約30 nm)可表現出鐵電相的弱鐵電性。參見Y. Li等人,IEEE Journal of the Electron Devices Society, vol. 5, no. 5, pp. 378-383, Sept. 2017, doi: 10.1109/JEDS.2017.2732166中的"A Ferroelectric Thin Film Transistor Based on Annealing-Free HfZrO Film"。似乎此行為是由於與較薄的膜相比表面能效應的降低及長時間暴露於熱,這與退火的功能等效,以產生此厚度的膜。然而,此研究承認本領域一般已知的:薄膜(約20 nm或更小)不在提高溫度下退火(單獨或與摻雜組合)及上述護面方法的情況下不會顯現出鐵電性行為。A study showed that thick films (about 30 nm) of hafnium oxide and zirconium oxide can exhibit weak ferroelectricity of the ferroelectric phase. See Y. Li et al., "A Ferroelectric Thin Film Transistor Based on Annealing-Free HfZrO Film". It appears that this behavior is due to reduced surface energy effects compared to thinner films and prolonged exposure to heat, which is functionally equivalent to annealing to produce films of this thickness. However, this study acknowledges what is generally known in the art: thin films (approximately 20 nm or smaller) do not exhibit ferroelectric behavior without annealing at elevated temperatures (alone or in combination with doping) and the aforementioned face protection methods.

因此,獲得所需的鐵電相傳統上取決於下列的複雜組合:(i) 該材料本身的沉積條件,(ii) 摻雜劑、界面,重要的是頂部界面,的選擇及(iii) 沉積後的熱處理。可很容易地理解,此因素的組合極大地限制了此材料在可能的基材、中間層、電極、組合物及製程方面的用途。實際上,實施此鐵電材料的裝置中的熱分佈可能與鐵電材料可能有用的所有必要或期望的應用不相容。舉例來說,頃觀察到可能需要特定的電極來調節電子功函數,可能需要界面來創建阻障層以防止化學反應及原子擴散,並且熱處理條件可能會受到多層堆疊中的其他層中引入的應力的限制。Thus, obtaining the desired ferroelectric phase has traditionally depended on a complex combination of (i) the deposition conditions of the material itself, (ii) the choice of dopants, interfaces, and importantly the top interface, and (iii) the deposition conditions. post heat treatment. It can be readily appreciated that this combination of factors greatly limits the usefulness of this material in terms of possible substrates, interlayers, electrodes, compositions and processes. Indeed, the heat distribution in devices implementing such ferroelectric materials may not be compatible with all necessary or desired applications in which ferroelectric materials may be useful. For example, it has been observed that specific electrodes may be required to tune the electronic work function, interfaces may be required to create barrier layers to prevent chemical reactions and atomic diffusion, and heat treatment conditions may be affected by stresses introduced in other layers in the multilayer stack limits.

鐵電穿隧接面(FTJs)係鐵電材料和其他界面介電材料一起被夾在二相似/不同電極之間的兩終端記憶體裝置,其根據該裝置的電阻開關儲存數據(即,低電阻狀態及高電阻狀態表示二不同的記憶體狀態並且從而儲存一位元的資料)。該電阻變化係由該二電極之間的穿隧阻障層高度的變化引起,這是因為該鐵電材料中永久電荷偶極的取向的切換。鐵電材料通常為結晶/多晶材料,其由於晶胞內的不對稱偶極電荷中心可藉由施加電場來開關而形成永久電荷偶極。由於該偶極的永久取向切換,在沒有電場的情況下,此材料顯示可改變該二電極之間的直接穿隧阻障層的極化(剩磁極化)。Ferroelectric tunnel junctions (FTJs) are two-terminal memory devices in which ferroelectric material and other interfacial dielectric materials are sandwiched together between two similar/dissimilar electrodes, which store data according to the resistive switching of the device (i.e., low The resistive state and the high resistive state represent two different memory states and thus store one bit of data). The change in resistance is caused by a change in the height of the tunneling barrier between the two electrodes due to the switching of the orientation of the permanent charge dipole in the ferroelectric material. Ferroelectric materials are typically crystalline/polycrystalline materials that form permanent charge dipoles due to asymmetric dipole charge centers within the unit cell that can be switched by applying an electric field. Due to the permanent orientation switching of the dipoles, in the absence of an electric field, this material was shown to change the polarization of the direct tunneling barrier between the two electrodes (remanent magnetic polarization).

通常,要使FTJ工作,該二電極之間需要固有的不對稱性。此不對稱性可藉由二方式達成,(i) 二電極使用兩種不同類型的接觸材料(兩種不同金屬或一種金屬和一種半導體),(ii) 使用非鐵電性的界面介電材料。Typically, for an FTJ to work, an inherent asymmetry between the two electrodes is required. This asymmetry can be achieved by (i) using two different types of contact materials (two different metals or a metal and a semiconductor) for the two electrodes, (ii) using a non-ferroelectric interfacial dielectric material .

鐵電穿隧接面(FTJ) (當時稱為極性開關(polar switch))的基本想法可歸功於Esaki等人並且於1971年制定。在過去10年中,該FTJ在文獻中得到了廣泛的研究並且使用了幾種材料例如鋯鈦酸鉛 - Pb(Zr xTi 1-x) O 3(PZT)、鐵酸鉍(BiFeO 3- BFO)、鈦酸鋇(BaTiO 3- BTO)、鑭鍶亞錳酸鹽(La 0.67Sr 0.33MnO 3– LSMO)、有機聚偏二氟乙烯(PVDF)及有機聚(偏二氟乙烯-三氟乙烯)- P(VDF-TrFE)。由於這些材料較差的BEOL製程相容性及整合複雜性,最近已有人深入研究基於氧化鉿的FTJ,因為其與CMOS製程特別是與某些摻雜劑(Zr、Si)具有良好的相容性能提高該材料的鐵電性。最近也引入界面層(SiO 2、Al 2O 3、WO x)的使用以將不對稱性引入FTJ堆疊內並且從穿隧電阻(TER)範圍及保持力的角度提高該記憶體的性能,但是結果仍然不足以允許利用超過幾個小時之可接受的保持時間完成超過2至3個記憶體階程式編寫。 The basic idea of a ferroelectric tunneling junction (FTJ) (then called a polar switch) can be attributed to Esaki et al. and formulated in 1971. The FTJ has been extensively studied in the literature over the past 10 years and several materials such as lead zirconate titanate-Pb(Zr x Ti 1-x )O 3 (PZT), bismuth ferrite (BiFeO 3 - BFO), barium titanate (BaTiO 3 - BTO), lanthanum strontium manganite (La 0.67 Sr 0.33 MnO 3 - LSMO), organic polyvinylidene fluoride (PVDF) and organic poly(vinylidene fluoride-trifluoro Ethylene)-P(VDF-TrFE). Due to the poor BEOL process compatibility and integration complexity of these materials, hafnium oxide-based FTJs have recently been intensively studied due to their good compatibility with CMOS processes, especially with certain dopants (Zr, Si) Improves the ferroelectricity of the material. The use of interfacial layers (SiO 2 , Al 2 O 3 , WO x ) was also recently introduced to introduce asymmetry into the FTJ stack and improve the performance of this memory from the perspective of tunneling resistance (TER) range and retention, but The results are still insufficient to allow more than 2 to 3 memory-level programming to be done with acceptable retention times of more than a few hours.

在第一主要態樣中,所揭示的標的關於一種鐵電穿隧接面(FTJ),其包含:基材;第一電極和第二電極,其中該第一電極或該第二電極的一部分已經被氧化以形成一界面層;配置於該第一電極與該第二電極之間的包含結晶材料的薄膜,該結晶材料包含氧化鉿和氧化鋯,其中該結晶材料顯現出原沉積態鐵電行為;及與該第一電極或該第二電極連接的電壓源。In a first main aspect, the disclosed subject matter relates to a ferroelectric tunnel junction (FTJ) comprising: a substrate; a first electrode and a second electrode, wherein the first electrode or a portion of the second electrode has been oxidized to form an interfacial layer; a thin film comprising crystalline material comprising hafnium oxide and zirconium oxide disposed between the first electrode and the second electrode, wherein the crystalline material exhibits as-deposited ferroelectricity behavior; and a voltage source connected to the first electrode or the second electrode.

在該第一主要態樣之一態樣中,該第一電極及該第二電極係獨立地選自TiN、W、Ni、Ru、Pt及Al。在該第一主要態樣之另一態樣中,該第一電極及該第二電極係獨立地選自TiN及W。在該第一主要態樣之另一態樣中,該鐵電穿隧接面能夠在4個不同電阻狀態之間切換。在該第一主要態樣之另一態樣中,該電阻狀態保持穩定至少10 3秒。在該第一主要態樣之另一態樣中,該FTJ在該DC域中具有介於約1.5倍與約10倍之間的記憶體區間(memory window)。在該第一主要態樣之另一態樣中,該FTJ具有介於約2倍與約5倍之間的記憶體區間。在該第一主要態樣之另一態樣中,該FTJ能夠顯現出鐵電活性。在該第一主要態樣之另一態樣中,該第一電極包含鎢並且該第二電極包含氮化鈦。在該第一主要態樣之另一態樣中,該結晶材料的小於50%總體積構成非鐵電相組分。在該第一主要態樣之另一態樣中,該結晶材料的小於40%總體積構成非鐵電相組分。在該第一主要態樣之另一態樣中,該結晶材料的小於40%總體積構成單斜晶相組分。在該第一主要態樣之另一態樣中,該結晶材料的小於50%總體積構成單斜晶相組分。在該第一主要態樣之另一態樣中,(i) 該結晶材料的大於50%總體積處於鐵電相;(ii) 該結晶材料的小於50%總體積構成非鐵電相組分;及(iii) 該結晶材料的小於25%總體積構成單斜晶相組分。在該第一主要態樣之另一態樣中,氧化鉿與氧化鋯的比率介於約1:3與約3:1之間。在該第一主要態樣之另一態樣中,該結晶材料具有低於約6原子百分比的碳含量。在該第一主要態樣之另一態樣中,該結晶材料係衍生自一或更多具有式I或式II的茂金屬前驅物:

Figure 02_image001
Figure 02_image003
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8係各自獨立地選自C 1-C 6直鏈烷基、C 1-C 6支鏈烷基、C 1-C 6鹵代直鏈烷基及C 1-C 6鹵代支鏈烷基。在該第一主要態樣之另一態樣中,該結晶材料係衍生自一或更多具有式I或式II的茂金屬前驅物:
Figure 02_image005
Figure 02_image007
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自獨立地為C 1-C 6直鏈烷基。在該第一主要態樣之另一態樣中,該結晶材料係衍生自一或更多具有式I或式II的茂金屬前驅物:
Figure 02_image009
Figure 02_image010
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自為甲基。在該第一主要態樣之另一態樣中,於極化電場測量時存在磁滯性及剩磁極化。該膜具有約0.2 nm至約10 nm的厚度。在該第一主要態樣之另一態樣中,該膜具有約0.2 nm至約5 nm的厚度。在該第一主要態樣之另一態樣中,該膜具有大於8μC/cm 2的剩磁極化(Pr)或大於16μC/cm 2的總迴路開度(total loop opening)。 In one aspect of the first main aspect, the first electrode and the second electrode are independently selected from TiN, W, Ni, Ru, Pt, and Al. In another aspect of the first principal aspect, the first electrode and the second electrode are independently selected from TiN and W. In another aspect of the first principal aspect, the ferroelectric tunnel junction is switchable between four different resistance states. In another aspect of the first principal aspect, the resistance state remains stable for at least 10 3 seconds. In another aspect of the first principal aspect, the FTJ has a memory window in the DC domain of between about 1.5 and about 10 times. In another aspect of the first principal aspect, the FTJ has a memory range between about 2X and about 5X. In another aspect of the first principal aspect, the FTJ can exhibit ferroelectric activity. In another aspect of the first principal aspect, the first electrode comprises tungsten and the second electrode comprises titanium nitride. In another aspect of the first principal aspect, less than 50% of the total volume of the crystalline material constitutes a non-ferroelectric phase component. In another aspect of the first principal aspect, less than 40% of the total volume of the crystalline material constitutes a non-ferroelectric phase component. In another aspect of the first major aspect, less than 40% of the total volume of the crystalline material constitutes a monoclinic phase component. In another aspect of the first principal aspect, less than 50% of the total volume of the crystalline material constitutes a monoclinic phase component. In another aspect of the first major aspect, (i) greater than 50% of the total volume of the crystalline material is in the ferroelectric phase; (ii) less than 50% of the total volume of the crystalline material constitutes a non-ferroelectric phase component and (iii) less than 25% of the total volume of the crystalline material constitutes a monoclinic phase component. In another aspect of the first primary aspect, the ratio of hafnium oxide to zirconium oxide is between about 1:3 and about 3:1. In another aspect of the first principal aspect, the crystalline material has a carbon content of less than about 6 atomic percent. In another aspect of the first major aspect, the crystalline material is derived from one or more metallocene precursors having Formula I or Formula II:
Figure 02_image001
or
Figure 02_image003
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently selected from C 1 -C 6 Straight chain alkyl, C 1 -C 6 branched chain alkyl, C 1 -C 6 halogenated straight chain alkyl and C 1 -C 6 halogenated branched chain alkyl. In another aspect of the first major aspect, the crystalline material is derived from one or more metallocene precursors having Formula I or Formula II:
Figure 02_image005
or
Figure 02_image007
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently a C 1 -C 6 straight chain alkyl. In another aspect of the first major aspect, the crystalline material is derived from one or more metallocene precursors having Formula I or Formula II:
Figure 02_image009
or
Figure 02_image010
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each methyl. In another aspect of the first principal aspect, hysteresis and remanent magnetic polarization are present at the time of polarized electric field measurements. The film has a thickness of about 0.2 nm to about 10 nm. In another aspect of the first primary aspect, the film has a thickness from about 0.2 nm to about 5 nm. In another aspect of the first major aspect, the film has a remanent polarization (Pr) greater than 8 μC/cm 2 or a total loop opening greater than 16 μC/cm 2 .

在第二主要態樣中,一種產生鐵電穿隧接面之方法,其包含:(i) 提供基材;(ii) 將第一電極沉積於該基材上;(iii) 於沉積溫度下將鐵電層沉積於該第一電極上,沉積該鐵電層的步驟包含:(a) 將該第一電極暴露於於該沉積溫度下不會分解的第一前驅物;(b) 將該基材暴露於第一反應氣體;(c) 將該基材暴露於於該沉積溫度下不會分解的第二前驅物;及(d) 將該基材暴露於第二反應氣體,其中該第一前驅物及該第二前驅物中之其一包含鋯,並且該第一前驅物及該第二前驅物中之另一者包含鉿;及(iv) 將第二電極沉積於該鐵電層上。In a second major aspect, a method of producing a ferroelectric tunnel junction comprising: (i) providing a substrate; (ii) depositing a first electrode on the substrate; (iii) at a deposition temperature depositing a ferroelectric layer on the first electrode, the step of depositing the ferroelectric layer comprising: (a) exposing the first electrode to a first precursor that does not decompose at the deposition temperature; (b) exposing the first electrode to a first precursor that does not decompose at the deposition temperature; exposing the substrate to a first reactive gas; (c) exposing the substrate to a second precursor that does not decompose at the deposition temperature; and (d) exposing the substrate to a second reactive gas, wherein the first one of a precursor and the second precursor comprises zirconium, and the other of the first precursor and the second precursor comprises hafnium; and (iv) depositing a second electrode on the ferroelectric layer superior.

在該第二主要態樣的另一態樣中,在步驟(iii)之前進行藉由氧化該第一電極產生界面層的步驟。在該第二主要態樣的另一態樣中,該第一反應氣體及該第二反應氣體各自獨立地為含有氧、水、過氧化氫及一氧化二氮中的一或多者的氣體。在該第二主要態樣的另一態樣中,該第一反應氣體及該第二反應氣體各自獨立地為含氧氣體、含臭氧氣體或含水氣體。在該第二主要態樣的另一態樣中,退火步驟係於大於約攝氏350度的溫度下進行。在該第二主要態樣的另一態樣中,沒有製程步驟於大於約攝氏400度的溫度下發生。在該第二主要態樣的另一態樣中,於該鐵電層與該第一電極之間或於該鐵電層與該第二電極之間沒有沉積界面層。在該第二主要態樣的另一態樣中,該第一氣體或該第二氣體包含以介於約2%與約50%之間的體積分率遞送的臭氧。在該第二主要態樣的另一態樣中,另外包含在沉積該第二電極之前的臭氧脈衝步驟。在該第二主要態樣的另一態樣中,該臭氧脈衝步驟遞送包含介於以體積計約2%與約50%之間的臭氧的氣流。在該第二主要態樣的另一態樣中,該沉積的結晶材料在不用額外熱處理的情況下顯現出剩磁極化。在該第二主要態樣的另一態樣中,該沉積的結晶材料具有大於8μC/cm 2的餘磁極化(Pr)或大於16μC/cm 2的總迴路開度。在該第二主要態樣的另一態樣中,該第一電極或該第二電極包含TiN並且該界面層包含TiO xN y,其中x和y為整數。在該第二主要態樣的另一態樣中,該第一電極包含鎢並且該第二電極包含氮化鈦。在該第二主要態樣的另一態樣中,另外包含至少一吹掃步驟。在該第二主要態樣的另一態樣中,該第一反應氣體及該第二反應氣體為不同氣體。在該第二主要態樣的另一態樣中,該第一前驅物及該第二前驅物各自獨立地為具有式I或式II的前驅物:

Figure 02_image001
Figure 02_image012
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8係各自獨立地選自C 1-C 6直鏈烷基、C 1-C 6支鏈烷基、C 1-C 6鹵代直鏈烷基及C 1-C 6鹵代支鏈烷基。 In another aspect of the second main aspect, the step of creating an interfacial layer by oxidizing the first electrode is performed before step (iii). In another aspect of the second main aspect, the first reactive gas and the second reactive gas are each independently a gas containing one or more of oxygen, water, hydrogen peroxide, and nitrous oxide . In another aspect of the second main aspect, the first reactive gas and the second reactive gas are each independently an oxygen-containing gas, an ozone-containing gas, or a water-containing gas. In another aspect of the second primary aspect, the annealing step is performed at a temperature greater than about 350 degrees Celsius. In another aspect of the second primary aspect, none of the process steps occurs at a temperature greater than about 400 degrees Celsius. In another aspect of the second primary aspect, no interfacial layer is deposited between the ferroelectric layer and the first electrode or between the ferroelectric layer and the second electrode. In another aspect of the second primary aspect, the first gas or the second gas comprises ozone delivered at a volume fraction between about 2% and about 50%. In another aspect of the second primary aspect, additionally comprising an ozone pulsing step prior to depositing the second electrode. In another aspect of the second primary aspect, the ozone pulsing step delivers a gas stream comprising between about 2% and about 50% ozone by volume. In another aspect of the second principal aspect, the deposited crystalline material exhibits remanent magnetic polarization without additional heat treatment. In another aspect of the second primary aspect, the deposited crystalline material has a residual magnetic polarization (Pr) greater than 8 μC/cm 2 or a total loop opening greater than 16 μC/cm 2 . In another aspect of the second main aspect, the first electrode or the second electrode comprises TiN and the interfacial layer comprises TiOxNy , where x and y are integers. In another aspect of the second primary aspect, the first electrode comprises tungsten and the second electrode comprises titanium nitride. In another aspect of the second primary aspect, at least one purging step is additionally included. In another aspect of the second primary aspect, the first reactive gas and the second reactive gas are different gases. In another aspect of the second main aspect, the first precursor and the second precursor are each independently a precursor having formula I or formula II:
Figure 02_image001
or
Figure 02_image012
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently selected from C 1 -C 6 Straight chain alkyl, C 1 -C 6 branched chain alkyl, C 1 -C 6 halogenated straight chain alkyl and C 1 -C 6 halogenated branched chain alkyl.

在該第二主要態樣之另一態樣中,該第一前驅物及該第二前驅物各自獨立地為具有式I或式II的前驅物:

Figure 02_image001
Figure 02_image014
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自獨立地為C 1-C 6直鏈烷基。 In another aspect of the second main aspect, the first precursor and the second precursor are each independently a precursor having formula I or formula II:
Figure 02_image001
or
Figure 02_image014
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently a C 1 -C 6 straight chain alkyl.

在該第二主要態樣之另一態樣中,該第一前驅物及該第二前驅物各自獨立地為具有式I或式II的前驅物:

Figure 02_image009
Figure 02_image017
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自為甲基。 In another aspect of the second main aspect, the first precursor and the second precursor are each independently a precursor having formula I or formula II:
Figure 02_image009
or
Figure 02_image017
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each methyl.

在該第二主要態樣的另一態樣中,該方法包含ALD製程。在該第二主要態樣的另一態樣中,該方法包含CVD製程。在該第二主要態樣的另一態樣中,該沉積溫度係介於約攝氏200度與低於約攝氏400度之間。在該第二主要態樣的另一態樣中,該沉積溫度係介於約攝氏265度與低於約攝氏390度之間。在該第二主要態樣的另一態樣中,該沉積溫度係介於約280至約攝氏380度之間。在該第二主要態樣的另一態樣中,該沉積溫度係低於約攝氏30度。在該第二主要態樣的另一態樣中,該基材包含矽、鍺、III-V族材料、過渡金屬二硫屬化物、氮化鈦、鈦、鉭、氮化鉭、鎢、鉑、銠、鉬、鈷、釕、鈀或其混合物,或介電質如氧化矽、氮化矽、氧化鋁、氧化鈦。在該第二主要態樣的另一態樣中,該沉積的結晶材料具有約0.2 nm及約20 nm的厚度。In another aspect of the second main aspect, the method includes an ALD process. In another aspect of the second main aspect, the method includes a CVD process. In another aspect of the second primary aspect, the deposition temperature is between about 200 degrees Celsius and less than about 400 degrees Celsius. In another aspect of the second primary aspect, the deposition temperature is between about 265 degrees Celsius and less than about 390 degrees Celsius. In another aspect of the second primary aspect, the deposition temperature is between about 280 and about 380 degrees Celsius. In another aspect of the second primary aspect, the deposition temperature is less than about 30 degrees Celsius. In another aspect of the second principal aspect, the substrate comprises silicon, germanium, group III-V materials, transition metal dichalcogenides, titanium nitride, titanium, tantalum, tantalum nitride, tungsten, platinum , rhodium, molybdenum, cobalt, ruthenium, palladium or their mixtures, or dielectrics such as silicon oxide, silicon nitride, aluminum oxide, titanium oxide. In another aspect of the second primary aspect, the deposited crystalline material has a thickness of about 0.2 nm and about 20 nm.

在第三主要態樣中,一種產生鐵電穿隧接面之方法,其包含:(i) 提供基材;(ii) 將第一電極沉積於該基材上;(iii) 脈衝包含氧和臭氧的電漿以氧化該底部電極的一部分以形成一界面層;(iv) 於沉積溫度下將鐵電層沉積於該第一電極上,沉積該鐵電層的步驟包含:(a) 將該第一電極暴露於於該沉積溫度下不會分解的第一前驅物;(b) 將該基材暴露於第一反應氣體;(c) 將該基材暴露於於該沉積溫度下不會分解的第二前驅物;及(d) 將該基材暴露於第二反應氣體,其中該第一前驅物及該第二前驅物中之其一包含鋯,並且該第一前驅物及該第二前驅物中之另一者包含鉿;及(v) 將第二電極沉積於該鐵電層上。In a third major aspect, a method of producing a ferroelectric tunnel junction comprising: (i) providing a substrate; (ii) depositing a first electrode on the substrate; (iii) pulsing oxygen and A plasma of ozone to oxidize a portion of the bottom electrode to form an interfacial layer; (iv) depositing a ferroelectric layer on the first electrode at a deposition temperature, the step of depositing the ferroelectric layer comprising: (a) the exposing the first electrode to a first precursor that does not decompose at the deposition temperature; (b) exposing the substrate to a first reactive gas; (c) exposing the substrate to the deposition temperature without decomposing and (d) exposing the substrate to a second reactive gas, wherein one of the first precursor and the second precursor comprises zirconium, and the first precursor and the second The other of the precursors comprises hafnium; and (v) depositing a second electrode on the ferroelectric layer.

在該第三主要態樣的另一態樣中,該第一反應氣體及該第二反應氣體各自獨立地為含有氧、水、過氧化氫及一氧化二氮中的一或多者的氣體。在該第三主要態樣的另一態樣中,該第一反應氣體及該第二反應氣體各自獨立地為含氧氣體、含臭氧氣體或含水氣體。在該第三主要態樣的另一態樣中,退火步驟係於大於或等於約攝氏350度的溫度下進行。在該第三主要態樣的另一態樣中,沒有製程步驟於大於約攝氏400度的溫度下發生。在該第三主要態樣的另一態樣中,於該鐵電層與該第一電極之間或於該鐵電層與該第二電極之間沒有沉積界面層。在該第三主要態樣的另一態樣中,該第一氣體或該第二氣體包含以介於約2%與約50%之間的體積分率遞送的臭氧。在該第三主要態樣的另一態樣中,該方法另外包含在沉積該第二電極之前的臭氧脈衝步驟。在該第三主要態樣的另一態樣中,該臭氧脈衝步驟遞送包含介於以體積計約2%與約50%之間的臭氧的氣流。在該第三主要態樣的另一態樣中,該沉積的結晶材料在不用額外熱處理的情況下顯現出剩磁極化。在該第三主要態樣的另一態樣中,該沉積的結晶材料具有大於8μC/cm 2的餘磁極化(Pr)或大於16μC/cm 2的總迴路開度。在該第三主要態樣的另一態樣中,該第一電極包含TiN並且該界面層包含TiO xN y,其中x和y為整數。在該第三主要態樣的另一態樣中,該第一電極包含鎢(W)並且該中間層包含WO x,其中x為整數。在該第三主要態樣的另一態樣中,該第一電極包含釕(Ru)並且該中間層包含RuO x,其中x為整數。在該第三主要態樣的另一態樣中,該第一電極包含鎢並且該第二電極包含氮化鈦。在該第三主要態樣的另一態樣中,該退火步驟係於於低於或等於約攝氏400度的溫度下進行。 In another aspect of the third major aspect, the first reactive gas and the second reactive gas are each independently a gas containing one or more of oxygen, water, hydrogen peroxide, and nitrous oxide . In another aspect of the third major aspect, the first reactive gas and the second reactive gas are each independently an oxygen-containing gas, an ozone-containing gas, or a water-containing gas. In another aspect of the third major aspect, the annealing step is performed at a temperature greater than or equal to about 350 degrees Celsius. In another aspect of the third major aspect, none of the process steps occurs at a temperature greater than about 400 degrees Celsius. In another aspect of the third main aspect, no interfacial layer is deposited between the ferroelectric layer and the first electrode or between the ferroelectric layer and the second electrode. In another aspect of the third major aspect, the first gas or the second gas comprises ozone delivered at a volume fraction between about 2% and about 50%. In another aspect of the third main aspect, the method additionally comprises an ozone pulsing step prior to depositing the second electrode. In another aspect of the third major aspect, the ozone pulsing step delivers a gas stream comprising between about 2% and about 50% ozone by volume. In another aspect of the third principal aspect, the deposited crystalline material exhibits remanent magnetic polarization without additional heat treatment. In another aspect of the third major aspect, the deposited crystalline material has a residual magnetic polarization (Pr) greater than 8 μC/cm 2 or a total loop opening greater than 16 μC/cm 2 . In another aspect of the third main aspect, the first electrode comprises TiN and the interfacial layer comprises TiOxNy , where x and y are integers. In another aspect of the third main aspect, the first electrode comprises tungsten (W) and the intermediate layer comprises WOx , where x is an integer. In another aspect of the third main aspect, the first electrode comprises ruthenium (Ru) and the intermediate layer comprises RuOx , where x is an integer. In another aspect of the third main aspect, the first electrode comprises tungsten and the second electrode comprises titanium nitride. In another aspect of the third major aspect, the annealing step is performed at a temperature less than or equal to about 400 degrees Celsius.

在該第一、第二或第三主要態樣的另一態樣中,該膜包含摻雜有La、Y、Gd或Sr的Hf xZr 1-xO 2或HfO 2。在該第一、第二或第三主要態樣的另一態樣中,交錯式記憶體陣列包含如請求項1至23中任一項之鐵電穿隧接面或由如請求項24至66中任一項之方法產生的鐵電穿隧接面,該鐵電穿隧接面包含記憶體單位晶胞(memory unit cell)。在該第一、第二或第三主要態樣的另一態樣中,一種包含如請求項1至23中任一項之鐵電穿隧接面的神經形態運算晶片(neuromorphic computing chip),其中該鐵電穿隧接面係突觸裝置(synaptic device)。在該第一、第二或第三態樣的另一態樣中,該鐵電穿隧接面具有約300 nm或更小的臨界尺寸(critical dimension)。 In another aspect of the first, second or third main aspect, the film comprises HfxZr1 -xO2 or HfO2 doped with La, Y, Gd or Sr. In another aspect of the first, second or third main aspect, the interleaved memory array comprises a ferroelectric tunnel junction as in any one of claims 1 to 23 or consists of a ferroelectric tunnel junction as in any one of claims 24 to 23 The ferroelectric tunnel junction produced by the method of any one of 66, the ferroelectric tunnel junction comprising a memory unit cell (memory unit cell). In another aspect of the first, second or third main aspect, a neuromorphic computing chip comprising a ferroelectric tunneling junction according to any one of claims 1 to 23, Wherein the ferroelectric tunnel junction is a synaptic device. In another aspect of the first, second or third aspect, the ferroelectric tunnel junction has a critical dimension of about 300 nm or less.

在另一態樣中,該先進茂金屬前驅物係美國專利第8,568,530號中揭示及/或請求保護的一或多種前驅物,其內容在此以引用的方式將其全文併入本文。In another aspect, the advanced metallocene precursor is one or more precursors disclosed and/or claimed in US Pat. No. 8,568,530, the contents of which are hereby incorporated by reference in their entirety.

本說明內容段並未明確說明該揭示及請求保護的標的之每個具體實例及/或逐漸新穎的態樣。取而代之地,本說明內容段僅提供對不同具體實例及超越習用技術和習知技藝的新穎性的對應點之初步討論。對於該揭示及請求保護的標的及具體實例的附加細節及/或可能的觀點,讀者可參考下文進一步討論的揭示內容之實施方式及對應圖式。This descriptive paragraph does not explicitly describe every specific instance and/or progressively novel aspect of this disclosed and claimed subject matter. Instead, this descriptive paragraph merely provides a preliminary discussion of various specific examples and corresponding points of novelty beyond conventional technology and the art. For additional details and/or possible perspectives on the disclosed and claimed subject matter and embodiments, the reader is referred to the disclosed embodiments and corresponding drawings discussed further below.

為求清楚起見,頃展示本文所述的不同步驟的討論順序。一般,本文揭示的步驟可以任何合適的順序執行。此外,儘管本文揭示的不同特徵、技術、配置等中各自可於本揭示的不同位置進行討論,但是其意在使各概念可彼此獨立地執行或視情況彼此組合地執行。因此,該揭示及請求保護的標的可以許多不同的方式體現並且觀察。For clarity, the order of discussion of the different steps described herein is presented. In general, the steps disclosed herein can be performed in any suitable order. Furthermore, although each of the various features, techniques, configurations, etc. disclosed herein may be discussed at different places in the disclosure, it is intended that the various concepts can be implemented independently of each other or in combination with each other as appropriate. Accordingly, the disclosed and claimed subject matter can be embodied and viewed in many different ways.

定義definition

除非另行指明,否則本說明書及申請專利範圍中使用的以下措辭對於本說明書將具有以下含義。Unless otherwise specified, the following expressions used in this specification and claims shall have the following meanings for this specification.

在本案中,單數的使用包括複數,除非另行明確地指明,否則“一”及“該”意指“至少一”。再者,措辭“包括”及其他形式的使用並無限制性。另外,除非另行明確指明,諸如“元件”或“組件”之類的措辭包括含一個單元的元件或組件以及含多於一單元的元件或組件。如本文所用,除非另行指明,否則連接詞“及”意在包括並且連接詞“或”並不意在排他。舉例來說,片語“又或者”意在排他。如本文所用,措辭“及/或”表示前述元素的任何組合,包括使用單一元素在內。In this case, use of the singular includes the plural and "a" and "the" mean "at least one" unless expressly stated otherwise. Furthermore, the use of the word "comprise" and other forms is not limiting. In addition, expressions such as "element" or "component" include elements or components comprising one unit as well as elements or components comprising more than one unit, unless explicitly stated otherwise. As used herein, unless stated otherwise, the conjunction "and" is intended to be inclusive and the conjunction "or" is not intended to be exclusive. For example, the phrase "or" is intended to be exclusive. As used herein, the word "and/or" means any combination of the aforementioned elements, including the use of a single element.

措辭“約”在與可測量的數值變量一起使用時,表示該變量的指示值及在該指示值的實驗誤差範圍內的所有變量值(例如,在該平均值的95%置信極限)或在該指示值的百分比範圍內(例如,± 10%、± 5%),以較大者為準。The word "about" when used in connection with a measurable numerical variable means the indicated value of the variable and all values of the variable within the experimental error of the indicated value (for example, within the 95% confidence limit of the mean) or within Within the percentage range of the indicated value (for example, ± 10%, ± 5%), whichever is greater.

為了達成本發明及其申請專利範圍的目的,該元素週期表族的編號方案係根據IUPAC元素週期表。For the purposes of this invention and its claim claims, the numbering scheme for the Periodic Table Groups is according to the IUPAC Periodic Table of the Elements.

如本文中“A及/或B”等片語中使用的措辭“及/或”意在包括“A及B”、“A或B”、“A”及“B”。The word "and/or" as used herein in the phrase "A and/or B" is intended to include "A and B", "A or B", "A" and "B".

措辭“取代基”、“根”、“基團”及“部分”可互換使用。The terms "substituent", "radical", "group" and "moiety" are used interchangeably.

如本文所用,措辭“含金屬錯合物”(或更簡單地,“錯合物”)及“前驅物”可互換使用並且表示可用以藉由沉積製程例如,舉例來說,ALD或CVD製備含金屬膜的含金屬分子或化合物。該含金屬錯合物可沉積、吸附、分解、遞送及/或通過基材或其表面,以形成含金屬膜。As used herein, the terms "metal-containing complex" (or more simply, "complex") and "precursor" are used interchangeably and mean that they can be prepared by a deposition process such as, for example, ALD or CVD A metal-containing molecule or compound containing a metal film. The metal-containing complex can be deposited, adsorbed, decomposed, delivered and/or passed through the substrate or its surface to form a metal-containing film.

如本文所用,措辭“含金屬膜”不僅包括如下文更充分定義的元素金屬膜,也包括含金屬及一或更多元素的膜,舉例來說金屬氮化物膜、金屬矽化物膜、金屬碳化物膜等。As used herein, the phrase "metal-containing film" includes not only elemental metal films as more fully defined below, but also films containing metal and one or more elements, for example, metal nitride films, metal silicide films, metal carbide films, film etc.

如本文所用,措辭“元素金屬”、“元素金屬膜”及“純金屬膜”可互換使用並且表示由純金屬組成或基本上由純金屬組成的膜。舉例來說,元素金屬膜可包括100%純金屬或該元素金屬膜可包括至少約70%、至少約80%、至少約90%、至少約95%、至少約96%、至少約97%、至少約98%、至少約99%、至少約99.9%或至少約99.99%的純金屬及一或更多雜質。然而,包含元素金屬的膜不同於包含金屬和非金屬(例如,C、N、O)的二元膜及包含金屬和二非金屬(例如,C、N、O)的三元膜,但是,包含元素金屬的膜可能包括一定量的雜質。除非上下文另行指明,否則措辭“金屬膜”應解釋為意指元素金屬膜。As used herein, the terms "elemental metal," "elemental metal film," and "pure metal film" are used interchangeably and mean a film consisting of, or consisting essentially of, a pure metal. For example, the elemental metal film can comprise 100% pure metal or the elemental metal film can comprise at least about 70%, at least about 80%, at least about 90%, at least about 95%, at least about 96%, at least about 97%, At least about 98%, at least about 99%, at least about 99.9%, or at least about 99.99% pure metal and one or more impurities. However, films comprising elemental metals differ from binary films comprising metals and nonmetals (e.g., C, N, O) and ternary films comprising metals and two nonmetals (e.g., C, N, O), however, Films containing elemental metals may include some amount of impurities. Unless the context indicates otherwise, the expression "metal film" should be interpreted to mean an elemental metal film.

如本文所用,措辭“沉積製程”及“熱沉積”係用以表示任何類型的沉積技術,其包括但不限於CVD和ALD。在各個具體實例中,CVD可採用習用(即,連續流動) CVD、液體注入CVD、電漿強化CVD或光輔助CVD的形式。CVD也可採用脈衝技術的形式,即脈衝CVD。ALD係用以藉由將本文揭示的至少一金屬錯合物汽化及/或使其通過基材表面上方來形成含金屬膜。關於習用的ALD製程,可參見,舉例來說George S. M. 等人, J. Phys. Chem.,1996, 100, 13121–13131。在其他具體實例中,ALD可採用習用(即,脈衝注入) ALD、液體注入ALD、光輔助ALD、電漿輔助ALD或電漿強化ALD的形式。措辭“氣相沉積製程”另外包括 Chemical Vapour Deposition:  Precursors, Processes, and Applications; Jones, A. C.; Hitchman, M. L., Eds.  The Royal Society of Chemistry:  Cambridge, 2009; Chapter 1, pp 1–36中描述的各種氣相沉積技術。 As used herein, the terms "deposition process" and "thermal deposition" are used to denote any type of deposition technique, including but not limited to CVD and ALD. In various embodiments, CVD can take the form of conventional (ie, continuous flow) CVD, liquid injection CVD, plasma enhanced CVD, or light assisted CVD. CVD can also take the form of pulse technology, namely pulse CVD. ALD is used to form metal-containing films by vaporizing and/or passing at least one metal complex disclosed herein over a substrate surface. For conventional ALD processes see, for example, George SM et al., J. Phys. Chem., 1996, 100 , 13121-13131. In other embodiments, ALD may take the form of conventional (ie, pulse infusion) ALD, liquid infusion ALD, light assisted ALD, plasma assisted ALD, or plasma enhanced ALD. The phrase "vapor deposition process" additionally includes those described in Chemical Vapor Deposition: Precursors, Processes, and Applications ; Jones, AC; Hitchman, ML, Eds. The Royal Society of Chemistry: Cambridge, 2009; Chapter 1, pp 1–36 Various vapor deposition techniques.

除非另行指明,否則“烷基”表示可為直鏈、支鏈(例如,甲基、乙基、丙基、異丙基、第三丁基等)、環狀(例如,環己基、環丙基、環戊基等)或多環的(例如,降冰片基、金剛烷基等)。合適的非環狀基團可為甲基、乙基、正-或異-丙基、正-、異-或第三-丁基、直鏈或支鏈戊基、己基、庚基、辛基、癸基、十二烷基、十四烷基及十六烷基。除非另行指明,否則烷基表示1至10個碳原子部分。該環狀烷基可為單環或多環。單環烷基的合適實例包括經取代的環戊基、環己基及環庚基。該取代基可為本文所述的任何非環狀烷基。如本文所述,該環狀烷基可具有任何非環狀烷基作為取代基。這些烷基部分可為經取代或未經取代。Unless otherwise specified, "alkyl" means can be straight chain, branched (for example, methyl, ethyl, propyl, isopropyl, tert-butyl, etc.), cyclic (for example, cyclohexyl, cyclopropyl group, cyclopentyl, etc.) or polycyclic (eg, norbornyl, adamantyl, etc.). Suitable acyclic groups may be methyl, ethyl, n- or i-propyl, n-, i- or tert-butyl, linear or branched pentyl, hexyl, heptyl, octyl , Decyl, Dodecyl, Tetradecyl and Hexadecyl. Unless otherwise specified, alkyl means a moiety of 1 to 10 carbon atoms. The cyclic alkyl group may be monocyclic or polycyclic. Suitable examples of monocycloalkyl include substituted cyclopentyl, cyclohexyl and cycloheptyl. The substituent can be any acyclic alkyl group described herein. As described herein, the cyclic alkyl group may have any acyclic alkyl group as a substituent. These alkyl moieties can be substituted or unsubstituted.

“鹵代烷基”表示如上定義的直鏈、環狀或支鏈飽和烷基,其中一或更多氫已被鹵素(例如,F、Cl、Br及I)取代。因此,舉例來說,氟化烷基(又名“氟烷基”)表示如上定義的直鏈、環狀或支鏈飽和烷基,其中一或更多氫已被氟取代(例如,三氟甲基、全氟乙基、2,2,2-三氟乙基、全氟異丙基、全氟環己基等)。此鹵代烷基部分(例如,氟烷基部分),若不是全鹵代/多鹵代的,則可為未經取代的或另外經取代的。"Haloalkyl" means a straight chain, cyclic or branched saturated alkyl group as defined above in which one or more hydrogens have been replaced by a halogen (eg, F, Cl, Br and I). Thus, by way of example, fluorinated alkyl (aka "fluoroalkyl") denotes a straight chain, cyclic or branched saturated alkyl group as defined above in which one or more hydrogens have been replaced by fluorine (e.g., trifluoro methyl, perfluoroethyl, 2,2,2-trifluoroethyl, perfluoroisopropyl, perfluorocyclohexyl, etc.). The haloalkyl moiety (eg, fluoroalkyl moiety), if not perhalogenated/polyhalogenated, may be unsubstituted or otherwise substituted.

本文使用的章節標題係為達組織的目的並且不應被解釋為限制所述的標的。本案中引用的所有文件或文件的部分,其包括但不限於,專利、專利申請案、文章、書籍及論文,在此為達任何目的而以引用的方式將其全文併入本文。若有任何併入的文獻及類似資料以與本案中該措辭的定義相矛盾的方式定義一措辭,則以本案為準。The section headings used herein are for organizational purposes and should not be construed as limiting the subject matter described. All documents or portions of documents cited in this case, including but not limited to, patents, patent applications, articles, books, and treatises, are hereby incorporated by reference in their entirety for any purpose. To the extent any incorporated literature and similar sources define a term in a manner that contradicts the definition of that term in this case, this case controls.

應當理解的是前述一般描述及以下詳細描述皆為說明性及解釋性的,而不是對請求保護的標的的限制。該揭示標的之目的、特徵、優點及想法對於本領域的習知技藝者來說將從說明書中提供的描述中顯而易見,並且本領域的習知技藝者將在本文中出現的描述之基礎上輕易地實踐該揭示標的。任何“較佳具體實例”的描述及/或顯示用於實踐該揭示標的之較佳模式的實例係為達解釋的目的而收錄並且意不在限制該申請專利範圍的範疇。It should be understood that both the foregoing general description and the following detailed description are illustrative and explanatory in nature and not restrictive of what is claimed. The purpose, features, advantages, and ideas of the disclosed subject matter will be apparent to those skilled in the art from the description provided in the specification, and those skilled in the art will be able to easily based on the description presented herein To practice the disclosure target. Any description of "preferred embodiments" and/or examples showing preferred modes for practicing the disclosed subject matter are included for purposes of explanation and are not intended to limit the scope of the claims.

對於本領域之習知技藝者來說同樣顯而易見的是可在不悖離本文揭示的標的之精神和範疇的情況下,基於說明書中描述的態樣對如何實踐該揭示標的進行各種修飾。It will also be apparent to those skilled in the art that various modifications can be made on how to practice the disclosed subject matter based on the aspects described in the specification without departing from the spirit and scope of the disclosed subject matter herein.

I.  具有多階開關的鐵電穿隧接面I. Ferroelectric Tunneling Junction with Multilevel Switching

鐵電隧道接面(FTJ)最近已被研究作為憶阻器(memristor)或人工突觸的最佳候選者之一,這要歸功於其適用於神經形態計算應用的獨特類比式程式編寫基礎。夾在TiN電極與W電極之間用特定前驅物(HfD-04及ZrD-04)於高溫下沉積的ALD HZO膜及特定後金屬退火(PMA)之運用允許多達 4 階的多階程式編寫,並且保持力與一般使用具有更高複雜性的雙層堆疊的FTJ的當前技術水準相當。本揭示內容為未來在神經形態運算晶片中實現FTJ鋪平了道路。Ferroelectric tunnel junctions (FTJs) have recently been investigated as one of the best candidates for memristors or artificial synapses, thanks to their unique analog programming basis for neuromorphic computing applications. ALD HZO film deposited at high temperature with specific precursors (HfD-04 and ZrD-04) sandwiched between TiN and W electrodes and application of specific post-metal annealing (PMA) allows multi-level programming up to 4 levels , and the retention is comparable to current state of the art generally using FTJs with double-layer stacks of higher complexity. This disclosure paves the way for future implementations of FTJs in neuromorphic computing chips.

本揭示內容展示一種於頂部電極與底部電極之間引入不對稱性的新技術。這能藉由使用該Hf和Zr前驅物(HfD-04和ZrD-04)的交替循環及於其間用臭氧脈衝氧化之鉿鋯氧化物(HZO)的高溫(>300C)原子層沉積(ALD)促成。This disclosure demonstrates a new technique for introducing asymmetry between the top and bottom electrodes. This can be achieved by high temperature (>300C) atomic layer deposition (ALD) of hafnium zirconium oxide (HZO) oxidized by alternating cycles of the Hf and Zr precursors (HfD-04 and ZrD-04) with an ozone pulse in between. contributed to.

此沉積以此方式構建FTJ堆疊使其可在沒有任何界面介電層的情況下製造,並且可在高記憶體區間(2倍至10倍)之間切換。在製造鐵電記憶體裝置的最先進系統中,通常使用較低溫ALD沉積FE材料,使該膜原沉積時為非晶形並且進而非FE,緊接著進行高溫退火(>500C)以使該膜結晶並且活化該膜的FE性質。對於具有界面層的FTJ,需要額外的處理步驟來沉積該界面材料。由於該前驅物能夠處理高溫(>300C)使本製程整合及堆疊能獲得原沉積態FE膜。此外,該製程本來就會氧化該底部電極(由於其高溫及高反應性臭氧製程)以產生界面金屬氧化物,從而引入該FTJ操作所需的不對稱性。可引入高於該沉積溫度的進一步退火以改善FE記憶體區間及可靠性指標,如保持力及耐久性。This deposition builds the FTJ stack in such a way that it can be fabricated without any interfacial dielectric layer and can be switched between high memory regimes (2x to 10x). In state-of-the-art systems for fabricating ferroelectric memory devices, lower temperature ALD is typically used to deposit FE material, rendering the film as-deposited amorphous and thus non-FE, followed by high temperature annealing (>500C) to crystallize the film And activate the FE properties of the membrane. For FTJs with an interfacial layer, additional processing steps are required to deposit this interfacial material. Since the precursor can handle high temperature (>300C), the process integration and stacking can obtain the original deposited FE film. Furthermore, the process inherently oxidizes the bottom electrode (due to its high temperature and highly reactive ozone process) to produce interfacial metal oxides, thereby introducing the asymmetry required for the FTJ operation. Further annealing above this deposition temperature can be introduced to improve FE memory range and reliability metrics such as retention and endurance.

此外,該HZO膜的優化,該FTJ堆疊展示穿隧電阻(TER)的良好可調性,這使其可程式編寫多達4個不同階,各階具有至少10 3秒的良好記憶保持力。該4個不同記憶階的含義允許一個單FTJ晶胞中儲存多達2位元資料,與該二元開關FTJ中每一晶胞儲存1位元不同。適度選擇ALD沉積溫度、臭氧稀釋及後金屬退火條件是獲得鐵電多域開關所需的期望斜方晶相(orthorhombic phase)的基礎,這對於FTJ中的多階開關至關重要。 Furthermore, with the optimization of the HZO film, the FTJ stack exhibits good tunability of the tunneling resistance (TER), which makes it programmable up to 4 different stages, each with a good memory retention of at least 10 3 s. The meaning of the 4 different memory levels allows storing up to 2 bits of data in a single FTJ cell, as opposed to storing 1 bit per cell in the binary switch FTJ. Moderate choice of ALD deposition temperature, ozone dilution, and post-metal annealing conditions are fundamental to obtain the desired orthorhombic phase required for ferroelectric multi-domain switches, which is crucial for multi-level switching in FTJs.

實證FTJ晶胞除了儲存多位元數位資料外,也可用作可儲存其於一定範圍內可逐漸調整的電阻值之類比記憶體。該FTJ在逐漸切換FTJ中電阻時顯示迄今為止尚未得到證實的>2倍動態範圍。It has been demonstrated that in addition to storing multi-bit digital data, the FTJ unit cell can also be used as an analog memory that can store its resistance value that can be gradually adjusted within a certain range. This FTJ exhibits a hitherto unproven >2x dynamic range when gradually switching the resistance in the FTJ.

本揭示內容首次顯示BEOL相容性製程,其中鉿鋯氧化物(HZO)開關層夾於不對稱的TiN電極與W電極之間,具有多達4個狀態的多階程式編寫及這些狀態經過至少10 3秒的良好保持力。在HZO沉積期間,氧化界面層(TiO xN y)藉由將該TiN底部電極界面氧化產生。此步驟的優點係於該沉積製程中伴隨發生並且不需要額外的製程步驟。在另一具體實例中,該第一電極包含W並且該氧化界面層包含WO x。在另一具體實例中,該第一電極包含Ru並且該氧化界面層包含RuO xThis disclosure shows for the first time a BEOL compatible process in which a hafnium zirconium oxide (HZO) switching layer is sandwiched between an asymmetric TiN electrode and a W electrode, with multi-level programming of up to 4 states and the states are passed through at least Good hold for 10 3 seconds. During HZO deposition, an oxidized interfacial layer ( TiOxNy ) was created by oxidizing the TiN bottom electrode interface. The advantage of this step is that it occurs concomitantly in the deposition process and does not require additional process steps. In another embodiment, the first electrode comprises W and the oxidized interfacial layer comprises WO x . In another specific example, the first electrode comprises Ru and the oxidized interfacial layer comprises RuOx .

解決上述問題的固有鐵電薄膜材料及其使用方法係揭示於此及2020年6月17日申請的美國臨時專利申請案第63/040,097號(代理人編號P20-094 US-PRO)及2021年6月15日申請的PCT申請案第PCT/EP2021/066028號(P20-094 WO-PCT)。這些申請案係以引用的方式將其全文併入。這樣做時,本文所述的材料及方法縮短了處理時間,使其尤其能順應當前製程的要求。 該揭示內容涉及具有9或更多階不同電阻的FTJ。本領域之習知技藝者可輕易地理解在這些材料沉積之後界面、電極及熱處理條件的後繼優化的潛力。Intrinsically ferroelectric thin film materials and methods of using them that address the above problems are disclosed herein and in U.S. Provisional Patent Application No. 63/040,097 (Attorney Docket P20-094 US-PRO) filed June 17, 2020 and 2021 PCT Application No. PCT/EP2021/066028 (P20-094 WO-PCT) filed on 15 June. These applications are incorporated by reference in their entirety. In doing so, the materials and methods described herein reduce processing time, making them especially amenable to current process requirements. This disclosure relates to FTJs with 9 or more orders of different resistances. Those skilled in the art can readily appreciate the potential for subsequent optimization of interfaces, electrodes, and thermal treatment conditions after deposition of these materials.

II. 固有鐵電材料II. Intrinsically Ferroelectric Materials

如上所述,該揭示並請求保護的標的關於包括氧化鉿和氧化鋯的混合物之結晶性鐵電薄膜材料,該結晶性鐵電材料包括具有實質(即,約40%或更多)部分處於鐵電相;以及用於製備及沉積這些材料的方法。在另一態樣中,該鐵電材料具有大部分體積分率的鐵電相。很顯然地,這些材料顯現出鐵電性質,無需進一步處理,例如後繼護面步驟或退火步驟。要成為鐵電性,所生產的材料具有以下一或多者:(i) 剩磁極化或(ii) 具有磁滯及迴路開度的極化場曲線(polarization field curve)。As noted above, the disclosed and claimed subject matter pertains to crystalline ferroelectric thin film materials comprising a mixture of hafnium oxide and zirconium oxide, the crystalline ferroelectric material comprising Electrophases; and methods for preparing and depositing these materials. In another aspect, the ferroelectric material has a majority volume fraction of the ferroelectric phase. Clearly, these materials exhibit ferroelectric properties without the need for further processing, such as subsequent coating steps or annealing steps. To be ferroelectric, a material is produced that has one or more of: (i) remanent polarization or (ii) a polarization field curve with hysteresis and loop opening.

為了成為鐵電性,該材料必須具有能夠支持該膜的某些部分的鐵電性的原子排列。較佳地,該膜體積的實質部分具有可支持鐵電性的原子排列。咸能理解對於薄膜、摻雜材料及一些層壓材料,該材料中的相分佈可能不容易藉由X射線繞射測定。在此情況下,任何其他適合用於確立該膜的相之技術,例如拉曼光譜​​、紅外光譜、X射線吸收光譜、穿透式電子顯微鏡或其組合,皆可用以測定該相分佈。舉例來說,https://onlinelibrary.wiley.com/doi/ full/10.1002/pssb.201900285描述一種確認一膜的相到約10%以內的技術。In order to be ferroelectric, the material must have an arrangement of atoms capable of supporting ferroelectricity in certain parts of the film. Preferably, a substantial portion of the film volume has an arrangement of atoms that supports ferroelectricity. It is understood that for thin films, doped materials, and some laminated materials, the phase distribution in the material may not be readily determined by X-ray diffraction. In this case, any other suitable technique for establishing the phase of the film, such as Raman spectroscopy, infrared spectroscopy, X-ray absorption spectroscopy, transmission electron microscopy or a combination thereof, can be used to determine the phase distribution. For example, https://onlinelibrary.wiley.com/doi/full/10.1002/pssb.201900285 describes a technique for confirming the phase of a film to within about 10%.

該材料可包含任何合適的氧化鉿和氧化鋯莫耳比 – 較佳為介於1:3與3:1之間的比率。該鐵電材料的厚度係適用於特定應用的任何厚度;該材料可做得更厚使該剩磁極化提高或使通過該材料厚度的洩漏電流減少。該材料可就幾何限制或為了提高該膜的電容量而做得更薄。The material may comprise any suitable molar ratio of hafnium oxide to zirconium oxide - preferably a ratio between 1:3 and 3:1. The thickness of the ferroelectric material is any thickness suitable for a particular application; the material can be made thicker to increase the remanent magnetic polarization or to reduce leakage current through the material thickness. The material can be made thinner for geometric constraints or to increase the capacitance of the film.

此鐵電膜的較佳厚度範圍為約0.2 nm至約20 nm,更佳為約0.2 nm至10 nm。也較佳為該材料形成具有約10 nm或更小的厚度的膜。在一些具體實例中,較佳為該材料形成具有約5 nm或更小的厚度的膜。A preferred thickness range of the ferroelectric film is about 0.2 nm to about 20 nm, more preferably about 0.2 nm to 10 nm. It is also preferred that the material is formed into a film having a thickness of about 10 nm or less. In some embodiments, it is preferred that the material forms a film having a thickness of about 5 nm or less.

然而,如上所述,較佳的及/或期望的厚度將根據具體應用而改變。因此,如前所述,在某些具體實例中,該材料顯現出如約20 nm或更小的薄膜之鐵電性質。在另一態樣中,該材料顯現出如約15 nm或更小的薄膜之鐵電性質。在另一態樣中,該材料顯現出如約10 nm或更小的薄膜之鐵電性質。在另一態樣中,該材料顯現出如約5 nm或更小的薄膜之鐵電性質。在另一態樣中,該材料顯現出如約3 nm或更小的薄膜之鐵電性質。在另一態樣中,該材料顯現出如約1 nm或更小的薄膜之鐵電性質。在另一態樣中,該材料顯現出如約0.5 nm或更小的薄膜之鐵電性質。在另一態樣中,該材料顯現出如約0.2 nm或更小的薄膜之鐵電性質。在另一態樣中,該材料顯現出如介於約0.2 nm至約20 nm的薄膜之鐵電性質。在另一態樣中,該材料顯現出如介於約0.2 nm至約15 nm的薄膜之鐵電性質。在另一態樣中,該材料顯現出如介於約0.2 nm至約10 nm的薄膜之鐵電性質。在另一態樣中,該材料顯現出如介於約0.2 nm至約5 nm的薄膜之鐵電性質。在另一態樣中,該材料顯現出如介於約0.2 nm至約3 nm的薄膜之鐵電性質。在另一態樣中,該材料顯現出如介於約0.2 nm至約1 nm的薄膜之鐵電性質。性質。在另一態樣中,該材料顯現出如介於約0.2 nm至約1 nm的薄膜之鐵電性質。However, as noted above, the preferred and/or desired thickness will vary depending on the particular application. Thus, as previously stated, in certain embodiments, the material exhibits ferroelectric properties as thin films of about 20 nm or less. In another aspect, the material exhibits ferroelectric properties as thin films of about 15 nm or smaller. In another aspect, the material exhibits ferroelectric properties as thin films of about 10 nm or less. In another aspect, the material exhibits ferroelectric properties as thin films of about 5 nm or less. In another aspect, the material exhibits ferroelectric properties as thin films of about 3 nm or less. In another aspect, the material exhibits ferroelectric properties as thin films of about 1 nm or smaller. In another aspect, the material exhibits ferroelectric properties as thin films of about 0.5 nm or smaller. In another aspect, the material exhibits ferroelectric properties as thin films of about 0.2 nm or smaller. In another aspect, the material exhibits ferroelectric properties as a thin film between about 0.2 nm to about 20 nm. In another aspect, the material exhibits ferroelectric properties as a thin film between about 0.2 nm to about 15 nm. In another aspect, the material exhibits ferroelectric properties as a thin film between about 0.2 nm to about 10 nm. In another aspect, the material exhibits ferroelectric properties as a thin film between about 0.2 nm to about 5 nm. In another aspect, the material exhibits ferroelectric properties as a thin film between about 0.2 nm to about 3 nm. In another aspect, the material exhibits ferroelectric properties as a thin film of between about 0.2 nm to about 1 nm. nature. In another aspect, the material exhibits ferroelectric properties as a thin film of between about 0.2 nm to about 1 nm.

在該揭示並請求保護的材料中,構成該晶體材料的約40%或更多的實質部分係處於鐵電相,因此該非鐵電原子排列組分總量小於該材料總體積的約60%。在另一具體實例中,該非鐵電原子排列組分總量小於該材料總體積的約50%。在另一具體實例中,該非鐵電原子排列組分總量小於該材料總體積的約40%。在另一具體實例中,該非鐵電原子排列組分總量小於該材料總體積的約30%。在另一具體實例中,該非鐵電原子排列組分總量小於該材料總體積的約25%。在另一具體實例中,該非鐵電原子排列組分總量小於該材料總體積的約20%。在另一具體實例中,該非鐵電原子排列組分總量小於該材料總體積的約15%。在另一具體實例中,該非鐵電原子排列組分總量小於該材料總體積的約10%。在另一具體實例中,該非鐵電原子排列組分總量小於該材料總體積的約5%。In the disclosed and claimed material, a substantial portion of about 40% or more of the crystalline material is in the ferroelectric phase, such that the total amount of non-ferroelectric atomic arrangement components is less than about 60% of the total volume of the material. In another embodiment, the total amount of non-ferroelectric atomic arrangement components is less than about 50% of the total volume of the material. In another embodiment, the total amount of non-ferroelectric atomic arrangement components is less than about 40% of the total volume of the material. In another embodiment, the total amount of non-ferroelectric atomic arrangement components is less than about 30% of the total volume of the material. In another embodiment, the total amount of non-ferroelectric atomic arrangement components is less than about 25% of the total volume of the material. In another embodiment, the total amount of non-ferroelectric atomic arrangement components is less than about 20% of the total volume of the material. In another embodiment, the total amount of non-ferroelectric atomic arrangement components is less than about 15% of the total volume of the material. In another embodiment, the total amount of non-ferroelectric atomic arrangement components is less than about 10% of the total volume of the material. In another embodiment, the total amount of non-ferroelectric atomic arrangement components is less than about 5% of the total volume of the material.

再者,在該揭示並請求保護的材料中,小於該材料總體積的約60%構成非鐵電單斜晶相組分。因此,在該揭示並請求保護的材料之一具體實例中,單斜晶相組分小於該材料總體積的約50%。在另一具體實例中,單斜晶相組分小於該材料總體積的約40%。在另一具體實例中,單斜晶相組分小於該材料總體積的約30%。在另一具體實例中,單斜晶相組分小於該材料總體積的約25%。在另一具體實例中,單斜晶相組分小於該材料總體積的約20%。在另一具體實例中,單斜晶相組分小於該材料總體積的約15%。在另一具體實例中,單斜晶相組分小於該材料總體積的約10%。在另一具體實例中,單斜晶相組分小於該材料總體積的約5%。Furthermore, in the disclosed and claimed material, less than about 60% of the total volume of the material constitutes a non-ferroelectric monoclinic phase component. Thus, in one embodiment of the disclosed and claimed material, the monoclinic phase component is less than about 50% of the total volume of the material. In another specific example, the monoclinic phase component is less than about 40% of the total volume of the material. In another specific example, the monoclinic phase component is less than about 30% of the total volume of the material. In another specific example, the monoclinic phase component is less than about 25% of the total volume of the material. In another specific example, the monoclinic phase component is less than about 20% of the total volume of the material. In another specific example, the monoclinic phase component is less than about 15% of the total volume of the material. In another specific example, the monoclinic phase component is less than about 10% of the total volume of the material. In another specific example, the monoclinic phase component is less than about 5% of the total volume of the material.

在該揭示並請求保護的標的中,該材料的較佳碳含量藉由合適的技術例如X射線光電子光譜法測量時低於約6原子百分比。在另一態樣中,該碳含量低於約5原子百分比。在另一態樣中,該碳含量低於約4原子百分比。在另一態樣中,該碳含量低於約3原子百分比。在另一態樣中,該碳含量低於約2原子百分比。在另一態樣中,該碳含量低於約1原子百分比。在另一態樣中,該碳含量介於約1原子百分比與約6百分比之間。在另一態樣中,該碳含量介於約1原子百分比與約5百分比之間。在另一態樣中,該碳含量介於約1原子百分比與約4百分比之間。在另一態樣中,該碳含量介於約1原子百分比與約3百分比之間。在另一態樣中,該碳含量介於約1原子百分比與約2百分比之間。In the disclosed and claimed subject matter, the preferred carbon content of the material is less than about 6 atomic percent as measured by a suitable technique, such as X-ray photoelectron spectroscopy. In another aspect, the carbon content is less than about 5 atomic percent. In another aspect, the carbon content is less than about 4 atomic percent. In another aspect, the carbon content is less than about 3 atomic percent. In another aspect, the carbon content is less than about 2 atomic percent. In another aspect, the carbon content is less than about 1 atomic percent. In another aspect, the carbon content is between about 1 atomic percent and about 6 percent. In another aspect, the carbon content is between about 1 atomic percent and about 5 percent. In another aspect, the carbon content is between about 1 atomic percent and about 4 atomic percent. In another aspect, the carbon content is between about 1 atomic percent and about 3 percent. In another aspect, the carbon content is between about 1 atomic percent and about 2 percent.

該固有鐵電材料係衍生自茂金屬前驅物,該茂金屬前驅物係選自具有式I (“(R 1-Cp)(R 2-Cp)-M-(OR 3)(R 4)”,其中Cp係環戊二烯基)及/或式II (“(R 5-Cp)(R 6-Cp)-M-(R 7)(R 8)”,其中Cp係環戊二烯基)的先進茂金屬前驅物:

Figure 02_image018
Figure 02_image020
其中      M = Zr或Hf,並且 R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8係各自獨立地選自C 1-C 6直鏈烷基、C 1-C 6支鏈烷基、C 1-C 6鹵代直鏈烷基及C 1-C 6鹵代支鏈烷基。 The intrinsic ferroelectric material is derived from a metallocene precursor selected from the group having the formula I (“(R 1 -Cp)(R 2 -Cp)-M-(OR 3 )(R 4 )” , wherein Cp is cyclopentadienyl) and/or formula II ("(R 5 -Cp)(R 6 -Cp)-M-(R 7 )(R 8 )", wherein Cp is cyclopentadienyl ) advanced metallocene precursors:
Figure 02_image018
Figure 02_image020
Where M = Zr or Hf, and R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently selected from C 1 -C 6 linear alkyl, C 1 - C 6 branched chain alkyl, C 1 -C 6 halogenated straight chain alkyl and C 1 -C 6 halogenated branched chain alkyl.

在另一態樣中,在式I中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為C 1-C 6直鏈烷基。在另一態樣中,在式I中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為相同的C 1-C 6直鏈烷基。在另一態樣中,在式I中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為甲基。在另一態樣中,在式I中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為乙基。在另一態樣中,在式I中R 1、R 2、R 5及R 6各自較佳為乙基。在另一態樣中,在式I中R 3、R 4、R 7及R 8各自較佳為甲基。在另一態樣中,在式I中R 1、R 2、R 5及R 6各自較佳為乙基並且R 3、R 4、R 7及R 8各自較佳為甲基。 In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula I is preferably a C 1 -C 6 linear alkyl group. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula I is preferably the same C 1 -C 6 linear alkyl group. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula I is preferably methyl. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula I is preferably ethyl. In another aspect, each of R 1 , R 2 , R 5 and R 6 in Formula I is preferably ethyl. In another aspect, each of R 3 , R 4 , R 7 and R 8 in formula I is preferably methyl. In another aspect, each of R 1 , R 2 , R 5 and R 6 in Formula I is preferably ethyl and each of R 3 , R 4 , R 7 and R 8 is preferably methyl.

在另一態樣中,在式II中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為C 1-C 6直鏈烷基。在另一態樣中,在式II中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為相同的C 1-C 6直鏈烷基。在另一態樣中,在式II中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為甲基。在另一態樣中,在式II中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為乙基。在另一態樣中,在式II中R 1、R 2、R 5及R 6各自較佳為乙基。在另一態樣中,在式II中R 3、R 4、R 7及R 8各自較佳為甲基。在另一態樣中,在式II中R 1、R 2、R 5及R 6各自較佳為乙基並且R 3、R 4、R 7及R 8各自較佳為甲基。 In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in formula II is preferably a C 1 -C 6 linear alkyl group. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula II is preferably the same C 1 -C 6 linear alkyl group. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula II is preferably methyl. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in formula II is preferably ethyl. In another aspect, each of R 1 , R 2 , R 5 and R 6 in formula II is preferably ethyl. In another aspect, each of R 3 , R 4 , R 7 and R 8 in formula II is preferably methyl. In another aspect, each of R 1 , R 2 , R 5 and R 6 in Formula II is preferably ethyl and each of R 3 , R 4 , R 7 and R 8 is preferably methyl.

在另一態樣中,該先進茂金屬前驅物係(MeCp) 2Zr(OMe)Me、(MeCp) 2Hf(OMe)Me、(MeCp) 2Zr(Me) 2、(MeCp) 2Hf(Me) 2、(EtCp) 2Zr(OMe)Me、(EtCp) 2Hf(OMe)Me、(EtCp) 2Zr(Me) 2、(EtCp) 2Hf(Me) 2及其組合中的一或多者。 In another aspect, the advanced metallocene precursor system (MeCp) 2 Zr(OMe)Me, (MeCp) 2 Hf(OMe)Me, (MeCp) 2 Zr(Me) 2 , (MeCp) 2 Hf( one or _ _ _ _ _ many.

在另一態樣中,該先進茂金屬前驅物係(MeCp) 2Zr(OMe)Me和(MeCp) 2Hf(OMe)Me的混合物、(MeCp) 2Hf(Me) 2和(MeCp) 2Hf(Me) 2的混合物、(EtCp) 2Zr(OMe)Me和(EtCp) 2Hf(OMe)Me的混合物及(EtCp) 2Hf(Me) 2和(EtCp) 2Hf(Me) 2的混合物中的一或多者。 In another aspect, the advanced metallocene precursor system is a mixture of (MeCp) 2 Zr(OMe)Me and (MeCp) 2 Hf(OMe)Me, (MeCp) 2 Hf(Me) 2 and (MeCp) 2 The mixture of Hf(Me) 2 , the mixture of (EtCp) 2 Zr(OMe)Me and (EtCp) 2 Hf(OMe)Me and the mixture of (EtCp) 2 Hf(Me) 2 and (EtCp) 2 Hf(Me) 2 One or more of a mixture.

在另一態樣中,該先進茂金屬前驅物係美國專利第8,568,530號中揭示及/或請求保護的前驅物中的一或多者,其內容在此以引用的方式將其全文併入本文。In another aspect, the advanced metallocene precursor is one or more of the precursors disclosed and/or claimed in U.S. Patent No. 8,568,530, the contents of which are hereby incorporated by reference in their entirety. .

III. 製備及沉積固有鐵電材料的方法III. Methods of Fabricating and Depositing Intrinsically Ferroelectric Materials

如上所示,在另一態樣中該揭示並請求保護的標的係關於本文所揭示之製備及沉積該固有鐵電材料的方法。在此方法中,該揭示並請求保護的固有鐵電材料係藉由迭代的沉積及吹掃(i) 茂金屬前驅物及(ii) 反應物來製備。As indicated above, in another aspect the disclosed and claimed subject matter relates to the methods of making and depositing the intrinsic ferroelectric materials disclosed herein. In this method, the disclosed and claimed intrinsically ferroelectric materials are prepared by iterative deposition and purging of (i) metallocene precursors and (ii) reactants.

A. 茂金屬前驅物A. Metallocene Precursors

如上所示,該鐵電材料係衍生自先進的茂金屬前驅物,該茂金屬前驅物具有式I (“(R 1-Cp)(R 2-Cp)-M-(OR 3)(R 4)”,其中Cp係環戊二烯基)及/或式II (“(R 5-Cp)(R 6-Cp)-M-(R 7)(R 8)”,其中Cp係環戊二烯基):

Figure 02_image022
Figure 02_image023
其中      M = Zr或Hf,並且 R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8係各自獨立地選自C 1-C 6直鏈烷基、C 1-C 6支鏈烷基、C 1-C 6鹵代直鏈烷基及C 1-C 6鹵代支鏈烷基。 As shown above, the ferroelectric material is derived from an advanced metallocene precursor having the formula I (“(R 1 -Cp)(R 2 -Cp)-M-(OR 3 )(R 4 )", wherein Cp is cyclopentadienyl) and/or formula II ("(R 5 -Cp)(R 6 -Cp)-M-(R 7 )(R 8 )", wherein Cp is cyclopentadienyl alkenyl):
Figure 02_image022
Figure 02_image023
Where M = Zr or Hf, and R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently selected from C 1 -C 6 linear alkyl, C 1 - C 6 branched chain alkyl, C 1 -C 6 halogenated straight chain alkyl and C 1 -C 6 halogenated branched chain alkyl.

在另一態樣中,在式I中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為C 1-C 6直鏈烷基。在另一態樣中,在式I中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為相同的C 1-C 6直鏈烷基。在另一態樣中,在式I中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為甲基。在另一態樣中,在式I中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為乙基。在另一態樣中,在式I中R 1、R 2、R 5及R 6各自較佳為乙基。在另一態樣中,在式I中R 3、R 4、R 7及R 8各自較佳為甲基。在另一態樣中,在式I中R 1、R 2、R 5及R 6各自較佳為乙基並且R 3、R 4、R 7及R 8各自較佳為甲基。 In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula I is preferably a C 1 -C 6 linear alkyl group. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula I is preferably the same C 1 -C 6 linear alkyl group. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula I is preferably methyl. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula I is preferably ethyl. In another aspect, each of R 1 , R 2 , R 5 and R 6 in Formula I is preferably ethyl. In another aspect, each of R 3 , R 4 , R 7 and R 8 in formula I is preferably methyl. In another aspect, each of R 1 , R 2 , R 5 and R 6 in Formula I is preferably ethyl and each of R 3 , R 4 , R 7 and R 8 is preferably methyl.

在另一態樣中,在式II中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為C 1-C 6直鏈烷基。在另一態樣中,在式II中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為相同的C 1-C 6直鏈烷基。在另一態樣中,在式II中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為甲基。在另一態樣中,在式II中R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自較佳為乙基。在另一態樣中,在式II中R 1、R 2、R 5及R 6各自較佳為乙基。在另一態樣中,在式II中R 3、R 4、R 7及R 8各自較佳為甲基。在另一態樣中,在式II中R 1、R 2、R 5及R 6各自較佳為乙基並且R 3、R 4、R 7及R 8各自較佳為甲基。 In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in formula II is preferably a C 1 -C 6 linear alkyl group. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula II is preferably the same C 1 -C 6 linear alkyl group. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula II is preferably methyl. In another aspect, each of R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 in Formula II is preferably ethyl. In another aspect, each of R 1 , R 2 , R 5 and R 6 in formula II is preferably ethyl. In another aspect, each of R 3 , R 4 , R 7 and R 8 in formula II is preferably methyl. In another aspect, each of R 1 , R 2 , R 5 and R 6 in Formula II is preferably ethyl and each of R 3 , R 4 , R 7 and R 8 is preferably methyl.

在另一態樣中,該先進茂金屬前驅物係(MeCp) 2Zr(OMe)Me、(MeCp) 2Hf(OMe)Me、(MeCp) 2Zr(Me) 2、(MeCp) 2Hf(Me) 2、(EtCp) 2Zr(OMe)Me、(EtCp) 2Hf(OMe)Me、(EtCp) 2Zr(Me) 2、(EtCp) 2Hf(Me) 2及其組合中的一或多者。 In another aspect, the advanced metallocene precursor system (MeCp) 2 Zr(OMe)Me, (MeCp) 2 Hf(OMe)Me, (MeCp) 2 Zr(Me) 2 , (MeCp) 2 Hf( one or _ _ _ _ _ many.

在另一態樣中,該先進茂金屬前驅物係(MeCp) 2Zr(OMe)Me和(MeCp) 2Hf(OMe)Me的混合物、(MeCp) 2Hf(Me) 2和(MeCp) 2Hf(Me) 2的混合物、(EtCp) 2Zr(OMe)Me和(EtCp) 2Hf(OMe)Me的混合物及(EtCp) 2Hf(Me) 2和(EtCp) 2Hf(Me) 2的混合物中的一或多者。 In another aspect, the advanced metallocene precursor system is a mixture of (MeCp) 2 Zr(OMe)Me and (MeCp) 2 Hf(OMe)Me, (MeCp) 2 Hf(Me) 2 and (MeCp) 2 The mixture of Hf(Me) 2 , the mixture of (EtCp) 2 Zr(OMe)Me and (EtCp) 2 Hf(OMe)Me and the mixture of (EtCp) 2 Hf(Me) 2 and (EtCp) 2 Hf(Me) 2 One or more of a mixture.

在另一態樣中,該先進茂金屬前驅物係美國專利第8,568,530號中揭示及/或請求保護的前驅物中的一或多者,其內容在此以引用的方式將其全文併入本文。In another aspect, the advanced metallocene precursor is one or more of the precursors disclosed and/or claimed in U.S. Patent No. 8,568,530, the contents of which are hereby incorporated by reference in their entirety. .

一般,適用於製備該固有鐵電材料的前驅物能夠於該期望鐵電材料的結晶溫度處或附近沉積,通常介於約200°C與約570°C之間,這取決於該材料的組成、基材及反應器設計等因素。較佳的溫度為約300℃ (或一般介於約280℃與約300℃之間),並且該較佳的溫度範圍係低於約450℃,更佳地低於約340℃。然而,本領域之習知技藝者應當認知到其他溫度可取決於所用的指定前驅物,並且此前驅物也落於該揭示並請求保護的標的之範疇內。另外應注意除了此處列出的某些前驅物,該前驅物的分解可於所述溫度範圍內發生。分解產物,特別是碳和有機物質,可能結合到該沉積氧化鉿或氧化鋯材料中。儘管此碳的結合可能有助於該鐵電相的穩定化,但是由於材料純度的原因,這可能是不合宜的。因此,如上文討論的,該材料的較佳碳含量低於約6原子百分比。Generally, precursors suitable for making the intrinsic ferroelectric material can be deposited at or near the crystallization temperature of the desired ferroelectric material, typically between about 200°C and about 570°C, depending on the composition of the material , substrate and reactor design and other factors. A preferred temperature is about 300°C (or generally between about 280°C and about 300°C), and the preferred temperature range is below about 450°C, more preferably below about 340°C. However, those skilled in the art will recognize that other temperatures may depend on the particular precursor used, and such precursors are also within the scope of the disclosed and claimed subject matter. It should also be noted that decomposition of precursors other than those listed here can occur within the stated temperature range. Decomposition products, especially carbon and organic matter, may be incorporated into the deposited hafnium oxide or zirconium oxide material. Although the incorporation of this carbon may contribute to the stabilization of the ferroelectric phase, this may be undesirable due to material purity. Thus, as discussed above, the preferred carbon content of the material is less than about 6 atomic percent.

B. 反應物B. Reactants

該反應物係含有氧(例如,臭氧、元素氧、分子氧/O 2)、水、過氧化氫及一氧化二氮中的一或多者的反應氣體。在一具體實例中,臭氧為較佳的反應氣體。在另一具體實例中,水為較佳的反應物氣體。 The reactant is a reactive gas containing one or more of oxygen (eg, ozone, elemental oxygen, molecular oxygen/O 2 ), water, hydrogen peroxide, and nitrous oxide. In one embodiment, ozone is a preferred reactive gas. In another embodiment, water is a preferred reactant gas.

圖2A至2D舉例說明本文揭示的鐵電穿隧接面的替代具體實例。圖2A顯示具有頂部電極102、鐵電材料層104及於基材108上的底部電極106之FTJ。圖2B顯示具有頂部電極202a、頂部界面層210a、鐵電材料層204a、底部界面層220a及基材(未顯示)上底部電極206a的FTJ具體實例200a。圖2C顯示具有頂部電極202b、鐵電材料層204b、底部界面層220b及基材(未顯示)上底部電極206b的FTJ具體實例200b。圖2D顯示具有頂部電極202c、頂部界面層210c、鐵電材料層204c及基材(未顯示)上底部電極206c的FTJ具體實例200c。在圖5A例示的具體實例中,該頂部電極包含TiN,該鐵電材料層包含氧化鉿和氧化鋯(HZO),該底部界面層包含氧化鎢(WOx),並且該底層包含鎢。2A-2D illustrate alternative embodiments of the ferroelectric tunnel junctions disclosed herein. FIG. 2A shows an FTJ with a top electrode 102 , a layer of ferroelectric material 104 and a bottom electrode 106 on a substrate 108 . 2B shows an FTJ embodiment 200a having a top electrode 202a, a top interface layer 210a, a layer of ferroelectric material 204a, a bottom interface layer 220a, and a bottom electrode 206a on a substrate (not shown). Figure 2C shows an FTJ embodiment 200b having a top electrode 202b, a layer of ferroelectric material 204b, a bottom interface layer 220b, and a bottom electrode 206b on a substrate (not shown). Figure 2D shows an FTJ embodiment 200c having a top electrode 202c, a top interface layer 210c, a layer of ferroelectric material 204c, and a bottom electrode 206c on a substrate (not shown). In the specific example illustrated in FIG. 5A, the top electrode comprises TiN, the ferroelectric material layer comprises hafnium oxide and zirconium oxide (HZO), the bottom interface layer comprises tungsten oxide (WOx), and the bottom layer comprises tungsten.

C. 製程步驟C. Process steps

圖3A舉例說明製備及沉積本文所述的固有鐵電材料之方程的具體實例。如圖例示的,基材502經歷ALD循環504,其中使基材502暴露於蒸氣201以形成並且將固有鐵電材料沉積為一薄膜層300。層300係於無需進一步熱處理或護面的情況下形成並且顯現出本身的鐵電性質(即,原沉積態)。當然,本領域之習知技藝者認知到層300可於其後視需要退火及/或護面,但是這樣做對於觀察到該原沉積層的鐵電行為不是必需的。舉例來說,能量可於其後藉由,但不限於,熱、電漿、脈衝電漿、螺旋電漿、高密度電漿、感應耦合電漿、X射線、電子束、光子、遠程電漿方法及其組合施於該材料。Figure 3A illustrates a specific example of the equations for making and depositing the intrinsic ferroelectric materials described herein. As illustrated, the substrate 502 is subjected to an ALD cycle 504 in which the substrate 502 is exposed to the vapor 201 to form and deposit the intrinsic ferroelectric material as a thin film layer 300 . Layer 300 is formed without further heat treatment or face protection and exhibits intrinsic ferroelectric properties (ie, as-deposited). Of course, those skilled in the art recognize that layer 300 may thereafter be annealed and/or protected as desired, but doing so is not necessary to observe the ferroelectric behavior of the as-deposited layer. For example, energy can be thereafter delivered by, but not limited to, heat, plasma, pulsed plasma, helical plasma, high-density plasma, inductively coupled plasma, X-rays, electron beams, photons, remote plasma Methods and combinations thereof are applied to the material.

該蒸氣301的構成成分在ALD循環504期間發生變化。特別是,使基材502交替地暴露於茂金屬前驅物505,緊接著吹掃,然後​​暴露於反應物506,緊接著另一吹掃。本製程繼續直到獲得層300的期望厚度。儘管ALD係較佳的氣相沉積技術,但是任何合適的氣相沉積技術皆可利用,例如CVD或脈衝CVD。因此,舉例來說,於圖3A中,ALD循環504可藉由CVD製程替代,其中茂金屬前驅物505及反應物506係採蒸氣201中混合物的方式提供並且同時提供給基材502。The composition of the vapor 301 changes during the ALD cycle 504 . In particular, substrate 502 is alternately exposed to metallocene precursor 505 followed by a purge, then exposed to reactant 506 followed by another purge. The process continues until the desired thickness of layer 300 is obtained. Although ALD is the preferred vapor deposition technique, any suitable vapor deposition technique may be used, such as CVD or pulsed CVD. Thus, for example, in FIG. 3A , ALD cycle 504 may be replaced by a CVD process in which metallocene precursor 505 and reactant 506 are provided as a mixture in vapor 201 and simultaneously to substrate 502 .

氧化鉿與氧化鋯的適當莫耳比可藉由幾種方法產生,包括在這些循環的一部分期間引入含鉿的前驅物,及在其他循環期間引入含鋯的前驅物。該循環可交替,組合在一起,或以任何其他合適順序排列以產生該總體期望莫耳比,因為緊密混合的材料及奈米層壓材料皆顯示具有所需的鐵電性質。應該注意的是其他元素可藉由與該鉿和鋯前驅物一起添加適當的前驅物,或於單獨循環中加於該氧化鉿-氧化鋯材料中。The appropriate molar ratio of hafnium oxide to zirconium oxide can be produced by several methods, including introducing a hafnium-containing precursor during some of these cycles, and a zirconium-containing precursor during other cycles. The cycles can be alternated, combined, or arranged in any other suitable order to produce the overall desired molar ratio, as both intimately mixed materials and nanolaminates exhibit desirable ferroelectric properties. It should be noted that other elements can be added to the hafnium oxide-zirconia material by adding appropriate precursors together with the hafnium and zirconium precursors, or in separate cycles.

其上以該固有鐵電材料形成為層300的基材502可包括任何合適的材料,其包括半導體材料如矽、鍺、III-V族材料、過渡金屬二硫屬化物和其混合物、金屬及導電性陶瓷如氮化鈦、鈦、鉭、氮化鉭、鎢、鉑、銠、鉬、鈷、釕、鈀或其混合物;或介電質如氧化矽、氮化矽、氧化鋁、氧化鈦、其他鐵電材料,其包括氧化鉿和氧化鋯的組合物、磁性材料及其混合物或堆疊。The substrate 502 on which the intrinsic ferroelectric material is formed as layer 300 may comprise any suitable material, including semiconductor materials such as silicon, germanium, III-V materials, transition metal dichalcogenides and mixtures thereof, metals, and Conductive ceramics such as titanium nitride, titanium, tantalum, tantalum nitride, tungsten, platinum, rhodium, molybdenum, cobalt, ruthenium, palladium or their mixtures; or dielectrics such as silicon oxide, silicon nitride, aluminum oxide, titanium oxide , Other ferroelectric materials including hafnium oxide and zirconium oxide compositions, magnetic materials and mixtures or stacks thereof.

視需要地,基材302可以適當地用任何合適的形貌圖案化或織構化,該形貌包括平坦表面、溝槽、通孔或奈米結構化表面。此列表代表可用於鐵電應用的典型基材,但不應被視為限制,因為許多其他合適的組合物及表面圖案對於本領域之習知技藝者來說是顯而易見的。關此,已知該基材會對形成於其上的膜的原子排列及相產生一定的影響,其包括影響該膜的結晶取向及結晶溫度。不管該特定基材及此效應的程度如何,本文所述並沉積於此基材上的固有鐵電材料仍然使其體積的實質部分處於原沉積態鐵電相。Substrate 302 may be suitably patterned or textured with any suitable topography, including planar surfaces, grooves, vias, or nanostructured surfaces, as desired. This list represents typical substrates that can be used in ferroelectric applications, but should not be considered limiting, as many other suitable compositions and surface patterns will be apparent to those skilled in the art. In this regard, the substrate is known to have certain effects on the atomic arrangement and phase of the film formed thereon, including affecting the crystallographic orientation and crystallization temperature of the film. Regardless of the particular substrate and the extent of this effect, the intrinsic ferroelectric materials described herein and deposited on such substrates still have a substantial portion of their volume in the as-deposited ferroelectric phase.

圖3A舉例說明製備及沉積本文所述的固有鐵電材料之製程的另一具體實例。在本具體實例中,將混合氧化鉿和氧化鋯的固有鐵電材料以厚度約8.4 nm的層501的方式製備並且沉積於PVD TiN (其與該鐵電材料直接接觸)、熱生長的SiO 2層及矽晶圓的堆疊基材302上。501層在沒有進一步熱處理或護面的情況下形成。在本具體實例中,該氧化鉿與氧化鋯的莫耳比為約1:1,誤差範圍為約10%。該鐵電材料藉由交替第一循環303 (其包括步驟(i) 脈衝(MeCp) 2Zr(OMe)Me 304、(ii) 吹掃、(iii) 脈衝臭氧305及(iv) 吹掃)及第二循環306 (其包括步驟(i) 脈衝(MeCp) 2Hf(OMe)Me 307、(ii) 吹掃、(iii) 脈衝臭氧308及(iv) 吹掃),藉由ALD將該鐵電材料從該蒸氣製備並且沉積為層501。 Figure 3A illustrates another embodiment of a process for fabricating and depositing the intrinsic ferroelectric materials described herein. In this particular example, an intrinsic ferroelectric material of mixed hafnium oxide and zirconium oxide was prepared as a layer 501 with a thickness of about 8.4 nm and deposited on PVD TiN (which was in direct contact with the ferroelectric material), thermally grown SiO2 layers and silicon wafers on the stacked substrate 302 . The 501 layer was formed without further heat treatment or face protection. In this specific example, the molar ratio of hafnium oxide to zirconium oxide is about 1:1, and the error range is about 10%. The ferroelectric material is obtained by alternating the first cycle 303 (which includes the steps of (i) pulse (MeCp) 2 Zr(OMe)Me 304, (ii) purge, (iii) pulse ozone 305 and (iv) purge) and In the second cycle 306 (which includes the steps of (i) pulse (MeCp) 2 Hf(OMe)Me 307, (ii) purge, (iii) pulse ozone 308 and (iv) purge), the ferroelectric Materials are prepared from this vapor and deposited as layer 501 .

本領域之習知技藝者將認知到其他前驅物,例如 (MeCp) 2HfMe 2和(MeCp) 2ZrMe 2及其他反應物,例如水、過氧化氫或氧電漿也可又或者交替地使用。本領域之習知技藝者將進一步認知到該脈衝及吹掃時間可分別根據設備而變化。在一具體實例中,脈衝持續約2至約3秒,緊接著約10秒的吹掃。在另一具體實例中,脈衝持續約10秒至約15秒,緊接著約30秒至約60秒的吹掃。在另一具體實例中,該前驅物的沉積順序可以顛倒。 Those skilled in the art will recognize that other precursors such as (MeCp) 2HfMe2 and (MeCp) 2ZrMe2 and other reactants such as water, hydrogen peroxide or oxygen plasma can also or alternatively be used . Those skilled in the art will further recognize that the pulse and purge times, respectively, can vary from device to device. In a specific example, the pulse lasts from about 2 to about 3 seconds, followed by a purge of about 10 seconds. In another specific example, the pulse lasts from about 10 seconds to about 15 seconds, followed by a purge of about 30 seconds to about 60 seconds. In another embodiment, the order of deposition of the precursors may be reversed.

圖3B舉例說明於包含底部電極(TiN)、熱SiO 2及p型Si的堆疊502上之包含固有鐵電性ZrO 2HfO 2的層501的具體實例。 Figure 3B illustrates a specific example of a layer 501 comprising intrinsic ferroelectric ZrO2HfO2 on a stack 502 comprising a bottom electrode (TiN), thermal SiO2 and p-type Si.

圖3C舉例說明提供基材3002,提供底部電極3004,將該底部電極暴露於Hf及/或Zr前驅物3006,將該底部電極暴露於反應氣體3008,重複3009步驟3006及3008以達成所需厚度3010,提供頂部電極3012,及執行退火步驟3014之製程。在較佳具體實例中,所有步驟3002至3014皆於低於攝氏400度的溫度下執行。3C illustrates providing a substrate 3002, providing a bottom electrode 3004, exposing the bottom electrode to Hf and/or Zr precursors 3006, exposing the bottom electrode to a reactive gas 3008, repeating 3009 steps 3006 and 3008 to achieve the desired thickness 3010, providing the top electrode 3012, and performing the process of the annealing step 3014. In a preferred embodiment, all steps 3002 to 3014 are performed at a temperature below 400 degrees Celsius.

圖4A舉例說明用以測量HZO薄膜性質的金屬-鐵電-金屬(MFM)電容器的示意圖。圖4B舉例說明內部試驗載具上的亞微米標度FTJ裝置之示意圖。為了確認該HZO薄膜的鐵電性開關,製造大面積金屬-鐵電-金屬(MFM)電容器(圖4A)。然後,為了將該HZO薄膜整合於FTJ堆疊中並且確認有效且可靠的記憶體開關,於具有不同嵌入式多晶矽串聯電阻器的內部試驗載具上形成亞微米標度FTJ。圖4B顯示整合之後的FTJ裝置的示意圖。在此作業中,在FTJ裝置的電氣特性分析期間使用20 kΩ串聯電阻器以避免可能發生該介電質擊穿的機會。請注意,頃於MFM電容器及FTJ裝置中使用相同的裝置堆疊以於不同裝置之間保持一致性。FIG. 4A illustrates a schematic diagram of a metal-ferroelectric-metal (MFM) capacitor used to measure properties of HZO thin films. Figure 4B illustrates a schematic diagram of a submicron scale FTJ device on an internal test mount. To confirm the ferroelectric switching of this HZO thin film, a large-area metal-ferroelectric-metal (MFM) capacitor was fabricated (Fig. 4A). Then, to integrate this HZO thin film in the FTJ stack and confirm efficient and reliable memory switching, sub-micron scale FTJs were formed on internal test mounts with different embedded polysilicon series resistors. Figure 4B shows a schematic diagram of the FTJ device after integration. In this assignment, a 20 kΩ series resistor was used during the electrical characterization of the FTJ device to avoid the chance that this dielectric breakdown could occur. Note that the same device stack is used in both the MFM capacitor and the FTJ device to maintain consistency between different devices.

對於簡單的大型(約200 μm 直徑) MFM堆疊製造,最初我們使用PVD製程沉積厚W層(50 nm)作為該底部電極(BE)。然後,藉由ALD來沉積該HZO膜(約4.5 nm)。緊接著該頂部電極(TE)沉積(藉由PVD​​沉積的50 nm TiN),於N 2中在400 °C下進行2分鐘PMA,該TE及SF6/Ar蝕刻的圖案化。這些簡單的大型MFM堆疊用於測量該膜的FE極化特徵,因為測量極化需要測量位移電流(displacement current),對於大多數常見的高k介電質而言,該位移電流接近儀器本底噪聲(instrument noise floor),這對於較小面積(<1 μm 2)裝置而言並不相同。另一方面,大型裝置的洩漏電流也夠高而可滿足靈敏測量的要求。為了整合該亞微米FTJ裝置,選擇HZO FE薄膜以提高電流密度而可於低電壓下執行脈衝寫入及讀取操作。膜沉積於直徑300 nm的鎢插塞埋於SiO 2中之內部試驗載具上。該製程從ALD HZO沉積(約4.5 nm)開始,緊接著藉由PVD​​進行50 nm TiN TE沉積,在N 2中於400°C下進行2分鐘PMA,TE的圖案化及最終的SF 6/Ar蝕刻以界定該TE區域,類似於該MFM製程流程。 For simple large (~200 μm diameter) MFM stack fabrication, initially we deposited a thick W layer (50 nm) as the bottom electrode (BE) using a PVD process. Then, the HZO film (about 4.5 nm) was deposited by ALD. Following the top electrode (TE) deposition (50 nm TiN deposited by PVD), PMA, patterning of the TE and SF6/Ar etch were performed in N2 at 400 °C for 2 min. These simple large MFM stacks are used to measure the FE polarization characteristics of this film, since measuring polarization requires measuring the displacement current, which is close to the instrument background for most common high-k dielectrics Instrument noise floor, which is not the same for smaller area (<1 μm 2 ) devices. On the other hand, the leakage current of large devices is high enough to meet the requirements of sensitive measurements. In order to integrate the sub-micron FTJ device, the HZO FE film was selected to increase the current density to perform pulsed write and read operations at low voltage. Films were deposited on internal test mounts with 300 nm diameter tungsten plugs buried in SiO2 . The process starts with ALD HZO deposition (about 4.5 nm), followed by 50 nm TiN TE deposition by PVD, 2 min PMA at 400°C in N 2 , patterning of TE and finally SF 6 /Ar Etching to define the TE region is similar to the MFM process flow.

圖5C舉例說明該固有鐵電材料(於400C下在N 2中進行2分鐘PMA之後的薄HZO)的掠角入射XRD圖譜。W和WO 3峰皆可見。該圖5C的插圖部分顯示HZO存在的高非單斜晶相並且沒有單斜晶峰。如圖5C所示,構成層501的材料的結晶峰顯示低單斜晶組分及高非單斜晶組分。藉由用McBriarty等人,https://onlinelibrary.wiley.com/doi/full/10.1002/pssb.201900285,描述的技術擬合該峰並且使用該峰面積,構成層501的材料的體積之計算單斜晶分率小於25%,其係單斜晶、非鐵電材料的較佳最大體積分率。我們可從該BE觀察到非常尖銳的金屬W峰。然而,除了該金屬W峰外,我們也觀察到WO x的主峰(prominent peak),其證實了EELS光譜的發現。仔細檢查(插圖5C)該HZO峰顯示大部分為非單斜晶晶粒,間接表明為斜方晶(鐵電)相或四方晶(反鐵電)相。沒有察覺到與少量熱力學安定的單斜晶相相關的小峰。這些XRD結果間接表明使用先進茂金屬型前驅物的ALD HZO薄膜生長考慮到適用於不同非揮發性記憶體及神經形態計算應用的BEOL相容性製程。 Figure 5C illustrates the grazing incidence XRD pattern of this intrinsic ferroelectric material (thin HZO after 2 min PMA in N2 at 400C). Both W and WO 3 peaks are visible. The inset portion of this Figure 5C shows the presence of a highly non-monoclinic phase of HZO and the absence of a monoclinic peak. As shown in FIG. 5C , the crystallization peaks of the material constituting layer 501 show a low monoclinic composition and a high non-monoclinic composition. By fitting the peak with the technique described by McBriarty et al., https://onlinelibrary.wiley.com/doi/full/10.1002/pssb.201900285, and using the peak area, the volume of the material making up layer 501 was calculated. The oblique crystal fraction is less than 25%, which is the preferred maximum volume fraction of monoclinic and non-ferroelectric materials. We can observe a very sharp metallic W peak from this BE. However, in addition to this metallic W peak, we also observed a prominent peak of WO x , which confirmed the findings of the EELS spectra. Careful inspection (Inset 5C) of this HZO peak reveals mostly non-monoclinic grains, indirectly suggesting an orthorhombic (ferroelectric) or tetragonal (antiferroelectric) phase. No small peak associated with a small amount of thermodynamically stable monoclinic phase was detected. These XRD results indirectly suggest that ALD HZO film growth using advanced metallocene-type precursors allows for a BEOL-compatible process suitable for different non-volatile memory and neuromorphic computing applications.

在某些具體實例中,該FTJ可併入交錯式陣列或記憶體單位晶胞中。在某些具體實例中,該FTJ可併入神經形態運算晶片或突觸裝置例如突觸憶阻器或突觸電晶體中。In some embodiments, the FTJs can be incorporated into interleaved arrays or memory unit cells. In some embodiments, the FTJ can be incorporated into a neuromorphic computing chip or a synaptic device such as a synaptic memristor or a synaptic transistor.

使用ALD製備並沉積本文所述的固有鐵電材料的製程之具體實例。該方法包括可藉著附加及/或視需要的步驟來擴充的幾個步驟。步驟1包括於介於約265°C與約500°C之間的沉積溫度下提供基材,但是較佳為處於約300°C或約300°C左右(例如,高於約285°C並且處於或低於約300°C)並且低於340°C。步驟2包括(i) 將該基材暴露於於該沉積溫度下不會分解的含有鉿或鋯或鉿和鋯兩者之第一前驅物,及(ii) 吹掃。步驟3包括(i) 將該基材暴露於含氧的反應氣體,及(ii) 吹掃。步驟4包括(i) 將該基材暴露於於該沉積溫度下不會分解的含鋯或鉿或鉿和鋯兩者的第二前驅物,及(ii) 吹掃。步驟5包括將該基材暴露於含氧的反應氣體。視需要的步驟6包括重複步驟2至5直到形成具有介於約1:3與約3:1之間的莫耳比之期望厚度的氧化鉿和氧化鋯膜為止。A specific example of a process using ALD to fabricate and deposit the intrinsic ferroelectric materials described herein. The method includes several steps that can be extended with additional and/or optional steps. Step 1 involves providing the substrate at a deposition temperature between about 265°C and about 500°C, but preferably at or around 300°C (e.g., above about 285°C and At or below about 300°C) and below 340°C. Step 2 comprises (i) exposing the substrate to a first precursor containing hafnium or zirconium or both hafnium and zirconium that does not decompose at the deposition temperature, and (ii) purging. Step 3 includes (i) exposing the substrate to an oxygen-containing reactive gas, and (ii) purging. Step 4 includes (i) exposing the substrate to a second precursor containing zirconium or hafnium or both hafnium and zirconium that does not decompose at the deposition temperature, and (ii) purging. Step 5 includes exposing the substrate to an oxygen-containing reactive gas. Optional step 6 includes repeating steps 2 to 5 until a hafnium oxide and zirconium oxide film of desired thickness with a molar ratio between about 1:3 and about 3:1 is formed.

在本揭示內容之製程中,該固有鐵電材料係形成並沉積為具有原沉積態(即,無需進一步退火及/或護面)並且藉由相測定技術或本領域之習知技藝者已知的電氣測試(例如,XRD、XAS、TEM、極化電壓測試、壓電顯微術或其組合)測量為實質體積分率的鐵電相的膜。在圖6的製程中使用及/或可使用的茂金屬前驅物包括上文揭示並討論的所有那些,特別包括(MeCp) 2Zr(OMe)Me、 (MeCp) 2Hf(OMe)Me、(MeCp) 2Zr(Me) 2及(MeCp) 2Hf(Me) 2。步驟3及/或步驟5的含氧反應氣體較佳為臭氧。本領域之習知技藝者將認知到其他反應氣體皆可使用,包括上文具體描述的那些(例如,水、過氧化氫)。 實施例 In the processes of the present disclosure, the intrinsic ferroelectric material is formed and deposited in an as-deposited state (i.e., without further annealing and/or masking) and is known by phase determination techniques or by those skilled in the art. Electrical testing (eg, XRD, XAS, TEM, polarization voltage testing, piezoelectric microscopy, or a combination thereof) of the film measures a substantial volume fraction of the ferroelectric phase. Metallocene precursors used and/or usable in the process of FIG. 6 include all of those disclosed and discussed above, including (MeCp) 2 Zr(OMe)Me, (MeCp) 2 Hf(OMe)Me, (MeCp) 2 Zr(OMe)Me, ( MeCp) 2 Zr(Me) 2 and (MeCp) 2 Hf(Me) 2 . The oxygen-containing reaction gas in step 3 and/or step 5 is preferably ozone. Those skilled in the art will recognize that other reactive gases may be used, including those specifically described above (eg, water, hydrogen peroxide). Example

現在將參考本揭示內容的更具體的具體實例及為此具體實例提供支持的實驗結果。下文提供的實施例是為了更充分地舉例說明該揭示標的並且不應被解釋為以任何方式限制該揭示標的。 HZO膜生長 Reference will now be made to a more specific embodiment of the present disclosure and to experimental results in support of this embodiment. The examples provided below are to more fully illustrate the disclosed subject matter and should not be construed as limiting the disclosed subject matter in any way. HZO film growth

該FE HZO膜藉由包含一個HZO超循環(supercycle)的原子層沉積於355°C下生長,暴露順序為HfD-04 (雙(甲基環戊二烯基)甲氧基甲基-鉿)/臭氧/ZrD-04 (雙(甲基環戊二烯基)甲基-甲氧化鋯)/臭氧。Hf-D04及Zr-D04皆為EMD Electronics的專利化學品。圖1顯示與醯胺型前驅物相比,此二環戊二烯基前驅物具有於更高(300°C至400°C)溫度下的ALD區間,其允許使用較低溫度的PMA製程以獲得期望的HZO晶粒。我們已經針對二不同臭氧濃度(4%及20%)沉積該膜,據發現其會產生不同的鐵電性質。HfD-04及ZrD-04前驅物在沉積期間分別保持於125°C及70°C的安瓿溫度下。不同的臭氧濃度會產生略微不同的生長速率(4%臭氧具有每週期略少的生長量)。 裝置製造 The FE HZO film was grown at 355°C by atomic layer deposition involving a HZO supercycle with the exposure sequence of HfD-04 (bis(methylcyclopentadienyl)methoxymethyl-hafnium) /Ozone/ZrD-04 (Bis(methylcyclopentadienyl)methyl-zirconium methoxide)/Ozone. Both Hf-D04 and Zr-D04 are proprietary chemicals of EMD Electronics. Figure 1 shows that this dicyclopentadienyl precursor has an ALD interval at a higher temperature (300°C to 400°C) than the amide-type precursor, which allows the use of a lower temperature PMA process to Obtain desired HZO grains. We have deposited this film for two different ozone concentrations (4% and 20%), which were found to result in different ferroelectric properties. The HfD-04 and ZrD-04 precursors were maintained at ampoule temperatures of 125°C and 70°C, respectively, during deposition. Different ozone concentrations produced slightly different growth rates (4% ozone had slightly less growth per cycle). Device manufacturing

對於簡單的金屬-FE-金屬(MFM)堆疊製造,我們使用PVD​​製程沉積W (50nm)作為該底部電極(BE)。然後,該HZO膜係藉由ALD於攝氏325度的溫度下沉積。在此之後緊接著頂部電極(TE) (藉由PVD​​沉積的20 nm TiN或W),在N 2環境中從400至600C經過2分鐘PMA,緊接著TE及SF 6蝕刻的圖案化。 For simple metal-FE-metal (MFM) stack fabrication, we deposited W (50nm) as the bottom electrode (BE) using a PVD process. Then, the HZO film was deposited by ALD at a temperature of 325 degrees Celsius. This was followed by patterning of the top electrode (TE) (20 nm TiN or W deposited by PVD), PMA from 400 to 600 C for 2 min in N2 ambient, followed by TE and SF6 etch.

對於該標度裝置,將膜沉積於具有埋於SiO 2中的300 nm直徑的鎢插塞之預先製造的試驗載具上(圖6B)。該製程從ALD HZO沉積開始,緊接著藉由PVD​​進行TE沉積(50 nm TiN),在N 2環境中於400°C下進行2分鐘PMA,光刻以界定TE區域及最終的SF 6蝕刻。 HZO膜的物理特性分析 大面積FTJ裝置 For this scaled device, films were deposited on prefabricated test mounts with 300 nm diameter tungsten plugs buried in SiO2 (FIG. 6B). The process starts with ALD HZO deposition, followed by TE deposition (50 nm TiN) by PVD, 2 min PMA at 400°C in N2 environment, photolithography to define TE areas and final SF6 etch. Analysis of Physical Properties of HZO Films in Large Area FTJ Devices

圖5A至5B舉例說明本揭示內容的HZO FTJ堆疊的具體實例。圖5A係W(50nm)/HZO(4.5nm)/TiN(50nm)在N 2中於400 °C退火2分鐘之後的橫截面TEM圖像。圖5B係橫過該橫截面的EELS製圖。該底部界面層(IL)顯示形成了WO x5A-5B illustrate specific examples of HZO FTJ stacks of the present disclosure. Figure 5A is a cross-sectional TEM image of W(50nm)/HZO(4.5nm)/TiN(50nm) annealed in N2 at 400 °C for 2 minutes. Figure 5B is an EELS drawing across the cross-section. The bottom interfacial layer (IL) shows the formation of WO x .

該底部(第一)電極及該頂部(第二)電極可為具有確保良好傳導的厚度之金屬或半導體電極。在該例示具體實例中,該頂部電極包含氮化鈦。在其他具體實例中,該頂部電極可包含氮化鈦、鎢、鎳、釕、鉑及鋁中的任何一者。在例示具體實例中,使用50nm厚的TiN。The bottom (first) electrode and the top (second) electrode may be metal or semiconductor electrodes of a thickness ensuring good conduction. In the illustrated embodiment, the top electrode comprises titanium nitride. In other embodiments, the top electrode may comprise any one of titanium nitride, tungsten, nickel, ruthenium, platinum, and aluminum. In the illustrated specific example, 50 nm thick TiN was used.

在該例示具體實例中,該底部電極包含鎢。在其他具體實例中,該頂部電極可包含氮化鈦、鎢、釕、鉑及鋁中的任何一者。在該例示具體實例中,使用50nm厚的W。In the illustrated embodiment, the bottom electrode comprises tungsten. In other embodiments, the top electrode may comprise any one of titanium nitride, tungsten, ruthenium, platinum, and aluminum. In this illustrated embodiment, a 50 nm thick W is used.

在該HZO沉積期間、之前或之後產生該界面層。該W底部電極的氧化產生包含WO x的界面層。在一具體實例中,該界面層包含WO 3並且氧電漿脈衝步驟發生於該鐵電材料的沉積之前。該氧電漿脈衝步驟包含元素氧(O)、分子氧(O 2)及臭氧(O 3)。 The interfacial layer is created during, before or after the HZO deposition. Oxidation of the W bottom electrode produces an interfacial layer comprising WOx . In one embodiment, the interfacial layer comprises WO 3 and the oxygen plasma pulsing step occurs prior to deposition of the ferroelectric material. The oxygen plasma pulsing step includes elemental oxygen (O), molecular oxygen ( O2 ) and ozone ( O3 ).

該EELS也顯示Hf與Zr之間的比率接近1:1。為了確認該HZO膜的結晶度,對同一樣品進行XRD分析。圖5C顯示該HZO薄膜的XRD圖案。我們可從該BE觀察到非常尖銳的金屬W峰。然而,除了該金屬W峰外,我們也觀察到WOx的主峰,其證實了該EELS光譜的發現。更仔細檢查(插圖5C)該HZO峰顯示大多為非單斜晶晶粒,間接表明為斜方晶(鐵電)相或四方晶(反鐵電)相。沒有發現與少量熱力學穩定單斜晶相相關的小峰。This EELS also shows that the ratio between Hf and Zr is close to 1:1. In order to confirm the crystallinity of this HZO film, XRD analysis was performed on the same sample. Figure 5C shows the XRD pattern of the HZO thin film. We can observe a very sharp metallic W peak from this BE. However, in addition to this metallic W peak, we also observed the main peak of WOx, which confirmed the findings of this EELS spectrum. Closer inspection (Inset 5C) of the HZO peak reveals mostly non-monoclinic grains, indirectly suggesting an orthorhombic (ferroelectric) or tetragonal (antiferroelectric) phase. No small peak associated with a small amount of thermodynamically stable monoclinic phase was found.

該鐵電層包含Hf xZr 1-xO 2。在替代具體實例中,該鐵電層可包含摻雜有La、Y、Gd、Sr或其組合的HfO 2The ferroelectric layer contains Hf x Zr 1-x O 2 . In alternative embodiments, the ferroelectric layer may comprise HfO2 doped with La, Y, Gd, Sr or combinations thereof.

在該例示具體實例中,於攝氏400度下執行2分鐘的後金屬退火(PMA)。In the illustrated embodiment, a post metal anneal (PMA) is performed at 400 degrees Celsius for 2 minutes.

圖6A舉例說明如使用鐵電測試儀測量的,在圖4A所例示的製程中形成並沈積的固有鐵電材料之極化-電場圖。為了表徵該材料的基本鐵電性質,我們運用頻率為10 KHz的典型雙重雙極三角脈衝序列進行極化對電場(P-E)的測量。圖5顯示新裝置及喚醒應力之後的P-E特性(±1.5V,1ms脈衝寬度,103個週期)。新裝置顯示接近30 µC/cm 2的2Pr區間。經過溫和的喚醒製程之後,該2Pr區間改善到達於40 µC/cm 2。這些結果確認使用先進茂金屬前驅物(HfD-04/ZrD-04)可實現鐵電性薄HZO (< 5 nm)的BEOL相容性整合而無需於使用醯胺系前驅物例如TEMA-Hf/​​TEMA-Zr時所需之更高溫度 (>= 500 °C)下的PMA。 6A illustrates a polarization-electric field diagram of an intrinsic ferroelectric material formed and deposited in the process illustrated in FIG. 4A, as measured using a ferroelectric tester. In order to characterize the fundamental ferroelectric properties of this material, we performed polarization pair electric field (PE) measurements using a typical double bipolar triangular pulse sequence at a frequency of 10 KHz. Figure 5 shows the PE characteristics of the new device and after wake-up stress (±1.5V, 1ms pulse width, 103 cycles). The new device shows a 2Pr interval close to 30 µC/cm 2 . After a mild wake-up process, the 2Pr range was improved to 40 µC/cm 2 . These results confirm that the BEOL-compatible integration of ferroelectric thin HZO (<5 nm) can be achieved using advanced metallocene precursors (HfD-04/ZrD-04) without the need for amide-based precursors such as TEMA-Hf/ZrD-04. PMA at higher temperatures (>= 500 °C) required for TEMA-Zr.

請注意該P-E迴路在x軸上不對稱。這是由於分別在該底部及頂部界面處的界面WOx及不同金屬(W及TiN)的原位生長所產生之堆疊的不對稱特性。Note that the P-E loop is not symmetrical on the x-axis. This is due to the asymmetric nature of the stack created by the in situ growth of the interfaces WOx and dissimilar metals (W and TiN) at the bottom and top interfaces, respectively.

圖6B舉例說明在喚醒應力前後的標度裝置的電流-電壓DC掃描。圖6顯示圖4B中所示的標度FTJ裝置(300 nm鎢插塞直徑尺寸)的電流-電壓(I-V)特徵。該裝置對於高達3V的DC掃描最初顯示非常小的記憶體區間。然而,在喚醒循環(±4.2V,1μs脈衝寬度(PW)持續103個循環)之後,該記憶體區間在低於1V的低電場區中顯著打開高達10倍。該開關操作可重複並且不包括在阻絲型RRAM開關中通常可見的電流的任何突然變化。這間接表明該電流磁滯係由於鐵電材料的極化開關(polarization switching)。Figure 6B illustrates current-voltage DC sweeps of the scaled device before and after wake-up stress. Figure 6 shows the current-voltage (I-V) characteristics of the scaled FTJ device (300 nm tungsten plug diameter size) shown in Figure 4B. The device initially showed very small memory bins for DC sweeps up to 3V. However, after a wake-up cycle (±4.2V, 1μs pulse width (PW) for 103 cycles), this memory region opens significantly up to 10 times in the low electric field region below 1V. This switching operation is repeatable and does not include any sudden changes in current typically seen in resistive wire RRAM switches. This indirectly indicates that the current hysteresis is due to the polarization switching of the ferroelectric material.

圖7A舉例說明該標度裝置的電阻與程式化電壓的關係並且顯示一個FTJ裝置經過20個週期的R-V特徵,其中對於可變程式電壓(V prog)下的程式脈衝(program pulse)及於固定讀取電壓V read=1.5V下的讀取脈衝(read pulse),該PW保持於100μs。從該R-V特徵(圖7A),我們觀察到該低電阻狀態(LRS)及高電阻狀態(HRS)分佈在20個週期內保持緊密分佈,具有約3倍記憶體區間(HRS和LRS的周期間變異性(σ R/R)分別為6.6%及5.9%)。再者,該電阻區間可藉由改變該寫入脈衝寬度來調節,如圖7(b)所示。圖7B舉例說明針對不同寫入脈衝寬度的標度裝置之電阻與程式化電壓的關係。這些結果間接表明該電阻區間可從1μs脈衝的約1.3倍調節至1000μs脈衝的約5倍。該R-V區間對脈衝寬度的相依性係由於接觸處的不完全極化電荷屏蔽導致的去極化場(depolarizing field)。這與RRAM中的阻絲型擊穿形成對比,其中該HRS能階由阻絲斷裂之後形成的穿隧阻障支配,因而對該脈衝寬度的相依性較小。我們也觀察到隨著該電壓振幅的變化,該電阻開關是相當緩慢的。這間接表明可藉由脈衝寬度及脈衝振幅獨立地調節的局部FE域開關。圖7C顯示4不同裝置的R-V特徵。該圖形表示低的裝置間差異並且顯示整個樣品的膜性質均勻性。使用不同的脈衝振幅,我們展示了4不同裝置的4穩定能階之間的漸進電阻開關(圖7D)。觀察到所有4狀態的緊密分佈,確認了該膜的均勻性及該製程的可重複性。 Figure 7A illustrates the resistance of the scaling device versus programming voltage and shows the RV characteristics of an FTJ device over 20 cycles for a program pulse at a variable programming voltage (V prog ) and at a fixed For a read pulse (read pulse) at a read voltage V read =1.5V, the PW is maintained for 100 μs. From the RV signature (FIG. 7A), we observed that the low-resistance state (LRS) and high-resistance state (HRS) distribution remained tightly distributed over 20 cycles, with about 3 times the memory interval (cycle period of HRS and LRS The variability (σ R /R) was 6.6% and 5.9%, respectively). Furthermore, the resistance range can be adjusted by changing the writing pulse width, as shown in FIG. 7( b ). Figure 7B illustrates the resistance of the scaling device versus programming voltage for different write pulse widths. These results indirectly suggest that this resistance interval can be tuned from about 1.3 times that of a 1 μs pulse to about 5 times that of a 1000 μs pulse. The dependence of this RV interval on pulse width is due to the depolarizing field due to incomplete polarizing charge screening at the contact. This is in contrast to wire-type breakdown in RRAM, where the HRS energy level is dominated by the tunneling barrier formed after the wire breaks and is thus less dependent on the pulse width. We also observed that the resistive switching was rather slow as the voltage amplitude varied. This indirectly suggests localized FE-domain switching that can be independently tuned by pulse width and pulse amplitude. Figure 7C shows the RV characteristics of 4 different devices. The graph represents low device-to-device variation and shows uniformity of film properties across the sample. Using different pulse amplitudes, we demonstrate progressive resistive switching between 4 stable energy levels of 4 different devices (Fig. 7D). A tight distribution of all 4 states was observed, confirming the uniformity of the film and the repeatability of the process.

記憶體內運算架構所需的類比開關行為係藉由用脈衝序列開關該FTJ展示,其中該電阻/導電度在高於2倍的範圍內逐漸變化。為了保持高線性度,我們選擇了提高脈衝振幅的脈衝序列,保持脈衝寬度恆定。圖8A顯示15個關於提高振幅的脈衝序列(-2V至-4V用於-50 mV步進的增強(potentiation),+2.2V至+4.2V用於50mV步進的減弱(depression),及+1.5V用於100μs PW的讀取電壓)之循環的增強及減弱曲線(置位及復位脈衝(set and reset pulse)期間的導電度與脈衝數的關係)。為了計算該類比開關的線性度及可重複性,15個輸入脈衝序列循環的增強及減弱曲線藉著圖示的中間響應相互疊加(圖8B)。我們用圖8C報告的模型擬合該中值曲線並且提取該非線性度(NL)度量測值。我們報告減弱的NL值為0.62,增強的NL值為2.0,與最近發表於文獻中的作品相比,這是FTJ報告的最佳值之一。類似地,我們已經針對具有恆定脈衝振幅及寬度的脈衝序列對該裝置進行測試(圖8D至8F)。圖8E顯示由圖8D產生的疊加響應,圖8F顯示NL度量測值的提取。在恆定脈衝測試的案例中,我們使用-3.3 V/100 µs進行增強並且使用+3.6 V/100 µs進行減弱。恆定脈衝振幅會導致更高的非線性度,這可能不適合記憶體內運算應用。儘管如此,其仍然可採能使位元/晶胞記憶體密度提高的多階數位記憶體的方式開關。The analog switching behavior required for in-memory computing architectures was demonstrated by switching the FTJ with a pulse train in which the resistance/conductivity was varied gradually over a factor of more than 2. To maintain high linearity, we chose a pulse sequence with increased pulse amplitude, keeping the pulse width constant. Figure 8A shows 15 pulse trains for increasing amplitudes (-2V to -4V for potentiation in -50 mV steps, +2.2V to +4.2V for depression in 50mV steps, and + 1.5V for a read voltage of 100μs PW) cycle ramp-up and ramp-down curves (conductivity during set and reset pulses vs. pulse number). In order to calculate the linearity and repeatability of the analog switch, the boost and decay curves of 15 cycles of the input pulse train were superimposed on each other with the intermediate response shown (FIG. 8B). We fit the median curve with the model reported in Figure 8C and extracted the nonlinearity (NL) metric measurements. We report NL values of 0.62 for attenuation and 2.0 for augmentation, which are among the best values reported by FTJ compared to recent works published in the literature. Similarly, we have tested this device for pulse sequences with constant pulse amplitude and width (Figures 8D to 8F). Figure 8E shows the superimposed response resulting from Figure 8D, and Figure 8F shows the extraction of NL metric measurements. In the case of the constant pulse test we used -3.3 V/100 µs for boost and +3.6 V/100 µs for cut. Constant pulse amplitude results in higher nonlinearity, which may not be suitable for in-memory computing applications. Nevertheless, it can still be switched in the form of multi-level digital memory which enables increased bit/cell memory density.

圖8A至8F舉例說明隨脈衝數變化的導電度,其舉例說明該標度裝置的4%臭氧的良好線性度。圖9舉例說明不同後金屬退火條件之後的電阻與電壓關係。圖10A至10B舉例說明於室溫下測量的多階狀態保持力隨時間的變化。Figures 8A to 8F illustrate conductivity as a function of pulse number, illustrating the good linearity of the scale device for 4% ozone. Figure 9 illustrates the resistance versus voltage relationship after different post-metal annealing conditions. Figures 10A-10B illustrate multi-stage state retention forces measured at room temperature as a function of time.

圖9顯示退火條件對該R-V區間的影響。在此圖形中,該二裝置的寫入PW皆保持於100μs。僅該退火的持續時間有變化,使該退火溫度保持恆定於400°C。再者,圖9顯示30分鐘的較長退火將該記憶體區間從3倍增加到5倍,這意味著較長的退火時間會產生更大的斜方晶相微晶。為了驗證我們的FTJ裝置的可靠性,我們也證實了該多階保持力及耐久性。在圖10A至10B中,我們顯示於室溫下測得10 3秒的多階保持力。請注意,為了程式編寫4種不同的電阻狀態,我們使用與圖7D相同的條件。LRS顯示該FE域略有鬆弛,間接表明不同狀態在較長時間之後可能重疊,但是穩定的2階保持力長達10年。圖11顯示在我們的亞微米級裝置上用單脈衝程式化技術及程式化之後讀取脈衝執行的10 3循環耐久性(程式編寫LRS狀態用-3.6V 100μs PW,程式編寫HRS狀態用3.9V 100μs PW,及讀取不同的狀態用1.5V 100μs PW)。二程式化狀態可用低可變性獲得穩定的約2倍記憶體區間。隨時間的保持力損失及有限的耐用性係關於FTJ裝置的文獻中觀察到的最大挑戰中之其二,通過界面工程優化該堆疊對於採用此技術使神經形態硬體能使用憶阻器來實現至關重要。 Figure 9 shows the effect of annealing conditions on this RV interval. In this graph, the write PW of both devices is held at 100 μs. Only the duration of the anneal was varied, keeping the anneal temperature constant at 400°C. Furthermore, Figure 9 shows that a longer anneal of 30 minutes increases the memory interval from 3-fold to 5-fold, which means that a longer anneal time produces larger orthorhombic phase crystallites. To verify the reliability of our FTJ device, we also demonstrated the multi-stage retention and durability. In Figures 10A to 10B we show a multi-step retention measured at room temperature for 10 3 s. Note that for programming the 4 different resistance states, we use the same conditions as in Figure 7D. LRS reveals a slight relaxation of this FE domain, indirectly suggesting that the different states may overlap after a longer time, but a stable 2-order retention for up to 10 years. Figure 11 shows the 10 3 cycle endurance of read pulse execution with single-pulse programming technique and post-programming on our sub-micron device (programmed LRS state with -3.6V 100μs PW, programmed HRS state with 3.9V 100μs PW, and read different states with 1.5V 100μs PW). The second stylized state can get stable about 2 times the memory range with low variability. Retention loss and limited durability over time are two of the biggest challenges observed in the literature on FTJ devices, and optimizing the stack through interface engineering is critical to the adoption of this technology to enable neuromorphic hardware using memristors. important.

本揭示內容的主要優點係沒有FTJ的電阻漂移的多階晶胞示範。圖10A及10B展示4階電阻開關,其中各電阻階保持穩定10^3秒。在FTJ中,由於該電偶極子弛豫,該電阻區間迅速塌陷,因此難以展示多重狀態。而且,多階開關取決於多重域的存在及其局部開關。A major advantage of the present disclosure is the multi-level cell demonstration without resistance drift of the FTJ. Figures 10A and 10B show 4-stage resistive switching, where each resistive stage remains stable for 10Λ3 seconds. In FTJs, due to the relaxation of the electric dipole, the resistance interval collapses rapidly, making it difficult to exhibit multiple states. Moreover, multilevel switching depends on the existence of multiple domains and their local switching.

本FTJ系統的優點係簡化的製程流程。該例示FTJ堆疊可在不沉積任何界面介電層的情況下製造,從而從該製程流程排除一個製程步驟。The advantage of this FTJ system is the simplified process flow. The exemplary FTJ stack can be fabricated without depositing any interfacial dielectric layer, thereby eliminating one process step from the process flow.

在本具體實例中,該界面層係於HZO沉積期間產生。該TiN電極的氧化產生包含TiO xN y的界面層。在該鐵電材料的沉積之前發生氧電漿脈衝步驟。該氧電漿脈衝步驟包含元素氧(O)、分子氧(O 2)及臭氧(O 3)。 In this embodiment, the interfacial layer is created during HZO deposition. Oxidation of the TiN electrode produces an interfacial layer comprising TiOxNy . An oxygen plasma pulsing step occurs prior to the deposition of the ferroelectric material. The oxygen plasma pulsing step includes elemental oxygen (O), molecular oxygen ( O2 ) and ozone ( O3 ).

本FTJ系統的另一優點係較低的總體熱預算。在其任何製程步驟中,在低於400C的溫度下製造晶片上後段製程(BEOL)相容性記憶體非常重要。典型的HZO膜由於低溫ALD製程而沉積為非晶態,於是該FE域需要高溫退火才能被活化。該例示製程利用高溫ALD前驅物使該膜具有原沉積態高鐵電性。通常,較佳的沉積溫度介於300°C至350°C之間,接著400°C退火便足以使其高度穩定。這使得該製程流程BEOL相容。Another advantage of the present FTJ system is the lower overall thermal budget. It is very important to fabricate on-wafer back-end-of-line (BEOL) compliant memory at temperatures below 400C in any of its process steps. Typical HZO films are deposited in an amorphous state due to low-temperature ALD processes, so the FE domains require high-temperature annealing to be activated. The exemplary process utilizes high temperature ALD precursors to impart high as-deposited ferroelectricity to the film. Typically, the preferred deposition temperature is between 300°C and 350°C, followed by annealing at 400°C is sufficient to make it highly stable. This makes the process flow BEOL compatible.

本FTJ系統的另一優點係更快的讀/寫操作。由於該FTJ依賴於穿隧電阻,因此與其他非揮發性記憶體技術(如ReRAM及PCM)相比,該裝置在其低電阻及高電阻狀態下皆具有高電阻。儘管從能量耗散的觀點來看這是合乎需要的,但是太高的電阻需要高電壓才能讀取,從而導致可靠性問題,並且較慢的脈衝會導致讀取及寫入速度過慢並更容易產生噪聲。由於我們不需要任何介電層來產生不對稱性,並且該膜具有高剩磁極化,因此該堆疊可設計為薄的並且仍然具有足以產生記憶體區間的FE偶極。這使得該例示FTJ堆疊在該鐵電材料的厚度及該裝置面積方面皆具有高度可擴展性。Another advantage of the present FTJ system is faster read/write operations. Because the FTJ relies on tunneling resistance, the device has high resistance in both its low and high resistance states compared to other non-volatile memory technologies such as ReRAM and PCM. While this is desirable from an energy dissipation standpoint, too high a resistance requires high voltages to read, causing reliability issues, and slower pulses result in slower and more read and write speeds. prone to noise. Since we don't need any dielectric layers to create the asymmetry, and the film has high remanent polarization, the stack can be designed to be thin and still have enough FE dipoles to create memory compartments. This makes the exemplary FTJ stack highly scalable both in terms of the thickness of the ferroelectric material and the device area.

下表舉例說明針對NamLab、IBM及Kioxia的標度裝置的FTJ基準參數。熱預算為攝氏400度;FE膜厚度為4.5 nm,面積為0.09 µm 2,開關比(on/off ratio)為約5.0,非線性度為+0.62/-2.29,RON為100 Mohms,讀取電壓為1.5 V,LRS電流密度為1.66x10 -3A/cm 2,並且多階保持力為4階(攝氏25度時為10 3秒)。 The table below illustrates the FTJ reference parameters for calibration devices from NamLab, IBM and Kioxia. The thermal budget is 400 degrees Celsius; the FE film thickness is 4.5 nm, the area is 0.09 µm 2 , the on/off ratio is about 5.0, the nonlinearity is +0.62/-2.29, the RON is 100 Mohms, and the reading voltage The current density of LRS is 1.5 V, the LRS current density is 1.66x10 -3 A/cm 2 , and the multi-step holding force is 4 steps (10 3 seconds at 25 degrees Celsius).

此應用演示用與BEOL相容的HZO製程條件製造的標度FTJ,該製程條件可利用高度可靠的裝置操作達到類比電阻值。此高性能裝置能藉由使用環戊二烯基前驅物的高溫ALD製程實現。This application demonstrates a scaled FTJ fabricated with BEOL compatible HZO process conditions that achieve analog resistance values with highly reliable device operation. This high-performance device can be achieved by a high-temperature ALD process using cyclopentadienyl precursors.

對本領域之習知技藝者顯而易見的是該揭示標的及本文提供的具體實施例可在不悖離該揭示標的的精神或範疇的情況下完成各種修飾及變化。因此,該揭示標的,包括由以下實施例提供的描述在內,意在涵蓋落入任何請求項及其等效物的範疇內之揭示標的的修飾及變化。It will be apparent to those skilled in the art that various modifications and changes can be made to the disclosed subject matter and the specific embodiments provided herein without departing from the spirit or scope of the disclosed subject matter. Accordingly, it is intended that the disclosed subject matter, including the description provided by the following examples, cover modifications and variations of the disclosed subject matter that fall within the scope of any claims and their equivalents.

材料及方法:Materials and methods:

該茂金屬前驅物可根據美國專利第8,568,530號製備或以其他方式製備,在此將該專利的全文併入本文。 表 KPI 目前的作品 NamLab Al 2O 3/HZO IBM WO x/HZO Kioxia SiO 2/HfSiO 熱預算[°C] 400 600 375 1000 FE膜厚度[nm] 4.5 12 4.9 4.5 裝置面積[µm 2] 0.09 31415 14400 0.09 開關比 ~5 ~10 ~7 ~2.5 非線性度* +2.0/-0.62 +0.85/-4.76 +1.9/-4.0 +2.2/-4.88 R ON[MΩ] 100 1000 100 150 讀取電壓[V] 1.5 2 0.3 3 開關速度[µs] 100 10-100 50 2 LRS讀取電流密度[A/cm 2] 1.66×10 -3 6.3×10 -10 8.3×10 -10 2.2×10 -3 多階保持力 4階(於室溫度下> 10 3秒) 4階(於室溫度下約10 3秒) 3階(於室溫度下約10 5秒) 沒報告 The metallocene precursor may be prepared according to US Patent No. 8,568,530 or otherwise prepared, the entirety of which is hereby incorporated herein. surface KPIs current works NamLab Al 2 O 3 /HZO IBM WO x /HZO Kioxia SiO 2 /HfSiO Thermal budget [°C] 400 600 375 1000 FE film thickness [nm] 4.5 12 4.9 4.5 Device area [µm 2 ] 0.09 31415 14400 0.09 Switch ratio ~5 ~10 ~7 ~2.5 Nonlinearity* +2.0/-0.62 +0.85/-4.76 +1.9/-4.0 +2.2/-4.88 R ON [MΩ] 100 1000 100 150 Read voltage [V] 1.5 2 0.3 3 Switching speed [µs] 100 10-100 50 2 LRS reading current density [A/cm 2 ] 1.66×10 -3 6.3× 10-10 8.3× 10-10 2.2×10 -3 multi-stage retention 4th stage (at room temperature > 10 3 seconds) 4th stage (about 10 3 seconds at room temperature) 3rd stage (about 10 5 seconds at room temperature) no report

儘管本發明已經以某種程度的特殊性進行描述及舉例說明,但是應當理解該揭示內容僅藉由示範方式完成,並且本領域之習知技藝者可在不悖離本發明的精神和範疇的情況下對條件及步驟順序採取多種改變。While the present invention has been described and illustrated with a certain degree of particularity, it should be understood that this disclosure is done by way of example only, and that those skilled in the art can make further modifications without departing from the spirit and scope of the invention. Various changes are made to the conditions and sequence of steps.

100,200a,200b,200c:鐵磁穿隧接面 102,202a,202b,202c:頂部電極 104,204a,204b,204c,300,501:鐵電材料層 106,206a,206b,206c:底部電極 108,302,502:基材 210a,210c:頂部界面層 220a,220b:底部界面層 301:蒸氣 303:第一循環 304:(MeCp) 2Zr(OMe)Me 305,308:臭氧 306:第二循環 307:(MeCp) 2Hf(OMe)Me 504:ALD循環 505:茂金屬前驅物 506:反應物 100, 200a, 200b, 200c: ferromagnetic tunneling junctions 102, 202a, 202b, 202c: top electrodes 104, 204a, 204b, 204c, 300, 501: ferroelectric material layers 106, 206a, 206b, 206c: bottom electrodes 108, 302, 502: substrate 210a, 210c: top interface layer 220a, 220b: bottom interface layer 301: vapor 303: first cycle 304: (MeCp) 2Zr (OMe)Me 305, 308: ozone 306: second cycle 307: (MeCp) 2Hf (OMe)Me 504: ALD Cycle 505: Metallocene Precursors 506: Reactants

為提供對該揭示標的之進一步理解並且被併入並構成本說明書的一部分而收錄的後附圖形舉例說明該揭示標的之具體實例並且與敘述內容一起用於解釋該揭示標的之原理。在該圖形中:The accompanying drawings, which are incorporated to provide a further understanding of the disclosed subject matter and are incorporated in and constitute a part of this specification, illustrate specific examples of the disclosed subject matter and together with the description, serve to explain the principle of the disclosed subject matter. In this graph:

圖1舉例說明氧化鉿和氧化鋯沉積的不同前驅物之ALD區間;Figure 1 illustrates the ALD interval of different precursors for hafnium oxide and zirconium oxide deposition;

圖2A至2D舉例說明本文揭示的鐵電穿隧接面的替代具體實例;2A-2D illustrate alternative embodiments of ferroelectric tunneling junctions disclosed herein;

圖3A舉例說明用於將本文揭示的固有鐵電材料的實例沉積於基材上之製程的具體實例;Figure 3A illustrates a specific example of a process for depositing examples of intrinsic ferroelectric materials disclosed herein on a substrate;

圖3B舉例說明於基材上底部電極(TiN)上之包含固有鐵電材料的層的具體實例;Figure 3B illustrates a specific example of a layer comprising an intrinsic ferroelectric material on a bottom electrode (TiN) on a substrate;

圖3C舉例說明用於將固有鐵電材料沉積於堆疊上之另一製程;Figure 3C illustrates another process for depositing intrinsic ferroelectric material on the stack;

圖4A舉例說明用以測量HZO薄膜性質的金屬-鐵電-金屬(MFM)電容器的示意圖;Figure 4A illustrates the schematic diagram of the metal-ferroelectric-metal (MFM) capacitor used to measure the properties of HZO thin films;

圖4B舉例說明內部試驗載具(in-house test vehicle)上的亞微米標度FTJ裝置的示意圖;Figure 4B illustrates a schematic diagram of a submicron scale FTJ device on an in-house test vehicle;

圖5A舉例說明沉積於50 nm鎢電極上並且覆蓋有50 nm TiN電極的HZO膜的橫截面HR-TEM圖像;Figure 5A illustrates a cross-sectional HR-TEM image of a HZO film deposited on a 50 nm tungsten electrode and covered with a 50 nm TiN electrode;

圖5B舉例說明橫越圖5A例示的裝置堆疊的電子能量損失(EELS)線掃描;Figure 5B illustrates an electron energy loss (EELS) line scan across the device stack illustrated in Figure 5A;

圖5C舉例說明後金屬退火之後的HZO薄膜的XRD圖;Figure 5C illustrates the XRD pattern of the HZO thin film after post-metal annealing;

圖6A舉例說明在喚醒應力(wake-up stress)前後的極化與電場的關係;Figure 6A illustrates the relationship between polarization and electric field before and after wake-up stress;

圖6B舉例說明在喚醒應力前後的標度裝置的電流-電壓DC掃描;Figure 6B illustrates current-voltage DC sweeps of the scaled device before and after wake-up stress;

圖7A舉例說明該標度裝置的電阻與程式化電壓(programming voltage)的關係;Figure 7A illustrates the relationship between the resistance of the scaling device and the programming voltage (programming voltage);

圖7B舉例說明該標度裝置對於不同寫入脈衝寬度的電阻與程式化電壓的關係;FIG. 7B illustrates the relationship between the resistance of the scaling device and the programming voltage for different write pulse widths;

圖7C舉例說明4標度裝置的電阻與程式化電壓的關係;Figure 7C illustrates resistance versus programming voltage for a 4-scale device;

圖7D舉例說明該標度裝置於4電阻級的穩定性;Figure 7D illustrates the stability of the scale device at 4 resistance levels;

圖8A至8F舉例說明導電度隨脈衝數量的變化,以此舉例說明該標度裝置的4%臭氧具體實例的良好線性度;Figures 8A to 8F illustrate the variation of conductivity with the number of pulses, thereby illustrating the good linearity of the 4% ozone embodiment of the scale device;

圖9舉例說明不同後金屬退火條件之後的電阻與電壓的關係;Figure 9 illustrates the relationship between resistance and voltage after different post-metal annealing conditions;

圖10A和10B舉例說明於室溫下測量的多階狀態隨時間的保持力;及Figures 10A and 10B illustrate the retention of multi-order states over time measured at room temperature; and

圖11舉例說明循環耐力性能(cycling endurance performance)。Figure 11 illustrates cycling endurance performance.

102:頂部電極 102: Top electrode

104:鐵電材料層 104: Ferroelectric material layer

106:底部電極 106: Bottom electrode

108:基材 108: Substrate

Claims (70)

一種鐵電穿隧接面,其包含: 基材; 第一電極和第二電極,其中該第一電極或該第二電極的一部分已經被氧化以形成一界面層; 配置於該第一電極與該第二電極之間的包含結晶材料的薄膜,該結晶材料包含氧化鉿和氧化鋯,其中該結晶材料顯現出原沉積態鐵電行為;及 與該第一電極或該第二電極連接的電壓源。 A ferroelectric tunnel junction comprising: Substrate; a first electrode and a second electrode, wherein a portion of the first electrode or the second electrode has been oxidized to form an interfacial layer; a thin film comprising a crystalline material comprising hafnium oxide and zirconium oxide disposed between the first electrode and the second electrode, wherein the crystalline material exhibits as-deposited ferroelectric behavior; and A voltage source connected to the first electrode or the second electrode. 如請求項1之鐵電穿隧接面,其中該第一電極及該第二電極係獨立地選自TiN、W、Ni、Ru、Pt及Al。The ferroelectric tunnel junction according to claim 1, wherein the first electrode and the second electrode are independently selected from TiN, W, Ni, Ru, Pt and Al. 如請求項1或2之鐵電穿隧接面,其中該第一電極及該第二電極係獨立地選自TiN及W。The ferroelectric tunnel junction according to claim 1 or 2, wherein the first electrode and the second electrode are independently selected from TiN and W. 如請求項1至3中任一項之鐵電穿隧接面,其中該鐵電穿隧接面能夠在4個不同電阻狀態之間切換。The ferroelectric tunnel junction according to any one of claims 1 to 3, wherein the ferroelectric tunnel junction can be switched between four different resistance states. 如請求項1至4中任一項之鐵電穿隧接面,其中該電阻狀態保持穩定至少10 3秒。 The ferroelectric tunneling junction according to any one of claims 1 to 4, wherein the resistance state remains stable for at least 10 3 seconds. 如請求項1至5中任一項之鐵電穿隧接面,其於該DC域中具有介於約1.5倍與約10倍之間的記憶體區間。The ferroelectric tunnel junction according to any one of claims 1 to 5, which has a memory area between about 1.5 times and about 10 times in the DC domain. 如請求項1至6中任一項之鐵電穿隧接面,其具有介於約2倍與約5倍之間的記憶體區間。The ferroelectric tunnel junction according to any one of claims 1 to 6, which has a memory area between about 2 times and about 5 times. 如請求項1至7中任一項之鐵電穿隧接面,其能夠顯現出鐵電活性。The ferroelectric tunnel junction according to any one of claims 1 to 7, which can exhibit ferroelectric activity. 如請求項1至8中任一項之鐵電穿隧接面,其中該第一電極包含鎢並且該第二電極包含氮化鈦。The ferroelectric tunnel junction according to any one of claims 1 to 8, wherein the first electrode comprises tungsten and the second electrode comprises titanium nitride. 如請求項1至9中任一項之鐵電穿隧接面,其中該結晶材料的小於50%總體積構成非鐵電相組分。The ferroelectric tunnel junction according to any one of claims 1 to 9, wherein less than 50% of the total volume of the crystalline material constitutes the non-ferroelectric phase component. 如請求項1至10中任一項之鐵電穿隧接面,其中該結晶材料的小於40%總體積構成非鐵電相組分。A ferroelectric tunnel junction as claimed in any one of claims 1 to 10, wherein less than 40% of the total volume of the crystalline material constitutes a non-ferroelectric phase component. 如請求項1至11中任一項之鐵電穿隧接面,其中該結晶材料的小於40%總體積構成單斜晶相組分。The ferroelectric tunnel junction according to any one of claims 1 to 11, wherein less than 40% of the total volume of the crystalline material constitutes a monoclinic phase component. 如請求項1至12中任一項之鐵電穿隧接面,其中該結晶材料的小於50%總體積構成單斜晶相組分。The ferroelectric tunnel junction according to any one of claims 1 to 12, wherein less than 50% of the total volume of the crystalline material constitutes a monoclinic phase component. 如請求項1至13中任一項之鐵電穿隧接面,其中 (i)    該結晶材料的大於50%總體積處於鐵電相; (ii)   該結晶材料的小於50%總體積構成非鐵電相組分;及 (iii)  該結晶材料的小於25%總體積構成單斜晶相組分。 The ferroelectric tunnel junction according to any one of claims 1 to 13, wherein (i) greater than 50% of the total volume of the crystalline material is in the ferroelectric phase; (ii) less than 50% of the total volume of the crystalline material constitutes a non-ferroelectric phase component; and (iii) Less than 25% of the total volume of the crystalline material constitutes a monoclinic phase component. 如請求項1至14中任一項之鐵電穿隧接面,其中氧化鉿與氧化鋯的比率介於約1:3與約3:1之間。The ferroelectric tunnel junction according to any one of claims 1 to 14, wherein the ratio of hafnium oxide to zirconium oxide is between about 1:3 and about 3:1. 如請求項1至15中任一項之鐵電穿隧接面,其中該結晶材料具有低於約6原子百分比的碳含量。The ferroelectric tunnel junction of any one of claims 1 to 15, wherein the crystalline material has a carbon content of less than about 6 atomic percent. 如請求項1至16中任一項之鐵電穿隧接面,其中該結晶材料係衍生自一或更多具有式I或式II的茂金屬前驅物:
Figure 03_image001
Figure 03_image003
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8係各自獨立地選自C 1-C 6直鏈烷基、C 1-C 6支鏈烷基、C 1-C 6鹵代直鏈烷基及C 1-C 6鹵代支鏈烷基。
The ferroelectric tunnel junction according to any one of claims 1 to 16, wherein the crystalline material is derived from one or more metallocene precursors having formula I or formula II:
Figure 03_image001
or
Figure 03_image003
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently selected from C 1 -C 6 Straight chain alkyl, C 1 -C 6 branched chain alkyl, C 1 -C 6 halogenated straight chain alkyl and C 1 -C 6 halogenated branched chain alkyl.
如請求項1至17中任一項之鐵電穿隧接面,其中該結晶材料係衍生自一或更多具有式I或式II的茂金屬前驅物:
Figure 03_image005
Figure 03_image007
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自獨立地為C 1-C 6直鏈烷基。
The ferroelectric tunnel junction according to any one of claims 1 to 17, wherein the crystalline material is derived from one or more metallocene precursors having formula I or formula II:
Figure 03_image005
or
Figure 03_image007
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently a C 1 -C 6 straight chain alkyl.
如請求項1至18中任一項之鐵電穿隧接面,其中該結晶材料係衍生自一或更多具有式I或式II的茂金屬前驅物:
Figure 03_image009
Figure 03_image010
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自為甲基。
The ferroelectric tunnel junction according to any one of claims 1 to 18, wherein the crystalline material is derived from one or more metallocene precursors having formula I or formula II:
Figure 03_image009
or
Figure 03_image010
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each methyl.
如請求項1至19中任一項之鐵電穿隧接面,其中於極化電場測量時存在磁滯性及剩磁極化。The ferroelectric tunneling junction according to any one of claims 1 to 19, wherein hysteresis and remanence polarization exist when the polarized electric field is measured. 如請求項1至20中任一項之鐵電穿隧接面,其中該膜具有約0.2 nm至約10 nm的厚度。The ferroelectric tunnel junction according to any one of claims 1 to 20, wherein the film has a thickness of about 0.2 nm to about 10 nm. 如請求項1至21中任一項之鐵電穿隧接面,其中該膜具有約0.2 nm至約5 nm的厚度。The ferroelectric tunnel junction according to any one of claims 1 to 21, wherein the film has a thickness of about 0.2 nm to about 5 nm. 如請求項1至22中任一項之鐵電穿隧接面,其中該膜具有大於8μC/cm 2的剩磁極化(Pr)或大於16μC/cm 2的總迴路開度(total loop opening)。 A ferroelectric tunnel junction as claimed in any one of claims 1 to 22, wherein the film has a remanence polarization (Pr) greater than 8 μC/cm 2 or a total loop opening (total loop opening) greater than 16 μC/cm 2 . 一種產生鐵電穿隧接面之方法,其包含: (i)   提供基材; (ii)  將第一電極沉積於該基材上; (iii) 於沉積溫度下將鐵電層沉積於該第一電極上,沉積該鐵電層的步驟包含: (a)  將該第一電極暴露於於該沉積溫度下不會分解的第一前驅物; (b) 將該基材暴露於第一反應氣體; (c)  將該基材暴露於於該沉積溫度下不會分解的第二前驅物;及 (d) 將該基材暴露於第二反應氣體, 其中該第一前驅物及該第二前驅物中之其一包含鋯,並且該第一前驅物及該第二前驅物中之另一者包含鉿;及 (iv) 將第二電極沉積於該鐵電層上。 A method of producing a ferroelectric tunnel junction, comprising: (i) provide the substrate; (ii) depositing a first electrode on the substrate; (iii) depositing a ferroelectric layer on the first electrode at a deposition temperature, the step of depositing the ferroelectric layer comprising: (a) exposing the first electrode to a first precursor that does not decompose at the deposition temperature; (b) exposing the substrate to a first reactive gas; (c) exposing the substrate to a second precursor that does not decompose at the deposition temperature; and (d) exposing the substrate to a second reactive gas, wherein one of the first precursor and the second precursor comprises zirconium, and the other of the first precursor and the second precursor comprises hafnium; and (iv) depositing a second electrode on the ferroelectric layer. 如請求項24之方法,其另外包含在步驟(iii)之前的藉由氧化該第一電極產生界面層的步驟。The method according to claim 24, further comprising a step of generating an interfacial layer by oxidizing the first electrode before step (iii). 如請求項24或25之方法,其中該第一反應氣體及該第二反應氣體各自獨立地為含有氧、水、過氧化氫及一氧化二氮中的一或多者的氣體。The method according to claim 24 or 25, wherein the first reaction gas and the second reaction gas are each independently a gas containing one or more of oxygen, water, hydrogen peroxide and nitrous oxide. 如請求項24至26中任一項之方法,其中該第一反應氣體及該第二反應氣體各自獨立地為含氧氣體、含臭氧氣體或含水氣體。The method according to any one of claims 24 to 26, wherein the first reaction gas and the second reaction gas are each independently an oxygen-containing gas, an ozone-containing gas or a water-containing gas. 如請求項24至27中任一項之方法,其中退火步驟係於大於約攝氏350度的溫度下進行。The method of any one of claims 24 to 27, wherein the annealing step is performed at a temperature greater than about 350 degrees Celsius. 如請求項24至28中任一項之方法,其中沒有製程步驟於大於約攝氏400度的溫度下發生。The method of any one of claims 24 to 28, wherein no process steps occur at a temperature greater than about 400 degrees Celsius. 如請求項24至29中任一項之方法,其中於該鐵電層與該第一電極之間或於該鐵電層與該第二電極之間沒有沉積界面層。The method of any one of claims 24 to 29, wherein no interfacial layer is deposited between the ferroelectric layer and the first electrode or between the ferroelectric layer and the second electrode. 如請求項24至30中任一項之方法,其中該第一氣體或該第二氣體包含以介於約2%與約50%之間的體積分率遞送的臭氧。The method of any one of claims 24 to 30, wherein the first gas or the second gas comprises ozone delivered at a volume fraction between about 2% and about 50%. 如請求項24至31中任一項之方法,其另外包含在沉積該第二電極之前的臭氧脈衝步驟。31. The method of any one of claims 24 to 31, additionally comprising an ozone pulsing step prior to depositing the second electrode. 如請求項24至32中任一項之方法,其中該臭氧脈衝步驟遞送包含介於以體積計約2%與約50%之間的臭氧的氣流。The method of any one of claims 24 to 32, wherein the ozone pulsing step delivers a gas stream comprising between about 2% and about 50% ozone by volume. 如請求項24至33中任一項之方法,其中該沉積的結晶材料在不用額外熱處理的情況下顯現出剩磁極化。The method of any one of claims 24 to 33, wherein the deposited crystalline material exhibits remanent magnetic polarization without additional heat treatment. 如請求項24至34中任一項之方法,其中該沉積的結晶材料具有大於8μC/cm 2的餘磁極化(Pr)或大於16μC/cm 2的總迴路開度。 The method of any one of claims 24 to 34, wherein the deposited crystalline material has a residual magnetic polarization (Pr) greater than 8 μC/cm 2 or a total loop opening greater than 16 μC/cm 2 . 如請求項24至35中任一項之方法,其中該第一電極或該第二電極包含TiN並且該界面層包含TiO xN y,其中x和y為整數。 The method of any one of claims 24 to 35, wherein the first electrode or the second electrode comprises TiN and the interfacial layer comprises TiOxNy , where x and y are integers. 如請求項24至36中任一項之方法,其中該第一電極包含鎢並且該第二電極包含氮化鈦。The method of any one of claims 24 to 36, wherein the first electrode comprises tungsten and the second electrode comprises titanium nitride. 如請求項24至37中任一項之方法,其另外包含至少一吹掃步驟。The method according to any one of claims 24 to 37, which additionally comprises at least one purging step. 如請求項24至38中任一項之方法,其中該第一反應氣體及該第二反應氣體為不同氣體。The method according to any one of claims 24 to 38, wherein the first reactive gas and the second reactive gas are different gases. 如請求項24至39中任一項之方法,其中該第一前驅物及該第二前驅物各自獨立地為具有式I或式II的前驅物:
Figure 03_image001
Figure 03_image012
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8係各自獨立地選自C 1-C 6直鏈烷基、C 1-C 6支鏈烷基、C 1-C 6鹵代直鏈烷基及C 1-C 6鹵代支鏈烷基。
The method according to any one of claims 24 to 39, wherein the first precursor and the second precursor are each independently a precursor of formula I or formula II:
Figure 03_image001
or
Figure 03_image012
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently selected from C 1 -C 6 Straight chain alkyl, C 1 -C 6 branched chain alkyl, C 1 -C 6 halogenated straight chain alkyl and C 1 -C 6 halogenated branched chain alkyl.
如請求項24至40中任一項之方法,其中該第一前驅物及該第二前驅物各自獨立地為具有式I或式II的前驅物:
Figure 03_image001
Figure 03_image014
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自獨立地為C 1-C 6直鏈烷基。
The method according to any one of claims 24 to 40, wherein the first precursor and the second precursor are each independently a precursor of formula I or formula II:
Figure 03_image001
or
Figure 03_image014
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each independently a C 1 -C 6 straight chain alkyl.
如請求項24至41中任一項之方法,其中該第一前驅物及該第二前驅物各自獨立地為具有式I或式II的前驅物:
Figure 03_image009
Figure 03_image017
其中(i) M係選自Zr及Hf,並且(ii) R 1、R 2、R 3、R 4、R 5、R 6、R 7及R 8各自為甲基。
The method according to any one of claims 24 to 41, wherein the first precursor and the second precursor are each independently a precursor of formula I or formula II:
Figure 03_image009
or
Figure 03_image017
Wherein (i) M is selected from Zr and Hf, and (ii) R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 and R 8 are each methyl.
如請求項24至42中任一項之方法,其中該方法包含ALD製程。The method according to any one of claims 24 to 42, wherein the method comprises an ALD process. 如請求項24至43中任一項之方法,其中該方法包含CVD製程。The method according to any one of claims 24 to 43, wherein the method comprises a CVD process. 如請求項24至44中任一項之方法,其中該沉積溫度係介於約攝氏200度與低於約攝氏400度之間。The method of any one of claims 24 to 44, wherein the deposition temperature is between about 200 degrees Celsius and less than about 400 degrees Celsius. 如請求項24至45中任一項之方法,其中該沉積溫度係介於約攝氏265度與低於約攝氏390度之間。The method of any one of claims 24 to 45, wherein the deposition temperature is between about 265 degrees Celsius and less than about 390 degrees Celsius. 如請求項24至46中任一項之方法,其中該沉積溫度係介於約攝氏280度至約攝氏380度之間。The method of any one of claims 24 to 46, wherein the deposition temperature is between about 280 degrees Celsius and about 380 degrees Celsius. 如請求項24至47中任一項之方法,其中該沉積溫度係低於約攝氏30度。The method of any one of claims 24 to 47, wherein the deposition temperature is less than about 30 degrees Celsius. 如請求項24至48中任一項之方法,其中該基材包含矽、鍺、III-V族材料、過渡金屬二硫屬化物、氮化鈦、鈦、鉭、氮化鉭、鎢、鉑、銠、鉬、鈷、釕、鈀或其混合物,或介電質如氧化矽、氮化矽、氧化鋁、氧化鈦。The method according to any one of claims 24 to 48, wherein the substrate comprises silicon, germanium, III-V materials, transition metal dichalcogenides, titanium nitride, titanium, tantalum, tantalum nitride, tungsten, platinum , rhodium, molybdenum, cobalt, ruthenium, palladium or their mixtures, or dielectrics such as silicon oxide, silicon nitride, aluminum oxide, titanium oxide. 如請求項24至49中任一項之方法,其中該沉積的結晶材料具有約0.2 nm及約20 nm的厚度。The method of any one of claims 24 to 49, wherein the deposited crystalline material has a thickness of about 0.2 nm and about 20 nm. 一種產生鐵電穿隧接面之方法,其包含: (i)   提供基材; (ii)  將第一電極沉積於該基材上; (iii) 脈衝包含氧和臭氧的電漿以氧化該底部電極的一部分以形成一界面層; (iv) 於沉積溫度下將鐵電層沉積於該第一電極上,沉積該鐵電層的步驟包含: (a)  將該第一電極暴露於於該沉積溫度下不會分解的第一前驅物; (b) 將該基材暴露於第一反應氣體; (c)  將該基材暴露於於該沉積溫度下不會分解的第二前驅物;及 (d) 將該基材暴露於第二反應氣體, 其中該第一前驅物及該第二前驅物中之其一包含鋯,並且該第一前驅物及該第二前驅物中之另一者包含鉿;及 (v)  將第二電極沉積於該鐵電層上。 A method of producing a ferroelectric tunnel junction, comprising: (i) provide the substrate; (ii) depositing a first electrode on the substrate; (iii) pulsing a plasma comprising oxygen and ozone to oxidize a portion of the bottom electrode to form an interfacial layer; (iv) depositing a ferroelectric layer on the first electrode at a deposition temperature, the step of depositing the ferroelectric layer comprising: (a) exposing the first electrode to a first precursor that does not decompose at the deposition temperature; (b) exposing the substrate to a first reactive gas; (c) exposing the substrate to a second precursor that does not decompose at the deposition temperature; and (d) exposing the substrate to a second reactive gas, wherein one of the first precursor and the second precursor comprises zirconium, and the other of the first precursor and the second precursor comprises hafnium; and (v) depositing a second electrode on the ferroelectric layer. 如請求項51之方法,其中該第一反應氣體及該第二反應氣體各自獨立地為含有氧、水、過氧化氫及一氧化二氮中的一或多者的氣體。The method according to claim 51, wherein the first reaction gas and the second reaction gas are each independently a gas containing one or more of oxygen, water, hydrogen peroxide and nitrous oxide. 如請求項51或52之方法,其中該第一反應氣體及該第二反應氣體各自獨立地為含氧氣體、含臭氧氣體或含水氣體。The method according to claim 51 or 52, wherein the first reaction gas and the second reaction gas are each independently oxygen-containing gas, ozone-containing gas or water-containing gas. 如請求項51至53中任一項之方法,其中退火步驟係於大於或等於約攝氏350度的溫度下進行。The method of any one of claims 51 to 53, wherein the annealing step is performed at a temperature greater than or equal to about 350 degrees Celsius. 如請求項51至54中任一項之方法,其中沒有製程步驟於大於約攝氏400度的溫度下發生。The method of any one of claims 51 to 54, wherein no process steps occur at a temperature greater than about 400 degrees Celsius. 如請求項51至55中任一項之方法,其中於該鐵電層與該第一電極之間或於該鐵電層與該第二電極之間沒有沉積界面層。The method of any one of claims 51 to 55, wherein no interfacial layer is deposited between the ferroelectric layer and the first electrode or between the ferroelectric layer and the second electrode. 如請求項51至56中任一項之方法,其中該第一氣體或該第二氣體包含以介於約2%與約50%之間的體積分率遞送的臭氧。The method of any one of claims 51 to 56, wherein the first gas or the second gas comprises ozone delivered at a volume fraction between about 2% and about 50%. 如請求項51至57中任一項之方法,其另外包含在沉積該第二電極之前的臭氧脈衝步驟。51. The method of any one of claims 51 to 57, additionally comprising an ozone pulsing step prior to depositing the second electrode. 如請求項51至58中任一項之方法,其中該臭氧脈衝步驟遞送包含介於以體積計約2%與約50%之間的臭氧的氣流。The method of any one of claims 51 to 58, wherein the ozone pulsing step delivers a gas stream comprising between about 2% and about 50% ozone by volume. 如請求項51至59中任一項之方法,其中該沉積的結晶材料在不用額外熱處理的情況下顯現出剩磁極化。The method of any one of claims 51 to 59, wherein the deposited crystalline material exhibits remanent magnetic polarization without additional heat treatment. 如請求項51至60中任一項之方法,其中該沉積的結晶材料具有大於8μC/cm 2的餘磁極化(Pr)或大於16μC/cm 2的總迴路開度。 The method of any one of claims 51 to 60, wherein the deposited crystalline material has a residual magnetic polarization (Pr) greater than 8 μC/cm 2 or a total loop opening greater than 16 μC/cm 2 . 如請求項51至61中任一項之方法,其中該第一電極包含TiN並且該界面層包含TiO xN y,其中x和y為整數。 The method of any one of claims 51 to 61, wherein the first electrode comprises TiN and the interfacial layer comprises TiOxNy , where x and y are integers. 如請求項51至62中任一項之方法,其中該第一電極包含鎢(W)並且該中間層包含WO x,其中x為整數。 The method of any one of claims 51 to 62, wherein the first electrode comprises tungsten (W) and the intermediate layer comprises WOx , where x is an integer. 如請求項51至63中任一項之方法,其中該第一電極包含釕(Ru)並且該中間層包含RuO x,其中x為整數。 The method of any one of claims 51 to 63, wherein the first electrode comprises ruthenium (Ru) and the intermediate layer comprises RuOx , where x is an integer. 如請求項51至64中任一項之方法,其中該第一電極包含鎢並且該第二電極包含氮化鈦。The method of any one of claims 51 to 64, wherein the first electrode comprises tungsten and the second electrode comprises titanium nitride. 如請求項51至65中任一項之方法,其中該退火步驟係於於低於或等於約攝氏400度的溫度下進行。The method of any one of claims 51 to 65, wherein the annealing step is performed at a temperature lower than or equal to about 400 degrees Celsius. 如請求項1至23中任一項之鐵電穿隧接面或如請求項24至66中任一項之方法,其中該膜包含摻雜有La、Y、Gd或Sr的Hf xZr 1-xO 2或HfO 2The ferroelectric tunnel junction according to any one of claims 1 to 23 or the method according to any one of claims 24 to 66, wherein the film comprises Hf x Zr doped with La, Y, Gd or Sr -x O 2 or HfO 2 . 一種交錯式記憶體陣列,其包含如請求項1至23中任一項之鐵電穿隧接面或由如請求項24至66中任一項之方法產生的鐵電穿隧接面,該鐵電穿隧接面包含記憶體單位晶胞(memory unit cell)。An interleaved memory array comprising the ferroelectric tunnel junction according to any one of claims 1 to 23 or the ferroelectric tunnel junction produced by the method according to any one of claims 24 to 66, the The ferroelectric tunnel junction includes a memory unit cell. 一種包含如請求項1至23中任一項之鐵電穿隧接面的神經形態運算晶片,其中該鐵電穿隧接面係突觸裝置。A neuromorphic computing chip comprising the ferroelectric tunneling junction according to any one of claims 1 to 23, wherein the ferroelectric tunneling junction is a synapse device. 如請求項1至23中任一項之鐵電穿隧接面,其具有約300 nm或更小的臨界尺寸。The ferroelectric tunnel junction according to any one of claims 1 to 23, which has a critical dimension of about 300 nm or less.
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