TW202306094A - Split die integrated circuit (ic) packages employing die-to-die (d2d) connections in die-substrate standoff cavity, and related fabrication methods - Google Patents

Abstract

Split die IC packages employing a D2D interconnect structure in a die-substrate standoff cavity (i.e., cavity) to provide D2D connections, and related fabrication methods. To facilitate D2D communications between multiple dies in the split die IC package, the package substrate also includes a D2D interconnect structure (e.g., interconnect bridge) that contains D2D interconnects (e.g., metal interconnects) coupled to the multiple dies to provide D2D signal routing between the multiple dies. The D2D interconnect structure is disposed in a cavity that is formed in a die standoff area between the dies and the package substrate as a result of the die interconnects being disposed between the dies and the package substrate standing off the dies from the package substrate. The D2D interconnect structure can be provided in the cavity in the IC package outside of the package substrate to reserve more area in the package substrate for other interconnections.

Description

Split-die integrated circuit (IC) packaging with die-to-die (D2D) connection in die-substrate stand-off cavity and related fabrication methods

The field of this case is related to integrated circuit (IC) packaging, and in particular to split-type semiconductor die IC packaging.

Integrated circuits (ICs) are the building blocks of electronic devices. ICs are packaged in IC packages (also known as "semiconductor packages" or "chip packages"). An IC package includes one or more semiconductor die(s) that are IC(s) mounted on and electrically coupled to a packaging substrate to provide physical support and an electrical interface to the semiconductor die(s). The package substrate includes one or more metallization layers that include electrical traces (eg, metal lines) with vertical interconnects (vias) that couple the electrical traces together in adjacent Between the metallization layers to provide a dielectric interface between the semiconductor die(s). The semiconductor die(s) are mounted to and electrically interface with exposed metal interconnects in the top or outer layers of the packaging substrate to electrically couple the semiconductor die(s) to electrical traces of the packaging substrate. The package substrate includes an outer outer layer with metal interconnects to provide an external interface between the semiconductor die in the IC package and external circuitry.

There are various IC packages based on the intended application. A split semiconductor die IC package (“split die” IC package) is a package that contains two (2) or more semiconductor dies, usually arranged side by side with each other. The semiconductor die is mounted on and electrically coupled to the packaging substrate to provide physical support and provide an electrical interface to the semiconductor die. Depending on the designed operation of the split IC package, a signal interface for die-to-die (D2D) communication may need to be provided between the split dies. For example, each split die may include D2D interface circuitry that provides a communication signal interface to the internal circuitry and to another die. In this regard, a split-die IC package may include a D2D interconnect structure that incorporates D2D connections between the D2D interface circuitry of each die to provide signaling between those die interface. A general split IC package uses a D2D interposer to provide a D2D interconnection structure. For example, the D2D interposer may be provided as a silicon interposer in a package substrate acting as a signal interface bridge. As another example, the D2D interposer may be an embedded wafer level package (eWLP) that includes multiple redistribution layers (RDL) as metallization layers to support D2D connectivity. In either case, however, providing additional metallization layers to provide D2D connectivity may increase the package height of the IC package in an undesired manner.

Aspects disclosed herein include an exemplary split-die integrated circuit (IC) package that employs die-to-die (D2D) ) interconnect structures to provide D2D connectivity. Related manufacturing methods are also disclosed. In an exemplary aspect, a split die IC package includes at least two semiconductor die (“die”) coupled to a package substrate. The package substrate includes one or more metallization layers, each metallization layer has metal interconnects (for example, metal lines or traces) that provide a connection between the die and external interconnects (for example, solder bumps). Signal routing between. Split-die IC packages include a plurality of die interconnects (e.g., die bumps with solder joints) between the die and the package substrate that electrically couple the die to the package substrate for signal routing. In an exemplary aspect, to facilitate D2D communication between multiple dies in a split die IC package, the package substrate also includes a D2D interconnect structure (eg, an interconnect bridge) that includes coupling D2D interconnects (eg, metal interconnects) to the plurality of dies to provide D2D signal routing between the plurality of dies. The D2D interconnect structure is placed between the die and the package substrate in the cavity formed in the die lift-off region due to the die interconnect being placed between the die and the package substrate to lift the die from the package substrate middle. In this way, D2D interconnect structures can be provided in IC packages in cavities outside the package substrate to reserve more area in the package substrate for other interconnects (such as between the die and external interconnects) . Providing D2D interconnect structures outside the package substrate can also reduce the overall height of the split die IC package because the area of the package substrate that would otherwise be consumed by metal interconnects for D2D connections can be used for other applications. Signal routing and/or other devices (eg, passive devices). Also, by providing the D2D interconnect structure in the cavity, the D2D interconnect can be located closer to the die than in the case of providing the D2D interconnect in the package substrate, and thus be shorter in length, thereby reducing its resistance to improve D2D Signaling speed.

In certain exemplary aspects, the D2D interconnect structure is formed from one or more redistribution layers (RDLs) built on the die module adjacent to the active side of the die. RDL is built on the die module and is coupled to the die's die interconnect used for D2D communication. The RDL can also be built on the die module in the limited area that will form the die standoff region, without forming an RDL that spans the entire horizontal area between the die module and the package substrate, which would increase the split Die IC package height. Providing the D2D interconnect structures as RDL(s) can lead to thinner metallization layers with smaller patterning dimensions for D2D interconnects than might be able to be fabricated in general laminate substrates (ie, Line (L)/Space (S) (L/S)). Thus, providing D2D interconnects in RDLs can lead to higher density of D2D interconnects in split IC packages. RDL also does not require the die interconnect using solder joints to connect the D2D interconnect structure to the die. This is particularly useful for dies with high density die interconnects coupled to D2D interconnects to provide D2D communication.

In other examples, the RDL layer of the D2D interconnect structure is formed on the die module as a reconstituted wafer for forming the reconstituted die module. In this regard, as part of a fan-out wafer-level packaging (FOLLP) process, a die may be formed on a first wafer and subsequently singulated and repositioned on a reconstituted wafer. Dies on the reconstituted wafer may be singulated to provide die modules as reconstituted die modules. Providing the die module as a reconfigurable die module allows good die placement control so that the die can be placed closer together to further reduce package size. Furthermore, providing the die module as a reconfigured die module may provide a convenient procedure for building RDL for D2D interconnect on the reconfigured die module in case there are multiple dies. In this way, the RDL can be coupled to the die interconnect of the die module when the RDL is fabricated on the reconfigurable die module. As part of fabricating a split-die IC package, a die module with built-in RDLs forming D2D interconnects may then be coupled to the package substrate.

Note that providing the D2D interconnect structure in the die standoff region outside the package substrate of the split die IC package does not exclude that the metallization layer in the package substrate is also used to provide the D2D interconnect. Including the D2D interconnect structure in the die standoff region outside the packaging substrate can reduce or minimize the need to provide D2D connections in the packaging substrate.

In this regard, in one exemplary aspect, an IC package is provided. The IC package includes a package substrate; a first die; and a second die; the IC package also includes a first plurality of die interconnects coupled to the package substrate and the first die die to establish a die standoff region between the first die and the packaging substrate. The IC package also includes a second plurality of die interconnects disposed in the die standoff region and coupled to the package substrate and a second die. A cavity is formed in the die standoff region between the first plurality of die interconnects and the second plurality of die interconnects. The IC package also includes a D2D interconnect structure disposed in the cavity. The D2D interconnect structure includes a plurality of D2D interconnects coupled to the first die and the second die.

In another exemplary aspect, a method of manufacturing an IC package is provided. The method includes forming a die module including an active side, a first die including a first active side adjacent to the active side, and a second die including a second active side adjacent to the active side. The second die is horizontally adjacent to the first die. The method also includes forming a D2D interconnection structure adjacent to the active side of the die module, the D2D interconnection structure including a plurality of D2D interconnections. The method also includes forming a first plurality of die interconnects coupled to the first active side of the first die. The method also includes forming a second plurality of die interconnects coupled to a second active side of a second die to form a cavity between the first plurality of die interconnects and the second plurality of die interconnects, And the D2D interconnect structure is arranged in the cavity. The method also includes arranging the die module on a packaging substrate, including: coupling a first plurality of die interconnects to the packaging substrate; and coupling a second plurality of die interconnects to the packaging substrate.

Referring now to the drawings, several exemplary aspects of the present case are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as superior or superior to other aspects.

Aspects disclosed herein include an exemplary split-die integration employing a die-to-die (D2D) interconnect structure in a die-substrate standoff cavity (i.e., cavity) to provide D2D connectivity Circuit (IC) packaging. Related manufacturing methods are also disclosed. In an exemplary aspect, a split die IC package includes at least two semiconductor die (“die”) coupled to a package substrate. The package substrate includes one or more metallization layers each having metal interconnects that provide signal routing between the die and external interconnects (eg, solder bumps). Split-die IC packages include a plurality of die interconnects (e.g., die bumps with solder joints) between the die and the package substrate that electrically couple the die to the package substrate for signal routing. In an exemplary aspect, to facilitate D2D communication between multiple dies in a split die IC package, the package substrate also includes a D2D interconnect structure (eg, an interconnect bridge) that includes coupling D2D interconnects (eg, metal lines) to the plurality of dies provide D2D signal routing between the plurality of dies. The D2D interconnect structure is placed between the die and the package substrate in the cavity formed in the die stand-off region due to the die interconnect being placed between the die and the package substrate to support the die from the package substrate middle. In this way, D2D interconnect structures can be provided in IC packages in cavities outside the package substrate to reserve more area in the package substrate for other interconnects (such as between the die and external interconnects) . Providing D2D interconnect structures outside the package substrate can also reduce the overall height of the split die IC package because the area of the package substrate that would otherwise be consumed by metal interconnects for D2D connections can be used for other signal routing and/or other devices (eg, passive devices). Also, by providing the D2D interconnect structure in the cavity, the D2D interconnect can be located closer to the die than in the case of providing the D2D interconnect in the package substrate, and thus be shorter in length, thereby reducing its resistance to improve D2D Signaling speed.

Before discussing an example of a split-die IC package that employs a D2D interconnect structure in the cavity to provide D2D connections between multiple die in the package, starting with FIG. A split die IC package including a D2D interconnect structure in a cavity.

In this regard, FIGS. 1A and 1B are top and cross-sectional side views, respectively, of a split semiconductor die (“die”) IC package 100 including a D2D interposer in a package substrate 104 for providing D2D connectivity. 102. Split die IC package 100 in FIG. 1B is shown as a cross-section along line A ₁ -A ₁ ′ in FIG. 1A . Referring to FIGS. 1A and 1B , split die IC package 100 includes at least two semiconductor die (“die”) 106 ( 1 ), 106 ( 2 ) coupled to package substrate 104 . In this example, the dies 106(1), 106(2) are arranged horizontally adjacent to each other in the X-axis direction, with a die separation region 108 formed between the dies 106(1), 106(2). Package substrate 104 includes one or more metallization layers each having metal interconnects (eg, metal lines or traces) that provide dies 106(1), 106(2) and external interconnects 110 ( For example, signal routing between solder balls). As shown in FIG. 1B , split die IC package 100 includes a plurality of die interconnects 112 (e.g., die with solder joints) between die 106(1), 106(2) and package substrate 104. bumps), these die interconnects 112 electrically couple the dies 106(1), 106(2) to the package substrate 104 for signal routing. In this example, the die interconnect 112 includes metal pillars 114 that are coupled to die bond wires on the active sides 116(1), 116(2) of the respective die 106(1), 106(2). disk (not shown). Metal posts 114 are coupled to package substrate 104 with solder joints 118 formed on metal posts 114 and coupled to package substrate 104 .

To facilitate D2D communication between the plurality of dies 106 ( 1 ), 106 ( 2 ) in the split die IC package 100 of FIGS. 1A and 1B , the package substrate 104 also includes a D2D interposer 102 . In this example, D2D interposer 102 is disposed in encapsulation substrate 104 below die separation region 108 . The D2D interposer 102 includes D2D interconnects 120 (eg, metal lines) coupled to the specific die interconnects 112 coupled to the respective dies 106(1), 106(2), which are dedicated to the dies 106(1), 106(2), D2D signal routing between 106(2) for D2D communication. As an example, such D2D signal routing may be the coupling of communication signals and common power rails. The D2D interposer 102 is usually located in the upper metallization layer of the packaging substrate 104 to reduce the length of the D2D interconnect 120 , thereby reducing resistance and increasing signal transmission speed.

Including the D2D interposer 102 in the packaging substrate 104 consumes space in the metallization layers of the packaging substrate 104 . This can contribute to increasing the height H ₁ of the package substrate in the Z-axis direction, and thereby increasing the overall height H ₂ of the split die IC package in the Z-axis direction, as shown in FIG. 1B . Also, including the D2D interconnect 120 in the package substrate 104 may be located close to other metal interconnects in the package substrate 104 , such as power rails, which can create signal interference. The D2D communication signals carried on the D2D interconnect 120 may be particularly sensitive to interference because these signals may be higher speed signals that are part of the D2D bus interface between the dies 106(1), 106(2). Furthermore, the location of the D2D interposer 102 below and adjacent to the die separation region 108 may affect the routing space in the package substrate 104 . Other metal interconnects in the package substrate 104 that route signals other than D2D communication signals are isolated from the D2D interposer 102 and thus have to be routed in areas other than the area of the D2D interposer 102 . This may affect routing options and capabilities in the packaging substrate 104 . For example, the D2D interposer 102 may interfere with the routing paths of the power distribution network in the packaging substrate 104, resulting in longer power distribution paths. This can contribute to increasing the voltage drop of the power distribution grid in the packaging substrate 104 . Furthermore, as the number and/or density of D2D interconnects 120 increases, D2D interposers 102 are more likely to be disposed in additional metallization layers of packaging substrate 104, thereby further consuming area that could be used for other signal routing. Or alternatively, additional D2D interconnects from one die 106(1), 106(2) may have to be routed via packaging substrate 104 to external interconnects 110 and back to the other die 106(2), 106(1) , so as to prevent the D2D interposer 102 from consuming additional space in the packaging substrate 104 .

2A and 2B are top and cross-sectional side views, respectively, of another exemplary split die IC package 200 employing the D2D interposer 102 in the split die IC package 100 of FIGS. 1A and 1B. An alternative D2D connection structure can avoid consuming space in the package substrate for the D2D connection. In this regard and as discussed in more detail below, the split die IC package 200 in FIGS. 2A and 2B includes a D2D interconnect structure 202 to provide a die-substrate standoff cavity (ie, cavity ) D2D connection in 204 . Die-substrate standoff cavity 204 is between semiconductor die ("die") 206(1), 206(2) and packaging substrate 208 as die interconnect 210 is disposed between die 206(1), 206(1), These die interconnects 210 couple dies 206 ( 1 ), 206 ( 2 ) to the packaging substrate 208 . In one example, the die-substrate standoff cavity 204 does not include the space inside the package substrate 208 or the dies 206(1), 206(2). Die interconnect 210 "supports" die 206(1), 206(2) from package substrate 208 by a corresponding height H3 of die interconnect 210 to form an arrangement between die 206(1), 206(2) Die-substrate support cavity 204 between package substrate 208 .

In this way, as shown in FIG. 2B , D2D interconnect structure 202 is provided in die-substrate standoff cavity 204 outside of package substrate 208 in split die IC package 200 . This may reserve more area in the package substrate 208 for other interconnects, such as between the dies 206(1), 206(2) and external interconnects 211 (eg, solder balls). Providing the D2D interconnection structure 202 outside the packaging substrate 208 also reduces the height H ₄ of the packaging substrate 208 relative to the height H 4 of the packaging substrate 208 would have been included in the packaging substrate 208 . The reduced height _H4 of the package substrate 208 reduces the overall height _H5 of the split die IC package 200 because of the interconnects (eg, metal lines, metal traces, The area consumed by vertical interconnects (vias, pads) can be used for other signal routing and/or other devices (eg, passive devices). Also, by providing the D2D interconnect structure 202 in the die-substrate support cavity 204 of the split die IC package 200, compared to the case where the D2D interconnect is provided in the package substrate 208, the D2D interconnect structure 202 The D2D interconnects may be located closer to the die 206(1), 206(2). This reduces the length of the D2D interconnect, thereby reducing its resistance to increase the speed of D2D signaling between the dies 206(1), 206(2).

Continuing to refer to FIGS. 2A and 2B , split die IC package 200 in FIG. 2B is shown as a cross-section along line A ₂ -A ₂ ′ in FIG. 2A . Dies 206 ( 1 ), 206 ( 2 ) are coupled to packaging substrate 208 . In this example, the dies 206(1), 206(2) are arranged horizontally adjacent to each other in the X-axis direction, with the die separation region 212 being the distance _D1 between the dies 206(1), 206(2). area. In this example, dies 206 ( 1 ), 206 ( 2 ) are included in die module 214 . In this example, the first and second die 206(1), 206(1) are arranged above the package substrate 208 in a vertical direction in the Z-axis direction, which is positive to a horizontal direction in the X-axis direction. pay. Die module 214 includes die 206(1), 206(2) and an overmolding compound 216 (e.g., epoxy resin) formed around die 206(1), 206(2) and in die separation region 212 ). For example, as discussed in more detail below, the die module 214 may include a reconstituted die 218 fabricated according to a fan-out wafer-level packaging (FOWLP) process. Providing die module 214 as reconstituted wafer 218 allows good die placement control so that dies 206(1), 206(2) can be placed closer together for further die reduction The width of the separation region 212 in the horizontal X-axis direction is used to reduce the size of the package. A dielectric layer 220 is disposed on top of the die module 214 . A packaging compound 222 , such as a molding compound, is disposed on the dielectric layer 220 as part of the split die IC package 200 .

As shown in FIG. 2B, first and second plurality of die interconnects 210(1), 210(2) are coupled to package substrate 208 and corresponding first and second die 206(1), 206( 2). The first and second die 206(1), 206(2) have respective active sides 224(1), 224(2) and backsides 226(1), 226(2). Die interconnect 210 ( 1 ) is coupled to active side 224 ( 1 ) of die 206 ( 1 ) and to packaging substrate 208 . Die interconnect 210 ( 2 ) is coupled to active side 224 ( 2 ) of die 206 ( 2 ) and to packaging substrate 208 . The first and second plurality of die interconnects 210(1), 210(2) coupled to the package substrate 208 and the corresponding first and second dies 206(1), 206(2) A die support region 228 is established between the two dies 206 ( 1 ), 206 ( 2 ) and the packaging substrate 208 . Die-substrate standoff cavities 204 are formed in die standoff regions 228 between die interconnects 210(1), 210(2). D2D interconnect structure 202 is arranged in die-substrate standoff cavity 204 . As discussed in more detail below with respect to FIG. 3 , D2D interconnect structure 202 includes D2D interconnect 232 coupled to first die 206(1) and second die 206(2) to provide die 206(1), D2D connections between 206(2). In this example, die 206(1) includes D2D interface circuitry 234(1) that provides a D2D communication interface to die 206(2). D2D interface circuitry 234 ( 1 ) is horizontally adjacent to die separation region 212 . Also, in this example, die 206(2) includes D2D interface circuitry 234(2) that provides a D2D communication interface to die 206(1). D2D interface circuitry 234( 2 ) is also horizontally adjacent to die separation region 212 . The D2D interface circuitry 234(1), 234(2) is disposed over and in contact with the D2D interconnect structure 202 to couple to the D2D interconnect 232 therein to connect the D2D interface circuitry 234(1) , 234(2) are coupled together for D2D communication.

In this example, the D2D interconnect structure 202 and its D2D interconnect 232 are not arranged in the packaging substrate 208 . In this example, D2D interconnects 232 are not coupled to package substrate 208 (which includes metal interconnects (e.g., metal lines, metal traces, vertical interconnect vias (vias), pads) in metallization layers ) to avoid consuming area in the packaging substrate 208 for the D2D connectivity provided by the D2D interconnect structure 202 .

3 is another cross-sectional side view of the split die IC package 200 of FIGS. 2A and 2B to illustrate additional exemplary details of including the D2D interconnect structure 202 in the die-substrate standoff cavity 204. . The cross-sectional side view of the split die IC package 200 in FIG. 3 is also along the line A ₂ -A ₂ ′ of the split die IC package 200 in FIG. 2A .

As shown in FIG. 3 , in this example, the die module 214 has an active side 236 adjacent to the package substrate 208 . The first and second active sides 224(1), 224(2) of the first and second die 206(1), 206(2) are arranged on the active side 236 of the package substrate 208 such that the Connections between the first and second die 206(1), 206(2) and the package substrate 208 are established via respective first and second die interconnects 210(1), 210(2). The first die interconnect 210(1) is coupled to the first active side 224(1) of the first die 206(1). The second die interconnect 210(2) is coupled to the second active side 224(2) of the second die 206(2). The first and second die interconnects 210(1), 210(2) each include respective first and second active sides 224( Metal pillars 238(1), 238(2) (eg, copper pillars) of die pads on 1), 224(2). Interconnect bumps 240 ( 1 ), 240 ( 2 ) (eg, solder bumps or solder caps) are disposed on metal pillars 238 ( 1 ), 238 ( 2 ) to form electrical connections to package substrate 208 . Package substrate 208 includes one or more metallization layers 242(1) for establishing electrical connections between die 206(1), 206(2) via die interconnects 210(1), 210(2)— 242(3). Die interconnects 210(1), 210(2) are coupled to one or more metal interconnects 243(1)-243(3) in metallization layers 242(1)-242(3) of package substrate 208 (eg, metal lines, metal traces, vertical interconnects (vias), pads). The height H ₃ of the die interconnects 210( 1 ), 210( 1 ) defines the height H ₃ of the die-substrate standoff cavity 204 in the vertical direction on the Z-axis. The D2D interconnect structure 202 has a height _H6 in the vertical direction on the Z axis that is smaller than the height _H3 of the die-substrate support cavity 204, so that the D2D interconnect structure 202 can be arranged on the die-substrate support cavity. cavity 204 without consuming area in package substrate 208 (if desired). The overmolding compound 216 is disposed adjacent to the first and second backsides 226(1), 226(2) of the first and second dies 206(1), 206(2).

As an example, as discussed in more detail below, die module 214 may be a reconstituted die module fabricated according to a FOWLP process. This may allow the D2D interconnect structure 202 to be more easily built on the die module 214 in one or more metallization layers as part of the split die IC package 200 manufacturing process. For example, D2D interconnect structure 202 may include one or more metallization layers 244(1)-244(3), each of which is an RDL 246(1)-246(3), each of which includes a metal interconnect 248(1)-248(3) (eg, metal lines, metal traces, vertical interconnect vias (vias), pads). For example, if metallization layers 244(1)-244(3) are RDLs 246(1)-246(3), then metal interconnects 248(1) in metallization layers 244(1)-244(3) Smaller L/S ratios are easier to achieve in -248(3). For example, the L/S ratio of metal interconnects 248(1)-248(3) is 2/2 or 1/1. As an example, the height _H3 of the die interconnects 210(1), 210(2) may be between 30-40 micrometers (µm), the height of each of the RDLs 246(1)-246(3) may be 7 µm or less, while metal interconnects 248(1)-248(3) may have an L/S ratio of 2/2 or less.

The first die 206 ( 1 ), in particular the D2D interface circuitry 234 ( 1 ), may be coupled to a metal interconnect 248 ( 1 ) in the first RDL 246 ( 1 ) for coupling to the D2D interconnect structure 202 . The second die 206(1) (in particular the D2D interface circuitry 234(2)) may also be coupled to the metal interconnect 248(1) in the first RDL 246(1) for coupling to the D2D interconnect structure 202 . In this way, the D2D interface circuitry 234( 1 ), 234( 2 ) can be coupled together for D2D communication via the D2D interconnect structure 202 . To make the connectivity more space efficient, the D2D interface circuitry 234(1), 234(2) in the first and second dies 206(1), 206(2) can be positioned as Vertically disposed above and/or overlapping or partially overlapping the die-substrate support cavity 204 to establish a connection to the D2D interconnect structure 202 .

4 is a diagram illustrating a method for fabricating a split-die IC package (including but not limited to the exemplary split-die IC package in FIGS. A flowchart of an exemplary process 400 for die IC package 200 ). As an example, the exemplary procedure 400 in FIG. 4 is described with respect to the split die IC package 200 in FIGS. Other split-die IC packages that offer D2D connectivity.

In this regard, referring to FIG. 4 , the first fabrication step includes forming a die module 214 including an active side 236 , a first die comprising a first active side 224 ( 1 ) adjacent to the active side 236 . grain 206(1), and a second die 206(2) comprising a second active side 224(1) adjacent to the active side 236, the second die 206(2) being horizontally adjacent to the first die 206( 1) (Block 402 in Figure 4). The next fabrication step in the process 400 includes forming the D2D interconnect structure 202 adjacent to the active side 236 of the die module 214 , the D2D interconnect structure 202 including the plurality of D2D interconnects 232 (block 404 in FIG. 4 ). The next fabrication step in routine 400 includes forming the first plurality of die interconnects 210(1) coupled to the first active side 224(1) of the first die 206(1) (block 406 in FIG. 4 ). The next fabrication step in routine 400 includes forming a second plurality of die interconnects 210(2) coupled to a second active side 224(2) of a second die 206(2) to A die-substrate support cavity 204 is formed between the die interconnect 210(1) and the second plurality of die interconnects 210(2), wherein the D2D interconnect structure 202 is disposed in the die-substrate support cavity 204 (block 408 in FIG. 4). The next fabrication step in process 400 includes disposing active side 236 of die module 214 on packaging substrate 208 (block 410 in FIG. 4 ). Arranging the active side 236 of the die module 214 on the package substrate 208 includes coupling a first plurality of die interconnects 210(1) to the package substrate 208 (block 412 in FIG. 4 ), and coupling a second plurality of Die interconnect 210(2) is coupled to package substrate 208 (block 414 in FIG. 4).

5A-5C are diagrams illustrating split-die IC packages (including but not limited to the exemplary ones in FIGS. A flowchart of another exemplary process 500 for split die IC packaging). 6A-6H illustrate an example for a split-die IC package employing a D2D interconnect structure in a die-substrate standoff cavity to provide D2D connectivity according to the exemplary fabrication sequence 500 in FIGS. 5A-5C. Sexual manufacturing stages 600A-600H. Manufacturing sequence 500 in FIGS. 5A-5C will now be discussed in conjunction with exemplary manufacturing stages 600A- 600H in FIGS. 6A-6H .

In this regard, referring to procedure 500 in FIG. 5A , the first step in fabricating split die IC package 200 may be to fabricate die module 214 as a reconstituted die module. As shown in fabrication stage 600A in FIG. 6A, this involves providing a carrier 602 comprising a first surface 604 for forming the reconstituted die module 214 into a reconstituted wafer 606, and forming the die 206(1), 206(2) are placed (and positioned) horizontally adjacent to each other in the X-axis direction on the carrier 602 (block 502 in FIG. 5A ). Carrier 602 provides a structure that allows die 206 ( 1 ), 206 ( 2 ) to be positioned and manipulated to form die module 214 . As discussed below, providing the die module 214 as a reconstituted wafer 606 may provide the die 206(1) on the die module 214 adjacent to the die 206 before the die module 214 is disposed on the packaging substrate 208. The active sides 224(1), 224(2) of , 206(2) form the capability of the D2D interconnect structure 202 . For example, D2D interconnect structure 202 may preferably be formed on die module 214 as one or more RDLs, such as RDLs 246(1)-246(3) in FIG. 3 . A temporary adhesive film 608 may be placed on the first surface 604 of the carrier 602 and the die 206(1), 206(2) subsequently disposed on the adhesive film 608 to provide an adhesive for the die 206(1), 206(2) To be firmly attached to the carrier 602.

As shown in the next fabrication stage 600B in FIG. 6B , the next step in forming the die module 214 into a reconstituted wafer 606 is to form the first surface 604 of the carrier and the corresponding first and second die An overmolding compound 216 (eg, epoxy molding) is disposed on and over the first and second backsides 226(1), 226(2) of the 206(1), 206(2) to secure the die 206(1), 206(2) and provide dielectric isolation from the die 206(1), 206(2) (block 504 in Figure 5A). As shown in the next fabrication stage 600C in FIG. 6C , the next step in forming die module 214 into reconstituted wafer 606 is: ), 226(2) Grind away the top surface 612 ( FIG. 6B ) of the overmolding compound 216 to the reduced surface 614 to the desired thickness D ₂ (block 506 in FIG. 5A ). Alternatively, the overmolding compound 216 may be ground down to the backsides 226(1), 226(2) of the dies 206(1), 206(2).

As shown in the next fabrication stage 600D in FIG. 6D , the next steps are to remove the carrier 602 from the reconstituted wafer 606 and place the second carrier 616 adjacent to the die 206(1), 206(2) The backsides 226(1), 226(2) of the 226(2) are attached to the reconstituted wafer 606 (block 508 in FIG. 5B). The carrier 602 is removed to expose the active sides 224(1), 224(2) of the dies 206(1), 206(2) (and more specifically, to expose the D2D interface circuitry 234(1), 234(2)) , thinking that the D2D interconnect structure 202 will be formed on the reconstituted wafer 606 and coupled to the active sides 224(1), 224(2) of the die 206(1), 206(2) and the D2D interface circuitry 234(1) , 234(2) Get ready. Adhesive layer 618 may be first disposed on second carrier 616, and then reconstituted wafer 606 is attached to second carrier 616 to secure reconstituted wafer 606 to second carrier 616, as shown in FIG. 6D.

Subsequently, as shown in the next fabrication stage 600E in FIG. 6E , the next step is: a portion of the first active side 224 ( 1 ) of the first die 206 ( 1 ) and the The D2D interconnect structure 202 is formed on a portion of the second active side 224(2) of the D2D (block 510 in FIG. 5B ) where it will be formed as a die-substrate standoff cavity 204 at a later stage of fabrication. The D2D interconnect structure 202 is arranged vertically adjacent to the horizontal die separation region 212 between the first die 206(1) and the second die 206(2) in the Z-axis direction. Manufacturing stage 600E illustrates: first RDL 246(1) is formed on reconstituted wafer 606 coupled to D2D interface circuitry 234(1), 234(2) of die 206(1), 206(2), As part of the D2D interconnect structure 202 . As shown in the next fabrication stage 600F in FIG. 6F, additional RDL(s) 246(2) may be formed on the first RDL 246(1) to form part of the D2D interconnect structure 202 (block in FIG. 5B 512). In this example, forming RDLs 246(1), 246(2) may include the general procedure for forming RDLs, including providing a coating on die module 214, removing coated portions with a patterning process to expose Die pads for D2D interface circuitry 234(1), 234(2), seed layers are deposited, and photolithographic processes are performed to form metal interconnects in RDLs 246(1), 246(2). When fully constructed, a solder mask 620 may also be formed on the D2D interconnect structure 202 to protect the RDLs 246(1), 246(2) from solder as the die interconnects 210(1), 210(2) are formed. exposed.

As shown in the next fabrication stage 600G in FIG. 6G, the next step is to form die interconnects 210(1), 210(2) on reconstituted wafer 606 and connect them with dies 206(1), 206( 2) Contact (block 514 in Figure 5C). This involves forming metal pillars 238(1), 238(2) and interconnect bumps 240(1), 240(2). As discussed above, this will create die stand-off region 228 in the region between die interconnects 210(1), 210(2) when die module 214 is formed from reconstituted wafer 606. Referring now to FIG. The cavity formed by the die standoff region 228 (FIGS. 2B and 3) between the die module 214 and the package substrate 208 will create the die-substrate standoff cavity 204, which is essential for final disassembly. The existing D2D interconnect structure 202 reserves headroom and space in the fractional die IC package 200 without consuming area in the package substrate 208 . If multiple die modules 214 are formed as part of the reconstituted wafer 606 , die singulation may be used to separate the die modules 214 . As shown in the next fabrication stage 600H in FIG. 6H , the next step is to remove the second carrier 616 and place the active side 236 of the die module 214 on the package substrate 208 to interconnect the die 210 ( 1 ), 210(2) are coupled to the package substrate 208 to form the split die IC package 200 (block 516 in FIG. 5C ).

Split-die IC package(s) employing a D2D interconnect structure in a die-substrate standoff cavity to provide D2D connectivity according to the exemplary fabrication sequence in FIGS. 4-6H (including but not limited to FIGS. 2A-3 The exemplary split die IC package in ) can be provided in or integrated into any processor-based device. Non-limiting examples include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location information units, mobile location information units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, conversation initiation Protocol (SIP) phones, tablets, phablets, servers, computers, laptops, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop mini computer, personal digital assistant (PDA), monitor, computer monitor, television, tuner, radio, satellite radio, music player, digital music player, portable music player, digital video player, video Players, DVD Players, Portable Digital Video Players, Automobiles, Vehicle Components, Avionics Systems, Drones, and Multicopters.

In this regard, FIG. 7 illustrates an example of a processor-based system 700 . A component of processor-based system 700 is IC 702 . Some or all of the ICs 702 in the processor-based system 700 may be provided in die-substrate stand-off cavities (i.e. , cavity) in a split die IC package(s) 704 (including but not limited to the exemplary split die IC package in FIGS. 2A-3 ) employing a D2D interconnect structure to provide D2D connectivity. In this example, processor-based system 700 may be formed as a split die IC package 704 and as a system on a chip (SoC) 706 . The processor-based system 700 includes a CPU 708 that includes one or more processors 710, which may also be referred to as CPU cores or processor cores. CPU 708 may have cache memory 712 coupled to CPU 708 for fast access to temporarily stored data. CPU 708 is coupled to system bus 714 and may couple masters and slaves included in processor-based system 700 to each other. CPU 708 communicates with these other devices by exchanging address, control and data information over system bus 714, as is well known. For example, CPU 708 may communicate a bus transaction request to memory controller 716, which is an example of a slave device. Although not shown in FIG. 7 , multiple system bus bars 714 may be provided, where each system bus bar 714 constitutes a different texture.

Other masters and slaves may be connected to system bus 714 . As illustrated in FIG. 7, these devices may include, by way of example, a memory system 720 including a memory controller 716 and memory array(s) 718, one or more input devices 722, one or more output devices 724 , one or more network peripheral devices 726 , and one or more display controllers 728 . Each of the memory system 720, one or more input devices 722, one or more output devices 724, one or more network peripherals 726, and one or more display controllers 728 may be provided on the same or different IC packages. Input device(s) 722 may include any type of input device including, but not limited to, input keys, switches, voice processors, and the like. Output device(s) 724 may include any type of output device including, but not limited to, audio, video, other visual indicators, and the like. Network perimeter device(s) 726 may be any device configured to allow the exchange of data to and from network 730 . Network 730 may be any type of network including, but not limited to, wired or wireless, private or public, local area network (LAN), wireless local area network (WLAN), wide area network (WAN), Bluetooth™ network, and the Internet. Network peripheral device(s) 726 may be configured to support any type of communication protocol desired.

CPU 708 may also be configured to access display controller(s) 728 via system bus 714 to control information sent to one or more displays 732 . Display controller(s) 728 sends information to be displayed to display(s) 732 via one or more video processors 734 , which process the information to be displayed into a format suitable for display(s) 732 . As an example, display controller(s) 728 and video processor(s) 734 may be included as split die IC package 704 and the same or different IC package, and in the same or different IC package that contains CPU 708 . Display(s) 732 may include any type of display including, but not limited to, cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light emitting diode (LED) display, and the like.

FIG. 8 illustrates an exemplary wireless communication device 800 including radio frequency (RF) components formed from one or more ICs 802, any of which may include any aspect disclosed herein and according to FIGS. 4-6H A split die IC package 803 employing a D2D interconnect structure in a die-substrate standoff cavity (i.e., cavity) to provide D2D connectivity in an exemplary fabrication process (including but not limited to those shown in FIGS. 2A-3 Exemplary Split Die IC Package). As an example, wireless communication device 800 may include or be included in any of the devices described above. As shown in FIG. 8 , the wireless communication device 800 includes a transceiver 804 and a data processor 806 . Data processor 806 may include memory to store data and program codes. Transceiver 804 includes a transmitter 808 and a receiver 810 that support two-way communication. In general, wireless communication device 800 may include any number of transmitters 808 and/or receivers 810 for any number of communication systems and frequency bands. All or a portion of transceiver 804 may be implemented on one or more analog ICs, RFICs, mixed signal ICs, and the like.

Transmitter 808 or receiver 810 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and fundamental frequency in multiple stages, such as for receiver 810, from RF to intermediate frequency (IF) in one stage and then from IF to fundamental frequency in another stage . In a direct conversion architecture, the signal is converted between RF and fundamental frequency in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communication device 800 in FIG. 8 , the transmitter 808 and the receiver 810 are implemented using a direct conversion architecture.

In the transmit path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808 . In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) to convert digital signals generated by the data processor 806 into I and Q analog output signals (e.g. , I and Q output currents) for further processing.

Within transmitter 808, low pass filters 814(1), 814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by previous digital-to-analog conversions. Amplifiers (AMPs) 816(1), 816(2) amplify the signals from low pass filters 814(1), 814(2), respectively, and provide I and Q fundamental frequency signals. Upconverter 818 upconverts the I and Q bases with I and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 822 via mixers 820(1), 820(2). frequency signal to provide up-converted signal 824. A filter 826 filters the upconverted signal 824 to remove undesired signals caused by upconversion and noise in the receive frequency band. A power amplifier (PA) 828 amplifies the upconverted signal 824 from filter 826 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a diplexer or switch 830 and transmitted via an antenna 832 .

In the receive path, antenna 832 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 830 and provided to a low noise amplifier (LNA) 834 . The duplexer or switch 830 is designed to operate with a specific receive (RX) and TX duplexer frequency separation such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Down conversion mixers 838(1), 838(2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q fundamental frequency signal. The I and Q baseband signals are amplified by AMPs 842(1), 842(2) and further filtered by low pass filters 844(1), 844(2) to obtain I and Q analog input signals which The signal is provided to a data processor 806 . In this example, data processor 806 includes analog-to-digital converters (ADCs) 846 ( 1 ), 846 ( 2 ) to convert analog input signals into digital signals to be further processed by data processor 806 .

In wireless communication device 800 of FIG. 8, TX LO signal generator 822 generates I and Q TX LO signals for up-conversion, and RX LO signal generator 840 generates I and Q RX LO signals for down-conversion . Each LO signal is a periodic signal with a specific fundamental frequency. TX phase locked loop (PLL) circuitry 848 receives timing information from data processor 806 and generates control signals for adjusting the frequency and/or phase of the TX LO signal from TX LO signal generator 822 . Similarly, RX PLL circuit 850 receives timing information from data processor 806 and generates control signals for adjusting the frequency and/or phase of the RX LO signal from RX LO signal generator 840 .

It will be further appreciated by those of ordinary skill in the art that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein may be implemented as electronic hardware, stored in memory or another computer readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size, and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of this case.

The various illustrative logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be used with processors, digital signal processors (DSPs), application specific integrated circuits designed to perform the functions described herein (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, individual gate or transistor logic, individual hardware components, or any combination thereof. A processor can be a microprocessor, but in the alternative the processor can be any general processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (eg, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors coordinated with a DSP core, or any other such configuration).

Aspects disclosed herein can be implemented in hardware and instructions stored in hardware and can be resident in, for example, random access memory (RAM), flash memory, read only memory (ROM) , Electrically Programmable ROM (EPROM), Electronically Erasable Programmable ROM (EEPROM), scratchpad, hard disk, removable disk, CD-ROM, or any other in the form of computer-readable media. An exemplary storage medium is coupled to the processor such that the processor can read information from/write to the storage medium. In the alternative, the storage medium may be integrated into the processor. The processor and storage medium can be resident in the ASIC. The ASIC may be resident in the remote station. In the alternative, the processor and storage medium may reside as separate components in a remote station, base station, or server.

Note also that the steps described in any exemplary aspect herein are described for the purpose of providing example and discussion. The described operations may be performed in numerous different orders than the illustrated order. Furthermore, operations described in a single operational step may actually be performed in a plurality of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that the operational steps illustrated in the flowcharts may be modified in many different ways, as would be apparent to those having ordinary skill in the art to which the present invention pertains. Those of ordinary skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be composed of voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. To represent.

The preceding description of this application is provided to enable any person skilled in the art to make or use this application. Various modifications to the present disclosure will be readily apparent to those having ordinary skill in the art to which the invention pertains, and the general principles defined herein may be applied to other variations. Thus, the present case is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Implementation examples are described in the following numbered aspects/clauses: 1. An integrated circuit (IC) package comprising: package substrate; first die; second grain; a first plurality of die interconnects coupled to the packaging substrate and the first die to create a die standoff region between the first die and the packaging substrate; a second plurality of die interconnects disposed in the die standoff region and coupled to the packaging substrate and a second die; a cavity formed in the die standoff region between the first plurality of die interconnects and the second plurality of die interconnects; and A die-to-die (D2D) interconnect structure disposed in the cavity, the D2D interconnect structure including a plurality of D2D interconnects coupled to the first die and the second die. 2. The IC package of clause 1, wherein the plurality of D2D interconnects are not coupled to the package substrate. 3. An IC package as in any one of clauses 1 and 2, wherein: the second die is horizontally adjacent to the first die in the horizontal direction; The first active side of the first die is disposed adjacent to the packaging substrate in a vertical direction orthogonal to the horizontal direction; and The second active side of the second die is arranged adjacent to the package substrate in the vertical direction. 4. The IC package of clause 3, wherein the height of the D2D interconnect structure in the vertical direction is less than the height of the die-substrate standoff cavity in the vertical direction. 5. An IC package as in any one of clauses 3 and 4, wherein: the second die is horizontally adjacent to the first die by a separation distance to form a horizontal die separation region between the first die and the second die; and The die-substrate standoff cavity is partially disposed adjacent to the horizontal die separation region in the vertical direction. 6. The IC package of any one of clauses 3-5, wherein the heights of the first plurality of die interconnects and the second plurality of die interconnects in the vertical direction define the height of the cavity in the vertical direction high. 7. The IC package of any of clauses 3-6, wherein the D2D interconnect structure includes a redistribution layer (RDL) including at least one metal interconnect coupled to the first die and the second die . 8. The IC package of clause 7, wherein the RDL includes a plurality of metal interconnects having a line-to-space (L/S) ratio of 2/2 or less. 9. An IC package as in any one of clauses 7 and 8, wherein: the height of the first plurality of die interconnects and the second plurality of die interconnects is between 30-40 micrometers (µm); The height of the RDL is less than or equal to 7 µm; and The RDL includes a plurality of metal interconnections having a line-to-space (L/S) ratio of 2/2 or less. 10. The IC package of any one of clauses 1-9, wherein: the first die includes a first active side and a first backside; the second die includes a second active side and a second backside; a first plurality of die interconnects coupling a first active side of a first die to the packaging substrate; and A second plurality of die interconnects couples the second active side of the second die to the packaging substrate. 11. The IC package of any one of clauses 1-10, further comprising: a reconstructed die module, the reconstructed die module comprising: adjacent to the active side of the packaging substrate; including a first active side on the active side and a first die on a first backside; including a second active side on the active side and a second die on a second backside; and A molding compound is disposed adjacent to the first backside of the first die and the second backside of the second die. 12. The IC package of any one of clauses 1-11, wherein: the second die is horizontally adjacent to the first die by a separation distance to form a horizontal die separation region between the first die and the second die; The first die includes first D2D interface circuitry horizontally adjacent to the horizontal die separation region; the second die includes second D2D interface circuitry horizontally adjacent to the horizontal die separation region; first D2D interface circuitry coupled to the D2D interconnect structure; second D2D interface circuitry coupled to the D2D interconnect structure; and The D2D interconnect structure couples the first D2D interface circuitry to the second D2D interface circuitry. 13. The IC package of clause 12, wherein: The D2D interconnection structure includes one or more metallization layers, each metallization layer includes one or more metal interconnections; a first die coupled to one or more metal interconnects in the one or more metallization layers of the D2D interconnect structure; and A second die is coupled to one or more metal interconnects in the one or more metallization layers of the D2D interconnect structure. 14. The IC package of clause 13, wherein: The one or more metallization layers include one or more redistribution layers (RDLs), each RDL including one or more metal interconnects; the first die is coupled to one or more metal interconnects in the one or more RDLs of the D2D interconnect structure; and The second die is coupled to one or more metal interconnects in the one or more RDLs of the D2D interconnect structure. 15. The IC package of any one of clauses 12-14, wherein: the second die is horizontally adjacent to the first die in the horizontal direction; the first D2D interface circuitry is arranged above the cavity in a vertical direction orthogonal to the horizontal direction; and The second D2D interface circuitry is arranged above the cavity in the vertical direction. 16. An IC package as in any one of clauses 1 and -15, wherein: the first plurality of die interconnects includes a plurality of metal pillars; and The second plurality of die interconnects includes a plurality of metal pillars. 17. The IC package of any one of clauses 1-16, wherein the package substrate includes one or more metallization layers, each metallization layer including a plurality of metal interconnections; a first plurality of die interconnects coupled to one or more metal interconnects among the plurality of metal interconnects in the package substrate; and A second plurality of die interconnects is coupled to one or more metal interconnects of the plurality of metal interconnects in the package substrate. 18. An IC package according to any one of clauses 1-17, which IC package is incorporated into a device selected from the group consisting of: set-top box, entertainment unit, navigation device, communication device, fixed location data cell, mobile location data unit, global positioning system (GPS) device, mobile phone, cellular phone, smart phone, session initiation protocol (SIP) phone, tablet device, phablet phone, server, computer, portable computer, Mobile Computing Devices, Wearable Computing Devices, Desktop Computers, Personal Digital Assistants (PDAs), Monitors, Computer Monitors, Televisions, Tuners, Radios, Satellite Radios, Music Players, Digital Music Players, Portable portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft. 19. A method of manufacturing an integrated circuit (IC) package comprising: forming a die module comprising an active side, a first die comprising a first active side adjacent to the active side, and a second die comprising a second active side adjacent to the active side, the second die is horizontally adjacent to the first die; forming a die-to-die (D2D) interconnection structure adjacent to the active side of the die module, the D2D interconnection structure including a plurality of D2D interconnections; forming a first plurality of die interconnects coupled to the first active side of the first die; and forming a second plurality of die interconnects coupled to a second active side of a second die to form a cavity between the first plurality of die interconnects and the second plurality of die interconnects, and the D2D interconnects A connecting structure is arranged in the cavity; The active side of the die module is arranged on the packaging substrate, including: coupling a first plurality of die interconnects to the packaging substrate; and A second plurality of die interconnects is coupled to the packaging substrate. 20. The method of clause 19, further comprising: not coupling the plurality of D2D interconnects to the packaging substrate. 21. The method of any one of clauses 19 and 20, wherein forming the D2D interconnect structure further comprises: horizontally coupling first D2D interface circuitry in the first die to the D2D interconnect structure; and The second D2D interface circuitry in the second die is coupled to the D2D interconnect structure to couple the second D2D interface circuitry to the first D2D interface circuitry. 22. The method of any one of clauses 19-21, wherein forming the die module comprises: providing a carrier comprising a first surface; placing a first die on the first surface of the carrier; and A second die is placed on the first surface of the carrier and horizontally adjacent to the first die. 23. The method of clause 22, wherein forming the die module further comprises: applying an adhesive film to the first surface of the carrier; and in: Placing a first die on the first surface of the carrier includes: placing a first die on the adhesive film; and Placing a second die on the first surface of the carrier includes placing a second die horizontally adjacent to the first die on the adhesive film. 24. The method of any one of clauses 22 and 23, further comprising: arranging packages on the first surface of the carrier and on the first backside of the first die and the second backside of the second die plastic compound. 25. The method of clause 24, further comprising: abrading the top surface of the overmolding compound toward the first backside of the first die and the second backside of the second die. 26. The method of any one of clauses 24 and 25, further comprising: removing the carrier from the die module; and A second carrier is attached to the die module adjacent to the first backside of the first die and the second backside of the second die. 27. The method of clause 26, further comprising: forming the D2D interconnect structure in the cavity on a portion of the first active side of the first die and a portion of the second active side of the second die. 28. The method of clause 27, wherein the D2D interconnect structure is arranged vertically adjacent to a horizontal die separation region between the first die and the second die. 29. The method of any one of clauses 27 and 28, wherein forming the D2D interconnect structure comprises: forming a first redistribution layer (RDL) in the cavity on a first active side of a first die and a second active side of a second die; and One or more additional RDLs are formed on the first RDL. 30. The method of any one of clauses 27-29, further comprising: removing the second carrier from the die module. 31. The method of any one of clauses 27-30, further comprising: coupling the first plurality of die interconnects and the second plurality of die interconnects to the packaging substrate.

100: Split semiconductor die ("die") IC package 102: D2D interposer 104: Package substrate 106(1): Die 106(2): Die 108: Die separation area 110: External interconnect 112: grain interconnection 114: metal pillar 116 (1): active side 116 (2): active side 118: solder joint 120: D2D interconnection 200: package 202: D2D interconnection structure 204: support cavity 206 (1 ): Die 206(2): Die 208: Package Substrate 210: Die Interconnect 210(1): Die Interconnect 210(2): Die Interconnect 211: External Interconnect 212: Die Separation Area 214: Die Module 216: Overmolding Compound 218: Reconstituted Die 220: Dielectric Layer 222: Encapsulation Compound 224(1): Active Side 224(2): Active Side 226(1): Backside 226(2) : back side 228: grain support area 232: D2D interconnection 234 (1): D2D interface circuit system 234 (2): D2D interface circuit system 236: active side 238 (1): metal column 238 (2): metal Post 240(1): Interconnect Bump 240(2): Interconnect Bump 242(1): Metallization Layer 242(2): Metallization Layer 242(3): Metallization Layer 243(1): Metal Interconnect Connect 243(2): Metal Interconnect 243(3): Metal Interconnect 244(1): Metallization Layer 244(2): Metallization Layer 244(3): Metallization Layer 246(1): RDL 246(2 ):RDL 246(3):RDL 248(1):Metal Interconnect 248(2):Metal Interconnect 248(3):Metal Interconnect 400:Program 402:Block 404:Block 406:Block 408:Block 410: Block 412: Block 414: Block 500: Program 502: Block 504: Block 506: Block 508: Block 510: Block 512: Block 514: Block 516: Block 600A: Manufacturing Stage 600B: Manufacturing Stage 600C: Manufacturing Stage 600D: Manufacturing Stage 600E: Manufacturing Stage 600F: Manufacturing Stage 600G: Manufacturing Stage 600H: Manufacturing Stage 602: Carrier 604: First Surface 606: Reconstituted Wafer 608: Adhesive Film 612: Top Surface 614: Surface 616: Second Carrier 618: Adhesive Layer 700 : System 702: IC 704: Split IC package 706: System on Chip (SoC) 708: CPU 710: Processor 712: Cache buffer memory 714: System bus 716: Memory controller 718: Memory Array 720: memory system 722: input device 724: output device 726: network peripheral device 728: display controller 730: network 732: display 734: video processor 800: wireless communication device 802: IC 803: split type Die IC package 804: transceiver 806: capital Material processor 808: transmitter 810: receiver 812(1): digital analog converter (DAC) 812(2): digital analog converter (DAC) 814(1): low pass filter 814(2): low pass filter Pass Filter 816(1): Amplifier (AMP) 816(2): Amplifier (AMP) 818: Upconverter 820(1): Mixer 820(2): Mixer 822: Transmit (TX) Terminal Oscillator (LO) Signal Generator 824: Upconverted Signal 826: Filter 828: Power Amplifier (PA) 830: Duplexer or Switch 832: Antenna 834: Low Noise Amplifier (LNA) 836: Filter 838(1):Down conversion mixer 838(2):Down conversion mixer 840:RX LO signal generator 842(1):AMP 842(2):AMP 844(1):Low pass filter 844(2): Low-pass filter 846(1): Analog-to-digital converter (ADC) 846(2): Analog-to-digital converter (ADC) 848: TX phase-locked loop (PLL) circuit 850: RX PLL circuit A ₁ : Line A ₁ ': Line A ₂ ': Line A ₂ ': Line D ₁ : Distance D ₂ : Thickness H ₁ : Height H ₂ : Height H 3: _Height H ₄ : Height H ₅ : Height H ₆ : Height X: Axis Y: Axis Z: Axis

1A and 1B are top and cross-sectional side views, respectively, of a split semiconductor die (“die”) integrated circuit (IC) package that includes a die-to-die (D2D ) connected D2D connection intermediary;

2A and 2B are top and cross-sectional side views, respectively, of an exemplary split-die IC package employing a D2D interconnect structure in a die-substrate standoff cavity (i.e., cavity) to provide D2D connections;

3 is another side view of the split die IC package in FIG. 2B illustrating more details of the D2D interconnect structure in the cavity providing the D2D connection;

4 is a schematic diagram for fabricating a split-die IC package (including but not limited to the exemplary split-die IC package in FIGS. 2A-3 ) employing a D2D interconnect structure in the cavity to provide D2D connectivity. Flowchart of an exemplary procedure;

5A-5C are schematic diagrams for fabricating a split-die IC package (including but not limited to the exemplary split-die IC package in FIGS. A flowchart of another exemplary procedure of );

6A-6H illustrate a split die IC package (including but not limited to, FIGS. Exemplary manufacturing stages during the exemplary split-die IC package in ;

FIG. 7 is a block diagram of an example processor-based system including disassembled device(s) employing a D2D interconnect structure in a cavity to provide D2D connectivity that may be packaged according to the example fabrication process in FIGS. 4-6H . Components in fractional die IC packages, including but not limited to the exemplary split die IC packages in Figures 2A-3; and

FIG. 8 is a block diagram of an exemplary wireless communication device including disassembled device(s) employing a D2D interconnect structure in a cavity to provide D2D connectivity that may be packaged according to the exemplary manufacturing process in FIGS. 4-6H . Radio frequency (RF) components in fractional die IC packages, including but not limited to the exemplary split die IC package in FIGS. 2A-3 .

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

200: Encapsulation

202:D2D interconnect structure

204: support cavity

206(1): grain

208: Package substrate

210: Die interconnection

210(1): Die Interconnection

210(2): Die Interconnection

211: External interconnection

212: Grain separation area

214: Grain module

216: Plastic compound

218: Reconstruct the chip

220: dielectric layer

222: Encapsulation compound

224(1): active side

224(2): active side

226(1): dorsal side

226(2): dorsal side

228: grain support area

232: D2D interconnection

234(1): D2D interface circuit system

234(2):D2D interface circuit system

A ₂ : Line

A ₂ ': line

D ₁ : distance

H ₃ : Height

H ₄ : Height

H ₅ : Height

Claims (31)

An integrated circuit (IC) package comprising: a packaging substrate; a first die; a second die; a first plurality of die interconnects coupled to the packaging substrate and the first die to establish a die standoff region between the first die and the packaging substrate ; a second plurality of die interconnects disposed in the die standoff region and coupled to the packaging substrate and the second die; a cavity formed in the die standoff region between the first plurality of die interconnects and the second plurality of die interconnects; and A die-to-die (D2D) interconnect structure disposed in the cavity, the D2D interconnect structure including a plurality of D2D interconnects coupled to the first die and the second die. The IC package of claim 1, wherein the plurality of D2D interconnects are not coupled to the package substrate. Such as the IC packaging of claim item 1, wherein: the second die is horizontally adjacent to the first die in a horizontal direction; A first active side of the first die is disposed adjacent to the package substrate in a vertical direction orthogonal to the horizontal direction; and A second active side of the second die is disposed adjacent to the package substrate in the vertical direction. The IC package according to claim 3, wherein a height of the D2D interconnect structure in the vertical direction is smaller than a height of the cavity in the vertical direction. Such as the IC packaging of claim item 3, wherein: the second die is horizontally adjacent to the first die by a separation distance to form a horizontal die separation region between the first die and the second die; and The cavity is partially disposed adjacent to the horizontal die separation region in the vertical direction. The IC package according to claim 3, wherein a height of the first plurality of die interconnects and the second plurality of die interconnects in the vertical direction defines a height of the cavity in the vertical direction. The IC package of claim 1, wherein the D2D interconnect structure includes a redistribution layer (RDL), the RDL including at least one metal interconnect coupled to the first die and the second die. The IC package of claim 7, wherein the RDL includes a plurality of metal interconnections having a line-to-space (L/S) ratio of 2/2 or less. Such as the IC packaging of claim item 7, wherein: a height of the first plurality of die interconnects and the second plurality of die interconnects is between 30-40 microns (µm); The RDL has a height less than or equal to 7 µm; and The RDL includes a plurality of metal interconnections having a line-to-space (L/S) ratio of 2/2 or less. Such as the IC packaging of claim item 1, wherein: The first die includes a first active side and a first backside; The second die includes a second active side and a second backside; the first plurality of die interconnects coupling the first active side of the first die to the packaging substrate; and The second plurality of die interconnects couple the second active side of the second die to the packaging substrate. The IC package of claim 1 further includes: a reconfigured die module, the reconfigured die module includes: Adjacent to an active side of the packaging substrate; including the first die on the active side with a first active side and a first backside; including the second die on the active side with a second active side and a second backside; and A molding compound is disposed adjacent to the first backside of the first die and the second backside of the second die. Such as the IC packaging of claim item 1, wherein: The second die is horizontally adjacent to the first die by a separation distance to form a horizontal die separation region between the first die and the second die; The first die includes a first D2D interface circuitry horizontally adjacent to the horizontal die separation region; The second die includes a second D2D interface circuitry horizontally adjacent to the horizontal die separation region; the first D2D interface circuitry is coupled to the D2D interconnect structure; the second D2D interface circuitry is coupled to the D2D interconnect structure; and The D2D interconnect structure couples the first D2D interface circuitry to the second D2D interface circuitry. Such as the IC packaging of claim item 12, wherein: The D2D interconnection structure includes one or more metallization layers, each metallization layer includes one or more metal interconnections; the first die is coupled to one or more metal interconnects in the one or more metallization layers of the D2D interconnect structure; and The second die is coupled to one or more metal interconnects in the one or more metallization layers of the D2D interconnect structure. Such as the IC package of claim 13, wherein: The one or more metallization layers include one or more redistribution layers (RDLs), each RDL including one or more metal interconnects; the first die is coupled to one or more metal interconnects in the one or more RDLs of the D2D interconnect structure; and The second die is coupled to one or more metal interconnects in the one or more RDLs of the D2D interconnect structure. Such as the IC packaging of claim item 12, wherein: the second die is horizontally adjacent to the first die in a horizontal direction; the first D2D interface circuitry is arranged above the cavity in a vertical direction orthogonal to the horizontal direction; and The second D2D interface circuitry is arranged above the cavity in the vertical direction. Such as the IC packaging of claim item 1, wherein: the first plurality of die interconnects includes a plurality of metal pillars; and The second plurality of die interconnects includes a plurality of metal pillars. The IC package according to claim 1, wherein the package substrate includes one or more metallization layers, each metallization layer includes a plurality of metal interconnections; the first plurality of die interconnects coupled to one or more metal interconnects among the plurality of metal interconnects in the package substrate; and The second plurality of die interconnects is coupled to one or more metal interconnects of the plurality of metal interconnects in the package substrate. Such as the IC package of claim 1, the IC package is integrated into a device selected from the group comprising: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, A mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet device, a tablet phone, a server, A computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, A radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multi-rotor aircraft. A method of manufacturing an integrated circuit (IC) package comprising the steps of: forming a die module, the die module includes an active side, a first die including a first active side adjacent to the active side, and a second active side adjacent to the active side a second die horizontally adjacent to the first die; forming a die-to-die (D2D) interconnection structure adjacent to the active side of the die module, the D2D interconnection structure including a plurality of D2D interconnections; forming a first plurality of die interconnects coupled to the first active side of the first die; and forming a second plurality of die interconnects coupled to the second active side of the second die to form a cavity between the first plurality of die interconnects and the second plurality of die interconnects, and the D2D interconnect structure is arranged in the cavity; Disposing the active side of the die module on a packaging substrate, including: coupling the first plurality of die interconnects to the packaging substrate; and The second plurality of die interconnects are coupled to the packaging substrate. The method according to claim 19, further comprising the step of: not coupling the plurality of D2D interconnects to the packaging substrate. The method according to claim 19, wherein forming the D2D interconnection structure further comprises the following steps: horizontally coupling a first D2D interface circuitry in the first die to the D2D interconnect structure; and A second D2D interface circuitry in the second die is coupled to the D2D interconnect structure to couple the second D2D interface circuitry to the first D2D interface circuitry. The method according to claim 19, wherein forming the die module includes the following steps: providing a carrier including a first surface; placing the first die on the first surface of the carrier; and The second die is positioned on the first surface of the carrier and horizontally adjacent to the first die. The method of claim 22, wherein forming the die module further comprises the following steps: applying an adhesive film to the first surface of the carrier; and in: Placing the first die on the first surface of the carrier includes: placing the first die on the adhesive film; and Placing the second die on the first surface of the carrier includes placing the second die horizontally adjacent to the first die on the adhesive film. As the method of claim 22, further comprising the steps of: arranging a package on the first surface of the carrier and on a first backside of the first die and a second backside of the second die plastic compound. The method of claim 24, further comprising the step of: grinding away a top surface of the overmolding compound toward the first backside of the first die and the second backside of the second die. As the method of claim 24, further comprising the following steps: removing the carrier from the die module; and A second carrier is attached to the die module adjacent to the first backside of the first die and the second backside of the second die. The method of claim 26, further comprising the step of: forming the D2D interconnection in the cavity on a portion of the first active side of the first die and a portion of the second active side of the second die structure. The method of claim 27, wherein the D2D interconnect structure is arranged vertically adjacent to a horizontal die separation region between the first die and the second die. The method according to claim 27, wherein forming the D2D interconnection structure includes the following steps: forming a first redistribution layer (RDL) in the cavity on the first active side of the first die and the second active side of the second die; and One or more additional RDLs are formed on the first RDL. The method according to claim 27, further comprising the step of: removing the second carrier from the die module. The method of claim 27, further comprising the step of: coupling the first plurality of die interconnects and the second plurality of die interconnects to the packaging substrate.

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