TW202303904A - Semiconductor package structure - Google Patents

Abstract

A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property(IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

Description

Semiconductor Package Structure

The invention relates to semiconductor packaging technology, in particular to a semiconductor packaging structure.

As the demand for more functionality and smaller devices continues to increase, package-on-package (PoP) technology, in which two or more packages are stacked vertically, is becoming more and more popular. PoP technology reduces the length of wires between different components such as controllers and storage devices. This provides better electrical performance because shorter interconnect traces result in faster signal propagation and reduce noise and crosstalk artifacts.

Although existing semiconductor packaging structures are generally adequate, they are not satisfactory in every respect. For example, meeting channel requirements for integrating different components into one package is a challenge. Therefore, there is a need to further improve the semiconductor package structure to provide flexibility in channel design.

According to some embodiments, a semiconductor package structure is provided. The semiconductor packaging structure includes a front-side wiring-focused layer, a stack structure, a back-side wiring-focused layer, a first IP core and a second IP core. The stack structure is disposed over the front heavy wiring layer and includes a first semiconductor die and a second semiconductor die over the first semiconductor die. The rear-side wiring layer is disposed above the stack structure. The first IP core is configured in the stack structure and is electrically coupled to the front-side heavy wiring layer through the first routing channel. The second IP core is configured in the stack structure and is electrically coupled to the rear heavy wiring layer through the second routing channel, wherein the second routing channel is separated from the first routing channel and is electrically insulated from the front heavy wiring layer.

According to some embodiments, there is provided a semiconductor wiring structure. The semiconductor wiring structure includes a first package structure, a first wiring channel and a second wiring channel. The first package structure has a front side and a back side, and includes a stack structure having a first IP core and a second IP core. The first routing channel electrically couples the first IP core to the first redistribution layer on the front side of the first package structure. The second routing channel independently electrically couples the second IP core to the second redistribution layer on the rear side of the first package structure, wherein the second routing channel is separated from the first routing channel and electrically connected to the first redistribution layer. insulation.

The following embodiments will be described in detail with reference to the accompanying drawings.

The following description is of the best contemplated mode of carrying out the invention. The description is made to illustrate the general principles of the invention and should not be construed as limiting. The scope of the invention is determined by reference to the appended claims.

The present invention will be described in connection with specific embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims. The drawings described are only schematic and non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and relative dimensions do not correspond to actual dimensions in the practice of the invention.

A semiconductor package structure and a semiconductor wiring structure are described according to some embodiments of the present disclosure. The semiconductor packaging structure provides separate routing channels for devices and IP cores (such as memory devices and memory IP cores), thereby improving the flexibility of routing channel design.

FIG. 1 is a cross-sectional view of a semiconductor package structure 100 according to some embodiments of the present disclosure. Additional features may be added to semiconductor package structure 100 . For different embodiments, some of the features described below may be replaced or eliminated. For simplicity of illustration, only a part of the semiconductor package structure 100 is shown.

As shown in FIG. 1 , according to some embodiments, a semiconductor package structure 100 includes a first package structure 100 a and a second package structure 100 b stacked vertically. The first package structure 100a has a front side and a back side opposite to the front side. The first package structure 100a has a first redistribution layer 102 on its front side and a second redistribution layer 124 on its rear side. Therefore, the first redistribution layer 102 may also be referred to as a front redistribution layer 102 , and the second redistribution layer 124 may also be referred to as a rear redistribution layer 124 .

The first redistribution layer 102 includes one or more conductive layers and a passivation layer, wherein the one or more conductive layers may be disposed in the one or more passivation layers. The conductive layer may include metals such as copper, titanium, tungsten, aluminum, etc. or combinations thereof. In some embodiments, the passivation layer includes a polymer layer, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, etc., or combinations thereof. Alternatively, the passivation layer may include a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination thereof. The material of the second redistribution layer 124 may be similar to the material of the first redistribution layer 102 , which will not be repeated here.

As shown in FIG. 1 , according to some embodiments, the first redistribution layer 102 includes more conductive layers and passivation layers than the second redistribution layer 124 . The first redistribution layer 102 may be thicker than the second redistribution layer 124, but the present disclosure is not limited thereto. For example, the second redistribution layer 124 may be thicker than or substantially equal to the first redistribution layer 102 .

In some embodiments, the first package structure 100 a includes a plurality of conductive structures 104 located under the first redistribution layer 102 and electrically coupled to the first redistribution layer 102 . In some embodiments, the conductive structure 104 includes a conductive material, for example, the metal conductive structure 104 may include microbumps, controlled collapse die attach (C4) bumps, ball grid array (BGA) balls, etc., or combinations thereof.

In some embodiments, the first package structure 100 a includes a stack structure including a first semiconductor die 106 and a second semiconductor die 112 vertically stacked above the first redistribution layer 102 . According to some embodiments, the first semiconductor die 106 and the second semiconductor die 112 each independently comprise a system on chip device (SoC), a logic device, a memory device, a radio frequency (RF) device, etc., or any combination thereof. For example, first semiconductor die 106 and second semiconductor die 112 may each independently include a microcontroller unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, Global Positioning System (GPS) devices, central processing unit (CPU) bare die, graphics processing unit (GPU) die, input and output (IO) die, dynamic random access memory (DRAM) IP core, static random access Memory (SRAM), High Bandwidth Memory (HBM), etc., or any combination thereof.

Although two semiconductor dies, first semiconductor die 106 and second semiconductor die 112 , are shown in FIG. 1 , there may be more than two semiconductor dies. For example, a stacked structure may include three semiconductor dies stacked vertically. Alternatively, the stacked structure may include four semiconductor dies, wherein two semiconductor dies are vertically stacked above one semiconductor die, and another semiconductor die is disposed above the semiconductor die and adjacent to the two semiconductor dies. In some embodiments, the stack structure further includes one or more passive components (not shown), such as resistors, capacitors, inductors, etc. or combinations thereof.

Referring to FIG. 1 , the first semiconductor die 106 includes a plurality of vias 108 electrically coupled to the first redistribution layer 102 . Vias 108 may be formed of a conductive material such as metal. For example, vias 108 may be formed of copper. In FIG. 1 , the via 108 has substantially vertical sidewalls and extends from the top surface of the first semiconductor die 106 to the bottom surface of the first semiconductor die 106 , but the disclosure is not limited thereto. The vias 108 in the first semiconductor die 106 may have other configurations and numbers.

In some embodiments, the first package structure 100 a includes a third redistribution layer 110 located between the first redistribution layer 102 and the second redistribution layer 124 . As shown in FIG. 1, the third redistribution layer 110 may be disposed between the top surface of the first semiconductor die 106 and the bottom surface of the second semiconductor die 112, and may extend beyond the sidewalls and the bottom surface of the first semiconductor die 106. the sidewall of the second semiconductor die 112 . The third redistribution layer 110 may be electrically coupled to the first semiconductor die 106 , the vias 108 in the first semiconductor die 106 , and the second semiconductor die 112 .

The material of the third redistribution layer 110 may be similar to the material of the first redistribution layer 102 , which will not be repeated here. As shown in FIG. 1, the first redistribution layer 102 includes more conductive layers and passivation layers than the third redistribution layer 110, and the third redistribution layer 110 includes more conductive layers than the second redistribution layer 124. and passivation layers, but the disclosure is not limited thereto. For example, the second redistribution layer 124 may include more conductive layers and passivation layers than the first redistribution layer 102 and the third redistribution layer 110 .

By setting the third rewiring layer 110, an additional wiring channel can be formed between the first semiconductor die 106 and the second semiconductor die 112, which facilitates layout planning flexibility and saves die bump fan-out width , as described below and illustrated in Figures 2A-2D.

FIG. 2A is a cross-sectional view of a stack structure 200a in the semiconductor package structure 100 according to some embodiments. For simplicity, only a part of the stack structure 200a is shown. In some embodiments, the stack structure 200a includes the first semiconductor die 106 and the second semiconductor die 112 .

The first semiconductor die 106 has an active surface 106a and a backside surface 106b opposite to the active surface 106a. The second semiconductor die 112 has an active surface 112a and a backside surface 112b opposite to the active surface 112a. The first semiconductor die 106 and the second semiconductor die 112 may be stacked face to face (FtF). That is, the active surface 112 a of the second semiconductor die 112 is close to the active surface 106 a of the first semiconductor die 106 .

Referring to FIG. 2A , a first intellectual property (intellectual property, IP) core 101 and a second IP core 103 may be disposed on the active surface 106 a of the first semiconductor die 106 . In some embodiments, the first IP core 101 is used to control the second package structure 100 b (as shown in FIG. 1 ), and the second IP core 103 is used to control other components electrically coupled to the first redistribution layer 102 .

According to some embodiments, since the third redistribution layer 110 is disposed between the first semiconductor die 106 and the second semiconductor die 112 , additional routing channels may be formed therebetween. Therefore, the signal from the first IP core 101 and the signal from the second IP core 103 may pass through different routing channels, for example, as shown by paths 101P and 103P respectively. Specifically, the routing channel of the first IP core 101 (indicated by the path 101P) can pass through the third redistribution layer 110 (as shown in Figure 1), and the routing channel of the second IP core 103 (indicated by the path 103P) The via hole 108 in the first semiconductor die 106 and the first redistribution layer 102 (as shown in FIG. 1 ) may pass through.

That is, compared with the routing channel of the first IP core 101 and the routing channel of the second IP core 103 passing through the first redistribution layer 102, in the present invention, the first IP core 101 and the second IP core 103 are provided with their respective wiring channels. In this way, these routing channels can be individually optimized to meet different channel requirements. In addition, the routing channels of the first IP core 101 will not affect the routing channels of the second IP core 103, thereby increasing the flexibility of channel design.

As shown in FIG. 2A, the first IP core 101 and the second IP core 103 are arranged side by side separately, but the present disclosure is not limited thereto. For example, according to some other embodiments, the first IP core 101 may be placed in the second IP core 103 . Alternatively, the first IP core 101 and the second IP core 103 may be disposed near different edges of the first semiconductor die 102 . In addition, there can be more than two IP cores.

FIG. 2B is a cross-sectional view of a stack structure 200b in the semiconductor package structure 100 according to some embodiments. To simplify the drawing, only a part of the stack structure 200b is shown. The stack structure 200b may include the same or similar elements as the stack structure 200a shown in FIG. 2A, and for the sake of simplicity, those elements will not be discussed in detail. In the following embodiments, the first IP core 101 is disposed on the active surface 112 a of the second semiconductor die 112 , and the second IP core 103 is disposed on the active surface 106 a of the first semiconductor die 106 .

As shown in FIG. 2B , the signal from the first IP core 101 and the signal from the second IP core 103 may pass through different routing channels, for example, as shown in path 101P and path 103P respectively. Specifically, the routing channel of the first IP core 101 (indicated by the path 101P) can pass through the third redistribution layer 110 (as shown in Figure 1), and the routing channel of the second IP core 103 (indicated by the path 103P) The via hole 108 in the first semiconductor die 106 and the first redistribution layer 102 (as shown in FIG. 1 ) may pass through.

FIG. 2C is a cross-sectional view of a stack structure 200c in the semiconductor package structure 100 according to some embodiments. To simplify the schematic diagram, only a part of the stack structure 200c is shown. The stack structure 200c may include the same or similar elements as the stack structure 200a shown in FIG. 2A, and for simplicity, those elements will not be discussed in detail. In the following embodiments, the first semiconductor die 106 and the second semiconductor die 112 may be stacked face to back (FtB). That is, the active surface 112 a of the second semiconductor die 112 is close to the backside surface 106 b of the first semiconductor die 106 .

As shown in FIG. 2C , the first IP core 101 and the second IP core 103 are disposed on the active surface 106 a of the first semiconductor die 106 . Signals from the first IP core 101 and signals from the second IP core 103 may pass through different routing channels. For example, indicated by path 101P and path 103P, respectively. Specifically, the routing channel (represented by the path 101P) of the first IP core 101 can pass through the via hole 108 in the first semiconductor die 106 and the third redistribution layer 110 (as shown in FIG. The wire channel of the second IP core 103 (indicated by path 103P) may pass through the first redistribution layer 102 (as shown in FIG. 1 ).

FIG. 2D is a cross-sectional view of a stack structure 200d in the semiconductor package structure 100 according to some embodiments. For simplicity of illustration, only a part of the stack structure 200d is shown. The stack structure 200d may include the same or similar elements as the stack structure 200a shown in FIG. 2A and for simplicity, those elements will not be discussed in detail. In the following embodiments, the first IP core 101 is disposed on the active surface 112 a of the second semiconductor die 112 , and the second IP core 103 is disposed on the active surface 106 a of the first semiconductor die 106 .

As shown in FIG. 2D , the signal from the first IP core 101 and the signal from the second IP core 103 may pass through different routing channels, for example, as shown in path 101P and path 103P respectively. Specifically, the routing channel of the first IP core 101 (indicated by the path 101P) can pass through the third redistribution layer 110 (as shown in Figure 1), and the routing channel of the second IP core 103 (indicated by the path 103P) It may pass through the first redistribution layer 102 (as shown in FIG. 1 ).

Referring to FIG. 1 , according to some embodiments, a plurality of conductive structures 114 are formed between the third redistribution layer 110 and the second semiconductor die 112 . The conductive structure 114 can electrically couple the second semiconductor die 112 to the third redistribution layer 110 . Depending on the routing channel design and the location of the IP core, the routing channel may also include conductive structures 114 .

In some embodiments, conductive structure 114 includes a conductive material, such as metal. The conductive structures 114 may include microbumps, controlled collapse die attach (C4) bumps, ball grid array (BGA) balls, etc., or combinations thereof.

In some embodiments, an underfill material 116 is formed between the second semiconductor die 112 and the third redistribution layer 110 and fills gaps between the conductive structures 114 to provide structural support. Underfill material 116 may surround each conductive structure 114 . In some embodiments, underfill material 116 is formed of a polymer, such as epoxy. After forming the conductive structure 114 between the second semiconductor die 112 and the third redistribution layer 110 , an underfill material 116 may be applied by capillary force. Underfill material 116 may then be cured by any suitable curing process.

As shown in FIG. 1 , the first package structure 100 a includes a molding material 118 surrounding the second semiconductor die 112 and the underfill material 116 and covering part of the top surface of the third redistribution layer 110 . In some embodiments, the molding material 118 adjoins the sidewalls of the second semiconductor die 112 and the top surface of the third redistribution layer 110 . The molding material 118 may protect the second semiconductor die 112 from the environment, thereby preventing damage to the second semiconductor die 112 due to, for example, stress, chemicals, and/or moisture.

The molding material 118 may include a non-conductive material such as a moldable polymer, epoxy, resin, etc., or combinations thereof. In some embodiments, molding material 118 is applied in liquid or semi-liquid form and then cured by any suitable curing process, such as a thermal curing process, UV curing process, etc., or combinations thereof. Molding material 118 may be shaped or molded with a mold (not shown).

Then, the molding material 118 may be partially removed by a planarization process, such as chemical mechanical polishing (CMP), until the top surface of the second semiconductor die 112 is exposed. In some embodiments, the top surface of the molding material 118 and the top surface of the second semiconductor die 112 are substantially coplanar. As shown in FIG. 1 , the sidewalls of the molding material 118 may be coplanar with the sidewalls of the first semiconductor die 106 .

In some embodiments, a plurality of conductive pillars 120 are formed adjacent to the stack structure (including the first semiconductor die 106 and the second semiconductor die 112 ) and the molding material 118 . The conductive pillars 120 may include metal pillars, such as copper pillars. In some embodiments, the conductive pillars 120 are formed by an electroplating process or any other suitable process. As shown in FIG. 1 , the conductive pillar 120 may have substantially vertical sidewalls.

As shown in FIG. 1 , the conductive pillar 120 may be disposed between the first redistribution layer 102 and the second redistribution layer 124 , and may be disposed on top and bottom surfaces of the third redistribution layer 110 . The conductive pillar 120 can be electrically coupled to the first redistribution layer 102 , the second redistribution layer 124 and the third redistribution layer 110 .

The position and quantity of the conductive pillars 120 can be adjusted according to the wiring design of the first package structure 100a. For example, in some other embodiments, the conductive pillar 120 is disposed between the second redistribution layer 124 and the third redistribution layer 110 , but not between the first redistribution layer 102 and the third redistribution layer 110 . The second redistribution layer 124 is electrically coupled to the third redistribution layer 110 through the conductive pillar 120 , and the third redistribution layer 110 is electrically coupled to the first redistribution layer 102 through the via 108 in the first semiconductor die 106 .

As shown in FIG. 1 , four conductive pillars 120 are disposed on opposite sides of the stacked structure, but the present disclosure is not limited thereto. For example, the number of conductive pillars 120 on opposite sides of the stack structure may be different. Alternatively, the conductive pillar 120 may be disposed on one side of the stacked structure.

As shown in FIG. 1 , the first package structure 100 a includes a molding material 122 surrounding the stack structure (including the first semiconductor die 106 and the second semiconductor die 112 ), the molding material 118 and the conductive pillars 120 . The molding material 122 may fill the conductive pillar 120 and the gap between the stacked structure and the conductive pillar 120 .

As shown in FIG. 1, the molding material 122 is adjacent to the sidewalls of the first semiconductor die 106 and the molding material 118, and covers the top surface of the first redistribution layer 102, the bottom surface of the second redistribution layer 124 and the third layer The top surface and the bottom surface of the wiring layer 110. The molding material 122 can protect the stacked structure and the conductive pillars 120 from environmental influences, thereby preventing the stacked structure and the conductive pillars 120 from being damaged due to stress, chemicals, and/or moisture, for example.

In some embodiments, molding material 122 includes a non-conductive material, such as a moldable polymer, epoxy, resin, etc., or combinations thereof. In some embodiments, the molding material 122 is applied in a liquid or semi-liquid form and then cured by any suitable curing process, such as a thermal curing process, a UV curing process, etc., or a combination thereof. The molding material 122 may be shaped or molded with a mold (not shown).

Then, the molding material 122 may be partially removed through a planarization process, such as chemical mechanical polishing (CMP), until the top surfaces of the conductive pillars 120 are exposed. In some embodiments, the molding material 122 and the top surfaces of the conductive pillars 120 are substantially coplanar. as the picture shows. As shown in FIG. 1 , the sidewalls of the molding material 122 may be coplanar with at least one of the sidewalls of the first redistribution layer 102 , the second redistribution layer 124 and the third redistribution layer 110 .

As shown in FIG. 1 , the second redistribution layer 124 may be disposed above the stacked structure and cover the top surface of the second semiconductor die 112 , the top surface of the conductive pillar 120 and the top surface of the molding material 122 .

As shown in FIG. 1 , according to some embodiments, the second encapsulation structure 100 b is disposed above the first encapsulation structure 100 a and is electrically coupled to the second redistribution layer 124 through a plurality of conductive structures 126 . In some embodiments, conductive structure 126 includes a conductive material, such as metal. The conductive structures 126 may include microbumps, controlled collapse die attach (C4) bumps, ball grid array (BGA) balls, etc., or combinations thereof.

As shown in FIG. 1 , according to some embodiments, the second package structure 100 b includes a substrate 128 . The substrate 128 may have a wiring structure therein. In some embodiments, the wiring structure of the substrate 128 includes a conductive layer, a conductive via, a conductive pillar, etc., or a combination thereof. The wiring structure of the substrate 128 may be formed of metal, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof.

The wiring structure of the substrate 128 may be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer may be formed of organic materials (eg, polymer substrates), non-organic materials (eg, silicon nitride, silicon oxide, silicon oxynitride, etc.), or combinations thereof. Any desired semiconductor elements may be formed in and on substrate 128 . However, for simplicity of illustration, only the flat substrate 128 is shown.

As shown in FIG. 1 , according to some embodiments, the second package structure 100b includes semiconductor elements 130 and 132 over the substrate 128 . Semiconductor elements 130 and 132 may include memory die, such as dynamic random access memory (DRAM). For example, semiconductor elements 130 and 132 may be double data rate (DDR) synchronous dynamic random access memory (SDRAM) dies for mobile systems. In an embodiment where the second package structure 100b includes a memory device, the IP core (eg, the first IP core 101 ) used in the second package structure 100b may be referred to as a memory IP core.

Semiconductor elements 130 and 132 may comprise the same or different devices. In some embodiments, the second package structure 100b further includes one or more passive components (not shown), such as resistors, capacitors, inductors, etc. or combinations thereof.

The first IP core 101 in the stack structure (as shown in FIGS. 2A-2D ) can be electrically coupled to the second package structure 100b through the first wiring channel, the first wiring channel includes the third redistribution layer 110, the conductive pillar 120 and the second redistribution layer 124 . The second IP core 103 in the stack structure (shown in FIGS. 2A-2D ) can be electrically coupled to the conductive structure 104 through the second routing channel including the first redistribution layer 110 . In an embodiment, according to the location of the IP core, as described above, the first routing channel or the second routing channel may further include the via 108 and/or the conductive structure 114 in the first semiconductor die 106 .

In other words, the routing channel between the IP core and the second package structure 100b may be separated from other routing channels, such as the routing channel between another IP core and the conductive structure 104 . Specifically, according to some embodiments, the routing channel between the IP core and the second package structure 100b is electrically insulated from the first redistribution layer 110 . Therefore, different routing channels can be optimized separately, increasing the flexibility of channel design.

FIG. 3 is a cross-sectional view of a semiconductor package structure 300 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 300 may include the same or similar components as the semiconductor package structure 100 shown in FIG. 1 . For simplicity, these elements will not be discussed in detail. In the following embodiments, the routing channel includes conductive pillars 134 over the first semiconductor die 106 and adjacent to the second semiconductor die 112 .

According to some embodiments, the conductive pillars 134 are electrically coupled to the second redistribution layer 124 , the first semiconductor die 106 , and the vias 108 in the first semiconductor die 106 . In an embodiment where the IP core for the second package structure 100b is formed on the bottom of the first semiconductor die 106, the routing channels between the IP core and the second package structure 100b may include vias in the first semiconductor die 106. The hole 108 , the conductive pillar 134 and the second redistribution layer 124 . In the embodiment in which the IP core for the second package structure 100b is formed on top of the first semiconductor die 106, the routing channel between the IP core and the second package structure 100b includes the conductive pillars 134 and the second redistribution layer 124 .

The conductive posts 134 may include metal posts, such as copper posts. In some embodiments, the conductive pillars 134 are formed by an electroplating process or any other suitable process. The conductive pillar 134 may have substantially vertical sidewalls. As shown in FIG. 3 , the conductive posts 134 may be surrounded by the molding material 118 . Conductive posts 134 may have substantially vertical sidewalls and may extend from a bottom surface of molding material 118 to a top surface of molding material 118 .

The position and quantity of the conductive pillars 134 can be adjusted according to the wiring design of the first package structure 100a. For example, more than one conductive pillar 134 may be disposed over the first semiconductor die 106 and may be disposed adjacent to one side or an opposite side of the second semiconductor die 112 . In addition, the semiconductor package structure 300 may further include one or more redistribution layers, such as the third redistribution layer 110 in FIG. 1 .

FIG. 4 is a cross-sectional view of a semiconductor package structure 400 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 400 may include the same or similar components as the semiconductor package structure 100 shown in FIG. 1 . For simplicity, these elements will not be discussed in detail. In the following embodiments, the routing channel includes a via 136 in the second semiconductor die 112 .

The via 136 may be electrically coupled to the second redistribution layer 124 , the conductive structure 114 , the first semiconductor die 106 , and the via 108 in the first semiconductor die 106 . In an embodiment where the IP core for the second package structure 100b is formed on the bottom of the first semiconductor die 106, the routing channel between the IP core and the second package structure 100b may include The via hole 108 , the conductive structure 114 , the via hole 136 , and the second redistribution layer 124 . In an embodiment where the IP core for the second package structure 100b is formed on top of the first semiconductor die 106, the routing path between the IP core and the second package structure 100b may include conductive structures 114, vias 136 and the second redistribution layer 124 .

In an embodiment in which the IP core for the second package structure 100b is formed on the bottom of the second semiconductor die 112, the routing path between the IP core and the second package structure 100b may include vias 136 and a second redistribution layer 124. In an embodiment where the IP core for the second package structure 100b is formed on top of the second semiconductor die 112, the routing path between the IP core and the second package structure 100b may include a second redistribution layer 124, and Vias 136 may be omitted.

In these embodiments, the routing channel between the second redistribution layer 124 and the IP core does not extend beyond the first semiconductor die 106 and the second semiconductor die 112 . In particular, the routing channel between the second redistribution layer 124 and the IP core passes through the area shielded by the first semiconductor die 106 and/or the second semiconductor die 112 .

Vias 136 may be formed of any conductive material, such as metal. Vias 136 are formed of copper, for example. As shown in FIG. 4 , the via 136 may have substantially vertical sidewalls and may extend from the top surface of the second semiconductor die 112 to the bottom surface of the second semiconductor die 112 , but the disclosure is not limited thereto. The vias 136 in the second semiconductor die 112 may have other configurations.

The position and quantity of the through holes 136 can be adjusted according to the wiring design of the first package structure 100a. For example, more than one via 136 may be provided in the second semiconductor die 112 . Alternatively, the semiconductor package structure 400 may further include one or more redistribution layers (such as the third redistribution layer 110 in FIG. 1 ) and/or one or more conductive pillars (such as the conductive pillar 134 in FIG. 3 ). .

FIG. 5 is a cross-sectional view of a semiconductor package structure 500 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 500 may include the same or similar components as the semiconductor package structure 100 shown in FIG. 1 . For simplicity, these elements will not be discussed in detail. In the following embodiments, the larger first semiconductor die 106 is disposed over the smaller second semiconductor die 112 .

As shown in FIG. 5 , the second semiconductor die 112 may include a plurality of vias 138 that may be electrically coupled to the first redistribution layer 102 , the conductive structure 114 , and the vias 108 in the first semiconductor die 106 . Vias 138 may be formed of any conductive material, such as metal. For example, vias 138 may be formed of copper. As shown in FIG. 5 , vias 138 may each have substantially vertical sidewalls and may extend from the top surface of second semiconductor die 112 to the bottom surface of second semiconductor die 112 . However, the vias 138 in the second semiconductor die 112 may have other configurations and numbers.

The via 138 may be electrically coupled to the first redistribution layer 102 , the conductive structure 114 , the first semiconductor die 106 , and the via 108 in the first semiconductor die 106 . In the embodiment in which the IP core for the second package structure 100b is formed on the bottom of the second semiconductor die 112, the routing channel between the IP core and the second package structure 100b may include a channel in the second semiconductor die 112. The hole 138 , the conductive structure 114 , the via 108 in the first semiconductor die 106 , and the second redistribution layer 124 . In an embodiment where the IP core for the second package structure 100b is formed on top of the second semiconductor die 112, the routing path between the IP core and the second package structure 100b may include the conductive structure 114, the first semiconductor die The via 108 in 106 and the second redistribution layer 124 .

In an embodiment where the IP core for the second package structure 100b is formed on the bottom of the first semiconductor die 106, the routing channels between the IP core and the second package structure 100b may include vias in the first semiconductor die 106. holes 108 and the second redistribution layer 124 . In an embodiment where the IP core for the second package structure 100b is formed on top of the first semiconductor die 106, the routing path between the IP core and the second package structure 100b may include the second redistribution layer 124 through Holes 108 may be omitted.

In these embodiments, the routing channel between the second redistribution layer 124 and the IP core does not extend beyond the first semiconductor die 106 and the second semiconductor die 112 . In particular, the routing channel between the second redistribution layer 124 and the IP core passes through the area shielded by the first semiconductor die 106 and/or the second semiconductor die 112 .

As shown in FIG. 5 , the first package structure 100 a may include one or more conductive pillars 140 under the first semiconductor die 106 and adjacent to the second semiconductor die 112 . Conductive posts 140 are optional. The conductive pillars 140 may include metal pillars, such as copper pillars. In some embodiments, the conductive pillars 140 are formed by an electroplating process or any other suitable process.

The conductive pillars 140 can be electrically coupled to the first redistribution layer 102 , the first semiconductor die 106 , and the vias 108 of the first semiconductor die 106 . Referring to FIG. 5, each conductive pillar 140 may have a substantially vertical sidewall. The conductive posts 140 may be surrounded by the molding material 118 and extend from the top surface of the molding material 118 to the bottom surface of the molding material 118 .

The position and quantity of the conductive pillars 140 can be adjusted according to the wiring design of the first package structure 100a. As shown in FIG. 5 , two conductive pillars 140 are disposed adjacent to opposite sides of the second semiconductor die 112 , but the disclosure is not limited thereto. For example, the number of conductive pillars 140 on opposite sides of the stack may be different. Alternatively, the conductive pillar 140 may be disposed on one side of the stacked structure.

FIG. 6 is a cross-sectional view of a semiconductor package structure 600 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 600 may include the same or similar elements as the semiconductor package structure 100 shown in FIG. 1 . For simplicity, these elements will not be discussed in detail. In the following embodiments, the stack structure includes a plurality of semiconductor elements 142 , 144 , 146 located above the first semiconductor die 106 and adjacent to the second semiconductor die 112 .

The semiconductor elements 142, 144, 146 may comprise active elements. For example, semiconductor components 142 , 144 , 146 may each independently include a system-on-chip device (SoC), a logic device, a memory device, a radio frequency (RF) device, etc., or any combination thereof. For example, semiconductor components 142, 144, 146 may each independently include a microcontroller unit (MCU) device, a microprocessor unit (MPU) device, a power management integrated circuit (PMIC) device, a global positioning system (GPS) device, a central Processing unit (CPU) die, graphics processing unit (GPU) die, input and output (IO) die, dynamic random access memory (DRAM) IP core, static random access memory (SRAM), high bandwidth memory body (HBM), etc., or any combination thereof.

In some other embodiments, the semiconductor elements 142, 144, 146 include passive elements, such as resistors, capacitors, inductors, etc., or combinations thereof. The semiconductor components 142, 144, 146 may comprise the same or different devices.

The semiconductor elements 142 , 144 , 146 may be electrically coupled to the first semiconductor die 106 . Each of the semiconductor elements 142 , 144 , 146 may be surrounded and covered by the molding material 118 . It should be noted that the locations and numbers of the semiconductor elements 142 , 144 , 146 , the first semiconductor die 106 and the second semiconductor die 112 are exemplary only, and the present disclosure is not limited thereto.

For example, semiconductor elements 142, 144, 146 may be stacked vertically. Alternatively, the stacked structure may include two semiconductor elements stacked vertically. In some other embodiments, the stack structure may include four semiconductor elements, wherein two semiconductor elements are vertically stacked above one semiconductor element, and another semiconductor element is disposed above the semiconductor element and adjacent to the two semiconductor elements.

According to the routing design of the first package structure 100a, the semiconductor package structure 600 may further include one or more redistribution layers (for example, the third redistribution layer 110 in FIG. 1 ), one or more conductive pillars (for example, the third The conductive pillar 134 in the figure) and/or one or more vias in the semiconductor wafer (such as the via 136 in FIG. 4).

FIG. 7 is a cross-sectional view of a semiconductor package structure 700 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 700 may include the same or similar components as the semiconductor package structure 600 shown in FIG. 6 . For simplicity, these elements will not be discussed in detail. In the following embodiments, the stack structure includes a plurality of semiconductor elements 142 , 144 , 146 below the first semiconductor die 106 and adjacent to the second semiconductor die 112 .

The semiconductor elements 142 , 144 , 146 can be similar to the semiconductor elements 142 , 144 , 146 in FIG. 6 , and will not be repeated here. The semiconductor devices 142 , 144 , 146 are electrically coupled to the first semiconductor die 106 . Each of the semiconductor elements 142 , 144 , 146 may be surrounded and covered by the molding material 118 . It should be noted that the number and positions of the semiconductor elements 142 , 144 , 146 , the first semiconductor die 106 and the second semiconductor die 112 in this embodiment are only illustrative, and the disclosure is not limited thereto.

For example, semiconductor elements 142, 144, 146 may be stacked vertically. Alternatively, the stacked structure may include two semiconductor elements stacked vertically. In some other embodiments, the stack structure may include four semiconductor elements, wherein two semiconductor elements are vertically stacked above one semiconductor element, and another semiconductor element is disposed above the semiconductor element and adjacent to the two semiconductor elements.

According to the wiring design of the first package structure 100a, the semiconductor package structure 700 may further include one or more redistribution layers (for example, the third redistribution layer 110 in FIG. 1 ), one or more conductive pillars (for example, the third The conductive pillar 134 in the figure) and/or one or more vias in the semiconductor die (eg, the via 136 in FIG. 4 ).

In short, by setting one or more redistribution layers, one or more conductive pillars and/or one or more via holes in the semiconductor die in the package structure, the IP core in the package structure can be transferred to another package structure. separate routing channels. Therefore, routing channels can be optimized individually, increasing the flexibility of channel design.

While the present invention has been described by way of examples and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as will be apparent to those skilled in the art. Accordingly, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

100, 300, 400, 500, 600, 700: Semiconductor package structure 100a: first package purchase 100b: the second package structure 101: The first IP core 101P, 103P: path 102: The first rewiring layer 103: The second IP core 104, 114, 126: conductive structure 106:The first semiconductor die 106a, 112a: active surfaces 106b, 112b: rear side 108: Through hole 110: The third rewiring layer 112: The second semiconductor die 116: Underfill material 118, 122: Molding material 120, 136, 134: conductive column 124: Second rewiring layer 128: Substrate 130, 132: semiconductor components 200a, 200b, 200c, 200d: stacked structure 142, 144, 146: semiconductor components 138: Through hole

The present invention can be more fully understood from the ensuing detailed description and examples when read in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments; 2A-2D are cross-sectional views of stacked structures in exemplary semiconductor packaging structures according to some embodiments; Figure 3 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments; 4 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments; FIG. 5 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments; FIG. 6 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments; and FIG. 7 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

100: Semiconductor package structure

100a: first package purchase

100b: the second package structure

102: The first rewiring layer

104, 114, 126: conductive structure

106:The first semiconductor die

108: Through hole

110: The third rewiring layer

112: The second semiconductor die

116: Underfill material

118, 122: Molding material

120: Conductive column

124: Second rewiring layer

128: Substrate

130, 132: semiconductor components

Claims (20)

A semiconductor packaging structure, comprising: One front focuses on the wiring layer; a stack structure disposed above the front heavy wiring layer and including a first semiconductor die and a second semiconductor die located above the first semiconductor die; a rear-focused wiring layer, disposed on the stacked structure; a first IP core, disposed in the stack structure, and electrically coupled to the front-side heavy wiring layer through a first routing channel; and A second IP core is arranged in the stack structure and is electrically coupled to the rear wiring layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and is separated from the front Focus on the electrical insulation of the wiring layer. The semiconductor package structure according to claim 1, further comprising a package structure disposed above the rear wiring-focused layer and electrically coupled to the second IP core through the second wiring channel. The semiconductor package structure as claimed in item 1, wherein the second wiring channel comprises: a conductive post adjacent to the stack structure and electrically coupled to the rear weighted wiring layer; and A third redistribution layer is located between the top surface of the first semiconductor die and the bottom surface of the second semiconductor die and is electrically coupled to the conductive pillar. The semiconductor package structure as claimed in claim 3, wherein the second routing channel further includes a plurality of vias located in the first semiconductor die. The semiconductor package structure according to claim 3, further comprising a molding material surrounding the conductive pillar and the stacked structure, wherein sidewalls of the molding material are coplanar with sidewalls of the third redistribution layer. The semiconductor package structure as claimed in claim 1, wherein the second routing channel includes a conductive pillar disposed above the first semiconductor die and adjacent to the second semiconductor die. The semiconductor package structure according to claim 6, further comprising a molding material surrounding the conductive pillar and the second semiconductor die, wherein sidewalls of the molding material are coplanar with sidewalls of the first semiconductor die. The semiconductor package structure as claimed in claim 6, wherein the second routing channel further includes a via hole in the first semiconductor die. The semiconductor package structure as claimed in claim 1, wherein the second wiring channel comprises a first via in the second semiconductor die. The semiconductor package structure as claimed in claim 9, wherein the second routing channel further includes a second via hole in the first semiconductor die. The semiconductor package structure according to claim 1, further comprising a conductive column disposed under the second semiconductor die and adjacent to the first semiconductor die, wherein the conductive column electrically couples the second semiconductor die to the The front side focuses on the routing layer. The semiconductor package structure according to claim 11, further comprising a molding material surrounding the conductive pillar and the first semiconductor die, wherein sidewalls of the molding material are coplanar with sidewalls of the second semiconductor die. The semiconductor package structure as claimed in claim 1, wherein the second routing channel passes through a region shielded by the first semiconductor die and/or the second semiconductor die. A semiconductor wiring structure, comprising: A first package structure having a front side and a back side, and including a stack structure having a first IP core and a second IP core; a first routing channel electrically coupling the first IP core to a first redistribution layer on the front side of the first package structure; and A second routing channel independently electrically couples the second IP core to a second redistribution layer on the rear side of the first package structure, wherein the second routing channel is separate from the first routing channel and separate from the The first redistribution layer is electrically insulated. The semiconductor wiring structure according to claim 14, further comprising a second packaging structure disposed on the second redistribution layer, wherein the second packaging structure receives control from the second IP core through the second wiring channel Signal. The semiconductor wiring structure as claimed in claim 14, wherein the stacked structure includes vertically stacked first semiconductor die and second semiconductor die, and the first IP core and the second IP core are each independently arranged on the second A semiconductor die or the second semiconductor die. The semiconductor wiring structure of claim 16, wherein the second wiring channel includes a via in the first semiconductor die and electrically coupling the second semiconductor die to the second redistribution layer. The semiconductor wiring structure of claim 16, wherein the second wiring channel includes a conductive pillar adjacent to the first semiconductor die and electrically coupling the second semiconductor die to the second redistribution layer. The semiconductor wiring structure of claim 16, wherein the second wiring channel includes a third redistribution layer extending between the first semiconductor die and the second semiconductor die. The semiconductor wiring structure as claimed in claim 19, wherein the second routing channel includes a conductive pillar adjacent to the stack structure and electrically coupling the second redistribution layer and the third redistribution layer.

Images