TW202303840A - Electronic device and manufacturing method thereof - Google Patents

Abstract

An electronic device includes a substrate, a dielectric layer, a conductive structure, a metal seed layer pattern, and a conductive metal line. The substrate includes a first alignment mark is laid on a first surface of the substrate. The dielectric layer is deposited on the first surface. The dielectric layer includes a second alignment mark that is laid on a second surface of the dielectric layer. The conductive structure is through the dielectric layer and is embedded in the substrate. The first alignment mark is aligned by the conductive structure. The conductive metal line and the metal seed layer pattern are deposited on the dielectric layer. The conductive metal line and the metal seed layer pattern are aligned to corresponding conductive structure through the second alignment mark. An orthogonal projection of the first alignment mark on the substrate overlaps an orthogonal projection of the second alignment mark on the substrate. A method of electrical device manufacturing was proposed that Al metal line connect with Cu after Cu CMP process.

Description

Electronic device and manufacturing method thereof

The present invention relates to an electronic device manufacturing process, and in particular to an electronic device including an alignment mark and a manufacturing method thereof.

In the manufacturing process of semiconductor devices, through silicon vias (TSV) and dielectric layers are polished by chemical mechanical polish (CMP). A metal layer is then formed on the dielectric layer for subsequent patterning process. However, in the above-mentioned CMP process, the alignment mark used for aligning the TSV will be ground flat, and then the process metal layer deposited on the TSV and the dielectric layer will cover the alignment mark, so that the contrast of the alignment mark ( contrast) is reduced and cannot be observed, resulting in extremely poor alignment of the metal layer for patterning the TSVs. Therefore, electrical problems (eg, open circuit) may occur in the semiconductor device.

The invention provides an electronic device with good alignment effect and electrical quality.

The invention provides an electronic device, which can be aligned after the grinding process, and can simplify the process and reduce the cost.

The invention provides an electronic device, which includes a substrate, a dielectric layer, a conductive structure, a seed layer pattern and a conductive metal wire. The substrate has a surface. The substrate includes a first alignment mark disposed on the first surface. A dielectric layer is deposited on the first surface. The dielectric layer includes a second alignment mark disposed on the second surface. The dielectric layer is located between the first surface and the second surface. Conductive structures penetrate the dielectric layer and are embedded in the substrate. The conductive structure is aligned through the first alignment mark. The conductive metal lines are disposed on the dielectric layer. The conductive metal lines are aligned and correspondingly connected to the conductive structure through the second alignment mark. The orthographic projection of the first alignment mark on the substrate overlaps the orthographic projection of the second alignment mark on the substrate.

According to an embodiment of the present invention, the width of the above-mentioned second alignment mark is smaller than or equal to the width of the first alignment mark.

According to an embodiment of the present invention, the height of the second alignment mark is smaller than or equal to the height of the first alignment mark.

According to an embodiment of the present invention, the seed layer pattern is further provided between the conductive structure and the conductive metal line. The orthographic projection of the seed layer pattern on the substrate overlaps the orthographic projection of the conductive metal lines on the substrate.

According to an embodiment of the present invention, the above-mentioned orthographic projection of the conductive structure on the substrate is located within the orthographic projection of the conductive metal line on the substrate.

The invention provides a manufacturing method of an electronic device, which includes the following steps. A substrate is provided, and the substrate has a first surface. A first patterning process is performed to form a first alignment mark on the first surface of the substrate. A dielectric layer is formed on the first surface. The dielectric layer has a second surface, and the dielectric layer is located between the first surface and the second surface. Alignment is performed through the first alignment mark to perform a second patterning process to form an opening in the dielectric layer to expose the substrate. A conductive structure is formed that penetrates the dielectric layer and is embedded in the substrate. A sacrificial layer of silicon carbide nitride (SiCN) is formed on the second surface and covers the conductive structure. A third patterning procedure is performed to form a second alignment mark on the second surface of the dielectric layer. The orthographic projection of the first alignment mark on the substrate overlaps the orthographic projection of the second alignment mark on the substrate. A metal layer is formed on the second surface. And, alignment is performed through the second alignment mark to pattern the metal layer. The patterned metal layer forms conductive metal lines. The orthographic projection of the conductive metal lines on the substrate corresponds to the orthographic projection of the overlapping conductive structure on the substrate.

According to an embodiment of the present invention, the above-mentioned third patterning process includes the following steps. A lithography process is performed on the sacrificial layer to form an opening in the sacrificial layer and expose the second surface. The orthographic projection of the opening of the sacrificial layer on the substrate corresponds to the orthographic projection of the superimposed first alignment mark on the substrate, and the dielectric layer is etched through the opening of the sacrificial layer to form the second alignment mark.

According to an embodiment of the present invention, the above metal layer has a third alignment mark disposed on the third surface of the metal layer. The metal layer is located between the second surface and the third surface, and the orthographic projection of the third alignment mark on the substrate overlaps the orthographic projection of the second alignment mark on the substrate.

According to an embodiment of the present invention, before the above step of forming the metal layer, it further includes forming a seed layer on the second surface and covering the conductive structure. The seed layer is located between the dielectric layer and the metal layer.

According to an embodiment of the present invention, the above-mentioned step of patterning the metal layer includes the following steps. A photoresist pattern is formed on the third surface by aligning the third alignment mark located on the second alignment mark. The orthographic projection of the photoresist pattern on the substrate corresponds to the orthographic projection of the overlapping conductive structure on the substrate. The metal layer and the seed layer are etched through the photoresist pattern to form conductive metal lines and patterns of the seed layer respectively. The seed layer pattern is electrically connected to the conductive structure and the conductive metal line. Finally remove the photoresist pattern.

Based on the above, in the electronic device and its manufacturing method proposed by the present invention, since the first alignment mark can still be observed after the conductive structure is formed in the grinding process, and the second alignment mark can be formed on the first alignment mark and the third alignment mark, so the alignment effect between the conductive metal line and the conductive structure can be improved. In addition, the registration marks have a height difference to improve contrast and visibility. The electronic device has a good alignment effect and electrical quality. In addition, the formation of alignment marks is simple and can effectively solve the problem of alignment failure caused by planarization after CMP, and the manufacturing method of the electronic device can simplify and reduce costs.

1 to 6 are cross-sectional views of the manufacturing process of an electronic device according to an embodiment of the present invention. Please refer to FIG. 6 , the electronic device 10 of the present embodiment includes a substrate 110 , a dielectric layer 120 , a conductive structure V1 and a conductive metal wire 152 . The substrate 110 includes a first alignment mark 114 . The dielectric layer 120 is disposed on the substrate 110 . The dielectric layer 120 includes a second alignment mark 124 . The conductive structure V1 penetrates the dielectric layer 120 and is embedded in the substrate 110 . The conductive metal line 152 covers the dielectric layer 120, and the conductive metal line 152 is electrically connected to the conductive structure V1. It should be noted that the orthographic projection of the first alignment mark 114 on the substrate 110 of the electronic device 10 in this embodiment overlaps the orthographic projection of the second alignment mark 124 on the substrate 110 . Therefore, after the conductive structure V1 is aligned through the first alignment mark 114 , the conductive metal line 152 can be aligned through the second alignment mark 124 overlapping the first alignment mark 114 to correspond to the overlapping conductive structure V1 . In this way, the electronic device 10 can improve the contrast and visibility of the alignment marks during the manufacturing process, so as to provide a good alignment effect during the patterning process. In addition, the electronic device 10 can ensure that the conductive metal wire 152 is electrically connected to the conductive structure V1 to provide good electrical quality. The manufacturing process of the above-mentioned electronic device 10 can be effectively simplified and reduced in cost.

In some embodiments, the electronic device 10 may be a semiconductor structure, such as including a silicon wafer or a silicon wafer. The conductive structure V1 of the electronic device 10 may be a copper through silicon via (TSV). On the upper surface of the substrate 110 (for example, the active area), the conductive structure V1 may be connected to an aluminum circuit line or an aluminum pad (also referred to as a conductive metal line 152 ). The conductive structure V1 can be embedded in the silicon substrate 110 to achieve subsequent bumpless connection technology. Under the above configuration, the electronic device 10 according to an embodiment of the present invention may be a silicon wafer with TSVs and circuit lines or pads, and the TSVs and conductive metal lines are heterogeneous metals, but not limited thereto. The electronic device 10 can be applied in the field of three-dimensional chip (3DIC), but not limited thereto. The manufacturing method of the electronic device 10 will be briefly described below.

Referring to FIG. 1 , a substrate 110 is provided. The substrate 110 has an upper surface and a lower surface. As shown in FIG. 1 , the upper surface can be defined as a first surface 111 . In some embodiments, the first surface 111 may be an active area of the electronic device 10 (shown in FIG. 6 ), but not limited thereto. The substrate 110 can be a semiconductor substrate, such as a silicon substrate or an aluminum gallium arsenide (AlGaAs) substrate, but not limited thereto.

In some embodiments, the height of the substrate 110 can be defined as: the maximum distance between the upper surface and the lower surface on the Z-axis. The Z axis is, for example, a normal direction perpendicular to the first surface 111 of the substrate 110 . The height of the substrate 110 is, for example, 700 microns to 850 microns, but not limited thereto.

Next, a first patterning procedure is performed to form a first alignment mark 114 on the first surface 111 of the substrate 110 . The first patterning process may be a photolithography etching process, including patterning the photoresist material after forming the photoresist material on the first surface 111 to form a mask. The first surface 111 of the substrate 110 is then etched with a mask to pattern the first alignment marks 114 with height differences. In some other embodiments, the first patterning process also includes drilling on the first surface 111 with a cutter or a laser to form the first alignment mark 114 . Then, remove the mask.

In some embodiments, the first alignment mark 114 has a height H1. The height H1 can be defined as: the maximum distance between the first surface 111 and the bottom surface 113 of the first alignment mark 114 on the Z axis. In some embodiments, the height H1 includes, for example, 100 nm to 500 nm, but is not limited thereto. In some embodiments, the height ratio of the first alignment mark 114 to the substrate 110 is, for example, 200:750000, but not limited thereto.

In some embodiments, the first alignment mark 114 has a width W1. The width W1 can be defined as: the maximum distance between two opposite sidewalls of the first alignment mark 114 in the direction perpendicular to the Z-axis. In some embodiments, the width W1 includes, for example, 300 nm to 5000 nm, but is not limited thereto. In some embodiments, the aspect ratio of the first alignment mark 114 is, for example, 1:10, but not limited thereto.

Referring to FIG. 2 , a dielectric layer 120 is then formed on the first surface 111 . The dielectric layer 120 has a second surface 121 . The dielectric layer 120 is located between the first surface 111 and the second surface 121 . In some embodiments, the second surface 121 is an upper surface of the dielectric layer 120 away from the first surface 111 . The material of the dielectric layer 120 is, for example, silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. The method for forming the dielectric layer 120 is, for example, chemical vapor deposition (CVD), but not limited thereto.

In some embodiments, dielectric layer 120 has a height. The height of the dielectric layer 120 can be defined as: the maximum distance between the first surface 111 and the second surface 121 on the Z axis. The height of the dielectric layer 120 is, for example, 50 nm to 200 nm, but not limited thereto. In some embodiments, a portion of the dielectric layer 120 covers and fills the first alignment mark 114 .

Next, alignment is performed through the first alignment marks 114 to perform a second patterning process to form openings 126 in the dielectric layer 120 . The second patterning process may be a photolithography etching process, including patterning the photoresist material after forming the photoresist material on the second surface 121 to form a mask. The dielectric layer 120 is then etched with a mask to pattern the opening 126 . The opening 126 can penetrate through the dielectric layer 120 and expose the first surface 111 of the substrate 110 . As shown in FIG. 2 , there may be multiple openings 126 , but not limited to the number shown in FIG. 2 .

Next, an etching process may be performed on the substrate 110 through the mask and the dielectric layer 120 to pattern the opening 116 . The opening 116 is disposed corresponding to the overlapping opening 126 . The opening 116 has a bottom surface 115 . There is a height difference between the bottom surface 115 of the opening 116 and the first surface 111 to define a height H2 of the opening 116 . The height H2 is, for example, 3 microns to 48 microns, but not limited thereto. The height H2 of the opening 116 is smaller than the height of the substrate 110 . That is to say, the opening 116 does not penetrate through the substrate 110 , and the bottom surface 115 is located in the substrate 110 .

Then, remove the mask.

In some embodiments, the opening 126 and the opening 116 can also be formed by one etch. The sidewalls of the opening 126 and the sidewalls of the opening 116 may be aligned or extend continuously to form an integrally formed surface, but not limited thereto. In some embodiments, the width of the top surface of the opening 126 may gradually decrease toward the opening 116 along the Z-axis. The width of the top surface of the opening 116 may gradually decrease toward the bottom surface 115 of the opening 116 along the Z axis. In section, the side profiles of the opening 126 and the opening 116 may be conical or trapezoidal with a wide top and a narrow bottom, but not limited thereto.

Next, a conductive structure V1 is formed in the opening 126 and the opening 116 . The method of forming the conductive structure V1 includes first forming a seed layer (not shown) on the opening 126 and the side walls of the opening 116 and the bottom surface 115, and then forming a conductive material layer (not shown) on the opening 126 and the opening 116 by electroplating. opening 116. In some embodiments, portions of the conductive material layer may also be disposed on the second surface 121 . In other embodiments, the conductive material layer may be directly filled into the opening 126 and the opening 116 without forming a seed layer. For example, the conductive material layer can be formed by physical vapor deposition or chemical vapor deposition. In some embodiments, the material of the conductive material layer includes metal or metal alloy, such as copper (Cu), copper alloy or other suitable metal or metal alloy, but not limited thereto.

Next, a grinding procedure is performed. The polishing process includes polishing the dielectric layer 120 and the conductive material layer through a chemical mechanical polishing (CMP) process. The ground conductive material layer can form the conductive structure V1. FIG. 2 shows two conductive structures V1, but the number is not limited thereto.

The conductive structure V1 is formed and filled in the opening 126 and the opening 116 . The conductive structure V1 penetrates the dielectric layer 120 and is embedded in the substrate 110 . In an embodiment of the present invention, the conductive structure V1 may be a through-silicon via (TSV). After the polishing process, the top surface of the conductive structure V1 is aligned with the second surface 121 of the dielectric layer 120 . In some embodiments, the height of the conductive structure V1 can be defined as: the maximum distance between the second surface 121 and the bottom surface 115 on the Z axis. The height of the conductive structure V1 may be the sum of the height of the opening 116 and the height of the dielectric layer 120 , but is not limited thereto. The height of the conductive structure V1 is, for example, 5 microns to 50 microns, but not limited thereto.

It should be noted here that the CMP process will not grind the first alignment mark 114 because the step of grinding to form the conductive structure V1 is after the dielectric layer 120 is formed to cover the first alignment mark 114 . In this way, the grinding process will not affect the first alignment mark 114 , and the height difference and visibility of the first alignment mark 114 can be maintained.

Next, a sacrificial layer 130 is formed on the second surface 121 and covers the conductive structure V1. The material of the sacrificial layer 130 includes silicon nitride (SiN) or silicon carbide nitride (SiCN), but not limited thereto. The sacrificial layer 130 can be used as a top cover layer to protect the conductive structure V1 to reduce the risk of contamination of the material of the conductive structure V1 in subsequent processes.

Then, referring to FIG. 3 , a third patterning process is performed to form a second alignment mark 124 on the second surface 121 of the dielectric layer 120 . In detail, the third patterning procedure includes the following steps. The alignment is performed through the first alignment mark 114 to perform a lithography process on the sacrificial layer 130 , including forming a photoresist material on the sacrificial layer 130 and then patterning the photoresist material to form a mask. The sacrificial layer 130 is then etched with a mask to pattern the opening 134 and expose the second surface 121 of the dielectric layer 120 . Specifically, the opening 134 can be aligned to the first alignment mark 114 . In this way, the orthographic projection of the opening 134 of the sacrificial layer 130 on the substrate 110 corresponds to the orthographic projection of the overlapping first alignment mark 114 on the substrate 110 .

Next, an etching process is performed on the dielectric layer 120 through the opening 134 of the sacrificial layer 130 to form a second alignment mark 124 with a height difference on the second surface 121 . Then, remove the mask.

In some embodiments, the second alignment mark 124 has a height H3. The height H3 can be defined as: the maximum distance between the second surface 121 and the bottom surface 123 of the second alignment mark 124 on the Z axis. In some embodiments, the height H3 includes, for example, 100 nm to 200 nm, but is not limited thereto. In some embodiments, the height ratio of the second alignment mark 124 to the dielectric layer 120 is, for example, 1:10, but not limited thereto.

In some embodiments, the height H3 of the second alignment mark 124 may be less than or equal to the height H1 of the first alignment mark 114 , but not limited thereto. In other embodiments, the height H3 of the second alignment mark 124 may be greater than the height H1 of the first alignment mark 114 .

In some embodiments, the second alignment mark 124 has a width W2. The width W2 can be defined as: the maximum distance between two opposite sidewalls of the second alignment mark 124 in the direction perpendicular to the Z-axis. In some embodiments, the width W2 includes, for example, 0.3 microns to 5 microns, but is not limited thereto. In some embodiments, the aspect ratio of the second alignment mark 124 is, for example, 1:10, but not limited thereto.

In some embodiments, the width of the opening 134 may be equal to the width W2 of the second alignment mark 124 . In other words, the sidewall of the opening 134 may be aligned with the sidewall of the second alignment mark 124 , but not limited thereto. In other embodiments, the width of the opening 134 may be larger or smaller than the width W2 of the second alignment mark 124 .

Under the above-mentioned setting, since the opening 134 can be arranged on the first alignment mark 114, and the second alignment mark 124 is set through the opening 134 and corresponds to the overlapping opening 134, so the first alignment mark 114 on the substrate 110 The orthographic projection overlaps the orthographic projection of the second mark 124 on the substrate 110 . Accordingly, the second alignment mark 124 is aligned with the first alignment mark 114 .

In some embodiments, the width W2 of the second alignment mark 124 may be smaller than or equal to the width W1 of the first alignment mark 114 , but not limited thereto. In other embodiments, the width W2 of the second alignment mark 124 may be greater than the width W1 of the first alignment mark 114 .

Next, the sacrificial layer 130 is removed.

Then, referring to FIG. 4 , a seed layer 140 is formed on the second surface 121 . The seed layer 140 covers the dielectric layer 120 and the conductive structure V1. Portions of the seed layer 140 are formed in the second alignment marks 124 . In some embodiments, the height of the seed layer 140 disposed in the second alignment mark 124 may be less than or equal to the height H3 of the second alignment mark 124 , but not limited thereto. The seed layer 140 can be used as a barrier layer for copper process to protect the conductive structure V1, so as to reduce the risk of contamination of the material of the conductive structure V1 in subsequent processes.

The material of the seed layer 140 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. In this embodiment, the material of the conductive layer 140 is titanium nitride as an example, but the invention is not limited thereto. The method for forming the seed layer 140 is, for example, physical vapor deposition or chemical vapor deposition, but not limited thereto.

Next, a metal layer 150 is formed on the second surface 121 . Specifically, the metal layer 150 is formed on the seed layer 140 . The seed layer 140 is located between the dielectric layer 120 and the metal layer 150 . The metal layer 150 has a third surface 151 . The metal layer 150 is located between the second surface 121 and the third surface 151 . The material of the metal layer 150 is, for example, aluminum metal (Al) or aluminum copper alloy (AlCu), but not limited thereto. In this embodiment, the material of the metal layer 150 is aluminum-copper alloy as an example, but the invention is not limited thereto.

In some embodiments, the height of the metal layer 150 can be defined as: the maximum distance between the third surface 151 and the upper surface of the conductive layer 140 on the Z-axis. The height of the metal layer 150 is, for example, 0.2 micron to 1 micron, but not limited thereto.

In this embodiment, since the part of the seed layer 140 is formed in the second alignment mark 124 , the part of the seed layer 140 overlapping the second alignment mark 124 forms a groove with a height difference. When the metal layer 150 is disposed on the seed layer 140 , the portion of the metal layer 150 overlapping the groove of the seed layer 140 forms a third alignment mark 154 with a height difference. The third alignment mark 154 is disposed on the third surface 151 of the metal layer 150 . Since the third alignment mark 154 overlaps the groove of the conductive layer 140 , the third alignment mark 154 will be aligned with the second alignment mark 124 . The orthographic projection of the third alignment mark 154 on the substrate 110 overlaps the orthographic projection of the second alignment mark 124 on the substrate 110 . In addition, the orthographic projection of the third alignment mark 154 on the substrate 110 overlaps the orthographic projection of the first alignment mark 114 on the substrate 110 . In this way, the formation of the third alignment mark 154 has the technical application of the alignment between the post-CMP process and the aluminum metal process, and this method effectively improves the dilemma that the original alignment cannot be achieved.

It is worth noting that since the metal layer 150 covering the first alignment mark 114 and the second alignment mark 124 can have a third alignment mark 154, and the third alignment mark 154 has a height difference groove, so the user The alignment mark (ie, the third alignment mark 154 aligned with the first alignment mark 114 or the second alignment mark 124 ) can still be observed on the third surface 151 of the metal layer 150 . Thereby, the contrast and visibility of the registration marks can be improved.

In some embodiments, the third alignment mark 154 has a height H4. The height H4 can be defined as: on the Z axis, the maximum distance between the third surface 151 and the bottom surface 153 of the third alignment mark 154 . In some embodiments, the height H4 includes, for example, 100 nm to 200 nm, but is not limited thereto. In some embodiments, the height ratio of the third alignment mark 154 to the metal layer 150 is, for example, 1:3, but not limited thereto.

In some embodiments, the third alignment mark 154 has a width W3. The width W3 can be defined as: the maximum distance between two opposite sidewalls of the third alignment mark 154 in the direction perpendicular to the Z-axis. In some embodiments, the width W3 includes, for example, 0.3 microns to 5 microns, but is not limited thereto. In some embodiments, the aspect ratio of the third alignment mark 154 is, for example, 1:20, but not limited thereto.

Next, referring to FIG. 5 and FIG. 6 , the metal layer 150 is patterned. The step of patterning the metal layer 150 includes the following steps. The photoresist pattern PR is formed on the third surface 151 by aligning the third alignment mark 154 located on the second alignment mark 124 . The method for forming the photoresist pattern PR includes forming a photoresist material on the third surface 151 , and performing alignment through the third alignment mark 154 to pattern the photoresist material to form the photoresist pattern PR. The orthographic projection of the photoresist pattern PR on the substrate 110 can be aligned with the orthographic projection of the conductive structure V1 on the substrate 110 . In some embodiments, the orthographic projection of the conductive structure V1 on the substrate 110 may be located within the orthographic projection of the photoresist pattern PR on the substrate 110 , but not limited thereto.

Then, the metal layer 150 and the seed layer 140 are patterned by using the photoresist pattern PR located on the third alignment mark 154 and the second alignment mark 124 as a mask. The above patterning process includes an etching process to respectively pattern the metal layer 150 to form the conductive metal line 152 and pattern the seed layer 140 to form the seed layer pattern 142 . The conductive metal lines 152 and the seed layer pattern 142 are disposed on the dielectric layer 120 . The seed layer pattern 142 is disposed between the conductive structure V1 and the conductive metal line 152 , and the seed layer pattern 142 is electrically connected to the conductive structure V1 and the conductive metal line 152 . The conductive metal wire 152 can be used as a pad on the active surface of the electronic device 10 . Under the above arrangement, the technology of heterogeneous metal connection between the copper conductive structure and the aluminum-copper conductive metal line can be achieved.

Next, the photoresist pattern PR is removed. So far, the fabrication of the electronic device 10 is roughly completed.

In some embodiments, since the conductive metal line 152 and the seed layer pattern 142 can be formed through the photoresist pattern PR, the orthographic projection of the seed layer pattern 142 on the substrate 110 overlaps the orthographic projection of the conductive metal line 152 on the substrate 110 . In addition, the conductive metal lines 152 can completely overlap the seed layer patterns 142 , that is, the sidewalls of the conductive metal lines 152 can be aligned with the sidewalls of the seed layer patterns 142 , but not limited thereto.

In other embodiments, the width of the conductive metal line 152 may be greater than the width of the top surface of the conductive structure V1, but not limited thereto. Therefore, the orthographic projection of the conductive structure V1 on the substrate 110 is located within the orthographic projection of the conductive metal line 152 on the substrate 110 . In this way, the electrical connection between the conductive metal wire 152 and the conductive structure V1 can be ensured, so that the electronic device 10 has good electrical quality.

In short, the electronic device 10 according to an embodiment of the present invention can perform alignment on the conductive structure V1 through the first alignment mark 114 . Next, the second alignment mark 124 overlapping the first alignment mark 114 can be formed through penetration. Alignment is then performed through the second alignment mark 124 to pattern the metal layer 150 . The patterned metal layer 150 forms conductive metal lines 152 , and the orthographic projection of the conductive metal lines 152 on the substrate 110 corresponds to the orthographic projection of the overlapping conductive structure V1 on the substrate 110 . Therefore, in the manufacturing process of the electronic device 10 of this embodiment, the first alignment mark 114 can still be observed after the conductive structure V1 is polished, and the second alignment mark 124 and the third alignment mark 154 can also be seen through. The arrangement with the height difference improves the contrast and visibility of the registration marks and reduces the effect of the heterogeneous metal connection on the contrast of the registration marks. In this way, the alignment effect of the conductive metal wire 152 to the conductive structure V1 is good, and the alignment can be effective to avoid disconnection. The electronic device 10 has good electrical quality. In addition, the use of the seed layer 140 as a barrier layer in the copper process can also protect the copper conductive structure V1 from the pollution risk caused by the exchange of aluminum and copper processes, and improve the electrical quality.

In summary, the electronic device and the manufacturing method thereof according to the above-mentioned embodiments of the present invention can still observe the first alignment mark after the conductive structure is formed in the grinding process, and can form the second alignment mark on the first alignment mark. The alignment mark and the third alignment mark can improve the alignment effect between the conductive metal line and the conductive structure to avoid wire breakage. In addition, the registration marks have a height difference to improve contrast and visibility. The electronic device has a good alignment effect and electrical quality. In addition, the formation of the alignment mark is simple and has good contrast, so that the manufacturing method of the electronic device can be simplified and the cost can be reduced.

10: Electronic device 110: Substrate 111: first surface 113, 115, 123, 153: bottom surface 114: The first alignment mark 116, 126, 134: opening 120: dielectric layer 121: second surface 124: Second alignment mark 130: sacrificial layer 140: Seed layer 142: Seed layer pattern 150: metal layer 151: third surface 152: Conductive metal wire 154: The third alignment mark H1, H2, H3, H4: Height PR: photoresist pattern V1: conductive structure W1, W2, W3: Width Z: axis

1 to 6 are cross-sectional views of the manufacturing process of an electronic device according to an embodiment of the present invention.

10: Electronic device

110: Substrate

114: The first alignment mark

120: dielectric layer

124: Second alignment mark

142: Seed layer pattern

152: Conductive metal wire

V1: conductive structure

Z: axis

Claims (10)

An electronic device comprising: a substrate having a first surface, the substrate including a first alignment mark disposed on the first surface; a dielectric layer disposed on the first surface, the dielectric layer includes a second alignment mark disposed on the second surface of the dielectric layer, and the dielectric layer is located between the first surface and the between said second surfaces; a conductive structure penetrates the dielectric layer and is embedded in the substrate, and the conductive structure performs alignment through the first alignment mark; and a conductive metal wire is disposed on the dielectric layer, and the conductive metal wire is aligned through the second alignment mark so as to be correspondingly connected to the conductive structure, Wherein the orthographic projection of the first alignment mark on the substrate overlaps the orthographic projection of the second alignment mark on the substrate. The electronic device according to claim 1, wherein the width of the second alignment mark is smaller than or equal to the width of the first alignment mark. The electronic device according to claim 1, wherein the height of the second alignment mark is smaller than or equal to the height of the first alignment mark. The electronic device according to claim 1, further comprising a seed layer pattern disposed between the conductive structure and the conductive metal line, wherein the orthographic projection of the seed layer pattern on the substrate overlaps the conductive The orthographic projection of the metal line on the substrate. The electronic device according to claim 1, wherein the orthographic projection of the conductive structure on the substrate is located within the orthographic projection of the conductive metal line on the substrate. A method of manufacturing an electronic device, comprising: providing a substrate having a first surface; performing a first patterning process to form a first alignment mark on the first surface of the substrate; forming a dielectric layer on the first surface, the dielectric layer has a second surface, and the dielectric layer is located between the first surface and the second surface; performing alignment through the first alignment mark to perform a second patterning process to form an opening in the dielectric layer to expose the substrate; forming a conductive structure penetrating through the dielectric layer and embedded in the substrate; forming a sacrificial layer on the second surface and covering the conductive structure; performing a third patterning process to form a second alignment mark on the second surface of the dielectric layer, wherein the orthographic projection of the first alignment mark on the substrate overlaps the second alignment mark an orthographic projection of the alignment mark on the substrate; forming a metal layer on the second surface; and Aligning through the second alignment mark to pattern the metal layer, the patterned metal layer forms a conductive metal line, and the orthographic projection of the conductive metal line on the substrate corresponds to overlapping the conductive An orthographic projection of the structure on the substrate. The method according to claim 6, wherein the third patterning procedure comprises: performing a lithography process on the sacrificial layer to form an opening in the sacrificial layer and exposing the second surface, and the orthographic projection of the opening of the sacrificial layer on the substrate corresponds to overlap the first alignment mark said orthographic projection on said substrate; and Etching the dielectric layer through the opening of the sacrificial layer to form the second alignment mark. The method according to claim 6, wherein the metal layer has a third alignment mark disposed on a third surface of the metal layer, and the metal layer is located between the second surface and the third surface , and the orthographic projection of the third alignment mark on the substrate overlaps the orthographic projection of the second alignment mark on the substrate. The method according to claim 8, wherein before the step of forming the metal layer, further comprising forming a seed layer on the second surface and covering the conductive structure, the seed layer is located on the between the dielectric layer and the metal layer. The method according to claim 9, wherein said step of patterning said metal layer comprises: By aligning the third alignment mark located on the second alignment mark to form a photoresist pattern on the third surface, the orthographic projection of the photoresist pattern on the substrate corresponds to overlapping the orthographic projection of the conductive structure on the substrate; Etching the metal layer and the seed layer through the photoresist pattern to respectively form the conductive metal line and the seed layer pattern, wherein the seed layer pattern is electrically connected to the conductive structure and the seed layer pattern. the conductive metal wire; and removing the photoresist pattern.

Images