TW202301632A - Memory array, method of forming the same, and memory device - Google Patents

Abstract

A test structure for memory arrays and methods of forming the same are disclosed. A memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

Description

Memory array test structure and its forming method

none

Semiconductor memory is used in integrated circuits for electronic applications including, for example, radios, televisions, cell phones and personal computer devices. Semiconductor memory includes two main types. One is volatile memory and the other is non-volatile memory. Volatile memory includes random access memory (random access memory, RAM), which can be further divided into static random access memory (static random access memory, SRAM) and dynamic random access memory (dynamic random access memory, DRAM) two subtypes. Both SRAM and DRAM are volatile because they lose their stored information when power is not supplied.

Non-volatile memory, on the other hand, retains the data stored on it. One type of non-volatile semiconductor memory is ferroelectric random access memory (FERAM or FRAM). Advantages of FERAM include its fast write/read speed and small size.

none

The following disclosure presents many different embodiments or examples in order to achieve the different features of the mentioned subject matter. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are examples only, not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where the first feature and the second feature are formed in direct contact. An embodiment in which an additional feature is formed between such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to facilitate describing an element or feature as shown in the drawings. A relationship to another component or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments provide a three-dimensional memory array test structure for testing connections in a ladder-like structure, and methods of forming the same. A three-dimensional memory array includes stacked memory cells including word lines extending in a direction parallel to a major surface of an underlying substrate. The word lines are arranged in a ladder-like structure, wherein individual lengths of the word lines decrease in a direction away from the substrate. An inter-metal dielectric (IMD) may be formed over the stepped structure, and a plurality of conductive vias may be formed through the IMD and extending to respective word lines in the stepped structure. Multiple conductive vias can be formed simultaneously using a single mask, saving time and cost, but at the risk of openings for the conductive vias not extending to a sufficient depth. Therefore, a test structure may be formed above the stepped structure to test whether each conductive via is successfully connected to a respective word line. The test structure includes wires connected to the respective conductive vias and interconnecting the respective word lines in the ladder-like structure. Some conductive lines extend in a direction parallel to the word lines, and some conductive lines extend in a direction perpendicular to the word lines. To determine whether all conductive vias are successfully connected to individual wordlines, a voltage difference may be applied across all wordlines at opposite ends of the test structure. The test structure can be used to screen memory arrays in which conductive vias are unsuccessfully connected to individual word lines, thereby reducing device defects.

1A and 1B illustrate an example of a memory array 200, according to some embodiments. FIG. 1A shows a perspective view of an example portion of a memory array 200 . FIG. 1B shows a circuit diagram of the memory array 200 . The memory array 200 includes a plurality of memory cells 202 arranged in a grid composed of columns and rows. The memory cells 202 can be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array 200 may be disposed in an interconnect layer of a semiconductor die, eg, over one or more active devices (eg, transistors) formed on a semiconductor substrate.

In some embodiments, memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 may include a transistor 204 and a memory film 90 . The memory film 90 can be used as a gate dielectric. In some embodiments, the gate of each transistor 204 is electrically coupled to a respective word line (eg, wire 72 ), and the first source/drain region of each transistor 204 is electrically coupled to a respective bit line. (bit line) (such as wire 106), and the second source/drain region of each transistor 204 is electrically coupled to an individual source line (source line) (such as wire 108), wherein the source line connects the second The source/drain regions are electrically coupled to ground. Memory cells 202 in the same horizontal column of the memory array 200 can share a common word line, and memory cells 202 in the same vertical row of the memory array 200 can share a common source line and a common bit line.

The memory array 200 includes a plurality of vertically stacked conductive lines 72 (eg, word lines), wherein the first material layer 52 is disposed between vertically adjacent conductive lines 72 . The wires 72 extend in a direction parallel to the main surface of the underlying substrate (not specifically shown in FIGS. 1A and 1B ). The wires 72 may have a stepped configuration such that the lower wires 72 are longer than the upper wires 72 and the lower wires 72 extend longitudinally beyond the ends of the higher wires 72 . For example, in FIG. 1A a multi-layer stack of wires 72 is shown, wherein the topmost wire 72 is the shortest and the bottommost wire 72 is the longest. The individual lengths of the wires 72 may increase towards the underlying substrate. In this case, a portion of each wire 72 can be taken from above the memory array 200 and conductive contacts can be made on the exposed portion of each wire 72 .

The memory array 200 further includes a plurality of wires 106 (eg, bit lines) and a plurality of wires 108 (eg, source lines). Lead 106 and lead 108 may each extend in a direction perpendicular to lead 72 . Dielectric material 102 is disposed between and separates adjacent conductive lines 106 and 108 . Pairs of wires 106 and 108 and intersecting wires 72 define the boundaries of individual memory cells 202, while dielectric material 98 is disposed between adjacent pairs of wires 106 and 108 and separates pairs of wires 106 and 108. 108. In some embodiments, the wire 108 is electrically coupled to ground. Although FIG. 1A depicts a specific configuration of wire 106 relative to wire 108 , it should be understood that the configuration of wire 106 and wire 108 may be reversed.

The memory array 200 may also include an oxide semiconductor (OS) layer 92 . The oxide semiconductor layer 92 may provide a channel region of the transistor 204 of the memory cell 202 . For example, when an appropriate voltage (for example, higher than the individual threshold voltage (threshold voltage, V _th ) of the corresponding transistor 204) is applied across the corresponding wire 72, the region of the oxide semiconductor layer 92 intersecting with the wire 72 can be Current is allowed to flow from wire 106 to wire 108 (eg, in the direction indicated by arrow 206).

The memory film 90 is disposed between the wire 72 and the oxide semiconductor layer 92 , and the memory film 90 can provide a gate dielectric for the transistor 204 . In some embodiments, the memory film 90 includes a ferroelectric (FE) material, such as hafnium oxide, hafnium zirconium oxide, hafnium oxide doped with silicon, or the like. Therefore, the memory array 200 may be called a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 90 may be a multi-layer structure, different ferroelectric materials, different types of memory layers (eg, capable of storing bits), or the like.

In embodiments where the memory film 90 includes a ferroelectric material, the memory film 90 can be polarized in one of two different directions. The polarization direction can be changed by applying a suitable voltage difference across the memory film 90 and generating a suitable electric field. Polarization may be relatively local (eg, generally within each boundary of memory cells 202 ), and a continuous region of memory film 90 may extend across a plurality of memory cells 202 . According to the polarization direction of a specific region of the memory film 90 , the threshold voltage of the corresponding transistor 204 changes to store a digital value (such as 0 or 1). For example, when a region of the memory film 90 has a first electric polarization direction, the corresponding transistor 204 may have a relatively low threshold voltage, and when a region of the memory film 90 has a second electric polarization direction, the corresponding transistor 204 may have have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (eg, less prone to errors) to read the corresponding digital value stored in the memory unit 202 .

To perform a write operation on a memory cell 202 , a write voltage is applied across a portion of the memory film 90 of the corresponding memory cell 202 . For example, the write voltage can be applied by applying appropriate voltages to corresponding wires 72 (eg, corresponding word lines) and corresponding wires 106 and 108 (eg, corresponding bit lines and source lines). Applying a write voltage through a portion of the memory film 90 can change the polarization direction of the area of the memory film 90 . Accordingly, the corresponding threshold voltage of the corresponding transistor 204 can be switched from a low threshold voltage to a high threshold voltage (or vice versa), and a digital value can be stored in the memory cell 202 . Because the wire 72 intersects with the wire 106 and the wire 108, an independent memory cell 202 can be selected for the write operation.

To perform a read operation on the memory cell 202, a read voltage (eg, a voltage between a low threshold voltage and a high threshold voltage) is applied to a corresponding conductive line 72 (eg, a corresponding word line). According to the polarization direction of the corresponding region of the memory film 90, the transistor 204 of the memory unit 202 can be activated or deactivated. Therefore, the corresponding wire 106 can be discharged or not discharged through the corresponding wire 108 (eg, the corresponding source line coupled to ground), and the digital value stored in the memory cell 202 can be read. Because wire 72 intersects wire 106 and wire 108 , an individual memory cell 202 can be selected for a read operation.

FIG. 1A further illustrates a reference cross-section of the memory array 200 used in subsequent figures. The section AA′ is along the longitudinal axis of the wire 72 and, for example, in a direction parallel to the current flow across the oxide semiconductor layer 92 of the transistor 204 . Section BB' is perpendicular to section AA' and to the longitudinal axis of wire 72 . Section BB′ extends through dielectric material 98 and dielectric material 102 . Section CC′ is parallel to section BB′ and extends through conductive wire 106 . For clarity of description, subsequent figures will refer to these reference sections. Section DD' is parallel to section BB' and extends through the stepped structure portion of wire 72 .

2-34C are illustrations of intermediate stages in the manufacture of memory array 200, according to some embodiments. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11B, Figure 12B, Figure 13B, Figure 14B Figure 15B, Figure 16B, Figure 17B, Figure 18B, Figure 19B, Figure 20B, Figure 21B, Figure 22B, Figure 23B and Figure 24B along the reference section in Figure 1A A-A' is shown. Figure 11C, Figure 12C, Figure 13C, Figure 14C, Figure 15C, Figure 16C, Figure 17C, Figure 18C, Figure 19C, Figure 20C, Figure 21C, Figure 26A, Figure 27A Figures 28A, 29A, 30A, 31A, 32A, 33A and 34A are drawn along the reference section BB' in Figure 1A. Figures 20D, 21D and 34C are drawn along reference section CC' in Figure 1A. Figure 22C, Figure 23C, Figure 24C, Figure 26B, Figure 27B, Figure 28B, Figure 29B, Figure 30B, Figure 31B, Figure 32B, Figure 33B and Figure 34B along the The reference section DD' in Figure 1A is shown. Figure 11A, Figure 12A, Figure 13A, Figure 14A, Figure 15A, Figure 16A, Figure 17A, Figure 18A, Figure 19A, Figure 20A, Figure 21A, Figure 22A, Figure 23A Figures 24A, 25A and 25C show top views. Figures 24D and 25B show perspective views.

In Figure 2, a substrate 50 is provided. Substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (eg, with p-type or n-type dopants) or undoped. adulterated. The substrate 50 may be an integrated circuit die, such as a logic die, a memory die, an application specific integrated circuit (ASIC) die, or the like. The substrate 50 may be a complementary metal oxide semiconductor (CMOS) grain and may be called a CMOS under array (CUA). The substrate 50 may be a wafer, such as a silicon wafer. Generally speaking, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer or the like. An insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates (such as multi-layer or graded substrates) may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide), alloy semiconductors ( Including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide and/or indium gallium arsenic phosphide) or a combination thereof.

FIG. 2 further illustrates circuitry that may be formed over the substrate 50 . The circuitry includes transistors on the top surface of the substrate 50 . The transistor may include a gate dielectric layer 302 over the top surface of the substrate 50 and a gate electrode 304 over the gate dielectric layer 302 . Source/drain regions 306 are disposed in substrate 50 on opposite sides of gate dielectric layer 302 and gate electrode 304 . Gate spacers 308 are formed along sidewalls of the gate dielectric layer 302 and separate the source/drain regions 306 and the gate electrodes 304 by a suitable lateral distance. Transistors may include fin field effect transistors (fin field effect transistors, finFETs), nanostructure (such as nanosheets, nanowires, gate full surround or similar) field effect transistors (nanostructure FETs, nano-FETs) ), a planar field effect transistor, the like, or a combination of the above, and can be formed by a gate-first process or a gate-last process.

A first interlayer dielectric 310 surrounds and separates the source/drain region 306 , gate dielectric layer 302 and gate electrode 304 , and a second interlayer dielectric 312 is above the first interlayer dielectric 310 . A source/drain contact 314 extends through the second ILD 312 and the first ILD 310 and is electrically coupled to the source/drain region 306 . A gate contact 316 extends through the second ILD 312 and is electrically coupled to the gate electrode 304 . An interconnect structure 320 is over the second ILD 312, the source/drain contacts 314 and the gate contacts 316, wherein the interconnect structure 320 includes one or more stacked dielectric layers 324 and is formed on one or more Conductive feature 322 in dielectric layer 324 . The interconnect structure 320 can be electrically connected to the gate contact 316 and the source/drain contact 314 to form a functional circuit. In some embodiments, the functional circuits formed by the interconnection structure 320 may include logic circuits, memory circuits, sense amplifiers, controllers, input/output circuits, image sensing circuits, the like, or combinations thereof. Although FIG. 2 discusses transistors formed over substrate 50, other active devices (eg, diodes or the like) and/or passive devices (eg, capacitors, resistors, or the like) may be formed as part of the functional circuitry. For brevity and clarity of illustration, the transistors, interlayer dielectrics, and interconnection structures 320 formed over the substrate 50 may be omitted in subsequent figures. Substrate 50 with transistors (such as source/drain regions 306, gate dielectric layer 302 and gate electrode 304), gate spacers 308, first interlayer dielectric 310, second interlayer dielectric 312 And interconnect structure 320 may be a CUA, a logic die, or the like.

In FIG. 3 , multilayer stack 58 is formed over substrate 50 . Although multilayer stack 58 is shown contacting substrate 50 , any number of intermediate layers may be disposed between substrate 50 and multilayer stack 58 . For example, one or more interconnect layers including conductive features in insulating layers (eg, low-k dielectric layers) may be disposed between substrate 50 and multilayer stack 58 . In some embodiments, conductive features may be patterned to provide power, ground and/or signal lines for active devices and/or memory array 200 on substrate 50 (see FIGS. 1A and 1B ).

Multilayer stack 58 includes alternating first material layers 52A-52D (collectively first material layers 52 ) and second material layers 54A-54C (collectively second material layers 54 ). In some embodiments, the second material layer 54 may be patterned in a subsequent step to define conductive lines 72 (eg, word lines). In embodiments where second material layer 54 is patterned to define conductive lines 72, second material layer 54 may comprise a conductive material such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, cobalt, Silver, gold, nickel, chromium, hafnium, platinum, combinations of the above, or the like. The first material layer 52 may include insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. In some embodiments, the second material layer 54 may be replaced with a conductive material in a subsequent step to define the wire 72 . In such an embodiment, the second material layer 54 may also include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or the like, and may include a material having a high Etch selective materials. In some embodiments, the first material layer 52 may include oxide (such as silicon oxide), and the second material layer 54 may include nitride (such as silicon nitride). For example, chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (atomic layer deposition, ALD), physical vapor deposition (physical vapor deposition, PVD), plasma enhanced chemical vapor deposition (plasma enhanced CVD, PECVD) or the like are individually formed into the first material layer 52 and the second material layer 54 . Although FIG. 3 depicts a specific number of first material layers 52 (eg, 4 layers) and second material layers 54 (eg, 3 layers), other embodiments may include different numbers of first material layers 52 and second material layers. 54.

FIGS. 4-8 illustrate patterning the multilayer stack 58 to form a stepped structure 68 (shown in FIG. 8 ). In FIG. 4 , photoresist 56 is formed over multilayer stack 58 . Photoresist 56 may be formed using spin coating techniques and may be patterned using acceptable photolithographic techniques. Patterning photoresist 56 may expose multilayer stack 58 in region 60 while masking the remainder of multilayer stack 58 . For example, the topmost layer (eg, first material layer 52D) of multilayer stack 58 in region 60 may be exposed.

In FIG. 5, the exposed portions of multilayer stack 58 in region 60 are etched using photoresist 56 as a mask. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etch (RIE), neutral beam etch (NBE), the like, or combinations thereof. Etching can be anisotropic. Etching may remove portions of first material layer 52D and second material layer 54C in region 60 and define opening 61 along opposing edges of multilayer stack 58 . Since the first material layer 52 and the second material layer 54 have different material compositions, different etchants may be used to remove exposed portions of these layers. In some embodiments, when the first material layer 52D is etched, the second material layer 54C acts as an etch stop layer, and when the second material layer 54C is etched, the first material layer 52C acts as an etch stop layer. Accordingly, portions of the first material layer 52D and the second material layer 54C may be selectively removed while avoiding removal of the remaining layers of the multilayer stack 58 and the opening 61 may be extended to a desired depth. Alternatively, a timed etching process may be used to stop the etching of the opening 61 after the opening 61 has reached a desired depth. In the resulting structure, first material layer 52C is exposed in region 60 .

In FIG. 6 , photoresist 56 is trimmed to expose additional portions of multilayer stack 58 . Photoresist 56 may be trimmed using acceptable photolithographic techniques. After trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60 and 62 are exposed. For example, the top surface of first material layer 52D in region 62 and the top surface of first material layer 52C in region 60 may be exposed.

The exposed portions of the multilayer stack 58 may then be etched using the photoresist 56 as a mask. Etching may be any suitable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. The etch process can be anisotropic. Etching may extend opening 61 further into multilayer stack 58 . Since the first material layer 52 and the second material layer 54 have different material compositions, different etchants may be used to remove exposed portions of these layers. In some embodiments, when the first material layer 52 is etched, the second material layer 54 acts as an etch stop layer, and when the second material layer 54 is etched, the first material layer 52 acts as an etch stop layer. Accordingly, portions of the first material layer 52 and the second material layer 54 may be selectively removed while avoiding removal of the remaining layers of the multilayer stack 58 and the opening 61 may be extended to a desired depth. Alternatively, a timed etching process may be used to stop the etching of the opening 61 after the opening 61 has reached a desired depth. Furthermore, during the etching process, the unetched portions of the first material layer 52 and the second material layer 54 serve as masks for the underlying layers, so that the first material layer 52D and the second material layer 54C (refer to FIG. 5 ) The previous pattern of may be transferred to the underlying first material layer 52C and the underlying second material layer 54B. In the resulting structure, first material layer 52C in region 62 is exposed and first material layer 52B in region 60 is exposed.

In FIG. 7 , photoresist 56 is trimmed to expose additional portions of multilayer stack 58 . Photoresist 56 may be trimmed using acceptable photolithographic techniques. After trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60 , 62 , and 64 are exposed. For example, the top surface of first material layer 52D in region 64 , the top surface of first material layer 52C in region 62 , and the top surface of first material layer 52B in region 60 may be exposed.

The exposed portions of the multilayer stack 58 may then be etched using the photoresist 56 as a mask. Etching may be any suitable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. The etch process can be anisotropic. Etching may extend opening 61 further into multilayer stack 58 . When the first material layer 52 is etched, the second material layer 54 may serve as an etch stop layer. Accordingly, a portion of the first material layer 52 can be selectively removed while avoiding removal of an underlying portion of the second material layer 54, and the opening 61 can be extended to a desired depth. Alternatively, a timed etching process may be used to stop the etching of the opening 61 after the opening 61 has reached a desired depth. Furthermore, during the etching process, the unetched portions of the first material layer 52 and the second material layer 54 act as masks for the underlying layers, so that the first material layer 52D, the second material layer 54C, the first material layer 52C The previous pattern of the second material layer 54B (see FIG. 6 ) may be transferred to the underlying first material layer 52B and the underlying first material layer 52C. In the resulting structure, second material layer 54C in region 64 is exposed, second material layer 54B in region 62 is exposed, and second material layer 54A in region 60 is exposed.

In Figure 8, photoresist 56 is removed. Photoresist 56 may be removed by an acceptable ashing or wet stripping process. Thus, a stepped structure 68 is formed. The stepped structure 68 includes a stack of alternating first material layers 52 and second material layers 54 . As shown in FIG. 8 , forming the stepped structure 68 may expose a portion of each of the second material layer 54A to the second material layer 54C from the upper second material layer 54 and the first material layer 52 . Therefore, in a subsequent process step, conductive contacts can be made in each second material layer 54 from above the stepped structure 68 .

In FIG. 9 , intermetal dielectric 70 is deposited over multilayer stack 58 . The IMD 70 may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), or the like. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG) , undoped silicate glass (undoped silicate glass, USG) or the like. In some embodiments, the IMD 70 may include an oxide (eg, silicon oxide or the like), a nitride (eg, silicon nitride or the like), combinations thereof, or the like. Other dielectric materials formed by any acceptable process may be used. The intermetallic dielectric 70 is along the sidewalls of the first material layer 52B to the first material layer 52D, the sidewalls of the second material layer 54B and the second material layer 54C, the top surface of the first material layer 52D, and the second material layer 54A. Extends to the top surface of the second material layer 54C.

In FIG. 10 , a removal process is applied to the IMD 70 to remove excess dielectric material above the multilayer stack 58 . In some embodiments, the removal process may be a planarization process, such as chemical mechanical polish (CMP), etch back process, a combination of the above, or the like. The planarization process exposes the multi-layer stack 58 so that the top surface of the first material layer 52D and the IMD 70 are flush with each other after the planarization process is completed.

In FIGS. 11A-13C , trenches 86 (shown in FIGS. 12A-13C ) are formed in the multilayer stack 58 . In embodiments where the second material layer 54 includes a conductive material, this defines the conductive lines 72 (shown in FIGS. 12A-13C ) from the second material layer 54 . Wires 72 may correspond to word lines in memory array 200 and wires 72 may provide gate electrodes for transistors 204 of the resulting memory array 200 . In Figures 11A to 19C, figures whose titles end in "A" show a plan view, figures whose titles end in "B" show a cross-sectional view along section A-A' in Figure 1A, and Figures with titles ending in "C" show cross-sections along section BB' in Figure 1A.

In FIGS. 11A-11C , a hard mask 80 is deposited over the multilayer stack 58 and the IMD 70 . Hard mask 80 may comprise, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. Hard mask 80 may be formed using spin coating techniques and may be patterned using acceptable photolithographic techniques. A patterned photoresist 82 is formed over the hard mask 80 . Patterned photoresist 82 may be formed by depositing a photosensitive layer over hard mask 80 using spin coating or the like. The photosensitive layer may then be patterned to form patterned photoresist 82 by exposing the photosensitive layer to a patterned energy source (eg, a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the photosensitive layer. A trench 86 exposing hard mask 80 is formed extending through patterned photoresist 82 . The pattern of the patterned photoresist 82 corresponds to the conductive lines that will be formed in the multilayer stack 58, discussed below in conjunction with FIGS. 12A-12C.

In FIGS. 12A-12C , hard mask 80 is patterned using patterned photoresist 82 as a mask to extend trenches 86 through hard mask 80 . Hard mask 80 may be patterned using an acceptable etch process, such as wet or dry etch, RIE, NBE, the like, or combinations thereof. Etching can be anisotropic. Accordingly, trench 86 extends through hard mask 80 and exposes multilayer stack 58 . The patterned photoresist 82 may then be removed by an acceptable process, such as a wet etch process, a dry etch process, a combination of the above, or the like.

In FIGS. 13A-13C , multilayer stack 58 is patterned using hard mask 80 as a mask to extend trenches 86 through multilayer stack 58 and expose substrate 50 . Multilayer stack 58 may be patterned using one or more acceptable etching processes, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. The etch process can be anisotropic. Accordingly, trench 86 extends through multilayer stack 58 . The second material layer 54A to the second material layer 54C are etched to form wires 72A to 72C (eg, word lines collectively referred to as wires 72 ) from each layer of the second material layer 54 . Trenches 86 separate adjacent conductive lines 72 and separate portions of first material layer 52 . Further in FIGS. 13A-13C , the hard mask 80 may be removed by an acceptable process, such as a wet etch process, a dry etch process, a planarization process, combinations thereof, or the like.

14A-17C illustrate the formation and patterning of the channel region of the transistor 204 (see FIGS. 1A and 1B ) in the trench 86 . In FIGS. 14A to 14C , the memory film 90 and the oxide semiconductor layer 92 are deposited in the trench 86 . Memory film 90 may be conformally deposited in trench 86 along the sidewalls of wire 72 , first material layer 52 and IMD 70 and along the top of first material layer 52D and IMD 70 . surface. The memory film 90 can be deposited by CVD, PVD, ALD, PECVD or the like.

Memory film 90 may provide a gate dielectric for transistors 204 formed in memory array 200 . The memory film 90 may comprise a material capable of switching between two different polarization directions by applying an appropriate voltage difference across the memory film 90 . The memory film 90 may be a high-k dielectric material, such as a hafnium (Hf)-based dielectric material or the like. In some embodiments, the memory film 90 includes a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. In some embodiments, the memory film 90 may include different ferroelectric materials or different types of memory materials. In some embodiments, the memory film 90 may be a multi-layer memory structure including a SiNx layer between two _SiOx layers (eg ONO structure).

Conformally deposited oxide semiconductor layer 92 is in trench 86 and over memory film 90 . The oxide semiconductor layer 92 includes a material suitable as a channel region of the transistor 204 (see FIG. 1A and FIG. 1B ). For example, the oxide semiconductor layer 92 may include zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide (ITO), Polycrystalline silicon (poly-Si), silicon (Si), amorphous silicon (a-Si), combinations thereof, or the like. The oxide semiconductor layer 92 can be deposited by CVD, PVD, ALD, PECVD, or the like. The oxide semiconductor layer 92 may extend along the sidewall and bottom surface of the trench 86 above the memory film 90 .

In FIGS. 15A to 15C , the oxide semiconductor layer 92 is etched using a suitable etching process (eg, an anisotropic etching process) to separate the oxide semiconductor layer 92 into a plurality of oxide semiconductor layers 92 . The horizontal portion of the oxide semiconductor layer 92 (for example, the portion of the oxide semiconductor layer 92 extending along the top surface of the memory film 90 ) can be removed, while the vertical portion of the oxide semiconductor layer 92 (for example, along the top surface of the memory film 90 ) remains. A portion of the oxide semiconductor layer 92 extending from the side surface of the substrate. A suitable etching process may be any acceptable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof.

In FIGS. 16A to 16C , the memory film 90 is etched using a suitable etching process (such as an anisotropic etching process) to separate the memory film 90 into a plurality of memory films 90 . The horizontal portion of the memory film 90 (for example, the part of the memory film 90 extending along the top surface of the substrate 50 and the first material layer 52D) can be removed, while the vertical portion of the memory film 90 (for example, along the wire 72, A portion of the memory film 90 extending from the side surfaces of the first material layer 52 and the intermetal dielectric 70 ). A suitable etching process may be any acceptable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. During the etching process, the oxide semiconductor layer 92 can cover part of the memory film 90 so that the memory film 90 after the etching process is L-shaped.

In FIGS. 17A-17C , dielectric material 98 is deposited to fill the remainder of trench 86 . Dielectric material 98 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. A removal process is applied to the dielectric material 98 , the oxide semiconductor layer 92 and the memory film 90 to remove excess material above the wire 72 , the first material layer 52 and the IMD 70 . In some embodiments, a planarization process, such as CMP, etch-back process, a combination of the above, or the like may be used. The planarization process exposes the top surface of the intermetal dielectric 70 and the first material layer 52D, so that the first material layer 52D, the intermetal dielectric 70, the memory film 90, and the oxide semiconductor layer 92 after the planarization process are completed and the top surfaces of the dielectric material 98 are flush with each other.

18A to 21D illustrate intermediate steps in the fabrication of dielectric material 102 , conductive lines 106 (eg, bit lines) and conductive lines 108 (eg, source lines) in memory array 200 . Wires 106 and 108 may extend in a direction perpendicular to wires 72 so that individual memory cells 202 of memory array 200 may be selected for read and write operations.

In FIGS. 18A to 18C , the trench 100 is patterned through the dielectric material 98 and the oxide semiconductor layer 92 . The trench 100 may be patterned in the dielectric material 98 and the oxide semiconductor layer 92 through a combination of photolithography and etching. Etching may be any acceptable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. Etching can be anisotropic. The trench 100 can be disposed between opposite sidewalls of the memory film 90, and the trench 100 can physically separate adjacent stacks of memory cells 202 in the memory array 200 (see FIG. 1A). The dielectric material 98 and the oxide semiconductor layer 92 adjacent to the intermetal dielectric 70 , the wire 72 and the first material layer 52 and in the regions 60 , 62 and 64 of the stepped structure 68 may be completely removed. In some embodiments (not shown in particular), the trench 100 can also be patterned to pass through the memory film 90 . Accordingly, trenches 100 can be disposed between the conductive lines 72 and opposite sidewalls of the first material layer 52, and the trenches 100 can physically separate adjacent stacks of memory cells 202 in the memory array 200 (see FIG. 1A).

In FIGS. 19A-19C , a dielectric material 102 is deposited in and fills the trench 100 . The dielectric material 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric material 102 may extend along the sidewall and bottom surface of the trench 100 above the oxide semiconductor layer 92 . After deposition, a planarization process (eg, CMP, etch back, or the like) may be performed to remove excess portions of the dielectric material 102 . In the obtained structure, the top surfaces of the first material layer 52D, the memory film 90, the oxide semiconductor layer 92, the intermetal dielectric 70, the dielectric material 98, and the dielectric material 102 may be substantially flush with each other ( For example, within the tolerance of the manufacturing process).

In some embodiments, the materials of dielectric material 98 and dielectric material 102 may be selected such that they are etch-selective relative to each other. For example, in some embodiments, dielectric material 98 is an oxide and dielectric material 102 is a nitride. In some embodiments, dielectric material 98 is a nitride and dielectric material 102 is an oxide. Other materials are also available.

FIG. 20A shows a reference cross-section of the memory array 200 used in subsequent figures. Section AA′ is along the longitudinal axis of wire 72 and in, for example, a direction parallel to the current flow across oxide semiconductor layer 92 of transistor 204 . Section BB' is perpendicular to section AA' and to the longitudinal axis of wire 72 . Section BB′ extends through dielectric material 98 and dielectric material 102 . Section CC' is parallel to section BB' and extends through a subsequently formed lead (such as lead 106 discussed below in FIGS. 21A-21D ). For clarity of description, subsequent figures will refer to these reference sections. In Figures 20A to 21D, the figures whose titles end in "A" show a plan view, and the figures whose titles end in "B" show a cross-sectional view along the section A-A' of Figure 20A, and the titles end in "B" Figures ending in "C" show a section along section BB' in Figure 20A, while drawings ending in "D" show a section along section CC' in Figure 20A picture.

In FIGS. 20A-20D , trenches 104 are patterned through dielectric material 98 . Trenches 104 may be used to form wires subsequently. Trenches 104 may be patterned through dielectric material 98 using a combination of photolithography and etching. Etching may be any acceptable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. Etching can be anisotropic. The etching may use an etchant that etches the dielectric material 98 without significantly etching the dielectric material 102 , the oxide semiconductor layer 92 , or the memory thin film 90 . The pattern of trenches 104 may correspond to subsequently formed conductive lines (eg, conductive lines 106 and 108 discussed below in FIGS. 21A-21D ). Portions of dielectric material 98 may remain between each pair of trenches 104 , and dielectric material 102 may be disposed between adjacent pairs of trenches 104 . Further, part of the oxide semiconductor layer 92 and the memory film 90 may remain adjacent to the trench 104 and between the trench 104 and each of the first material layers 52 and the wires 72 . Part of the oxide semiconductor layer 92 and the memory film 90 can be used as a part of the transistor 204 formed later. In some embodiments, in order to selectively etch the material of the dielectric material 98 other than the oxide semiconductor layer 92 and the memory film 90, a different etch may be used to pattern the trenches relative to the process used to pattern the trenches 100. 104.

In FIGS. 21A-21D , trenches 104 are filled with a conductive material to form leads 106 and leads 108 . A memory cell 202 and a transistor 204 are formed, each of which includes a wire 106 , a wire 108 , a wire 72 , a part of the memory thin film 90 and a part of the oxide semiconductor layer 92 . Leads 106 and 108 may each comprise a conductive material such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like. Leads 106 and 108 may be formed using, for example, CVD, ALD, PVD, PECVD, or the like. After the conductive material is deposited, planarization (eg, CMP, etch back, or the like) may be performed to remove excess portions of the conductive material to form wires 106 and 108 . In the obtained structure, the top surfaces of the first material layer 52D, the intermetal dielectric 70, the memory film 90, the oxide semiconductor layer 92, the dielectric material 98, the dielectric material 102, the wire 106, and the wire 108 can be are substantially flush with each other (eg, within manufacturing tolerances).

Wires 106 may correspond to bit lines in memory array 200 , and wires 108 may correspond to source lines in memory array 200 . Further, the wires 106 and 108 can provide source/drain electrodes of the transistors 204 in the memory array 200 . Although FIG. 21D shows only a cross-sectional view of wire 106 , the cross-sectional view of wire 108 may be similar to FIG. 21D .

Although in the above description, the channel region of the transistor 204, the wire 106, and the wire 108 are formed after the formation of the stepped structure 68, in some embodiments, the steps may be formed after the channel region of the transistor 204, the wire 106, and the wire 108 are formed. like structure 68 . For example, the fabrication steps depicted and discussed in FIGS. 4-10 may be performed after the fabrication steps depicted and discussed in FIGS. 11A-21D to form the stepped structure 68 . The same or similar processes may be used in the embodiments of the step-structure-first process and the step-structure-post-process.

FIG. 22A shows a reference cross-section of the memory array 200 used in subsequent figures. Section AA′ is along the longitudinal axis of wire 72 and in, for example, a direction parallel to the current flow across oxide semiconductor layer 92 of transistor 204 . Section DD' is perpendicular to section AA' and to the longitudinal axis of wire 72 . Section DD′ extends through region 60 of stepped structure 68 . For clarity of description, subsequent figures will refer to these reference sections. In Figures 22A to 24C, the figures whose titles end in "A" show a plan view, the figures whose titles end in "B" show a cross-sectional view along section A-A' of Figure 22A, and Figures with titles ending in "C" show cross-sections along section DD' of Figure 22A.

In FIGS. 22A-22C , trenches 110 are formed in the IMD 70 . Trenches 110 may be used subsequently to form conductive contacts. More specifically, trenches 110 may subsequently be used to form conductive contacts (eg, word line contacts, gate contacts, or the like) extending to conductive lines 72 . As shown in FIGS. 22A-22C , the trench 110 may extend through the IMD 70 and may expose the top surface of the wire 72 . The stepped shape of the leads 72 provides a surface on each lead 72 to which the trenches 110 may extend. Trenches 110 may be formed using a combination of photolithography and etching. Etching may be any acceptable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. Etching can be anisotropic.

In some embodiments, the trench 110 in the IMD 70 may be formed by a process having high etch selectivity to the material of the IMD 70 . Accordingly, trenches 110 in IMD 70 may be formed without significant removal of wire 72 material. In some embodiments, the openings exposing the respective wires 72A to 72C may be formed at the same time. Due to the difference in the thickness of the IMD 70 over the respective wires 72A to 72C, the exposure of wire 72C to etching may be longer than that of wire 72B, which may be longer than that of wire 72A. , and so on, wherein the period during which the wire 72A is exposed to etching is the shortest. Exposure to etching may result in some material loss, dents, or other damage in wire 72, with wire 72C being the most damaged, wire 72B being less damaged, and wire 72A being the least damaged. Forming the trenches 110 through the IMD 70 and exposing the respective wires 72A-72C saves the cost and time associated with performing multiple masking and etching steps. However, some trenches 110 may not be sufficiently etched such that some wires 72 are not exposed. Thus, to detect any defective connections to conductors 72, a test structure (such as test structure 120 discussed below in FIGS. 24A-24D ) may be formed over memory array 200 . This reduces device defects.

In FIGS. 23A-23C , conductive contacts 112 are formed in trenches 110 . The conductive contacts 112 extend through the IMD 70 to each of the wires 72 and can be electrically coupled to the wires 72 . In some embodiments, conductive contacts 112 may be referred to as word line contacts, gate contacts, or the like. The conductive contact 112 may be formed by forming a liner (not specifically shown, such as a diffusion barrier layer, an adhesion layer, or the like) and a conductive material in the trench 110 . The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel or the like. A planarization process (eg, CMP) may be performed to remove excess material from the surface of the IMD 70 . The remaining liner and conductive material form conductive contacts 112 in trenches 110 . As depicted in FIGS. 23B and 23C , conductive contacts 112 may extend to each of leads 72A-72C.

In FIGS. 24A-24D , a first dielectric layer 114 , a conductive contact 116 , a second dielectric layer 115 , and a wire 118 are formed over the structure of FIGS. 23A-23C . Conductive contact 112 , conductive contact 116 , and wire 118 collectively form test structure 120 . The first dielectric layer 114 and the second dielectric layer 115 may include a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. In some embodiments, the first dielectric layer 114 and the second dielectric layer 115 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The first dielectric layer 114 and the second dielectric layer 115 may be deposited using a suitable process, such as CVD, ALD, PVD, PECVD or the like.

Trenches (not specifically shown) for conductive contacts 116 and wires 118 are formed through the second dielectric layer 115 and the first dielectric layer 114 . The trenches in the second dielectric layer 115 expose the top surface of the first dielectric layer 114 , and the trenches in the first dielectric layer 114 expose the top surfaces of the conductive contacts 112 . The trenches can be formed using a combination of photolithography and etching. Etching may be any acceptable etching process, such as wet or dry etching, RIE, NBE, the like, or combinations thereof. Etching can be anisotropic. The trenches in the second dielectric layer 115 and the first dielectric layer 114 may be formed using multiple etching processes.

Conductive contacts 116 and wires 118 are then formed in the trenches in the first dielectric layer 114 and the second dielectric layer 115 , respectively. Conductive contacts 116 and wires 118 may be formed by forming a liner (not specifically shown, such as a diffusion barrier layer, an adhesion layer, or the like) and forming a conductive material over the liner. Conductive contacts 116 and wires 118 may be formed using one or more deposition processes simultaneously or separately. The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel or the like. A planarization process such as CMP may be performed to remove excess material from the surface of the second dielectric layer 115 .

Figure 24D shows a perspective view of the obtained structure. In order to more clearly show the relationship between the wire 72, the conductive contact 112, the conductive contact 116, and the wire 118, the perspective view includes the wire 72, the conductive contact 112, the conductive contact 116, and the wire. 118 while omitting other structures. FIGS. 24A-24D further illustrate conductive pathways through the test structure 120 . A conductive path may extend from the outside of the memory array 200 into the memory array 200 at location 1 . The conductive path extends through lead 118 , conductive contact 116 , and conductive contact 112 to lead 72A. The conductive path then extends through locations 2 and 3 and through conductive contact 112 , conductive contact 116 , and wire 118 to wire 72B. The conductive path continues through memory array 200 to location 24 , which extends outside of memory array 200 . Each wire 72 is connected to a first vertically adjacent wire 72 and a second vertically adjacent wire 72 (for example, wire 72B is connected to wire 72A and wire 72C), a horizontally adjacent wire 72 (for example, wire 72C is connected to wire 72B and wire 72C) or connections outside of memory array 200 (eg, wire 72A connects to wire 72B and outside connections). Conductors 118 include conductors 118 extending in a direction parallel to the longitudinal axis of conductors 72 and connecting vertically adjacent conductors 72 . The wires 118 further include wires 118 oriented perpendicular to the longitudinal axis of the wires 72 and connecting horizontally adjacent wires 72 , or wires 118 providing connections outside the memory array 200 .

Test structure 120 may be used to determine whether any connections between conductive contacts 116 are defective. For example, a voltage difference may be applied to memory array 200 at location 1 and location 24 . Since the conductive paths extend through all wires 72, conductive contacts 112, conductive contacts 116, and wires 118 in memory array 200, current measurements may be taken in order to determine if there are any defective connections. Thus, the memory array 200 can be screened for defective connections and device defects can be avoided. Furthermore, as described above, the trenches 110 and the conductive contacts 112 connected to the respective wires 72A-72C can be formed simultaneously, which can reduce cost, reduce manufacturing time, and increase device throughput.

FIG. 25A to FIG. 25C illustrate scribe lines separating a plurality of memory arrays 200 . FIG. 25A shows a top view of four memory arrays 200 , FIG. 25B shows a perspective view of two memory arrays 200 , and FIG. 25C shows a top view of a wafer 300 including a plurality of memory arrays 200 . The memory array 200 is arranged in a grid pattern in the wafer 300 , which may be concentrated above the wafer 300 . The dicing lines separate individual memory arrays 200 , and subsequent memory arrays 200 are cut into small pieces along the dicing lines. As shown in FIGS. 25A and 25B , cut lines may extend through at least some of the wires 118 (eg, wires 118 extending in a direction perpendicular to the longitudinal axis of the wire 72 ), such that the wires 118 are then segmented. As shown in FIG. 25C , dicing lines may be provided in regions 301 between adjacent memory arrays 200 , wherein the regions 301 are removed by dicing. At least a portion of the test structure 120 may extend above the region 301 , and these portions of the test structure 120 may be removed by dicing. FIG. 25C further illustrates a defective memory array 200D that can be detected and removed by individual test structures 120 . This reduces device defects.

26A to 34C illustrate an embodiment where the second material layer 54 both includes a sacrificial material, which is to be replaced by a conductive material. In Figures 26A to 34C, the drawings whose names end with "A" show the cross section along the section BB' of Figure 1A, and the drawings whose names end with "B" show the section along the Section DD' of Figure 1A, and figures whose titles end in "C" depict a section along section CC' of Figure 1A.

FIGS. 26A and 26B illustrate the multilayer stack 58 after performing steps similar or identical to those illustrated and discussed in FIGS. 3 through 10 above to form the stepped structure 68 and the intermetal dielectric 70. Multilayer stack 58 includes alternating first material layers 52A-52D (collectively first material layers 52 ) and second material layers 54A-54C (collectively second material layers 54 ). In subsequent steps, the second material layer 54 may be replaced by a conductive material to define the conductive lines 422 (eg, the word lines shown in FIGS. 33A to 34C ). The second material layer 54 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The first material layer 52 may include insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. In order to facilitate the subsequent etching step, the first material layer 52 may be formed from a material having a high etch selectivity with respect to etching the second material layer 54, and may be formed by relatively etching both the second material layer 54 and the first material layer 52. A material having high etch selectivity forms the substrate 50 . In some embodiments, the substrate 50 may be formed of silicon carbide, the first material layer 52 may be formed of an oxide such as silicon oxide, and the second material layer 54 may be formed of a nitride such as silicon nitride. Each of the second material layer 54 and the first material layer 52 may be formed using, for example, CVD, ALD, PVD, PECVD, or the like. Although FIGS. 26A and 26B depict specific numbers of second material layers 54 and first material layers 52 , other embodiments may include different numbers of second material layers 54 and first material layers 52 .

Further in FIGS. 26A and 26B , a first patterned photoresist 400 is formed over the multilayer stack 58 , and a first trench 402 is formed extending through the multilayer stack 58 . A photosensitive layer may be deposited over the first material layer 52D using spin coating or the like to form the first patterned photoresist 400 . The photosensitive layer may then be patterned by exposing the photosensitive layer to a patterned energy source (eg, a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the photosensitive layer, thereby forming the first patterned photoresist 400 .

In the illustrated embodiment, the first trench 402 extends through the multilayer stack 58 to expose the substrate 50 . In some embodiments, first trench 402 extends through some, but not all, layers of multilayer stack 58 . The first trench 402 may be formed using acceptable photolithography and etching techniques, such as by etching the first layer of material 52 and the second layer of material 52 at a faster rate relative to the material of the substrate 50 material layer 54) etching process. Etching may be any acceptable etching process, such as reactive ion etching, neutral particle beam etching, the like, or combinations thereof. Etching can be anisotropic. In an embodiment in which the substrate 50 is formed of silicon carbide, the first material layer 52 is formed of silicon oxide, and _the second material layer ₅₄ is formed of silicon nitride, hydrogen (H ₂ ) or oxygen (O ₂ ) dry etching to form the first trench 402 .

In FIGS. 27A and 27B , the first trench 402 is enlarged to form a first sidewall recess 404 . Specifically, part of the sidewall of the second material layer 54 exposed by the first trench 402 is recessed, thereby forming a first sidewall groove 404 . Although the sidewalls of the second material layer 54 are shown as straight, the sidewalls may be concave or convex. The first sidewall recess 404 may be formed by an acceptable etching process, such as being selective to the material of the second material layer 54 (eg, selectively etching at a faster rate relative to the materials of the first material layer 52 and the substrate 50 ). material of the second material layer 54). Etching can be isotropic. In embodiments where the substrate 50 is formed of silicon carbide, the first material layer 52 is formed of silicon oxide, and the second material layer 54 is formed of silicon nitride, the first material layer can be enlarged by wet etching using phosphoric acid (H ₃ PO ₄ ). groove 402 . However, any suitable etching process may be used, such as dry selective etching. The first patterned photoresist 400 can be removed by an acceptable ashing or wet stripping process before or after forming the first sidewall groove 404 .

In FIGS. 28A and 28B , a conductive material 406 and a sacrificial material 408 are formed in the first sidewall recess 404 and fill and/or overfill the first trench 402 . One or more additional layers (eg, seed layer, glue layer, barrier layer, diffusion layer, fill layer, and the like) may also be filled in the first trench 402 and the first sidewall groove 404 . In some embodiments, sacrificial material 408 may be omitted. In embodiments comprising a seed layer, the seed layer may comprise titanium nitride, tantalum nitride, titanium, tantalum, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides of the foregoing, or similar. Conductive material 406 may be formed of a conductive material, which may be a metal (eg, tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum), nitride, alloys of the above, or the like. In embodiments where the first material layer 52 is formed of an oxide such as silicon oxide, the seed layer may be formed of titanium nitride and the conductive material 406 may be formed of tungsten. The sacrificial material 408 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The sacrificial material 408 may comprise a material having a high etch selectivity relative to the materials of the first material layer 52, the conductive material 406, and the substrate 50, so that the sacrificial material 408 may be subsequently removed without removing or damaging the first material layer 52. , the conductive material 406 or the substrate 50 . Each conductive material 406 and sacrificial material 408 may be formed by an acceptable deposition process, such as CVD, ALD, PVD, or the like.

Once conductive material 406 and sacrificial material 408 are deposited to fill and/or overfill first trench 402, conductive material 406 and sacrificial material 408 may be planarized to remove excess material outside first trench 402 such that after planarization The conductive material 406 and the sacrificial material 408 completely extend over the top of the first trench 402 . In one embodiment, conductive material 406 and sacrificial material 408 may be planarized using, for example, a CMP process. However, any suitable planarization process, such as a polishing process, may also be used.

In FIGS. 29A and 29B , a second patterned photoresist 410 is formed over the multilayer stack 58 and a second trench 412 is formed extending through the multilayer stack 58 . The second patterned photoresist 410 may be formed by depositing a photosensitive layer over the first material layer 52D using spin coating or the like. The photosensitive layer may then be patterned to form the second patterned photoresist 410 by exposing the photosensitive layer to a patterned energy source (eg, a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the photosensitive layer.

In the illustrated embodiment, the second trench 412 extends through the multilayer stack 58 to expose the substrate 50 . In some embodiments, second trench 412 extends through some, but not all, layers of multilayer stack 58 . Second trench 412 may be formed using acceptable photolithography and etching techniques, such as using an etch process that is selective to multilayer stack 58 (eg, etching first material layer 52 and first material layer 52 at a faster rate relative to the material of substrate 50 material of the second material layer 54). Etching may be any acceptable etching process, such as RIE, NBE, the like, or combinations thereof. Etching can be anisotropic. In an embodiment in which the substrate 50 is formed of silicon carbide, the first material layer 52 is formed of silicon oxide, and _the second material layer ₅₄ is formed of silicon nitride, hydrogen (H ₂ ) or oxygen (O ₂ ) dry etching to form the second trench 412 .

In FIGS. 30A and 30B , the second trench 412 is enlarged to form a second sidewall recess 414 . Specifically, the remaining portion of the second material layer 54 is removed to form the second sidewall groove 414 . Therefore, the second sidewall groove 414 exposes a portion of the conductive material 406 . The second sidewall groove 414 may be formed by an acceptable etching process, for example, selective to the material of the second material layer 54 (eg, selectively etched at a faster rate relative to the materials of the first material layer 52 and the substrate 50 ). material of the second material layer 54). The etching can be any acceptable etching process, and in some embodiments, can be similar to the etching process used to form the first sidewall recess 404 discussed in FIGS. 27A and 27B . Before or after forming the second sidewall grooves 414, the second patterned photoresist 410 may be removed by an acceptable ashing or wet stripping process.

In FIGS. 31A and 31B , a conductive material 416 and a sacrificial material 418 are formed in the second sidewall recess 414 and fill and/or overfill the second trench 412 . One or more additional layers (eg, seed layer, glue layer, barrier layer, diffusion layer, fill layer, and the like) may also be filled in the second trench 412 and the second sidewall groove 414 . In some embodiments, sacrificial material 418 may be omitted. In embodiments comprising a seed layer, the seed layer may comprise titanium nitride, tantalum nitride, titanium, tantalum, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides of the foregoing, or similar. Conductive material 416 may be formed of a conductive material, which may be a metal (eg, tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum), nitride, alloys of the foregoing, or the like. In embodiments where the first material layer 52 is formed of an oxide such as silicon oxide, the seed layer may be formed of titanium nitride and the conductive material 416 may be formed of tungsten. The sacrificial material 418 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The sacrificial material 418 may comprise a material having a high etch selectivity relative to the materials of the first material layer 52, the conductive material 416, and the substrate 50, so that the sacrificial material 418 may be subsequently removed without removing or damaging the first material layer 52. , the conductive material 416 or the substrate 50 . Each conductive material 416 and sacrificial material 418 may be formed by an acceptable deposition process, such as CVD, ALD, PVD, or the like.

Once conductive material 416 and sacrificial material 418 are deposited to fill and/or overfill second trench 412, conductive material 416 and sacrificial material 418 may be planarized to remove excess material outside second trench 412 such that after planarization The conductive material 416 and the sacrificial material 418 completely extend over the top of the second trench 412 . In one embodiment, conductive material 416 and sacrificial material 418 may be planarized using, for example, a CMP process. However, any suitable planarization process, such as a polishing process, may also be used.

In FIGS. 32A and 32B , the sacrificial material 408 and the sacrificial material 418 may be removed by an acceptable process to form a third trench 420 . Acceptable processes may be wet etch processes, dry etch processes, combinations thereof, or the like. In some embodiments, the sacrificial material 408 and the sacrificial material 418 may be removed by an isotropic etching process, wherein the etching process is selective to the material of the sacrificial material 408 and the sacrificial material 418 . Accordingly, sacrificial material 408 and sacrificial material 418 may be removed without removing or damaging first material layer 52 , conductive material 406 , conductive material 416 , or substrate 50 .

In FIGS. 33A and 33B, conductive material 406 and conductive material 416 are etched to enlarge third trench 420 and form leads 422A to 422C from the layers of conductive material 406 and conductive material 416 (eg, collectively referred to as lead 422C). 422 character lines). The third trench 420 separates adjacent conductive lines 422 and separates portions of the first material layer 52 . As leads 422 are formed from adjacent portions of conductive material 406 and conductive material 416, each lead 422 may include a seam, as depicted in FIGS. 33A and 33B. Etching conductive material 406 and conductive material 416 to expand third trench 420 may expose sidewalls of first material layer 52 . In some embodiments, conductive material 406 and conductive material 416 may be etched using, for example, an anisotropic etch process, although any suitable etch process may be used. In some embodiments, the etching process is performed until the material of the conductive material 406 and the conductive material 416 extending beyond the sidewalls of the first material layer 52 is removed, and the sidewalls of the conductive material 406 and the conductive material 416 are flush with the sidewalls of the first material layer 52 side wall. Accordingly, the wire 422 may have a width similar to or the same as that of the first material layer 52 . Although the sidewalls of the conductive lines 422 are shown as straight, the sidewalls may be concave or convex.

Forming wires 422 by forming and replacing second material layer 54 in multilayer stack 58 improves the aspect ratio of the rows of memory array 200 and avoids twisting or collapse of features during formation. This reduces device defects and improves device performance. The steps in FIGS. 26A to 33B may be performed instead of the steps in FIGS. 11A to 13C, and the remaining steps for forming the memory array 200 are the same as described above (for example, performing the steps in FIGS. 3 to 10 , followed by the steps in Figures 26A to 33B, and finally the steps in Figures 14B to 24D).

Figures 34A-34C illustrate the embodiment of Figures 26A-33B after performing the steps of Figures 14B-24D. The structure of FIG. 34B may be similar to that shown in FIG. 24C, except that the wire 72 is replaced by a wire 422 formed of conductive material 406 and conductive material 416 .

Embodiments may realize several advantages. For example, simultaneously forming trenches 110 extending to lines 72A-72C, and simultaneously forming conductive contacts 112 in trenches 110 reduces process time, reduces costs associated with additional patterning processes, and increases throughput. In order to confirm defective connections, a test structure 120 may be formed over the memory array 200 . Therefore, defective memory array 200 can be removed and device defects can be reduced.

According to an embodiment of the present disclosure, a memory array includes a first word line above a semiconductor substrate, the longitudinal axis of the first word line extends in a first direction; Square second word line, the second direction is perpendicular to the main surface of the semiconductor substrate, the longitudinal axis of the second word line extends in the first direction; the memory film contacting the first word line and the second word line ; the oxide semiconductor layer contacting the first source line and the first bit line, the memory film is between the oxide semiconductor layer and each of the first word line and the second word line; and the first word line and the first word line A test structure above the second word line, the test structure includes a first wire electrically coupling the first word line to the second word line, the longitudinal axis of the first wire extends in a first direction. In one embodiment, the first word line has a first length greater than a second length of the second word line. In one embodiment, the test structure further includes a second wire, the second wire is electrically coupled to the first word line, the second wire extends to the boundary of the memory array, and the longitudinal axis of the second wire is in the first direction. Extend upwards. In one embodiment, the device further includes a third word line adjacent to the first word line in a third direction perpendicular to the first direction, and the memory film and the oxide semiconductor layer are adjacent to the first word line in the third direction. Between the word line and the third word line, the test structure further includes a second wire, the second wire electrically couples the first word line to the third word line, and the longitudinal axis of the second wire is in the third direction extend. In one embodiment, the first word line includes a seam between the first conductive material and the second conductive material. In one embodiment, the device further includes a third wordline lower than the first wordline in the second direction, the longitudinal axis of the third wordline extends in the first direction, and the test structure further includes a second conductive line The first word line is electrically coupled to the third word line, and the longitudinal axis of the second wire extends in the first direction. In one embodiment, the first wordline has a first length greater than the second length of the second wordline, and the third wordline has a third length greater than the first length.

According to another embodiment of the present disclosure, an apparatus includes a first word line above a semiconductor substrate, the first word line has a first length in a first direction; a second word line above the semiconductor substrate, the second word line The element line has a second length in the first direction, and the second length is equal to the first length; the first intermetal dielectric above the first word line; contacting the first word line and the first intermetal dielectric The first memory film; the first oxide semiconductor layer above the first memory film, the first oxide semiconductor layer contacts the source line and the bit line; extends through the first intermetal dielectric and is electrically coupled a first conductive contact to the first word line; a second conductive contact electrically coupled to the second word line; and extending over the first IMD and electrically coupling the first conductive contact to A first conductor of the second conductive contact, the first conductor extending in a second direction perpendicular to the first direction. In one embodiment, in a third direction perpendicular to the main surface of the semiconductor substrate, the first distance between the first word line and the semiconductor substrate is equal to the second distance between the second word line and the semiconductor substrate . In one embodiment, the intermetal dielectric has a stepped structure in a cross-sectional view. In one embodiment, the device further includes a second memory film contacting the second word line; a second oxide semiconductor layer above the second memory film, and the second oxide semiconductor layer contacts the source line and the bit line and a first dielectric material separating the first oxide semiconductor layer and the second oxide semiconductor layer. In one embodiment, the device further includes a second intermetal dielectric over the second word line, the second memory film contacts the second intermetal dielectric; and separates the first intermetal dielectric from the second A second dielectric material of the IMD, the second dielectric material comprising a material different from the first dielectric material. In one embodiment, the device further includes a third word line above the semiconductor substrate, the third word line has a third length in the first direction, the third length is different from the first length and the second length; electrically coupled A third conductive contact connected to the first word line; a fourth conductive contact electrically coupled to the third word line; and a second wire electrically coupled to the third conductive contact to the fourth conductive contact. The two wires extend in the first direction. In one embodiment, in the first direction, the first oxide semiconductor layer is between the first conductive contact and the third conductive contact.

According to yet another embodiment of the present disclosure, a method includes depositing a multilayer stack over a semiconductor substrate, the multilayer stack including alternating first and second materials; patterning the multilayer stack such that the multilayer stack includes a stepped structure in cross-sectional view; Forming an intermetallic dielectric above the stepped structure of the multilayer stack; forming a plurality of word lines in the multilayer stack; depositing a memory film in the multilayer stack and adjacent to the plurality of word lines; depositing an oxide semiconductor layer in the above the memory film; etching the intermetallic dielectric to form a first opening exposing a first word line in the plurality of word lines and a second opening exposing a second word line in the plurality of word lines, The first opening extends to a first depth, and the second opening extends to a second depth different from the first depth; a first conductive contact is formed in the first opening and electrically coupled to the first word line, and a second opening is formed Two conductive contacts are in the second opening and are electrically coupled to the second word line; The contact is electrically coupled to the second conductive contact. In one embodiment, the first conducting wire, the first word line and the second word line extend in a first direction. In one embodiment, the method further includes etching the intermetal dielectric to form a third opening exposing the first word line and a fourth opening exposing the third word line in the plurality of word lines, the third opening and the fourth opening extends to the first depth; forming a third conductive contact in the third opening and electrically coupled to the first word line, and forming a fourth conductive contact in the fourth opening and electrically coupled to the first word line three word lines; and forming a second conductive line above the IMD, the third conductive contact and the fourth conductive contact, the second conductive line electrically couples the third conductive contact to the fourth conductive contact. In one embodiment, the first word line and the second word line extend in a first direction, and the second conductive line extends in a second direction perpendicular to the first direction. In one embodiment, the first material includes a dielectric material, the second material includes a conductive material, and forming the plurality of word lines in the multilayer stack includes patterning the multilayer stack to separate adjacent words formed of the second material. Wire. In one embodiment, the first material includes oxide, the second material includes nitride, and forming a plurality of word lines in the multilayer stack includes patterning the multilayer stack and replacing the second material with a conductive material.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24: position 50: Substrate 52, 52A, 52B, 52C, 52D: first material layer 54, 54A, 54B, 54C: second material layer 56: photoresist 58: Multi-layer stacking 60,62,64: area 61: opening 68: Ladder-like structure 70: Intermetal dielectric 72, 72A, 72B, 72C: Wire 80: hard mask 82:Patterned photoresist 86: Groove 90:Memory film 92: oxide semiconductor layer 98: Dielectric material 100,104: Groove 102: Dielectric material 106,108: Wire 110: Groove 112: Conductive contact 114: the first dielectric layer 115: second dielectric layer 116: Conductive contact 118: wire 120: Test structure 200,200D: memory array 202: memory unit 204: Transistor 206: Arrow 300: Wafer 301: area 302: gate dielectric layer 304: gate electrode 306: source/drain region 308:Gate spacer 310: the first interlayer dielectric 312: Second interlayer dielectric 314: Source/Drain Contacts 316: gate contact 320: Interconnect structure 322: Conductive features 324: dielectric layer 400: First patterned photoresist 402: The first groove 404: first side wall groove 406: Conductive material 408: Sacrificial material 410: Second patterned photoresist 412: second groove 414: second side wall groove 416: Conductive material 418:Sacrificial material 420: The third groove 422, 422A, 422B, 422C: Wire A-A',BB',CC',D-D': section

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. 1A and 1B illustrate a perspective view and a circuit diagram of a memory array, according to some embodiments. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11A, Figure 11B, Figure 11C, Figure 12A Figure, Figure 12B, Figure 12C, Figure 13A, Figure 13B, Figure 13C, Figure 14A, Figure 14B, Figure 14C, Figure 15A, Figure 15B, Figure 15C, Figure 16A, Figure 16B, Figure 16C, Figure 17A, Figure 17B, Figure 17C, Figure 18A, Figure 18B, Figure 18C, Figure 19A, Figure 19B, Figure 19C, Figure 20A, Figure 20B Figure, Figure 20C, Figure 20D, Figure 21A, Figure 21B, Figure 21C, Figure 21D, Figure 22A, Figure 22B, Figure 22C, Figure 23A, Figure 23B, Figure 23C, Figure 24A, Figure 24B, Figure 24C, Figure 24D, Figure 25A, Figure 25B, Figure 25C, Figure 26A, Figure 26B, Figure 27A, Figure 27B, Figure 28A, Figure 28B Figure, Figure 29A, Figure 29B, Figure 30A, Figure 30B, Figure 31A, Figure 31B, Figure 32A, Figure 32B, Figure 33A, Figure 33B, Figure 34A, Figure 34B and Figure 34C illustrates various views of fabricating a semiconductor device including a memory array, according to some embodiments.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

52: The first material layer

72: wire

90:Memory film

92: oxide semiconductor layer

98: Dielectric material

102: Dielectric material

106,108: Wire

200: memory array

202: memory unit

204: Transistor

206: Arrow

A-A',BB',CC',D-D': section

Claims (20)

A memory array comprising: a first wordline above a semiconductor substrate, wherein a longitudinal axis of the first wordline extends in a first direction; a second word line above the first word line in a second direction perpendicular to a main surface of the semiconductor substrate, wherein a longitudinal axis of the second word line is at the first extend in the direction a memory film contacting the first word line and the second word line; an oxide semiconductor layer contacting a first source line and a first bit line, wherein the memory film is between the oxide semiconductor layer and each of the first word line and the second word line; as well as A test structure is above the first word line and the second word line, the test structure includes a first wire electrically coupling the first word line to the second word line, wherein the first A longitudinal axis of the wire extends in the first direction. The memory array of claim 1, wherein the first word line has a first length greater than a second length of the second word line. The memory array of claim 1, wherein the test structure further includes a second wire, wherein the second wire is electrically coupled to the first word line, and wherein the second wire extends to the memory array A boundary of , and wherein a longitudinal axis of the second conductive line extends in the first direction. The memory array according to claim 1, further comprising a third word line adjacent to the first word line in a third direction perpendicular to the first direction, wherein the memory film and the oxide The semiconductor layer is between the first word line and the third word line in the third direction, wherein the test structure further includes a second wire, wherein the second wire electrically couples the first word line to the third word line, and wherein a longitudinal axis of the second conductive line extends in the third direction. The memory array of claim 1, wherein the first word line includes a seam between the first conductive material and the second conductive material. The memory array as claimed in claim 1, further comprising a third word line lower than the first word line in the second direction, wherein a longitudinal axis of the third word line is in the first direction Extending upward, wherein the test structure further includes a second wire electrically coupling the first word line to the third word line, wherein a longitudinal axis of the second wire extends in the first direction. The memory array of claim 6, wherein the first wordline has a first length greater than a second length of the second wordline, and wherein the third wordline has a third length greater than the first length. A device comprising: a first word line above a semiconductor substrate, the first word line has a first length in a first direction; a second word line above the semiconductor substrate, the second word line has a second length in the first direction, wherein the second length is equal to the first length; a first intermetal dielectric over the first word line; a first memory film, contacting the first word line and the first intermetal dielectric; A first oxide semiconductor layer is above the first memory film, and the first oxide semiconductor layer is in contact with a source line and a bit line; a first conductive contact extending through the first IMD and electrically coupled to the first word line; a second conductive contact electrically coupled to the second word line; and a first wire extending over the first intermetal dielectric and electrically coupling the first conductive contact to the second conductive contact, wherein the first wire is in a second direction perpendicular to the first direction extend in the direction. The device according to claim 8, wherein in a third direction perpendicular to a main surface of the semiconductor substrate, a first distance between the first word line and the semiconductor substrate is equal to that of the second word line A second distance between the element line and the semiconductor substrate. The device as claimed in claim 8, wherein the intermetallic dielectric has a stepped structure in a cross-sectional view. The device as described in claim 8, further comprising: a second memory film contacting the second word line; a second oxide semiconductor layer on the second memory film, the second oxide semiconductor layer contacts the source line and the bit line; and A first dielectric material separates the first oxide semiconductor layer from the second oxide semiconductor layer. The device as described in claim 11, further comprising: a second IMD over the second word line, wherein the second memory film contacts the second IMD; and A second dielectric material separates the first IMD from the second IMD, the second dielectric material comprising a material different from the first dielectric material. The device as described in claim 8, further comprising: a third word line above the semiconductor substrate, the third word line has a third length in the first direction, wherein the third length is different from the first length and the second length; a third conductive contact electrically coupled to the first word line; a fourth conductive contact electrically coupled to the third word line; and A second wire electrically couples the third conductive contact to the fourth conductive contact, wherein the second wire extends in the first direction. The device according to claim 13, wherein in the first direction, the first oxide semiconductor layer is between the first conductive contact and the third conductive contact. A method comprising: depositing a multilayer stack over a semiconductor substrate, the multilayer stack including alternating a first material and a second material; patterning the multilayer stack such that the multilayer stack includes a stepped structure in cross-sectional view; forming an intermetal dielectric over the stepped structure of the multilayer stack; forming a plurality of word lines in the multilayer stack; depositing a memory film in the multilayer stack adjacent to the word lines; Depositing an oxide semiconductor on the memory film layer; Etching the IMD to form a first opening exposing a first word line among the word lines and a second opening exposing a second word line among the word lines openings, wherein the first opening extends to a first depth, and wherein the second opening extends to a second depth different from the first depth; forming a first conductive contact in the first opening and electrically coupled to the first word line, and a second conductive contact in the second opening and electrically sexually coupled to the second word line; and A first conductive line is formed over the IMD, the first conductive contact and the second conductive contact, wherein the first conductive line electrically couples the first conductive contact to the second conductive contact. The method of claim 15, wherein the first conductive line, the first word line and the second word line extend in a first direction. The method as described in claim 15, further comprising: Etching the IMD to form a third opening exposing a first word line and a fourth opening exposing a third word line among the word lines, wherein the third opening and the fourth opening extends to the first depth; forming a third conductive contact and a fourth conductive contact, the third conductive contact is in the third opening and is electrically coupled to the first word line, the fourth conductive contact is in the fourth opening and is electrically coupled sexually coupled to the third word line; and A second conductive line is formed over the IMD, the third conductive contact and the fourth conductive contact, wherein the second conductive line electrically couples the third conductive contact to the fourth conductive contact. The method of claim 17, wherein the first word line and the second word line extend in a first direction, and wherein the second conductive line extends in a second direction perpendicular to the first direction extend. The method of claim 15, wherein the first material comprises a dielectric material, wherein the second material comprises a conductive material, and wherein forming the wordlines in the multilayer stack includes patterning the multilayer stack to separate The adjacent word lines formed by the second material. The method of claim 15, wherein the first material comprises oxide, wherein the second material comprises nitride, and wherein forming the word lines in the multilayer stack includes patterning the multilayer stack and replacing with a conductive material the second material.

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