TW202245391A - Dc-dc power conversion system and power conversion method thereof - Google Patents

Abstract

A DC-DC power conversion system includes a resonant switched-capacitor converter and a controller. The resonant switched-capacitor converter is used to receive an input voltage and is switched between a first state and a second state to generate an output voltage. The resonant switched-capacitor converter includes an input node, a resonant tank, an output capacitor, a first set of switches and a second set of switches. The input node is used to receive the input voltage. The output capacitor is used to generate the output voltage. The first set of switches is coupled to the resonant tank and the output capacitor, and is used to receive a first control signal to be turned on in the first state, and to be turned off in the second state. The second set of switches is coupled to the resonant tank and the output capacitor, and is used to receive a second control signal to be turned on in the second state, and to be turned off in the first state. The controller adjusts the first control signal and the second control signal according to the output voltage.

Description

DC-DC power conversion system and power conversion method thereof

The invention relates to electronic circuits, in particular to a DC-DC power conversion system and a power conversion method thereof.

A DC-DC converter is a device that converts a DC voltage into a different DC voltage. It is commonly used in mobile electronic devices such as mobile phones and notebook computers to provide power. A resonant switched-capacitor converter (RSCC) is a DC-DC converter that generates no power consumption or only a small amount of power consumption when transmitting power.

A resonant switched capacitor converter converts an input voltage to an output voltage with a fixed conversion ratio. When the input voltage is too large, the resonant switched capacitor converter still generates an excessively large output voltage with a fixed conversion ratio, causing damage to the electronic device.

The related art utilizes an additional buck converter (bulk converter) to control the input voltage of the resonant switched capacitor converter, so as to control the output voltage of the resonant switched capacitor converter. However, the buck converter occupies a large amount of circuit area, resulting in increased manufacturing costs.

An embodiment of the present invention provides a DC-DC power conversion system, including a resonant switched capacitor converter and a controller. The resonant switched capacitor converter is used for receiving an input voltage, and switching between a first state and a second state to generate an output voltage. The resonant switched capacitor converter includes an input terminal, a resonant tank, an output capacitor, a first set of switches, and a second set of switches. The input end is used for receiving the input voltage. The output capacitor has a first terminal for generating an output voltage; and a second terminal coupled to the ground terminal. The first group of switches is coupled to the resonance tank and the output capacitor, and is used for receiving the first control signal to be turned on in the first state and turned off in the second state. The second group of switches is coupled to the resonant tank and the output capacitor, and is used for receiving the second control signal to be turned on in the second state and turned off in the first state. The output terminal is coupled to the output capacitor for outputting the output voltage. The controller is coupled to the first set of switches and the second set of switches, and is used to adjust the first control signal according to the output voltage to control the first conduction time of the first set of switches, and adjust the second control signal according to the output voltage to control the second set of switches. The second conduction time of the group switch.

An embodiment of the present invention provides another power conversion method, which is suitable for a DC-DC power conversion system. The DC-DC power conversion system includes a resonant switched capacitor converter and a controller. The resonant switched capacitor converter includes a resonant tank, an output capacitor, a first set of switches coupled to the resonant tank and the output capacitor, and a second set of switches. Coupled to the resonant tank and output capacitor. The power conversion method includes switching a resonant switched capacitor converter between a first state and a second state to generate an output voltage, a controller adjusts a first control signal and a second control signal according to the output voltage, and a first set of switches receives the first control signal The signal is turned on for a first conduction time in the first state, and the second group of switches is turned on for a second conduction time in the second state when receiving the second control signal.

FIG. 1 is a block diagram of a DC-DC power conversion system 1 in an embodiment of the present invention. The DC-DC power conversion system 1 uses a resonant switched-capacitor converter (RSCC) to convert the input voltage Vin to the output voltage Vout, and the output voltage Vout can be adjusted without a step-down converter (bulk converter). The output voltage Vout is maintained at a fixed value, so as to provide over-voltage protection without greatly increasing the circuit area. The input voltage Vin and the output voltage Vout are DC voltages, and the output voltage Vout can be greater than or less than the input voltage Vin. In some embodiments, the DC-DC power conversion system 1 can down-convert the input voltage Vin to generate the output voltage Vout, and the ratio of the input voltage Vin to the output voltage Vout can be greater than 2:1. For example, the ratio of the input voltage Vin to the output voltage Vout can be 4 to 1, and when the input voltage Vin exceeds 60V, the output voltage Vout can still be maintained below 13V.

The DC-DC power conversion system 1 includes a resonant switched capacitor converter (RSCC) 10 , a controller 12 , an input 14 and an output 16 . The controller 12 can repeatedly and alternately switch the RSCC 10 between the first state and the second state. The RSCC 10 can receive an input voltage Vin, and switch between a first state and a second state to generate an output voltage Vout.

The RSCC 10 may include a first resonant tank 103 , an output capacitor Co, a first set of switches 101 and a second set of switches 102 . The input terminal 14 can receive an input voltage Vin from a front-end capacitor or a front-end circuit. The first resonant tank 103 can receive the input voltage Vin from the input terminal 14 and generate a sinusoidal voltage and a sinusoidal current, which can achieve zero current switching of the RSCC 10 and reduce power loss of the RSCC 10 . The first set of switches 101 can be coupled to the first resonant tank 103 and the output capacitor Co, and can receive a first control signal Sc1 to be turned on in a first state and turned off in a second state. The second set of switches 102 can be coupled to the first resonant tank 103 and the output capacitor Co, and can receive the second control signal Sc2 to be turned on in the second state and turned off in the first state. The first group of switches 101 and the second group of switches 102 can respectively control the coupling relationship between the first resonant tank 103 and the output capacitor Co in the first state and the second state according to the first control signal Sc1 and the second control signal Sc2, The output voltage Vout is generated by the output capacitor Co. In some embodiments, in the first state, the first group of switches 101 can connect the first resonant tank 103 in series between the input terminal 14 and the output capacitor Co; in the second state, the second group of switches 102 can connect the first resonance tank 103 in parallel. A resonant tank 103 and an output capacitor Co. The output terminal 16 can be coupled to the output capacitor Co, and can output the output voltage Vout to subsequent circuits, such as a central processing unit.

The controller 12 is coupled to the first set of switches 101 and the second set of switches 102, and can adjust the first control signal Sc1 according to the output voltage Vout to control the first conduction time of the first set of switches 101 in a steady state, and according to The output voltage Vout adjusts the second control signal Sc2 to control the second conduction time of the second set of switches 102 to generate the output voltage Vout.

Although FIG. 1 shows one particular connection of RSCC 10, in some embodiments, the internal circuitry of RSCC 10 may be connected in other ways. For example, the first resonant tank 103 may be coupled to the output capacitor Co, and the first group of switches 101 and the second group of switches 102 may not be directly coupled to the output capacitor Co, and the coupling methods of other circuits are the same as those in FIG. 1 .

FIG. 2 is a schematic circuit diagram of a DC-DC power conversion system 1 in FIG. 1 . The RSCC 10 in FIG. 2 can provide a voltage conversion ratio of 4:1, its rated input voltage range can be between 48V and 60V, and the output voltage Vout can be maintained below 13V. The RSCC 10 includes a storage capacitor C3, a first resonant tank 103, a second resonant tank 104, an output capacitor Co, and transistors Q1 to Q10. The transistors Q1 to Q10 may be N-type metal-oxide semiconductor field-effect transistors (MOSFETs), but are not limited thereto.

The first resonance tank 103 includes a first resonance capacitor C1 and a first resonance inductor L1. The first resonant capacitor C1 has a first terminal and a second terminal. The first resonant inductor L1 has a first end; and a second end coupled to the first end of the output capacitor Co. The second resonance tank 104 includes a second resonance capacitor C2 and a second resonance inductor L2. The second resonance capacitor C2 has a first terminal and a second terminal. The second resonant inductor L2 has a first end; and a second end coupled to the first end of the output capacitor Co. The output capacitor Co has a first terminal capable of generating the output voltage Vout; and a second terminal coupled to the ground terminal. The ground terminal can provide a ground voltage Vss, such as 0V.

Transistors Q1 to Q3 , Q7 and Q8 can form a first set of switches 101 . The transistor Q1 has a first end coupled to the input end 14 ; a second end; and a control end for receiving the first control signal Sc1 . The transistor Q2 has a first terminal; a second terminal coupled to the first terminal of the first resonant capacitor C1; and a control terminal for receiving the first control signal Sc1. The transistor Q3 has a first end coupled to the second end of the first resonant capacitor C1; a second end coupled to the first end of the first resonant inductor L1; and a control end for receiving the first control signal Sc1 . The transistor Q7 has a first end coupled to the first end of the second resonant inductor L2; a second end coupled to the first end of the second resonant capacitor C2; and a control end for receiving the first control signal Sc1 . The transistor Q8 has a first terminal coupled to the second terminal of the second resonant capacitor C2; a second terminal coupled to the ground terminal; and a control terminal for receiving the first control signal Sc1.

Transistors Q4 to Q6 , Q9 and Q10 may form a second set of switches 102 . The transistor Q4 has a first terminal coupled to the first terminal of the second resonance capacitor C2; a second terminal coupled to the first terminal of the storage capacitor C3; and a control terminal for receiving the second control signal Sc2. The transistor Q5 has a first terminal coupled to the second terminal of the storage capacitor C3; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2. The transistor Q6 has a first end coupled to the second end of the second resonant capacitor C2; a second end coupled to the first end of the second resonant inductor L2; and a control end for receiving the second control signal Sc2 . The transistor Q9 has a first end coupled to the first end of the first resonant inductor L1; a second end coupled to the first end of the first resonant capacitor C1; and a control end for receiving the second control signal Sc2 . The transistor Q10 has a first terminal coupled to the second terminal of the first resonant capacitor C1; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2.

During operation, the first resonant tank 103 and the second resonant tank 104 respectively provide a voltage conversion ratio of 2:1, the input voltage Vin can be 4 times the output voltage Vout, and the voltage across the storage capacitor C2 can be 2 times the output voltage Vout, and the cross-voltages of the first resonant capacitor C1, the second resonant capacitor C2, and the output capacitor Co can respectively be 1 times the output voltage Vout, so that the RSCC 10 can provide a voltage conversion ratio of 4:1.

In the first state, the first group of switches 101 and the second group of switches 102 can be configured such that the first terminal of the storage capacitor C3 is coupled to the input terminal 14, and the first terminal of the first resonant capacitor C1 is coupled to the storage capacitor C3 The second end of the first resonant capacitor C1 is coupled to the first end of the second resonant capacitor C2 and the first end of the output capacitor Co, the second end of the second resonant capacitor C2 and the first end of the output capacitor Co The two terminals are coupled to the ground terminal, the first resonant capacitor C1 can charge the output capacitor Co, and the second resonant capacitor C2 can discharge the output capacitor Co.

In the second state, the first set of switches 101 and the second set of switches 102 can be configured such that the first end of the output capacitor Co is coupled to the first end of the first resonant capacitor C1 and the second end of the second resonant capacitor C2 , the first terminal of the storage capacitor C3 is coupled to the first terminal of the second resonant capacitor C2, and the second terminal of the storage capacitor C3 is coupled to the ground terminal. The first resonance capacitor C1 can discharge the output capacitor Co, and the second resonance capacitor C2 can charge the output capacitor Co.

The RSCC 10 can alternately switch between the first state and the second state to continuously charge and discharge all capacitors in the RSCC 10 to maintain charge balance, and at the same time transmit power from the input terminal 14 to the output terminal 16 to generate the output voltage Vout. In order to achieve the charge balance of all capacitors in the RSCC 10, the controller 12 can adjust the first control signal Sc1 and the second control signal Sc2 to have equal duty cycles, so that the first resonant tank 103 and the second resonant tank 104 respectively generate The sinusoidal current Io1 and current Io2 with opposite phases and the same average magnitude, and both the current Io1 and the current Io2 are half (Io/2) of the output current Io of the RSCC 10 in the first state and the second state.

The controller 12 can adjust the first control signal Sc1 according to the output voltage Vout to control the first turn-on time and the first turn-off time of the first set of switches 101, and adjust the second control signal Sc2 according to the output voltage Vout to control the second set of switches 102. The second on-time and the second off-time. For example, when the output voltage Vout is lower than the upper limit of the output voltage (such as 13V), the controller 12 can adjust the first control signal Sc1 to be close to 50% of the duty cycle, so that the first conduction time of the first group of switches 101 is substantially It is equal to the first cut-off time of the first set of switches 101, and the second control signal Sc2 is adjusted to be close to 50% duty cycle, so that the second turn-on time of the second set of switches 102 is substantially equal to the second turn-on time of the second set of switches 102. cut-off time, and then generate 1/4 of the input voltage Vin as the output voltage Vout. When the output voltage Vout exceeds the upper limit of the output voltage, the controller 12 can make the first conduction time of the first group of switches 101 shorter than the first period of the first group of switches 101 by adjusting the first control signal Sc1 to be less than 50% of the duty cycle. Cut-off time, and adjust the second control signal Sc2 to be less than 50% of the duty cycle and control the second on-time of the second group of switches 102 to be less than the second off-time of the second group of switches 102, thereby adjusting the output voltage Vout at the output voltage within the upper limit to provide overvoltage protection. When the output voltage Vout is much higher than 13V, the controller 12 can adjust the first control signal Sc1 and the second control signal Sc2 to close to 0% duty cycle to turn off the RSCC 10 and provide overvoltage protection. The first on-time and the second on-time are non-overlapping, and the length of the first on-time can be equal to the length of the second on-time, and the length of the first off-time can be equal to the length of the second off-time.

In some embodiments, when starting up, the first on-time and the second on-time may be equal to the preset on-time, and gradually increase from the preset on-time to the on-time in a steady state. The preset on-time can be much shorter than 50% duty cycle of the first control signal Sc1 and the second control signal Sc2. For example, the preset on-time may be equal to the 0% duty cycle of the first control signal Sc1 and the second control signal Sc2. When starting up, the input voltage Vin may have a surge due to the influence of the switching of the power switch, the controller 12 can gradually adjust the first control signal Sc1 and the second control signal Sc2 from 0% duty cycle (preset conduction time) to 48 % duty cycle (on-time in steady state), so as to stabilize the DC-DC power conversion system 1 without being affected by the input voltage Vin during startup.

The DC-DC power conversion system 1 adjusts the first control signal Sc1 and the second control signal Sc2 according to the output voltage Vout to adjust the output voltage Vout, and provides overvoltage protection without greatly increasing the circuit area.

FIG. 3 is a flowchart of the power conversion method 300 of the DC-DC power conversion system 1 . The power conversion method 300 includes steps S302 to S308 for adjusting the output voltage Vout. Any reasonable technical changes or step adjustments fall within the scope of the disclosure of the present invention. Steps S302 to S308 are described below:

Step S302: RSCC 10 is switched between the first state and the second state to generate the output voltage Vout;

Step S304: the controller 12 adjusts the first control signal Sc1 and the second control signal Sc2 according to the output voltage Vout;

Step S306: the first group of switches 101 receives the first control signal Sc1 to conduct the first conduction time in the first state;

Step S308: The second switch 102 is turned on for a second conduction time when it receives the second control signal Sc2 and is in the second state.

The detailed description of the power conversion method 300 can be found in the preceding paragraphs, and will not be repeated here.

FIG. 4 is a schematic circuit diagram of a controller 12 . The controller 12 includes a voltage divider 120 , a first comparison circuit 121 , a second comparison circuit 122 , a first sum gate 123 , a flip-flop 124 , a second sum gate 125 and a third sum gate 126 . The voltage divider 120 is coupled to the first end of the output capacitor Co, the first comparison circuit 121 is coupled to the voltage divider 120, the second comparison circuit 122 is coupled to the first comparison circuit 121, and the first AND gate 123 is coupled to In the second comparison circuit 122 , the flip-flop 124 is coupled to the first AND gate 123 , and the second AND gate 125 and the third AND gate 126 are coupled to the flip-flop 124 .

The voltage divider 120 can receive the output voltage Vout from the first terminal of the output capacitor Co to generate a divided voltage Vd of the output voltage Vout. The voltage divider 120 may include resistors Rd1 and Rd2. The resistor Rd1 includes a first terminal coupled to the first terminal of the output capacitor Co; and a second terminal. The resistor Rd2 includes a first terminal coupled to the second terminal of the resistor Rd1 for providing a divided voltage Vd; and a second terminal coupled to the ground terminal.

The first comparison circuit 121 can compare the divided voltage Vd and the reference voltage Vref to generate a first comparison voltage Va. The reference voltage Vref may correspond to an output voltage upper limit of the output voltage Vout. The reference voltage Vref can be a fixed voltage level. Increasing the reference voltage Vref can increase the upper limit of the output voltage. The first comparison circuit 121 may include a comparator 1210 and a capacitor Cc. The comparator 1210 includes a positive input terminal for receiving the reference voltage Vref; an inverting input terminal coupled to the second terminal of the resistor Rd1 for receiving the divided voltage Vd; and an output terminal for receiving the divided voltage Vd according to the reference voltage Vref and the divided voltage. The difference between the voltage Vd outputs a comparison current. Comparator 1210 may have a gain gm. The comparison current may be positively correlated with the difference between the reference voltage Vref and the divided voltage Vd. The capacitor Cc includes a first terminal coupled to the output terminal of the comparator 1210 ; and a second terminal coupled to the ground terminal. The comparison current can charge the capacitor Cc to generate the first comparison voltage Va. When the divided voltage Vd is less than the reference voltage Vref, the difference between the reference voltage Vref and the divided voltage Vd is positive, and the first comparison voltage Va is larger; when the divided voltage Vd exceeds the reference voltage Vref, the reference voltage Vref and the divided voltage If the difference between the voltages Vd is negative, the first comparison voltage Va is smaller.

The second comparison circuit 122 can compare the first comparison voltage Va and the ramp voltage Vramp to generate a second comparison voltage Vc. The ramp voltage Vramp can be a sawtooth wave, which can be generated by an external signal generator according to the clock signal CLK. The period of the sawtooth wave and the period of the clock signal CLK can be the same. The second comparison circuit 122 includes a positive input end coupled to the first end of the capacitor Cc for receiving the first comparison voltage Va; an inverting input end for receiving the ramp voltage Vramp; and an output end for receiving the first comparison voltage Va; A difference between the comparison voltage Va and the ramp voltage Vramp outputs a second comparison voltage Vc. When the ramp voltage Vramp is smaller than the first comparison voltage Va, the second comparison voltage Vc can be at a logic high level; when the ramp voltage Vramp exceeds the first comparison voltage Va, the second comparison voltage Vc can be at a logic low level.

The first AND gate 123 can perform an AND operation on the second comparison voltage Vc and the clock signal CLK to generate the control signal Vb. The first AND gate 123 may include a first input end coupled to the output end of the second comparison circuit 122 for receiving the second comparison voltage Vc; a second input end for receiving the clock signal CLK; and an output end, Used to output the control signal Vb. The frequency of the clock signal CLK may be positively correlated with the switching frequencies of the first set of switches 101 and the second set of switches 102 . For example, the 1/2 frequency of the clock signal CLK can be the switching frequency of the first set of switches 101 and the second set of switches 102 . If the output voltage Vout exceeds the upper limit of the output voltage, the waveforms of the control signal Vb and the second comparison voltage Vc may be the same. If the output voltage Vout is lower than the upper limit of the output voltage, the waveforms of the control signal Vb and the clock signal CLK can be the same.

，用以將反向輸出訊號Sqb。正反器124可在每次控制訊號Vb的上升緣對輸出訊號Sq及反向輸出訊號Sqb進行反向切換(toggle)。 The flip-flop 124 can generate an output signal Sq and an inverted output signal Sqb according to the control signal Vb. The output signal Sq and the inverted output signal Sqb can be mutually inverted signals. The flip-flop 124 can be a JK flip-flop, including a J input terminal for receiving a logic high level SH; a K input terminal for receiving a logic high level SH; a clock input terminal ck coupled to the first and The output terminal of the gate 123 is used to receive the control signal Vb; the output terminal Q is used to output the output signal Sq; and the reverse output terminal

, used to reverse the output signal Sqb. The flip-flop 124 can reversely switch the output signal Sq and the reverse output signal Sqb every time the control signal Vb rises.

The second AND gate 125 can perform an AND operation on the control signal Vb and the output signal Sq to generate the first control signal Sc1. The third AND gate 126 can perform an AND operation on the control signal Vb and the inverted output signal Sqb to generate the second control signal Sc2.

The operation of the controller 12 in FIG. 4 will be explained below with FIG. 5 . FIG. 5 is a waveform diagram of the controller 12 when the divided voltage Vd exceeds the reference voltage Vref in FIG. 4, wherein the horizontal axis represents time, and the vertical axis represents signal magnitude.

Between time t1 and t2, the ramp voltage Vramp is smaller than the first comparison voltage Va, and the control signal Vb is at a logic high level. The flip-flop 124 can output a logic high level as the control signal Vb, and can output a logic low level as the inverted output signal Sqb, so the second AND gate 125 performs an AND operation on the control signal Vb and the output signal Sq to generate a logic high The level is used as the first control signal Sc1, and the third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate a logic low level as the second control signal Sc2. The time t1 to t2 may be the first conduction time of the first set of switches 101 , represented by a time period Td1 . When the output voltage Vout exceeds the upper limit of the output voltage, the length of the period Td1 can be shortened as the output voltage Vout exceeds the upper limit of the output voltage.

Between time t2 and t4, the ramp voltage Vramp exceeds the first comparison voltage Va, and the control signal Vb is at a logic low level. The flip-flop 124 maintains the control signal Vb at a logic high level, and maintains the inverted output signal Sqb at a logic low level, so the second AND gate 125 performs an AND operation on the control signal Vb and the output signal Sq to generate a logic low The level is used as the first control signal Sc1, and the third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate a logic low level as the second control signal Sc2.

Between time t4 and t5, the ramp voltage Vramp is smaller than the first comparison voltage Va, and the control signal Vb is at a logic high level. The flip-flop 124 switches the control signal Vb to a logic low level at the rising edge of the control signal Vb, and switches the inverted output signal Sqb to a logic high level, so the second AND gate 125 performs AND on the control signal Vb and the output signal Sq The operation is performed to generate a logic low level as the first control signal Sc1, and the third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate a logic high level as the second control signal Sc2. The time t4 to t5 may be the second conduction time of the second set of switches 102 , represented by a time period Td3 . When the output voltage Vout exceeds the upper limit of the output voltage, the length of the period Td3 can be shortened as the output voltage Vout exceeds the upper limit of the output voltage. The duration Td3 and the duration Td1 may be equal in length.

Between time t5 and t7, the ramp voltage Vramp exceeds the first comparison voltage Va, and the control signal Vb is at a logic low level. The flip-flop 124 maintains the control signal Vb at a logic low level, and maintains the inverted output signal Sqb at a logic high level, so the second AND gate 125 performs an AND operation on the control signal Vb and the output signal Sq to generate a logic low The level is used as the first control signal Sc1, and the third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate a logic low level as the second control signal Sc2. The time t2 to t7 may be the first turn-off time of the first set of switches 101 .

The controller 12 can switch the second control signal Sc2 to a logic high level again at time t8 in the same manner. The time t5 to t8 may be the second turn-off time of the second set of switches 102 .

If the output voltage Vout is lower than the upper limit of the output voltage, the divided voltage Vd will be lower than the reference voltage Vref, the first comparison voltage Va will be greater than the maximum value of the ramp voltage Vramp, the control signal Vc will maintain a logic high level, and the second comparison voltage Vc will maintain At the logic high level, the waveform of the control signal Vb is the same as that of the clock signal CLK. The first control signal Sc1 is at a logic high level between time t1 and t3, and is at a logic low level between time t3 and t4. The second control signal Sc2 is at a logic high level between time t4 and t6, and is at a logic low level between time t6 and t7. Between time t3 and t4 and between time t6 and t7, the first control signal Sc1 and the second control signal Sc2 are forced to be set to a logic low level to ensure that the first set of switches 101 and the second set of switches 102 will not turn on at the same time. Time t3 to t4 is represented by a period Td2.

FIG. 6 is a simulated waveform diagram when both the first control signal Sc1 and the second control signal Sc2 of the DC-DC power conversion system in FIG. 1 are substantially at 50% duty cycle. FIG. 7 is a simulated waveform diagram when both the first control signal Sc1 and the second control signal Sc2 of the DC-DC power conversion system in FIG. 1 are substantially 25% duty cycle. The simulation environment in Figures 6 and 7 is the DC-DC power conversion system 1 in Figure 2, the input voltage Vin is 48V, the capacitance value of the first resonance capacitor C1 and the capacitance value of the second resonance capacitor C2 are 4uF, and the storage capacitor C3 The capacitance of the capacitor is 100uF, the inductance of the first resonant inductor L1 and the second resonant inductor L2 is 25nH, and the switching frequency of the first set of switches 101 and the second set of switches 102 is 500kHz.

When both the first control signal Sc1 and the second control signal Sc2 are substantially at 50% duty cycle, the waveform diagram in Figure 6 shows that the output voltage Vout oscillates around 12V, and the output voltage Vout is approximately equal to 1/ of the input voltage Vin 4. The ripple (ripple) is about 0.02V (peak to peak). The output current Io is a sinusoidal current, the cross-voltage VC1 of the first resonant capacitor C1 and the cross-voltage VC2 of the second resonant capacitor C2 are complete sinusoidal voltages and are opposite to each other, and the current Io1 and current Io2 are complete sinusoidal currents and mutually for reverse. Between time t1 and t2, the current Io1 charges the output capacitor Co and the current Io2 discharges the output capacitor Co to generate the output voltage Vout. Between time t2 and t3, the current Io1 discharges the output capacitor Co and the current Io2 charges the output capacitor Co to generate the output voltage Vout.

When both the first control signal Sc1 and the second control signal Sc2 are substantially at 25% duty cycle, the waveform diagram in Figure 7 shows that the output voltage Vout oscillates around 11.7V, and the output voltage Vout is less than 1/ of the input voltage Vin 4. The cross-voltage VC1 of the first resonant capacitor C1 and the cross-voltage VC2 of the second resonant capacitor C2 are part of the sine wave voltage and part of the square wave voltage, and the cross-voltage VC1 and the cross-voltage VC2 are opposite to each other, and the current Io1 and the current Io2 are Some sine wave currents are opposite to each other. Between time t1 and t2, the current Io1 charges the output capacitor Co and the current Io2 discharges the output capacitor Co to generate the output voltage Vout. Between time t2 and t3, the current Io1 and the current Io2 are 0A. Between time t3 and t4, the current Io1 discharges the output capacitor Co and the current Io2 charges the output capacitor Co to generate the output voltage Vout. Between time t4 and t5, the current Io1 and the current Io2 are 0A. Since the current Io1 and the current Io2 are partial sine wave currents, only part of the output capacitor Co is charged and discharged, so an output voltage Vout less than 1/4 of the input voltage Vin is generated.

FIG. 8 is a schematic circuit diagram of another resonant switched capacitive converter 10 . The difference between the resonant switched capacitor converter 10 in FIG. 8 and FIG. 2 is that the first resonant capacitor C1 and the first resonant inductance L1 in FIG. 8 are directly coupled to each other, and the second resonant capacitor C2 and the second resonant inductance L2 are mutually connected. Directly coupled, the first resonant inductor L1 and the second resonant inductor L2 are not directly coupled to the output capacitor Co. The resonant switched capacitive converter 10 in FIG. 8 can replace the resonant switched capacitive converter 10 in FIG. 2 .

The first resonance tank 103 includes a first resonance capacitor C1 and a first resonance inductor L1. The first resonant capacitor C1 has a first terminal and a second terminal. The first resonant inductor L1 is coupled to the second end of the first resonant capacitor C1; and the second end. The second resonance tank 104 includes a second resonance capacitor C2 and a second resonance inductor L2. The second resonance capacitor C2 has a first terminal and a second terminal. The second resonant inductor L2 has a first end coupled to the second end of the second resonant capacitor C2; and a second end. The output capacitor Co has a first terminal capable of generating the output voltage Vout; and a second terminal coupled to the ground terminal.

Transistors Q1 to Q3 , Q7 and Q8 can form a first set of switches 101 . The transistor Q1 has a first terminal coupled to the input terminal 14 ; a second terminal coupled to the first terminal of the storage capacitor C3 ; and a control terminal for receiving the first control signal Sc1 . The transistor Q2 has a first terminal coupled to the second terminal of the storage capacitor C3; a second terminal coupled to the first terminal of the first resonant capacitor C1; and a control terminal for receiving the first control signal Sc1. The transistor Q3 has a first terminal coupled to the second terminal of the first resonant inductor L1; a second terminal coupled to the first terminal of the output capacitor Co; and a control terminal for receiving the first control signal Sc1. The transistor Q7 has a first terminal coupled to the first terminal of the output capacitor Co; a second terminal coupled to the first terminal of the second resonant capacitor C2; and a control terminal for receiving the first control signal Sc1. The transistor Q8 has a first terminal coupled to the second terminal of the second resonant inductor L2; a second terminal coupled to the ground terminal; and a control terminal for receiving the first control signal Sc1.

Transistors Q4 to Q6 , Q9 and Q10 may form a second set of switches 102 . The transistor Q4 has a first terminal coupled to the first terminal of the second resonance capacitor C2; a second terminal coupled to the first terminal of the storage capacitor C3; and a control terminal for receiving the second control signal Sc2. The transistor Q5 has a first terminal coupled to the second terminal of the storage capacitor C3; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2. The transistor Q6 has a first terminal coupled to the second terminal of the second resonant inductor L2; a second terminal coupled to the first terminal of the output capacitor Co; and a control terminal for receiving the second control signal Sc2. The transistor Q9 has a first terminal coupled to the first terminal of the output capacitor Co; a second terminal coupled to the first terminal of the first resonant capacitor C1; and a control terminal for receiving the second control signal Sc2. The transistor Q10 has a first terminal coupled to the second terminal of the first resonant inductor L1; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2.

The operation of the resonant switched capacitor converter 10 in FIG. 8 is similar to that in FIG. 2 , and its description can be found in the previous paragraphs, and will not be repeated here.

FIG. 9 is a schematic circuit diagram of another resonant switched capacitive converter 10 , which can replace the resonant switched capacitive converter 10 in FIG. 2 . The RSCC 10 of FIG. 9 may include a first resonant tank 103, a second resonant tank 104, a storage capacitor C92, an output capacitor Co, and transistors Q91 to Q910. The transistors Q91 to Q910 can be N-type MOSFETs, but are not limited thereto.

The first resonance tank 103 includes a first resonance capacitor C91 and a first resonance inductor L91. The first resonant capacitor C91 has a first terminal and a second terminal. The first resonant inductor L91 has a first end coupled to the second end of the first resonant capacitor C91; and a second end. Coupled to ground. The storage capacitor C92 has a first terminal and a second terminal. The second resonance tank 104 includes a second resonance capacitor C93 and a second resonance inductor L92. The second resonant capacitor C92 has a first terminal and a second terminal. The second resonant inductor L92 has a first end coupled to the second end of the second resonant capacitor C92; and a second end. The output capacitor Co has a first terminal capable of generating an output voltage Vout; and a second terminal.

Transistors Q91 , Q93 , Q95 , Q98 and Q99 form a first set of switches 101 . The transistor Q91 has a first terminal coupled to the input terminal 14 ; a second terminal coupled to the first terminal of the second resonant capacitor C93 ; and a control terminal for receiving the first control signal Sc1. The transistor Q93 has a first terminal coupled to the first terminal of the storage capacitor C92; a second terminal coupled to the first terminal of the first resonant capacitor C91; and a control terminal for receiving the first control signal Sc1. The transistor Q95 has a first terminal coupled to the second terminal of the second resonant inductor L92; a second terminal coupled to the first terminal of the output capacitor Co; and a control terminal for receiving the first control signal Sc1. The transistor Q98 has a first terminal coupled to the second terminal of the storage capacitor C92; a second terminal coupled to the ground terminal; and a control terminal for receiving the first control signal Sc1. The transistor Q99 has a first terminal coupled to the second terminal of the first resonant inductor L91; a second terminal coupled to the first terminal of the output capacitor Co; and a control terminal for receiving the first control signal Sc1.

Transistors Q92 , Q94 , Q96 , Q97 and Q910 may form the second set of switches 102 . The transistor Q92 has a first terminal coupled to the first terminal of the second resonant capacitor C93; a second terminal coupled to the first terminal of the storage capacitor C92; and a control terminal for receiving the second control signal Sc2. The transistor Q94 has a first end coupled to the first end of the first resonant capacitor C91; a second end coupled to the first end of the output capacitor Co; and a control end for receiving the second control signal Sc2. The transistor Q96 has a first terminal coupled to the second terminal of the second resonant inductor L92; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2. The transistor Q97 has a first end coupled to the second end of the storage capacitor C92; a second end coupled to the first end of the output capacitor Co; and a control end for receiving the second control signal Sc2. The transistor Q910 has a first terminal coupled to the second terminal of the first resonant inductor L91; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2.

During operation, the first resonant tank 103 and the second resonant tank 104 respectively provide a voltage conversion ratio of 2:1, and the storage capacitor C92 provides a voltage conversion ratio of 1:1, so that the RSCC 10 provides a voltage conversion ratio of 4:1. The voltage across the second resonant capacitor C93 can be 3 times the output voltage Vout, the voltage across the storage capacitor C can be 2 times the output voltage Vout, and the voltage across the first resonant capacitor C91 and the output capacitor Co can be 1 times respectively The output voltage Vout. In some embodiments, the storage capacitor C92 can also be connected in series with the inductor to form another resonant tank.

In the first state, the first set of switches 101 and the second set of switches 102 can be set so that the first end of the second resonant capacitor C93 is coupled to the input end 14, and the first end of the second resonant inductance L92 is coupled to the first end. The second end of the two resonant capacitors C93, the second end of the first resonant inductance L91 is coupled to the second end of the second resonant inductance L92, the second end of the first resonant capacitor C91 is coupled to the second end of the first resonant inductance L91 One end, the first end of the storage capacitor C92 is coupled to the first end of the first resonant capacitor C91, the second end of the storage capacitor C92 is coupled to the ground end, and the first end of the output capacitor Co is coupled to the first resonant inductor The second terminal of L91, the second terminal of the second resonant inductor L92, and the second terminal of the output capacitor Co are coupled to the ground terminal. The second resonant capacitor C93 and the output capacitor Co can be charged, and the storage capacitor C92 can discharge the first resonant capacitor C91 and the output capacitor Co.

In the second state, the first group of switches 101 and the second group of switches 102 can be set so that the first end of the output capacitor Co is coupled to the first end of the first resonant capacitor C91 and the second end of the storage capacitor C92, and the output The second terminal of the capacitor Co is coupled to the ground terminal, the first terminal of the first resonance inductor L91 is coupled to the second terminal of the first resonance capacitor C91, the second terminal of the first resonance inductor L91 is coupled to the ground terminal, and the second terminal of the first resonance inductor L91 is coupled to the ground terminal. The first end of the two resonant capacitors C93 is coupled to the first end of the storage capacitor C92, the first end of the second resonant inductance L92 is coupled to the second end of the second resonant capacitor C93, and the second end of the first resonant inductance L91 Coupled to ground. The first resonant capacitor C91 can discharge the output capacitor Co, and the second resonant capacitor C93 can discharge the storage capacitor C92 and the output capacitor Co.

The RSCC 10 can alternately switch between the first state and the second state to continuously charge and discharge all capacitors in the RSCC 10 to maintain charge balance, and at the same time transmit power from the input terminal 14 to the output terminal 16 to generate the output voltage Vout.

FIG. 10 is a schematic circuit diagram of another resonant switched capacitor converter in FIG. 1 . The resonant switched capacitive converter 10 in FIG. 10 can replace the resonant switched capacitive converter 10 in FIG. 2 . The RSCC 10 in FIG. 10 may include a first resonant tank 103, a second resonant capacitor C102, a third resonant capacitor C103, an output capacitor Co, and transistors Q101 to Q1010. The transistors Q101 to Q1010 can be N-type MOSFETs, but are not limited thereto.

The second resonant capacitor C102 has a first terminal and a second terminal. The third resonance capacitor C103 has a first terminal and a second terminal. The first resonance tank 103 includes a first resonance capacitor C101 and a first resonance inductor L101. The first resonant capacitor C101 has a first terminal and a second terminal. The first resonant inductor L101 has a first end; and a second end coupled to the first end of the output capacitor Co. The output capacitor Co has a first terminal capable of generating the output voltage Vout; and a second terminal coupled to the ground terminal. The third resonance capacitor C103 has a first terminal and a second terminal. The second resonant capacitor C102 has a first terminal and a second terminal.

Transistors Q101 to Q104 can form the first set of switches 101 . The transistor Q101 has a first terminal coupled to the input terminal 14 ; a second terminal coupled to the first terminal of the third resonant capacitor C103 ; and a control terminal for receiving the first control signal Sc1. The transistor Q102 has a first end coupled to the second end of the third resonant capacitor C103; a second end coupled to the first end of the second resonant capacitor C102; and a control end for receiving the first control signal Sc1 . The transistor Q103 has a first end coupled to the second end of the second resonant capacitor C102; a second end coupled to the first end of the first resonant capacitor C101; and a control end for receiving the first control signal Sc1 . The transistor Q104 has a first end coupled to the second end of the first resonant capacitor C101; a second end coupled to the first end of the first resonant inductor L101; and a control end for receiving the first control signal Sc1 .

Transistors Q105 to Q1010 may form the second set of switches 102 . The transistor Q105 has a first end coupled to the first end of the second resonant inductor L102; a second end coupled to the first end of the third resonant capacitor C103; and a control end for receiving the second control signal Sc2 . The transistor Q106 has a first end coupled to the first end of the second resonant inductor L102; a second end coupled to the first end of the second resonant capacitor C102; and a control end for receiving the second control signal Sc2 . The transistor Q107 has a first end coupled to the first end of the second resonant inductor L102; a second end coupled to the first end of the first resonant capacitor C101; and a control end for receiving the second control signal Sc2 . The transistor Q108 has a first terminal coupled to the second terminal of the third resonant capacitor C103; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2. The transistor Q109 has a first terminal coupled to the second terminal of the second resonant capacitor C102; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2. The transistor Q1010 has a first terminal coupled to the second terminal of the first resonant capacitor C101; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2.

During operation, the input voltage Vin can be 4 times the output voltage Vout, and the voltage across the third resonant capacitor C103, the second resonant capacitor C102, the first resonant capacitor C101 and the output capacitor Co can be 1 times the output voltage Vout respectively, The RSCC 10 is made to provide a 4 to 1 voltage conversion ratio.

In the first state, the first group of switches 101 and the second group of switches 102 can sequentially connect the third resonant capacitor C103, the second resonant capacitor C102, the first resonant capacitor C101, the first resonant inductor L101 and the output capacitor Co to the input Between terminal 14 and ground terminal. The first resonant capacitor C101 can charge the output capacitor Co.

In the second state, the first set of switches 101 and the second set of switches 102 can be connected in parallel with the output capacitor Co, and the first resonant inductor L101 in series and the first resonant capacitor C101, the second resonant capacitor C102, and the third resonant capacitor in parallel C103 is between the output terminal 16 and the ground terminal. The first resonant capacitor C101 , the second resonant capacitor C102 and the third resonant capacitor C103 can discharge the output capacitor Co. The RSCC 10 can alternately switch between the first state and the second state to continuously charge and discharge all capacitors in the RSCC 10 to maintain charge balance, and at the same time transmit power from the input terminal 14 to the output terminal 16 to generate the output voltage Vout.

The present invention is not limited to the RSCC applied to the conversion voltage ratio of 4:1, and those skilled in the art can also use the RSCC in the embodiment of the present invention as an RSCC with other conversion voltage ratios or other forms of switched capacitor converters ( switched-capacitor converter, SCC) instead.

The embodiments in Figures 1, 2, 4, 8-10 adjust the first control signal Sc1 and the second control signal Sc2 according to the output voltage Vout to adjust the output voltage Vout, and provide overvoltage protection without greatly increasing the circuit area. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

:輸出端 Q1至Q10, Q91至Q910, Q101至Q1010:電晶體 Rd1, Rd2:電阻 Sc1:第一控制訊號 Sc2:第二控制訊號 SH:邏輯高準位 Sq:輸出訊號 Sqb:反向輸出訊號 t1至t8:時間 Td1至Td3:時段 V:伏特 Va:第一比較電壓 Vb:控制訊號 Vc第二比較電壓 VC1, VC2:跨壓 Vd:分壓 Vin:輸入電壓 Vramp:斜坡電壓 Vref:參考電壓 Vss:接地電壓 Vout:輸出電壓 1: DC-DC power conversion system 10, RSCC: resonant switched capacitor converter 101: first set of switches 102: second set of switches 103: first resonance tank 104: second resonance tank 12: controller 120: voltage divider Device 121: first comparison circuit 1210: comparator 122: second comparison circuit 123: first sum gate 124: flip-flop 125: second sum gate 126: third sum gate 14: input terminal 16: output terminal 300: Power conversion method S302 to S308: step A: ampere Cc: capacitor CLK: clock signal ck: clock input terminal Co: output capacitors C1 to C3, C91 to C93, C101 to C103: capacitor gm: gain Io: output current Io1 , Io2: current J, K: input terminals L1, L2, L91, L92, L101, L102: inductance Q,

: Output terminals Q1 to Q10, Q91 to Q910, Q101 to Q1010: transistors Rd1, Rd2: resistors Sc1: first control signal Sc2: second control signal SH: logic high level Sq: output signal Sqb: reverse output signal t1 to t8: Time Td1 to Td3: Period V: Volt Va: First comparison voltage Vb: Control signal Vc Second comparison voltage VC1, VC2: Cross voltage Vd: Divided voltage Vin: Input voltage Vramp: Ramp voltage Vref: Reference voltage Vss: ground voltage Vout: output voltage

FIG. 1 is a block diagram of a DC-DC power conversion system in an embodiment of the present invention. FIG. 2 is a schematic circuit diagram of a DC-DC power conversion system in FIG. 1 . FIG. 3 is a flow chart of the power conversion method of the DC-DC power conversion system in FIG. 1 . Figure 4 is a schematic circuit diagram of the controller in Figure 1. Figure 5 is the waveform diagram of the controller in Figure 4. FIG. 6 is a simulated waveform diagram when both the first control signal Sc1 and the second control signal Sc2 of the DC-DC power conversion system in FIG. 1 are substantially at 50% duty cycle. FIG. 7 is a simulated waveform diagram when both the first control signal Sc1 and the second control signal Sc2 of the DC-DC power conversion system in FIG. 1 are substantially 25% duty cycle. FIG. 8 is a schematic circuit diagram of another resonant switched capacitor converter in FIG. 1 . FIG. 9 is a schematic circuit diagram of another resonant switched capacitor converter in FIG. 1 . FIG. 10 is a schematic circuit diagram of another resonant switched capacitor converter in FIG. 1 .

1: DC-DC power conversion system

10: Resonant Switched Capacitor Converter

101: The first set of switches

102: The second set of switches

103: The first resonance tank

12: Controller

14: input terminal

16: output terminal

Co: output capacitance

Sc1: the first control signal

Sc2: Second control signal

Vin: input voltage

Vout: output voltage

Claims (20)

A DC-DC power conversion system comprising: an input terminal for receiving the input voltage; A resonant switched-capacitor converter (resonant switched-capacitor converter), used to receive an input voltage, and switch between a first state and a second state to generate an output voltage, the resonant switched-capacitor converter includes : a first resonance tank; an output capacitor having a first end for generating the output voltage; and a second end coupled to a ground end; a first set of switches, coupled to the first resonant tank and the output capacitor, for receiving a first control signal to be turned on in the first state and turned off in the second state; and A second set of switches, coupled to the first resonant tank and the output capacitor, for receiving a second control signal to be turned on in the second state and turned off in the first state; an output terminal coupled to the output capacitor for outputting the output voltage; and A controller, coupled to the first group of switches and the second group of switches, used to adjust the first control signal according to the output voltage to control a first conduction time of the first group of switches, and according to the output voltage The second control signal is adjusted to control a second conduction time of the second set of switches. The DC-DC power conversion system as described in Claim 1, wherein the controller includes: a voltage divider, coupled to the first end of the output capacitor, for generating a divided voltage of the output voltage; a first comparison circuit, coupled to the voltage divider, for comparing the divided voltage with a reference voltage to generate a first comparison voltage; a second comparison circuit, coupled to the first comparison circuit, for comparing the first comparison voltage and a ramp voltage to generate a second comparison voltage; a first AND gate, coupled to the second comparison circuit, for performing an AND operation (AND operation) on the second comparison voltage and a clock signal to generate a control signal; a flip-flop coupled to the first AND gate for generating an output signal and an inverted output signal according to the control signal; a second AND gate, coupled to the flip-flop, for performing an AND operation on the control signal and the output signal to generate the first control signal; and A third AND gate, coupled to the flip-flop, is used for performing an AND operation on the control signal and the inverted output signal to generate the second control signal. The DC-DC power conversion system as claimed in claim 1, wherein in the first state, the first group of switches is used to connect the first resonant tank in series between the input terminal and the output capacitor. The DC-DC power conversion system as claimed in claim 1, wherein in the second state, the second set of switches are used to connect the first resonant tank and the output capacitor in parallel. The DC-DC power conversion system as claimed in claim 1, wherein the controller is configured to alternately switch the resonant switched capacitor converter between the first state and the second state. The DC-DC power conversion system as claimed in claim 1, wherein the first on-time is less than a first off-time of the first set of switches, and the second on-time is less than a second off-time of the second set of switches time. The DC-DC power conversion system as claimed in claim 1, wherein a length of the first on-time is equal to a length of the second on-time. The DC-DC power conversion system as described in Claim 1, wherein The first resonance tank contains: a first resonant capacitor having a first end and a second end; and a first resonant inductor having a first end; and a second end coupled to the first end of the output capacitor; The resonant switched capacitor converter further includes a second resonant tank, including: a second resonant capacitor having a first terminal and a second terminal; and a second resonant inductor having a first end; and a second end coupled to the first end of the output capacitor; This first set of switches contains: A first transistor having a first terminal; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the first control signal; A second transistor having a first end coupled to the second end of the first resonant capacitor; a second end coupled to the first end of the first resonant inductance; and a control end, for receiving the first control signal; A third transistor having a first end coupled to the first end of the second resonant inductor; a second end coupled to the first end of the second resonant capacitor; and a control end, for receiving the first control signal; and A fourth transistor has a first end coupled to the second end of the second resonant capacitor; a second end coupled to the ground end; and a control end for receiving the first control signal; and This second set of switches contains: A fifth transistor having a first end coupled to the first end of the first resonant inductor; a second end coupled to the first end of the first resonant capacitor; and a control end, for receiving the second control signal; A sixth transistor has a first terminal coupled to the second terminal of the first resonant capacitor; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control terminal signal; A seventh transistor having a first end coupled to the first end of the second resonant capacitor; a second end; and a control end for receiving the second control signal; and An eighth transistor having a first end coupled to the second end of the second resonant capacitor; a second end coupled to the first end of the second resonant inductance; and a control end, used for receiving the second control signal. The DC-DC power conversion system as described in Claim 1, wherein The first resonance tank contains: a first resonant capacitor having a first end and a second end; and a first resonant inductor having a first end coupled to the second end of the first resonant capacitor; and a second end; The resonant switched capacitor converter further includes a second resonant tank, including: a second resonant capacitor having a first terminal and a second terminal; and a second resonant inductor having a first end coupled to the second end of the second resonant capacitor; and a second end; This first set of switches contains: A first transistor having a first terminal; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the first control signal; A second transistor has a first terminal coupled to the second terminal of the first resonant inductor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the first control signal; A third transistor has a first terminal coupled to the first terminal of the output capacitor; a second terminal coupled to the first terminal of the second resonant capacitor; and a control terminal for receiving the first control signal; and A fourth transistor has a first end coupled to the second end of the second resonant inductor; a second end coupled to the ground end; and a control end for receiving the first control signal; and This second set of switches contains: A fifth transistor has a first terminal coupled to the first terminal of the output capacitor; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the second control signal; A sixth transistor has a first end coupled to the second end of the first resonant inductor; a second end coupled to the ground end; and a control end for receiving the second control signal; a seventh transistor having a first terminal; coupled to the first terminal of the second resonant capacitor; a second terminal; and a control terminal for receiving the second control signal; and An eighth transistor has a first terminal coupled to the second terminal of the second resonant inductor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the second control signal. The DC-DC power conversion system as described in Claim 1, wherein The first resonance tank contains: a first resonant capacitor having a first end and a second end; and a first resonant inductor having a first end coupled to the second end of the first resonant capacitor; and a second end; The resonant switched capacitor converter further includes a storage capacitor with a first end and a second end; This first set of switches contains: A first transistor has a first terminal coupled to the first terminal of the storage capacitor; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the first control signal; A second transistor has a first terminal coupled to the second terminal of the first resonant inductor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the first control signal; and A third transistor having a first terminal coupled to the second terminal of the storage capacitor; a second terminal coupled to the ground terminal; and a control terminal for receiving the first control signal; and This second set of switches contains: A fifth transistor has a first terminal coupled to the first terminal of the first resonant capacitor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the second control signal; A sixth transistor has a first end coupled to the second end of the first resonant inductor; a second end coupled to the ground end; and a control end for receiving the second control signal; a seventh transistor having a first terminal; a second terminal coupled to the first terminal of the storage capacitor; and a control terminal for receiving the second control signal; and An eighth transistor has a first terminal coupled to the second terminal of the storage capacitor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the Second control signal. The DC-DC power conversion system as described in Claim 1, wherein The first resonance tank contains: a first resonant capacitor having a first end and a second end; and a first resonant inductor having a first end; and a second end coupled to the first end of the output capacitor; The resonant switched capacitor converter also includes: a second resonant capacitor having a first terminal and a second terminal; and a second resonant inductor having a first end; and a second end coupled to the first end of the output capacitor; This first set of switches contains: A second transistor having a first end coupled to the second end of the second resonant capacitor; a second end coupled to the first end of the first resonant capacitor; and a control end, for receiving the first control signal; A third transistor having a first end coupled to the second end of the first resonant capacitor; a second end coupled to the first end of the first resonant inductance; and a control end, for receiving the first control signal; and a third transistor having a first terminal; a second terminal coupled to the first terminal of the second resonant capacitor; and a control terminal for receiving the first control signal; and This second set of switches contains: A fifth transistor having a first end coupled to the first end of the second resonant inductor; a second end coupled to the first end of the first resonant capacitor; and a control end, for receiving the second control signal; A sixth transistor has a first terminal coupled to the second terminal of the first resonant capacitor; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control terminal signal; A seventh transistor having a first end; coupled to the first end of the second resonant inductor; a second end coupled to the first end of the second resonant capacitor; and a control end, for receiving the second control signal; and An eighth transistor has a first end coupled to the second end of the second resonant capacitor; a second end coupled to the ground end; and a control end for receiving the second control signal. The DC-DC power conversion system as claimed in claim 1, wherein the ratio of the input voltage to the output voltage is greater than 2:1. The DC-DC power conversion system as claimed in claim 1, wherein when starting up, the first on-time and the second on-time are equal to a preset on-time that is much less than 50% duty cycle. A power conversion method, suitable for a DC-DC power conversion system, the DC-DC power conversion system includes a resonant switched capacitor converter and a controller, the resonant switched capacitor converter includes a first resonance tank, a An output capacitor, a first group of switches coupled to the first resonance tank and the output capacitor, and a second group of switches coupled to the first resonance tank and the output capacitor, the method comprising: The resonant switched capacitor converter switches between a first state and a second state to generate an output voltage; The controller adjusts a first control signal and a second control signal according to the output voltage; The first group of switches receives the first control signal to conduct a first conduction time in the first state; and The second group of switches is turned on for a second turn-on time when receiving the second control signal and in the second state. The method as claimed in claim 14, wherein in the first state, the first group of switches connects the first resonant tank in series between the input terminal and the output capacitor. The method as claimed in claim 14, wherein in the second state, the second set of switches are connected in parallel with the first resonant tank and the output capacitor. The method of claim 14, wherein the controller alternately switches the resonant switched capacitor converter between the first state and the second state. The method as described in claim 14, wherein: The first set of switches receives the first control signal to cut off a first cut-off time; the second set of switches receives the second control signal to cut off a second cut-off time; and The first on-time is shorter than the first off-time, and the second on-time is shorter than the second off-time. The method of claim 14, wherein a length of the first on-time is equal to a length of the second on-time. The method as claimed in claim 14, wherein the first on-time and the second on-time are equal to a preset on-time that is much less than 50% duty cycle at power-on.

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