TW202245160A - Package carrier and manufacturing method thereof and chip package structure - Google Patents

Abstract

A package carrier includes a first redistribution structure layer, a plurality of conductive connecting members, a connection structure layer, at least one stiffener and a molding compound. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and a plurality of pads. A top surface and a bottom surface of each of the pads are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface of the first redistribution structure layer and located at least between the conductive connecting members. The molding compound is disposed on the first surface of the first redistribution structure layer and covers the conductive connecting members and the stiffener.

Description

Packaging carrier board, manufacturing method thereof, and chip packaging structure

The invention relates to a package carrier board, its manufacturing method and a chip package structure using the package carrier board.

In the prior art, because a two-dimensional semi-integrated circuit (two and a half dimension integrated circuit stacking, 2.5D IC) stacking needs to use a silicon interposer, the packaging cost remains high. In order to effectively reduce packaging costs, organic interposers are currently used to replace silicon interposers. However, during the assembly process of the organic interposer, the assembly surface is often warped due to heat, which makes the coplanarity of the surface of the carrier poor, and thus the chips cannot be successfully assembled on the carrier.

The invention provides a package carrier board, which has good surface coplanarity and better structural reliability.

The present invention provides a method for manufacturing a packaging carrier, which is used to manufacture the above-mentioned packaging carrier, which can effectively reduce the manufacturing cost.

The present invention provides a chip package structure, including the above-mentioned package carrier board, which can have a better package yield.

The packaging carrier of the present invention includes a first redistribution circuit structure layer, a plurality of conductive connectors, a connection structure layer, at least one rib and packaging glue. The first redistribution wiring structure layer has a first surface and a second surface opposite to each other. The conductive connector is disposed on the first surface of the first redistribution circuit structure layer and is electrically connected with the first redistribution circuit structure layer. The connection structure layer is configured on the second surface of the first redistribution circuit structure layer. The connection structure layer includes a substrate and a plurality of pads. The top surface and the bottom surface of each pad are respectively exposed to the upper surface and the lower surface of the substrate. The pad is electrically connected to the first redistribution circuit structure layer. The reinforcing rib is configured on the first surface of the first redistribution circuit structure layer and is at least located between the conductive connectors. The encapsulant is disposed on the first surface of the first redistribution circuit structure layer, and covers the conductive connectors and the reinforcing ribs.

The manufacturing method of the packaging carrier of the present invention includes the following steps. A substrate and a plurality of conductive strips are provided. The conductive strips are embedded in the base, and one end of each conductive strip is exposed to one side of the base. A first redistribution wiring structure layer is formed on the side of the substrate. A plurality of conductive connectors and at least one reinforcing rib are formed on the first redistribution circuit structure layer, wherein the reinforcing rib is at least located between the conductive connectors. An encapsulant is formed on the first redistribution circuit structure layer to cover the conductive connectors and the reinforcing ribs. After the encapsulation compound is formed, part of the base and part of the conductive strips are removed to form a connection structure layer. The connection structure layer includes a substrate and a plurality of pads. The top surface and the bottom surface of each pad are respectively exposed to the upper surface and the lower surface of the substrate.

The chip package structure of the present invention includes a package carrier and at least a chip. The package carrier includes a first redistribution circuit structure layer, a plurality of conductive connectors, a connection structure layer, at least one rib and encapsulant. The first redistribution wiring structure layer has a first surface and a second surface opposite to each other. The conductive connector is disposed on the first surface of the first redistribution circuit structure layer and is electrically connected to the first redistribution circuit structure layer. The connection structure layer is configured on the second surface of the first redistribution circuit structure layer. The connection structure layer includes a substrate and a plurality of pads. The top surface and the bottom surface of each pad are respectively exposed to the upper surface and the lower surface of the substrate. The pad is electrically connected to the first redistribution circuit structure layer. The reinforcing rib is configured on the first surface of the first redistribution circuit structure layer and is at least located between the conductive connectors. The encapsulant is disposed on the first surface of the first redistribution circuit structure layer, and covers the conductive connectors and the reinforcing ribs. The chip is disposed on the package carrier board and electrically connected to the pads of the connection structure layer.

Based on the above, in the design of the package carrier of the present invention, the conductive connectors and the ribs are arranged on the same surface of the first redistribution circuit structure layer, and the encapsulant covers the conductive connectors and the ribs, thereby suppressing the And the warping of the packaging carrier is reduced, so that the packaging carrier of the present invention has better flatness and structural reliability. Furthermore, in the manufacturing process of the package carrier of the present invention, no temporary substrate is needed, and therefore no laser debond process is required, which can effectively reduce the manufacturing cost. In addition, during the manufacturing process of the package carrier of the present invention, the encapsulant covers the conductive connectors and ribs, so that the back of the package carrier becomes flat, which facilitates subsequent assembly of chips on the front of the package carrier. In addition, since the packaging carrier of the present invention has better flatness, the chip packaging structure using the packaging carrier of the present invention can have better packaging yield.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

1A to 1E are schematic cross-sectional views of a manufacturing method of a package carrier according to an embodiment of the present invention. Regarding the manufacturing method of the package carrier of this embodiment, firstly, referring to FIG. 1A , a base 112a and a plurality of conductive strips 114a are provided. The conductive strips 114a are embedded in the base 112a, and one end 115 of each conductive strip 114a is exposed to one side 113 of the base 112a. Here, the material of the substrate 112a is, for example, glass, silicon or other dielectric materials.

Next, please refer to FIG. 1B , a first redistribution wiring structure layer 120 is formed on one side 113 of the substrate 112 a. In detail, the first redistribution wiring structure layer 120 includes a plurality of dielectric layers 121 , 123 , a plurality of redistribution wiring layers 122 , 124 , a plurality of conductive vias 125 , 127 and a plurality of connection pads 126 . The redistribution circuit layers 122 , 124 and the dielectric layers 121 , 123 are alternately stacked on one side 113 of the substrate 112 a, and the connection pads 126 are located on the dielectric layer 123 . The redistribution circuit layer 122 directly contacts and is electrically connected to one end 115 of each conductive strip 114 a, and is electrically connected to the redistribution circuit layer 124 through the conductive via 125 . The redistribution circuit layer 124 is electrically connected to the connection pad 126 through the conductive via 127 .

Next, please refer to FIG. 1C, forming a plurality of conductive connectors 130a and at least one rib (a plurality of ribs 140a are schematically shown) on the first redistribution circuit structure layer 120, wherein the rib 140a is at least located on the conductive connector Between 130a. Furthermore, the conductive connector 130 a in this embodiment is, for example, a solder ball, wherein the conductive connector 130 a is directly located on the connection pad 126 of the first redistribution wiring structure layer 120 . The reinforcing rib 140a is directly located on the dielectric layer 123 and does not contact the connection pad 126 , wherein the material of the reinforcing rib 140a is, for example, steel, aluminum, copper, silicon or glass, but not limited thereto. It should be noted that the present embodiment does not limit the order of forming the conductive connectors 130 a and the reinforcing ribs 140 a , and the order of forming the conductive connectors 130 a and the reinforcing ribs 140 a can be determined by itself according to requirements.

Afterwards, referring to FIG. 1D , an encapsulant 150 is formed on the first redistribution wiring structure layer 120 to cover the conductive connectors 130 a and the ribs 140 a. Here, the encapsulant 150 completely covers the conductive connector 130a and the rib 140a. If necessary, a grinding procedure can be optionally added to grind the over-thick encapsulant 150 .

Finally, referring to FIG. 1D and FIG. 1E , after forming the encapsulant 150 , a thinning process is performed to remove part of the substrate 112 a and part of the conductive strips 114 a to form the connection structure layer 110 . Here, the connection structure layer 110 includes a substrate 112 and a plurality of pads 114 , wherein the substrate 112 is substantially a part of the base 112 a, and the pads 114 are substantially a part of the conductive strips 114 a. The top surface S1 and the bottom surface S2 of each pad 114 are respectively exposed to the upper surface S3 and the lower surface S4 of the substrate 112 . In one embodiment, the top surface S1 and the bottom surface S2 of each pad 114 are respectively aligned with the upper surface S3 and the lower surface S4 of the substrate 112 . In addition, it should be noted that, here, the surface treatment procedure can be selectively performed on the connection structure layer 110 according to the requirements of subsequent wafer bonding. For example, if the material of the base material 112 is silicon, a dielectric material layer needs to be added; if the material of the base material 112 is glass, there is no need to add a dielectric material layer. In addition, according to the subsequent bonding method (such as micro-solder joint bonding or hybrid bonding bonding), different surface treatment procedures must be performed on the pads 114 . So far, the fabrication of the package carrier 100a has been completed.

In terms of structure, please refer to FIG. 1E again. The package carrier 100 a includes a first redistribution circuit structure layer 120 , conductive connectors 130 a , connection structure layer 110 , ribs 140 a and encapsulant 150 . The first redistribution wiring structure layer 120 has a first surface F1 and a second surface F2 opposite to each other. The conductive connector 130 a is disposed on the first surface F1 of the first redistribution circuit structure layer 120 and is electrically connected to the first redistribution circuit structure layer 120 . The connection structure layer 110 is disposed on the second surface F2 of the first redistribution wiring structure layer 120 . The connection structure layer 110 includes a substrate 112 and pads 114 . The top surface S1 and the bottom surface S2 of each pad 114 are respectively exposed to the upper surface S3 and the lower surface S4 of the substrate 112 . The pad 114 is electrically connected to the first redistribution wiring structure layer 120 . The reinforcing rib 140a is disposed on the first surface F1 of the first redistribution wiring structure layer 120 and at least located between the conductive connectors 130a. The encapsulant 150 is disposed on the first surface F1 of the first redistribution wiring structure layer 120 and covers the conductive connector 130 a and the reinforcing rib 140 .

In short, the packaging carrier 100a of this embodiment suppresses and reduces the warpage of the carrier by providing the ribs 140a. Moreover, the build-up process of the circuit board is integrated in the package carrier 100 a of this embodiment, that is, the first redistribution circuit structure layer 120 . The conductive connectors 130a and the ribs 140a are disposed on the same surface of the first redistribution circuit structure layer 120, and the encapsulant 150 covers the conductive connectors 130a and the ribs 140a, thereby suppressing and reducing the warping of the packaging substrate 100a. curvature, so that the packaging carrier 100a of this embodiment has better flatness and structural reliability. In addition, in the manufacturing process of the package carrier 100a of this embodiment, no temporary substrate is needed, and thus no laser debond process is required, which can effectively reduce the manufacturing cost.

FIGS. 1F to 1J are schematic cross-sectional views illustrating a method of disposing a chip on the package carrier shown in FIG. 1E to form a chip package structure.

Next, please refer to FIG. 1F , dispose at least one chip (two chips 200 are schematically shown) on the package carrier 100a, wherein the chip 200 can be bonded or hybrid bonded through a micro solder joint (micro bump) bonding to electrically connect with the pads 114 of the connection structure layer 110 . Here, as shown in FIG. 1F , the chip 200 is electrically connected to the pad 114 through the micro solder joint 210 , and then the underfill 220 is filled between the package carrier 100 a and the chip 200 so that the underfill 220 covers Micro-solder joints 210 . In one embodiment, the contact pitch of the wafer 200 is 10 microns to 80 microns.

Next, referring to FIG. 1G , an encapsulation material 230 is formed on the connection structure layer 110 of the packaging substrate 100 a and covers the peripheral surface 201 of the chip 200 to increase structural strength and reliability. Optionally, the sealing material 230 is ground, so that the back surface 203 of the wafer 200 is exposed to the surface 231 of the sealing material 230 , which can have a better heat dissipation effect.

Afterwards, please refer to FIG. 1G and FIG. 1H at the same time, and perform a dry etching process to remove part of the encapsulant 150 to expose at least the first bottom surface 132a of each conductive connection member 130a. Here, the encapsulant 150 also exposes the second bottom surface 142a of each rib 140a at the same time. The rib 140a has a length H, and the encapsulant 150 has a thickness T, and the length H is equal to the thickness T. Referring to FIG. In another non-illustrated embodiment, the length of the ribs may also be smaller than the thickness of the encapsulant, which means that the ribs may not be exposed to the encapsulant.

Finally, please refer to FIG. 1I and FIG. 1J at the same time to perform a singulation procedure to cut the sealing material 230 and the package carrier 100 a along the cutting line L to form the chip package structure 10 a.

In terms of structure, please refer to FIG. 1J again. The chip package structure 10a of this embodiment includes the above-mentioned package carrier 100a and chip 200 in FIG. The pad 114 is electrically connected. Further, the chip 200 can be electrically connected to the pad 114 of the connection structure layer 110 through micro bump bonding or hybrid bond bonding. Moreover, the chip package structure 10a of this embodiment further includes a sealing material 230, which is disposed on the connection structure layer 110 of the package carrier 100a, and covers the peripheral surface 201 of the chip 210, and the back surface 203 of the chip 200 is exposed to the sealing material 230 The surface 231 of. Here, the edge of the sealing material 230 exposes the edge of the packaging substrate 100a, and the encapsulant 150 exposes the first bottom surface 132a of each conductive connector 130a and the second bottom surface 142a of the rib 140a.

In application, as shown in FIG. 1J , the chip package structure 10 a can be electrically connected to the pads 22 on the driving substrate 20 through the conductive connector 130 a, and thus electrically connected to the driving substrate 20 . Here, the driving substrate 20 may be, for example, a printed circuit board, but is not limited thereto.

In the manufacturing process of the package carrier 100a of this embodiment, since the encapsulant 150 covers the conductive connectors 130a and the ribs 140a, the back surface of the package carrier 100a becomes flat. Therefore, when the chip package structure 10a is subsequently manufactured, since the package carrier 100a has better flatness, it is beneficial for the chip 200 to be arranged on the front side of the package carrier 100a, and it is suitable for using micro bumps. ) bonding or hybrid bond (hybrid bond) bonding to realize the electrical connection between the chip 200 and the pads 114 , which may have a better packaging yield.

It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2A to 2D are schematic cross-sectional views of a manufacturing method of a package carrier according to another embodiment of the present invention. The manufacturing method of the packaging carrier of this embodiment is similar to the manufacturing method of the above-mentioned packaging carrier, the difference between the two is: after the step in FIG. After that, referring to FIG. 2A , a second redistribution circuit structure layer 160 is formed on the first redistribution circuit structure layer 120 . In detail, the second redistribution circuit structure layer 160 includes a plurality of dielectric layers 161 , 163 , a redistribution circuit layer 162 , a plurality of conductive vias 165 , 167 and a plurality of connection pads 164 . The redistribution wiring layer 162 and the dielectric layers 161 and 163 are alternately stacked on the first redistribution wiring structure layer 120 , and the connection pad 164 is located on the dielectric layer 163 . The redistribution circuit layer 162 is electrically connected to the first redistribution circuit structure layer 120 through the conductive via 165 . The connection pad 164 is electrically connected to the redistribution circuit layer 162 through the conductive via 167 . Here, the line width and line spacing of the second redistribution wiring structure layer 160 are larger than the line width and line spacing of the first redistribution wiring structure layer 120 .

Next, please refer to FIG. 2B, forming a plurality of conductive connectors 130b and at least one rib (a plurality of ribs 140b are schematically shown) on the second redistribution circuit structure layer 160, wherein the rib 140b is at least located on the conductive connectors Between 130b. Furthermore, the conductive connectors 130b in this embodiment are, for example, solder balls, wherein the conductive connectors 130b are directly located on the connection pads 164 of the second redistribution wiring structure layer 160 . The reinforcing rib 140b is directly located on the dielectric layer 163 and does not contact the connection pad 164 , wherein the material of the reinforcing rib 140b is, for example, steel, aluminum, copper, silicon or glass, but not limited thereto. It should be noted that the present embodiment does not limit the order of forming the conductive connectors 130 b and the reinforcing ribs 140 b , and the order of forming the conductive connectors 130 b and the reinforcing ribs 140 b can be determined according to requirements.

Afterwards, referring to FIG. 2C , an encapsulant 150 is formed on the second redistribution wiring structure layer 160 to cover the conductive connectors 130 b and the ribs 140 b. Here, the encapsulant 150 completely covers the conductive connector 130b and the reinforcing rib 140b. If necessary, a grinding procedure can be optionally added to grind the over-thick encapsulant 150 .

Finally, referring to FIG. 2C and FIG. 2D , after forming the encapsulant 150 , a thinning process is performed to remove part of the substrate 112 a and part of the conductive strips 114 a to form the connection structure layer 110 . The connection structure layer 110 includes a substrate 112 and a plurality of pads 114 , wherein the substrate 112 is substantially a part of the base 112 a , and the pads 114 are substantially a part of the conductive strips 114 a. The top surface S1 and the bottom surface S2 of each pad 114 are respectively exposed to the upper surface S3 and the lower surface S4 of the substrate 112 . In addition, it should be noted that, here, the surface treatment procedure can be selectively performed on the connection structure layer 110 according to the requirements of subsequent wafer bonding. For example, if the material of the base material 112 is silicon, a dielectric material layer needs to be added; if the material of the base material 112 is glass, there is no need to add a dielectric material layer. In addition, according to the subsequent bonding method (such as micro-solder joint bonding or hybrid bonding bonding), different surface treatment procedures must be performed on the pads 114 . So far, the fabrication of the package carrier 100b has been completed.

FIGS. 2E to 2I are schematic cross-sectional views illustrating a method of disposing a chip on the package carrier shown in FIG. 2D to form a chip package structure.

Next, please refer to FIG. 2E , disposing at least one chip (two chips 200 are schematically shown) on the package carrier 100b, wherein the chip 200 can be bonded or hybrid bonded through micro bumps. bonding to electrically connect with the pads 114 of the connection structure layer 110 . Here, as shown in FIG. 2E , the chip 200 is electrically connected to the pad 114 through the micro solder joint 210 , and then the underfill 220 will be filled between the package carrier 100 b and the chip 200 so that the underfill 220 can cover Micro-solder joints 210 . In one embodiment, the contact pitch of the wafer 200 is 10 microns to 80 microns.

Next, please refer to FIG. 2F , a sealing material 230 is formed on the connection structure layer 110 of the packaging substrate 100 b and covers the peripheral surface 201 of the chip 200 to increase structural strength and reliability. Optionally, the sealing material 230 is ground, so that the back surface 203 of the wafer 200 is exposed to the surface 231 of the sealing material 230 , which can have a better heat dissipation effect.

Afterwards, please refer to FIG. 2F and FIG. 2G at the same time, and perform a dry etching process to remove part of the encapsulant 150 to expose at least the first bottom surface 132b of each conductive connection member 130b. Here, the rib 140b has a length H', and the encapsulant 150 has a thickness T, and the length H' is smaller than the thickness T.

Finally, please refer to FIG. 2H and FIG. 2I at the same time to perform a singulation process to cut the sealing material 230 and the package carrier 100b along the cutting line L to form the chip package structure 10b.

In application, as shown in FIG. 2I , the chip package structure 10b can be electrically connected to the pads 22 on the driving substrate 20 through the conductive connectors 130b , so as to be electrically connected to the driving substrate 20 . Here, the driving substrate 20 may be, for example, a printed circuit board, but is not limited thereto.

3A to 3C are schematic cross-sectional views of a manufacturing method of a package carrier according to another embodiment of the present invention. The manufacturing method of the packaging carrier of this embodiment is similar to the manufacturing method of the above-mentioned packaging carrier, the difference between the two is: after the step in FIG. After that, referring to FIG. 3A , a second redistribution circuit structure layer 170 is formed on the first redistribution circuit structure layer 120 . In detail, the second redistribution wiring structure layer 170 includes a plurality of dielectric layers 171 , 173 , a redistribution wiring layer 172 and a plurality of conductive vias 175 , 177 . The redistribution wiring layer 172 and the dielectric layers 171 and 173 are alternately stacked on the first redistribution wiring structure layer 120 . The redistribution circuit layer 172 is electrically connected to the first redistribution circuit structure layer 120 through the conductive via 175 . Here, the line width and line spacing of the second redistribution wiring structure layer 170 are larger than the line width and line spacing of the first redistribution wiring structure layer 120 .

Next, please refer to FIG. 3A again, forming a plurality of conductive connectors 130c and at least one rib (a plurality of ribs 140c are schematically shown) on the second redistribution circuit structure layer 170, wherein the rib 140c is at least located on the conductive connection between pieces 130c. Furthermore, the conductive connector 130c in this embodiment is, for example, a copper pillar, wherein the conductive connector 130c is directly located on the conductive via 177 of the second redistribution wiring structure layer 170 . The reinforcing rib 140c is directly located on the dielectric layer 173 and does not contact the conductive via 177 , wherein the material of the reinforcing rib 140c is, for example, steel, aluminum, copper, silicon or glass, but not limited thereto. It should be noted that the present embodiment does not limit the order of forming the conductive connectors 130c and the reinforcing ribs 140c, and the order of forming the conductive connectors 130c and the reinforcing ribs 140c can be determined according to requirements.

Afterwards, referring to FIG. 3B , an encapsulant 150 is formed on the second redistribution wiring structure layer 170 to cover the conductive connectors 130c and the ribs 140c. Here, the encapsulant 150 completely covers the conductive connector 130c and the reinforcing rib 140c. If necessary, a grinding procedure can be optionally added to grind the over-thick encapsulant 150 .

Finally, referring to FIG. 3B and FIG. 3C , after forming the encapsulant 150 , a thinning process is performed to remove part of the base 112 a and part of the conductive strips 114 a to form the connection structure layer 110 . The connection structure layer 110 includes a substrate 112 and a plurality of pads 114 , wherein the substrate 112 is substantially a part of the base 112 a , and the pads 114 are substantially a part of the conductive strips 114 a. The top surface S1 and the bottom surface S2 of each pad 114 are respectively exposed to the upper surface S3 and the lower surface S4 of the substrate 112 . In addition, it should be noted that, here, the surface treatment procedure can be selectively performed on the connection structure layer 110 according to the requirements of subsequent wafer bonding. For example, if the material of the base material 112 is silicon, a dielectric material layer needs to be added; if the material of the base material 112 is glass, there is no need to add a dielectric material layer. In addition, according to the subsequent bonding method (such as micro-solder joint bonding or hybrid bonding bonding), different surface treatment procedures must be performed on the pads 114 . So far, the fabrication of the package carrier 100c has been completed.

FIGS. 3D to 3H are schematic cross-sectional views illustrating a manufacturing method for disposing a chip on the package carrier shown in FIG. 3C to form a chip package structure.

Next, please refer to FIG. 3D , disposing at least one chip (two chips 200 are schematically shown) on the package carrier 100c, wherein the chip 200 can be bonded or hybrid bonded through micro solder joints. bonding to electrically connect with the pads 114 of the connection structure layer 110 . Here, as shown in FIG. 3D , the chip 200 is electrically connected to the pad 114 through the micro solder joint 210 , and then the underfill 220 will be filled between the package carrier 100c and the chip 200 so that the underfill 220 can cover Micro-solder joints 210 . In one embodiment, the contact pitch of the wafer 200 is 10 microns to 80 microns.

Next, referring to FIG. 3E , a sealing material 230 is formed on the connection structure layer 110 of the packaging substrate 100 c and covers the peripheral surface 201 of the chip 200 to increase structural strength and reliability. Optionally, the sealing material 230 is ground, so that the back surface 203 of the wafer 200 is exposed to the surface 231 of the sealing material 230 , which can have a better heat dissipation effect.

Afterwards, referring to FIG. 3E and FIG. 3F , a dry etching process is performed to remove part of the encapsulant 150 to expose at least the first bottom surface 132c of each conductive connector 130c. Here, the rib 140c has a length H'', and the encapsulant 150 has a thickness T, and the length H'' is smaller than the thickness T.

Finally, referring to FIG. 3G and FIG. 3H at the same time, a singulation process is performed to cut the sealing material 230 and the packaging carrier 100c along the cutting line L to form the fabrication of the chip packaging structure 10c.

In application, as shown in FIG. 3H, the chip package structure 10c can be electrically connected to the solder ball 30 through the conductive connector 130c, and the solder ball 30 is electrically connected to the pad 22 on the driving substrate 20, so that the chip The packaging structure 10c is electrically connected to the driving substrate 20 . Here, the driving substrate 20 may be, for example, a printed circuit board, but is not limited thereto.

FIG. 4A is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention. Please refer to FIG. 1J and FIG. 4A at the same time. The chip package structure 10d of this embodiment is similar to the chip package structure 10a of FIG. The properties of wafer 200 are different from those of wafer 250 and the dimensions of wafer 200 are also different from the dimensions of wafer 250 . That is to say, the chip packaging structure 10d of this embodiment is heterogeneously integrated with different chips 200 and 250 . In addition, in the chip packaging structure 10d of the present embodiment, a reinforcing rib 240 is also included, which is arranged between the chip 200 and the chip 250, and is directly located on the substrate 112 of the connection structure layer 110 without contacting the pad 114, thereby This increases the structural strength of the overall chip package structure 1Od.

FIG. 4B is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention. Please refer to FIG. 1J and FIG. 4B at the same time. The chip package structure 10e of this embodiment is similar to the chip package structure 10a of FIG. It is disposed on the first surface F1 of the first redistribution circuit structure layer 120 , and is located between the conductive connecting member 130 e and the first redistribution circuit structure layer 120 . In detail, the build-up structure layer 180 includes a glass fiber substrate 182, a first patterned conductive layer 184, a second patterned conductive layer 186, and at least one first via hole (two first via holes 183 are schematically shown) , at least one second via hole (two second via holes 185 are schematically shown) and at least one third via hole (three third via holes 187 are schematically shown). The first patterned conductive layer 184 and the second patterned conductive layer 186 are respectively located on opposite sides of the glass fiber substrate 182 . The third via hole 187 penetrates the fiberglass substrate 182 and electrically connects the first patterned conductive layer 184 and the second via hole 185 . The first patterned conductive layer 184 is electrically connected to the first redistribution circuit structure layer 120 through the first via hole 183 . The second patterned conductive layer 186 is electrically connected to the third via hole 187 through the second via hole 185 . The conductive connector 130e is connected to the second patterned conductive layer 186 and is electrically connected to the first redistribution wiring structure layer 120 through the build-up structure layer 180 .

5A to 5D are schematic bottom views of various package carriers according to various embodiments of the present invention. Please refer to FIG. 5A, 5C and FIG. 5D at the same time. In the packaging substrates 100f, 100h, and 100i, the ribs 140f, 140h, and 140i are continuous structural layers. Through their material properties (ie, rigidity), the overall packaging can be increased. The structural strength of the boards 100f, 100h, and 100i can suppress and reduce warping of the package carrier boards 100f, 100h, and 100i. In detail, in the package carrier 100f of FIG. 5A, a plurality of ribs 140f are arranged in a grid to form a continuous structural layer, and the conductive connectors 130 (such as solder balls) are located in the grid; In the package carrier 100h of FIG. 5C, the rib 140h is a single continuous structural layer and surrounds the conductive connector 130; in the package carrier 100i of FIG. 5D, the rib 140i includes a first rib 144i and a plurality of first ribs 144i Two reinforcing ribs 146i, wherein the first reinforcing rib 144i is a single continuous structure layer and surrounds the periphery of the conductive connectors 130; In addition, please refer to FIG. 5B, in the package carrier 100g, since the package carrier 100g itself has a certain structural strength, the rigidity can be increased through a plurality of ribs 140g dispersedly arranged with each other, thereby enhancing the package carrier 100g. structural strength and further suppress and reduce warping of the package carrier 100g.

To sum up, in the design of the packaging carrier of the present invention, the conductive connectors and the ribs are arranged on the same surface of the first redistribution circuit structure layer, and the encapsulant covers the conductive connectors and the ribs, thereby The warping of the package carrier can be suppressed and reduced, so that the package carrier of the present invention has better flatness and structural reliability. Furthermore, in the manufacturing process of the package carrier of the present invention, no temporary substrate is needed, and therefore no laser debond process is required, which can effectively reduce the manufacturing cost. In addition, during the manufacturing process of the package carrier of the present invention, the encapsulant covers the conductive connectors and ribs, so that the back of the package carrier becomes flat, which facilitates subsequent assembly of chips on the front of the package carrier. In addition, since the packaging carrier of the present invention has better flatness, the chip packaging structure using the packaging carrier of the present invention can have better packaging yield.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10a, 10b, 10c, 10d, 10e: chip package structure 20: Drive substrate 22: Pad 30: solder ball 100a, 100b, 100c, 100e, 100f, 100g, 100h, 100i: package carrier 110:Connection structure layer 112: Substrate 112a: Base 113: one side 114: Pad 114a: Conductive strip 115: one end 120: The first redistribution line structure layer 121, 123: dielectric layer 122, 124: Redistribution line layer 125, 127: Conductive vias 126: connection pad 130, 130a, 130b, 130c, 130e: conductive connectors 132a, 132b, 132c: first bottom surface 140a, 140b, 140c, 140f, 140g, 140h, 140i, 240: reinforcement 142a: second bottom surface 144i: the first rib 146i: Second rib 150: encapsulation colloid 160, 170: the second redistribution line structure layer 161, 163, 171, 173: dielectric layer 162, 172: Redistribution line layer 164: connection pad 165, 167, 175, 177: Conductive vias 180: Layer-increasing structure layer 182: Glass fiber substrate 183: the first via hole 184: the first patterned conductive layer 185: Second via hole 186: the second patterned conductive layer 187: The third via hole 200, 250: chip 201: surrounding surface 203: back 210: micro solder joints 220: primer 230: sealing material 231: surface H, H', H'': Length L: cutting line F1: first surface F2: second surface S1: top surface S2: bottom surface S3: upper surface S4: lower surface T: Thickness

1A to 1E are schematic cross-sectional views of a manufacturing method of a package carrier according to an embodiment of the present invention. FIGS. 1F to 1J are schematic cross-sectional views illustrating a method of disposing a chip on the package carrier shown in FIG. 1E to form a chip package structure. 2A to 2D are schematic cross-sectional views of a manufacturing method of a package carrier according to another embodiment of the present invention. FIGS. 2E to 2I are schematic cross-sectional views illustrating a method of disposing a chip on the package carrier shown in FIG. 2D to form a chip package structure. 3A to 3C are schematic cross-sectional views of a manufacturing method of a package carrier according to another embodiment of the present invention. FIGS. 3D to 3H are schematic cross-sectional views illustrating a manufacturing method for disposing a chip on the package carrier shown in FIG. 3C to form a chip package structure. FIG. 4A is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention. FIG. 4B is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention. 5A to 5D are schematic bottom views of various package carriers according to various embodiments of the present invention.

100a: Package carrier board

110:Connection structure layer

112: Substrate

114: Pad

120: The first redistribution line structure layer

130a: Conductive connector

140a: reinforcement

150: encapsulation colloid

F1: first surface

F2: second surface

S1: top surface

S2: bottom surface

S3: upper surface

S4: lower surface

Claims (20)

A package carrier, comprising: The first redistribution circuit structure layer has a first surface and a second surface opposite to each other; a plurality of conductive connectors disposed on the first surface of the first redistribution wiring structure layer and electrically connected to the first redistribution wiring structure layer; a connection structure layer configured on the second surface of the first redistribution circuit structure layer, the connection structure layer includes a base material and a plurality of pads, the top surface and the bottom surface of each pad are respectively exposed to the base material and the pads are electrically connected to the first redistribution circuit structure layer; At least one rib is disposed on the first surface of the first redistribution wiring structure layer and at least located between the conductive connectors; and The encapsulant is disposed on the first surface of the first redistribution wiring structure layer, and covers the conductive connectors and the at least one reinforcing rib. The package carrier as claimed in claim 1, wherein each of the conductive connectors includes solder balls or copper pillars. The packaging carrier board as described in claim item 1 further includes: The second redistribution circuit structure layer is configured on the first surface of the first redistribution circuit structure layer, and is located between the conductive connectors and the first redistribution circuit structure layer, wherein the conductive connectors The second redistribution circuit structure layer is electrically connected to the first redistribution circuit structure layer. The package carrier as claimed in claim 3, wherein the line width and line spacing of the second redistribution wiring structure layer are larger than the line width and line spacing of the first redistribution wiring structure layer. The packaging carrier board as described in claim item 1 further includes: A build-up structure layer, configured on the first surface of the first redistribution circuit structure layer, and located between the conductive connectors and the first redistribution circuit structure layer, the build-up structure layer comprising a glass fiber substrate , a first patterned conductive layer, a second patterned conductive layer, at least one first via hole, at least one second via hole and at least one third via hole, the first patterned conductive layer and the second patterned conductive layer Layers are respectively located on opposite sides of the fiberglass substrate, the at least one third via hole penetrates the fiberglass substrate and electrically connects the first patterned conductive layer and the at least one second via hole, and the first patterned conductive layer The conductive layer is electrically connected to the first redistribution circuit structure layer through the at least one first via hole, and the second patterned conductive layer is electrically connected to the at least one first via hole through the at least one second via hole, The conductive connectors are connected to the second patterned conductive layer and electrically connected to the first redistribution wiring structure layer through the build-up structure layer. The package carrier as claimed in claim 1, wherein the at least one rib has a length, and the encapsulant has a thickness, and the length is less than or equal to the thickness. The package carrier as claimed in claim 1, wherein the material of the base material of the connection structure layer includes glass or silicon. The package carrier as claimed in claim 1, wherein the material of the at least one rib includes steel, aluminum, copper, silicon or glass. The package carrier as claimed in claim 1, wherein the at least one rib is a plurality of ribs, and the ribs are arranged in a dispersed manner or in a grid. The package carrier as claimed in claim 1, wherein the at least one rib is a continuous structural layer. A method for manufacturing a package carrier board, comprising: A base and a plurality of conductive strips are provided, the conductive strips are embedded in the base, and one end of each of the conductive strips is exposed to one side of the base; forming a first redistribution wiring structure layer on the side of the substrate; forming a plurality of conductive connectors and at least one rib on the first redistribution circuit structure layer, wherein the at least one rib is at least located between the conductive connectors; forming an encapsulant on the first redistribution wiring structure layer to cover the conductive connectors and the at least one rib; and removing part of the base and part of the conductive strips to form a connection structure layer, the connection structure layer includes a base material and a plurality of pads, and the top surface and the bottom surface of each pad are respectively exposed on the base material surface and subsurface. The manufacturing method of the packaging carrier as described in claim item 11 further includes: Before forming the conductive connectors and the at least one rib on the first redistribution circuit structure layer, forming a second redistribution circuit structure layer on the first redistribution circuit structure layer, wherein the second redistribution circuit structure layer The line width and line spacing of the circuit structure layer are larger than the line width and line space of the first redistributed circuit structure layer. The method for manufacturing a package carrier as claimed in claim 11, wherein each of the conductive connectors includes solder balls or copper pillars. The method for manufacturing a package carrier as claimed in claim 11, wherein the material of the at least one rib includes steel, aluminum, copper, silicon or glass. The method for manufacturing a package carrier as claimed in claim 11, wherein the at least one rib has a length, and the encapsulant has a thickness, and the length is less than or equal to the thickness. A chip packaging structure, comprising: Package carrier board, including: The first redistribution circuit structure layer has a first surface and a second surface opposite to each other; a plurality of conductive connectors disposed on the first surface of the first redistribution wiring structure layer and electrically connected to the first redistribution wiring structure layer; The connection structure layer is configured on the second surface of the first redistribution circuit structure layer, and includes a base material and a plurality of pads, the top surface and the bottom surface of each pad are respectively exposed on the upper surface of the base material and the lower surface, and the pads are electrically connected to the first redistribution circuit structure layer; At least one rib is disposed on the first surface of the first redistribution wiring structure layer and at least located between the conductive connectors; and an encapsulant, disposed on the first surface of the first redistribution wiring structure layer, and covering the conductive connectors and the at least one reinforcing rib; and At least one chip is disposed on the package carrier board and electrically connected to the pads of the connection structure layer. The chip package structure as described in claim 16, further comprising: The sealing material is arranged on the connection structure layer of the packaging carrier and covers the peripheral surface of at least one chip, wherein the backside of the at least one chip is exposed on the surface of the sealing material. The chip package structure as claimed in claim 16, wherein the at least one chip is electrically connected to the pads through micro-solder joint bonding or hybrid bonding bonding. The chip package structure as claimed in claim 16, wherein the encapsulant at least exposes the first bottom surface of each of the conductive connectors. The chip package structure as claimed in claim 19, wherein the encapsulant also exposes the second bottom surface of each rib.

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