TW202238800A - Apparatus and methods for energy field-assisted release of microelectronic devices from carrier structures - Google Patents
Apparatus and methods for energy field-assisted release of microelectronic devices from carrier structures Download PDFInfo
- Publication number
- TW202238800A TW202238800A TW110120544A TW110120544A TW202238800A TW 202238800 A TW202238800 A TW 202238800A TW 110120544 A TW110120544 A TW 110120544A TW 110120544 A TW110120544 A TW 110120544A TW 202238800 A TW202238800 A TW 202238800A
- Authority
- TW
- Taiwan
- Prior art keywords
- pick
- particles
- microelectronic
- carrier structure
- wafer
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
本文揭示之實施例係關於用於輔助自載體結構釋放微電子器件之裝置及方法。更具體言之,本文揭示之實施例係關於使用能量場來增強黏附至諸如載體晶圓及安裝膜之載體結構的不同尺寸及組態之微電子器件之釋放以用於在取置操作中移除此種器件之裝置及方法。Embodiments disclosed herein relate to apparatus and methods for assisting release of microelectronic devices from carrier structures. More specifically, embodiments disclosed herein relate to the use of energy fields to enhance the release of microelectronic devices of various sizes and configurations adhered to carrier structures such as carrier wafers and mounting films for removal during pick and place operations. Devices and methods for removing such devices.
隨著微電子器件及系統之效能提高,相關聯需求係改良此類微電子器件、此類器件之總成及併有此類總成之系統的效能,同時保持或甚至縮小微電子器件總成之形狀因數(例如,長度、寬度及高度)。此種需求通常但不排他地與行動系統(例如,智慧型電話、平板電腦、膝上型電腦及其他緊湊高效能系統)相關聯。為了保持或減小微電子器件(例如,半導體晶粒)之總成的佔據面積及高度,配備有用於堆疊之器件之間的垂直電(例如,信號、功率、接地/偏壓)通信之所謂的矽通孔(TSV)之堆疊器件之三維(3D)總成已經變得更加常見,結合了部件厚度之減小,及在接合線(例如,堆疊器件之間的空間)中使用預成型及原位形成之介電材料來減小接合線厚度,同時增加接合線均勻性。此種預成型之介電材料包括例如所謂的非導電膜(NCF)及晶圓級底部填充(WLUF),此等術語通常可互換使用。原位形成之介電材料可包括氧化矽及非常薄之聚合物。雖然有效地降低了3D微電子器件部件總成之高度,但微電子器件(例如半導體晶粒)之厚度降低至約50 μm或更小增加了器件脆性及對微裂紋及應力下之裂紋之敏感性,該應力諸如來自與處理裝置接觸之壓縮(例如衝擊)應力及例如在取置操作中使用真空自具有拾取頭或「拾取器」之支撐結構拾取微電子器件期間所經受之拉伸及彎曲應力。微電子器件總成之非限制性實例包括可能遭受應力致裂之多個堆疊之薄微電子器件,包括半導體記憶體晶粒總成,單獨或與其他晶粒功能(例如邏輯)組合,包括所謂的高頻寬記憶體(HBMx)、混合記憶體立方體(HMC)及晶片至晶圓(C2W)總成。As the performance of microelectronic devices and systems increases, there is an associated need to improve the performance of such microelectronic devices, assemblies of such devices, and systems incorporating such assemblies, while maintaining or even shrinking microelectronic device assemblies The shape factor (eg, length, width, and height) of the . Such a need is typically, but not exclusively, associated with mobile systems such as smartphones, tablets, laptops, and other compact, high-performance systems. In order to maintain or reduce the footprint and height of an assembly of microelectronic devices (e.g., semiconductor dies), so-called Three-dimensional (3D) assembly of stacked devices with through-silicon vias (TSVs) has become more common, combining a reduction in part thickness with the use of preforms and In-situ formed dielectric material reduces bond wire thickness while increasing bond wire uniformity. Such preformed dielectric materials include, for example, so-called non-conductive films (NCFs) and wafer-level underfills (WLUFs), which terms are often used interchangeably. In-situ formed dielectric materials can include silicon oxide and very thin polymers. While effectively reducing the height of 3D microelectronic device component assemblies, reducing the thickness of microelectronic devices (such as semiconductor dies) to about 50 μm or less increases device brittleness and susceptibility to microcracks and cracks under stress Stresses such as compressive (e.g., impact) stresses from contact with handling devices and stretching and bending experienced, for example, during pick-and-place operations using a vacuum to pick up microelectronic devices from a support structure with a pick-up head or "picker" stress. Non-limiting examples of microelectronic device assemblies include multiple stacked thin microelectronic devices that may be subject to stress cracking, including semiconductor memory die assemblies, alone or in combination with other die functions such as logic, including so-called High Bandwidth Memory (HBMx), Hybrid Memory Cube (HMC) and Chip-to-Wafer (C2W) assemblies.
在實施例中,一種取置裝置包含:載體結構,用於在其上支撐經切割微電子器件;包括拾取頭之拾取工具,拾取頭可在支撐在載體結構上之經切割微電子器件之各別位置上方移動;及位於載體結構下方之能量源,其經組態及定位以發射與拾取頭基本對準之能量場,以吸引或排斥載體結構及支撐在其上之經切割微電子器件之間的材料顆粒。In an embodiment, a pick-and-place apparatus comprises: a carrier structure for supporting thereon a diced microelectronic device; a pick-up tool including a pick-up head capable of placing a pick-and-place on each of the diced microelectronic devices supported on the carrier structure. and an energy source positioned below the carrier structure configured and positioned to emit an energy field substantially aligned with the pick-up head to attract or repel the carrier structure and diced microelectronic devices supported thereon material particles between.
在實施例中,一種方法包含:提供載體結構,該載體結構具有黏附至其上表面之經切割微電子器件;將拾取工具之拾取頭定位在載體結構上之選定目標微電子器件上方;用拾取工具起始目標微電子器件之向上拾取。基本上在起始向上拾取之同時,激活能量源,以自載體結構下方發射能量場,並基本上與拾取頭對準,以執行以下操作之一:向上排斥目標微電子器件遠離載體結構,或基本上在目標微電子器件下方吸引載體結構之一或多個部分向下遠離微電子器件。In an embodiment, a method comprises: providing a carrier structure having a diced microelectronic device adhered to an upper surface thereof; positioning a pick head of a pick-up tool over a selected target microelectronic device on the carrier structure; The tool initiates an upward pick of the target microelectronic device. substantially simultaneously with the initiation of upward pick-up, activating the energy source to emit an energy field from below the carrier structure and substantially aligned with the pick-up head to either: repel the target microelectronic device upwardly away from the carrier structure, or One or more portions of the carrier structure are attracted downwardly and away from the microelectronic device substantially below the target microelectronic device.
在實施例中,一種方法包含:使用具有嵌入其中之顆粒之黏附膜,藉由承載積體電路之器件晶圓之作用表面將器件晶圓黏附至載體晶圓;自器件晶圓之背側減薄器件晶圓;藉由器件晶圓之背側將減薄之器件晶圓黏附至載體結構,以形成總成;在該總成附近施加能量場以使該等顆粒施加向上之原動力以將該載體晶圓與該器件晶圓分離,並將該載體晶圓自該器件晶圓移除。In an embodiment, a method comprises: adhering a device wafer to a carrier wafer by an active surface of the device wafer carrying integrated circuits using an adhesive film having particles embedded therein; Thin device wafer; adhering the thinned device wafer to a carrier structure by the backside of the device wafer to form an assembly; applying an energy field near the assembly so that the particles exert an upward motive force to the The carrier wafer is separated from the device wafer, and the carrier wafer is removed from the device wafer.
優先權主張priority claim
本申請案主張於2021年3月16日提交之標題為「APPARATUS AND METHODS FOR ENERGY FIELD-ASSISTED RELEASE OF MICROELECTRONIC DEVICES FROM CARRIER STRUCTURES」之美國臨時專利申請案第63/161,561號之申請日的權益。This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 63/161,561, filed March 16, 2021, entitled "APPARATUS AND METHODS FOR ENERGY FIELD-ASSISTED RELEASE OF MICROELECTRONIC DEVICES FROM CARRIER STRUCTURES."
揭示用於自載體結構能量場輔助釋放半導體晶圓及半導體晶粒形式之微電子器件之裝置及方法。該裝置及方法特別適合於釋放及移除黏附在載體結構上之非常薄之半導體晶粒及半導體晶圓,在移除過程中顯著降低了損壞之可能性。Apparatus and methods for energy field assisted release of semiconductor wafers and microelectronic devices in the form of semiconductor dies from carrier structures are disclosed. The device and method are particularly suitable for releasing and removing very thin semiconductor dies and semiconductor wafers adhering to carrier structures, significantly reducing the possibility of damage during the removal process.
以下描述提供了具體細節,諸如尺寸、形狀、材料組成及定向,以便提供本發明之實施例之全面描述。然而,熟習此項技術者將瞭解並明白,可在無需使用此等特定細節之情況下實踐本發明之實施例,因為本發明之實施例可結合工業中所使用之習知製造技術來實踐。此外,以下提供之描述可能不形成用於自各種載體結構釋放微電子器件及用於各種目之之完整製程流程,例如在取置操作之上下文中移除黏附至載體晶圓之減薄之半導體晶圓及移除黏附至載體晶圓或安裝膜之減薄之半導體晶粒。以下僅詳細描述理解本發明之實施例所必需的彼等過程動作及結構。形成如本文所述被操縱之微電子器件並經受形成微電子部件組件、封裝及系統之進一步處理動作的額外動作可藉由習知製造製程來執行。The following description provides specific details, such as size, shape, material composition, and orientation, in order to provide a comprehensive description of embodiments of the invention. It will be understood and understood by those skilled in the art, however, that embodiments of the invention may be practiced without the use of these specific details, since embodiments of the invention may be practiced in conjunction with conventional fabrication techniques used in the industry. Furthermore, the description provided below may not form a complete process flow for releasing microelectronic devices from various carrier structures and for various purposes, such as removal of thinned semiconductor adhered to a carrier wafer in the context of a pick and place operation Wafers and removal of thinned semiconductor die adhered to carrier wafers or mounting films. Only those process actions and structures necessary for understanding the embodiments of the present invention are described in detail below. Additional acts of forming microelectronic devices manipulated as described herein and subjecting them to further processing acts to form microelectronic component assemblies, packages and systems may be performed by conventional fabrication processes.
現在參考圖1及圖2,作為本發明之實施例之特定背景,且如上所述,隨著封裝尺寸要求(即,形狀因子)變得更小,不僅必須減小堆疊之微電子器件之總成中的每個微電子器件(例如,半導體晶粒及自其中切割半導體晶粒之晶圓)之佔據面積,而且必須減小其厚度。如熟習此項技術者已知,處理展現(例如)介於約600 μm與約775 μm之間的初始厚度之半導體(例如,矽)晶圓以在其所謂的作用表面上形成積體電路,此後自其背側顯著減薄晶圓以滿足前述形狀因數需求。產生薄至約50 μm之經切割半導體晶粒之半導體晶圓已經商業化,且產生薄至約30 μm或更小(例如,約20 μm)之晶粒之半導體晶圓正在開發中。當前趨向於半導體晶粒形式之更薄微電子器件,特別是當記憶體器件包括大量(例如,8、12、16個或更多)與邏輯晶粒結合之堆疊記憶體晶粒及堆疊晶粒之其他組合時,隨著需要保持或甚至減小堆疊高度(例如為了結合至行動裝置中)將繼續。此種超薄晶粒亦可結合相鄰堆疊晶粒之間的近零接合線(NZB)間隔之實施來使用。NZB開發之一個實例涉及使用來自晶粒表面之電漿激活之氧化矽或超薄聚合物作為接合線介電質且保持金屬與金屬接觸界面之相鄰堆疊晶粒之間的混合接合,或與跨越接合線之相鄰疊加半導體晶粒之電路之對準金屬接觸元件的擴散接合相結合。在對此類超薄、易碎半導體晶粒或晶圓(自其切割此類晶粒)進行處理期間減小應力對於防止成品率損失(即,自給定晶圓或其他基板,或一批晶圓或基板產生之有缺陷晶粒之百分比)變得更加顯著,該處理引起之應力可能由在切割成半導體晶粒之前之超薄器件晶圓處理(例如,自變薄之器件晶圓移除載體晶圓)及在自用於晶片至晶圓(C2W)或多個晶粒堆疊處理(例如,熱壓接合)之載體結構拾取晶粒期間對超薄半導體晶粒之處理引起。Referring now to FIGS. 1 and 2, as specific background to embodiments of the present invention, and as noted above, as package size requirements (i.e., form factors) become smaller, not only must the total number of stacked microelectronic devices be reduced. The footprint of each microelectronic device (eg, a semiconductor die and the wafer from which the semiconductor die is cut) must be reduced and its thickness must be reduced. As is known to those skilled in the art, processing a semiconductor (e.g., silicon) wafer exhibiting an initial thickness of, for example, between about 600 μm and about 775 μm to form integrated circuits on its so-called active surface, Thereafter the wafer is significantly thinned from its backside to meet the aforementioned form factor requirements. Semiconductor wafers producing diced semiconductor grains as thin as about 50 μm have been commercialized, and semiconductor wafers producing grains as thin as about 30 μm or less (eg, about 20 μm) are under development. The current trend is toward thinner microelectronic devices in the form of semiconductor dies, especially when memory devices include large numbers (e.g., 8, 12, 16 or more) of stacked memory dies combined with logic dies and stacked dies Other combinations will continue as needed to maintain or even reduce the stack height (eg for incorporation into mobile devices). Such ultra-thin die can also be used in conjunction with the implementation of near zero bond wire (NZB) spacing between adjacent stacked die. One example developed by NZB involves hybrid bonding between adjacent stacked die using plasma-activated silicon oxide or ultra-thin polymers from the die surface as bond wire dielectric and maintaining metal-to-metal contact interfaces, or with The diffusion bonding of the aligned metal contact elements of the circuits of adjacent stacked semiconductor dies across the bonding wires is combined. Reducing stress during processing of such ultra-thin, brittle semiconductor die or wafers from which such die are cut is critical to preventing yield loss (i.e., from a given wafer or other substrate, or batch of wafers). The percentage of defective die produced by the wafer or substrate) becomes more pronounced, and the stresses induced by this process may be caused by the processing of ultra-thin device wafers before dicing into semiconductor dies (e.g., removal from thinned device wafers) carrier wafer) and handling of ultra-thin semiconductor die during die pick-up from a carrier structure for wafer-to-wafer (C2W) or multiple die stacking processing (eg, thermocompression bonding).
儘管處理引起之微電子器件之微裂紋及裂紋之許多來源係已知的,但當此種器件之厚度降低至約60至65 μm以下時,一種特定之損傷誘導機制已經變得明顯,且當器件厚度進一步降低時,已經發展成顯著問題。如熟習此項技術者所熟知,可在半導體(例如矽)晶圓上製造大量半導體晶粒形式之微電子器件。在將相互橫向間隔開之器件位置處之積體電路連同自積體電路向晶圓背面延伸之可選導電矽通孔(TSV)一起形成在晶圓之所謂的作用表面之中及之上之後,如上所述,將晶圓自初始厚度減薄至最終顯著減小之厚度,曝露TSV之端部(若存在)。隨後,使用例如塗覆金剛石之晶圓鋸、雷射劃片製程、電漿劃片製程或所謂的「隱身(stealth)」劃片製程將周邊支撐在膜框架上之以聚合物安裝膜(有時稱為「安裝帶」)之形式黏附固定至載體結構之減薄的晶圓分離或「切割」為離散半導體晶粒。在切割之後,在薄膜框架上橫向拉伸安裝膜以分離經切割之晶粒,接著藉由取置工具之拾取頭自安裝膜上一個接一個地拾取晶粒,拾取頭具有連接至真空源且開放至拾取面上之真空通道,拾取面可移動至緊靠待拾取之每個目標晶粒之上。在許多情況下,隨著拾取頭在真空通道中及拾取面上開始之真空用來自安裝膜之黏合劑中拉出目標晶粒,噴射器用來連同拾取頭之向上運動一起向上推動待自安裝膜下面拾取之晶粒。Although many sources of handling-induced microcracks and cracks in microelectronic devices are known, a specific damage-inducing mechanism has become apparent when the thickness of such devices is reduced below about 60 to 65 μm, and when This has developed into a significant problem as the device thickness is further reduced. As is well known to those skilled in the art, a large number of microelectronic devices in the form of semiconductor dies can be fabricated on semiconductor (eg, silicon) wafers. After forming integrated circuits at mutually laterally spaced device locations together with optional conductive through-silicon vias (TSVs) extending from the integrated circuits to the backside of the wafer in and on the so-called active surface of the wafer As described above, the wafer is thinned from an initial thickness to a final substantially reduced thickness, exposing the ends of the TSVs, if present. Subsequently, a polymer mounting film (with a polymer) is mounted peripherally on a film frame using, for example, a diamond-coated wafer saw, a laser scribing process, a plasma scribing process, or a so-called "stealth" scribing process. A thinned wafer adhered to a carrier structure in the form of what is sometimes called a "mounting tape") is separated or "diced" into discrete semiconductor die. After dicing, the mounting film is stretched laterally on the film frame to separate the diced die, and then the die are picked up from the mounting film one by one by the pick-up head of the pick-and-place tool, which has a connection to a vacuum source and Vacuum channels open to the pick-up surface, which can be moved into close proximity to each target die to be picked. In many cases, the ejector is used to push up the film to be self-mounted in conjunction with the upward movement of the pick-up head as the vacuum initiated by the pick-up in the vacuum channel and on the pick-up face pulls the target die from the adhesive from the mount film. The grains picked up below.
傳統上,當用拾取頭(拾取頭包括多個通向面朝下之拾取面之真空通道)自安裝膜上之黏合劑中拾取半導體晶粒時,拾取面移動至半導體晶粒正上方之位置,藉由將真空通道打開至拾取面並穿過所有真空通道之晶粒覆蓋區,對晶粒施加真空。然而,已經判定,正拾取之半導體晶粒之中心區域通常比半導體晶粒之周邊區域更容易自安裝膜黏合劑剝離。在拾取極薄(例如約50 μm厚或更薄)之半導體晶粒之情況下,儘管對拾取面施加了真空,但仍黏附至安裝膜之半導體晶粒之部分與自膜釋放且被真空拉靠在拾取面上之彼等部分之間的應力可能導致晶粒之損壞,甚至破裂。圖1說明自黏附膜之不均勻的晶粒剝離DP,而圖2說明由於不成功之晶粒拾取導致的安裝膜上之斷裂晶粒BD。圖3說明延伸穿過半導體晶粒之一部分之裂紋。此種現象通常回應於晶粒之半導體材料上之應力,應力在晶粒之中心區域與晶粒之一或多個周邊區域之間,當晶粒被拾取頭之拾取面自安裝膜向上拉動時,晶粒之中心區域隨著拾取頭向上移動,晶粒之一或多個周邊區域仍然黏附至安裝膜之黏合劑上。換言之,在固定至拾取面且自黏附膜釋放之半導體晶粒之至少一個(例如,中心)區域與保持黏附至安裝膜之至少另一(例如,周邊)區域之間的拉伸及彎曲應力可能會導致半導體晶粒之微開裂或甚至開裂。微裂紋尤其令人擔憂,因為此種對半導體晶粒之損壞在晶粒與其他晶粒組裝、封裝及測試之前可能本身不明顯,從而導致整個多晶粒封裝之丟棄。在高價之基於處理器之系統(諸如,行動裝置、平板電腦、膝上型電腦、伺服器等)之操作期間,在併入較高級封裝之後,封裝之所謂「早期死亡率」失效之可能性亦同樣令人擔憂。Traditionally, when picking up a semiconductor die from an adhesive on a mounting film with a pick-up head (the pick-up head includes multiple vacuum channels leading to a face-down pick-up surface), the pick-up surface moves to a position directly above the semiconductor die , apply a vacuum to the die by opening the vacuum channels to the pick-up surface and across the die footprint of all vacuum channels. However, it has been determined that the central region of the semiconductor die being picked is generally easier to peel from the mounting film adhesive than the peripheral region of the semiconductor die. In the case of picking up an extremely thin (e.g., about 50 μm thick or thinner) semiconductor die, the portion of the semiconductor die that adheres to the mounting film is released from the film and pulled by the vacuum despite applying a vacuum to the pick-up surface. The stress between those parts resting on the pick-up face can lead to damage or even cracking of the die. FIG. 1 illustrates uneven die delamination DP from the adhesive film, while FIG. 2 illustrates broken die BD on the mounting film due to unsuccessful die pick-up. Figure 3 illustrates a crack extending through a portion of a semiconductor die. This phenomenon usually responds to stress on the semiconductor material of the die, between the central region of the die and one or more peripheral regions of the die, when the die is pulled upward from the mounting film by the pick-up face of the pick-up head , the central area of the die moves up with the pick-up head, and one or more peripheral areas of the die remain adhered to the adhesive of the mounting film. In other words, tensile and bending stresses between at least one (e.g. central) region of the semiconductor die secured to the pick-up surface and released from the adhesive film and at least one other (e.g. peripheral) region remaining adhered to the mounting film may Can cause micro-cracking or even cracking of semiconductor grains. Microcracking is of particular concern because such damage to a semiconductor die may not itself be apparent until the die is assembled with other die, packaged, and tested, resulting in the discarding of the entire multi-die package. Possibility of so-called "early mortality" failure of packages after incorporating higher-level packages during operation of high-priced processor-based systems such as mobile devices, tablets, laptops, servers, etc. It is also worrying.
本文提供之附圖僅用於說明目的,並不意味著為任何特定材料、部件、結構、器件或系統之實際視圖。作為例如製造技術及/或公差之結果,可預期附圖中描繪之形狀之變化。因此,本文中所描述之實施例不應解釋為限於所說明之特定形狀或區域,而是包括例如由製造導致之形狀偏差。舉例而言,說明或描述為箱形之區域可具有粗糙及/或非線性特徵,而說明或描述為圓形之區域可包括一些粗糙及/或線性特徵。此外,所示表面之間的銳角可為圓形的,反之亦然。因此,附圖中說明之區域本質上為示意性的,且其形狀不旨在說明區域之精確形狀,且不限制本申請專利範圍之範疇。附圖不一定按比例繪製。The drawings provided herein are for illustration purposes only and are not meant to be actual views of any particular material, component, structure, device or system. Variations in the shapes depicted in the figures are to be expected as a result, for example, of manufacturing techniques and/or tolerances. Thus, embodiments described herein should not be construed as limited to the particular shapes or regions illustrated but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as a box may have rough and/or nonlinear features, while a region illustrated or described as a circle may include some rough and/or linear features. Furthermore, acute angles between surfaces shown may be rounded and vice versa. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present application. The drawings are not necessarily drawn to scale.
在描述本發明之方法及裝置之實施例中,為了方便起見,不同附圖及不同實施例中之相同元件由相同或相似之參考元件識別。In describing the embodiments of the method and apparatus of the present invention, the same elements in different drawings and different embodiments are identified by the same or similar reference elements for convenience.
參考圖4A至圖4D,說明根據本發明之實施例的用於自載體結構移除經切割之微電子器件(例如,半導體晶粒)的方法及裝置。如圖4A所示,在作用表面202上承載積體電路204之減薄之器件晶圓200 (例如,自約600 μm至約775 μm之初始厚度減薄至例如約50 μm或更小之最終厚度)在背面206塗覆有其中嵌入顆粒306之材料302。材料302可例如具有在約2 μm與約20 μm之間的厚度。此種操作可在減薄之器件晶圓200固定至載體晶圓100時實現,如虛線所示,且載體晶圓在減薄操作期間支撐器件晶圓200。顆粒306可例如具有在約1 μm及約15 μm之間,例如約5 μm、約10 μm之尺寸(例如直徑)。通常,材料302之至少約一半厚度之顆粒尺寸係合適的。材料302可包含或不包含黏合材料,且可溶於水(例如,去離子(DI)水)或另一種良性溶劑。可選擇材料302以平衡實體特性與在曝露於水或其他溶劑時之降解敏感性。用於材料302之合適材料包括例如來自位於日本東京(Tokyo, Japan)之DISCO之HogoMax水溶性樹脂及來自位於美國密蘇里州羅拉市(Rolla, MO)之Brewer Science公司之WaferBOND® HT-10.10。其他合適之材料可自信越化學工業株式會社(Shin-Etsu Chemical Co.,Ltd.)、Brewer Science、3M等獲得。顆粒306可首先用接觸黏合劑固定至減薄之器件晶圓之背面206,藉由重力或氣流移除鬆散之顆粒,接著藉由例如旋塗、噴塗或輥塗將材料302施加至安裝背面206,顆粒306上,作為預成型黏附膜。或者,顆粒306可懸浮在液體形式之材料302中並分配在背面206上。若需要,大量之材料302(例如,卷、晶圓大小之段)可用嵌入在黏合材料302中之顆粒306及層壓在黏合材料上之保護膜預成型,用於在將材料302施加至背面206之前儲存及處理。如圖4B所示,器件晶圓200接著藉由其背面206經由材料302黏附至安裝膜400上之黏合材料402,安裝膜支撐在膜框架404上,之後移除載體晶圓(未展示)。下面結合圖5A至圖5C之實施例描述合適之黏合材料之實例。接著,如圖4C所示,器件晶圓200被切割為由通道210分開之單個微電子器件(例如半導體晶粒)208。可使用乾法製程(諸如雷射劃片、隱形劃片或電漿劃片)來進行切割,以避免損害材料302之完整性。如圖所示,在每個經切割之微電子器件208下面之切割材料302被完全切斷之後,產生可延伸至安裝膜400之黏合材料402中之通道210。此外,如圖4D所示,具有拾取頭502之拾取工具500包括延伸至拾取面504之真空通道(未展示)與能量場源600同時位於目標微電子器件208之上並緊鄰目標微電子器件208,能量場源600與拾取頭502對準,且自能量場源600產生能量場602。Referring to FIGS. 4A-4D , methods and apparatus for removing diced microelectronic devices (eg, semiconductor dies) from a carrier structure in accordance with embodiments of the present invention are illustrated. As shown in FIG. 4A , a thinned device wafer 200 (e.g., from an initial thickness of about 600 μm to about 775 μm thinned to a final thickness of, for example, about 50 μm or less) carrying integrated circuits 204 on an active surface 202. thickness) on the
在該實施例之一種實施中,顆粒306可為被磁場排斥之抗磁材料,且能量場源600可包含一或多個電磁體,自電磁體產生磁場形式之能量場602。抗磁材料包括但不限於銅、鉍及熱解石墨。因此,目標微電子器件208下面之抗磁顆粒306可被磁場602排斥,從而排斥抗磁顆粒306上面之目標微電子器件208遠離黏合材料402並朝向拾取頭502。應理解,在由拾取頭502拾取期間,僅需要目標微電子器件208之微小提昇距離來顯著減小(若非破壞)黏合材料402對材料302之黏附並減輕目標微電子器件208之各個部分之間的應力。In one implementation of this embodiment, the
在此實施例之另一實施中,能量場源600可包含電磁源,該電磁源經組態以產生振盪、時變磁場形式之能量場602,且顆粒306可包含非磁性導電金屬,例如鋁或銅。由於楞次定律,時變磁場在顆粒306中感應電流,導致排斥效應以將微電子器件208自黏合劑402提起。應瞭解,在拾取頭502拾取期間,僅需要微小之提昇距離以實質上減少(若非破壞)黏合材料402對材料302之黏附且減輕目標微電子器件208上之應力。In another implementation of this embodiment, the
在以上兩者任一實施中,在藉由噴射去離子(DI)水或適於溶解材料302之其他溶劑自安裝膜400拾取微電子器件208之後,可自每個目標微電子器件208之背面212清潔任何殘留材料302及嵌入之顆粒306,接著將其鎖存在容器中,並回收顆粒306以供再次使用。In either implementation, after the
應注意,儘管圖4A至圖4D之實施例已經在用於減薄之半導體晶圓及經切割之微電子器件之載體結構包含支撐在膜框架上之安裝膜之環境中進行了描述,但實施例不限於此。舉例而言,可將減薄之晶圓支撐並黏附至剛性載體基板上,使用乾法在其上進行切割,且用能量場輔助釋放來拾取經切割之微電子器件,拾取係自嵌入至黏附膜中之能量場敏感之顆粒進行的,該黏附膜將經切割之微電子器件固定至剛性載體基板。It should be noted that although the embodiments of FIGS. 4A-4D have been described in the context of a carrier structure for thinned semiconductor wafers and diced microelectronic devices comprising a mounting film supported on a film frame, the implementation Examples are not limited to this. For example, a thinned wafer can be supported and adhered to a rigid carrier substrate on which dicing can be performed using a dry process, and the diced microelectronic devices can be picked up with energy field assisted release, from embedding to adhered energy field sensitive particles in the film, the adhesive film secures the diced microelectronic device to the rigid carrier substrate.
參考圖5A至圖5C,說明根據本發明之實施例之用於自載體結構移除經切割之微電子器件(例如,半導體晶粒)之另一方法及裝置。如圖5A所示,減薄之器件晶圓200藉由其背面206黏附至具有顆粒306嵌入其中並駐留在安裝膜400上之黏合材料402。黏合材料402可為熱固性或熱塑性材料,且可溶於水或另一種良性溶劑。黏合材料402可具有自約2 μm至約50 μm之厚度,但較小之厚度最大值(例如約20 μm)可為足夠的。可選擇黏合材料402以平衡黏附特性與當曝露於水或另一種溶劑時對降解之敏感性。用於材料402之合適材料包括例如來自位於日本東京之DISCO之HogoMax水溶性樹脂、來自位於美國密蘇里州羅拉市之Brewer Science公司之WaferBOND® HT-10.10及來自信越化學工業株式會社之SPIS TA。顆粒306可包含鐵磁材料,諸如鐵、鎳、鈷或前述任一者之合金。顆粒306可具有例如約1 μm至約10 μm,例如約5 μm之尺寸(例如直徑)。顆粒306可塗覆有化學惰性塗層,例如適合於材料402之材料,以減輕顆粒306與減薄之器件晶圓200接觸而引起之污染問題。顆粒306可首先用接觸黏合劑固定至安裝膜400上,藉由重力或氣流除去鬆散之顆粒,接著藉由例如旋塗、噴塗或輥塗將黏合材料402施加至安裝膜400上,顆粒306上,作為預成型黏附膜。或者,顆粒306可懸浮在液體形式之黏合材料402中且與黏合材料402同時分配。若需要,安裝膜400上之大量黏合材料402 (例如,卷、晶圓大小之段)可用嵌入黏合材料402中之顆粒306及層壓在黏合材料上之保護膜預成型,用於在將安裝膜400施加至膜框架404之前儲存及處理,之後剝離保護膜。接著,如圖5B所示,器件晶圓200被切割為由通道210分開之單個微電子器件(例如半導體晶粒)208。使用諸如雷射劃片、隱形劃片或電漿劃片之乾法進行切割,以避免黏合材料402之過早降解。如圖所示,在經切割之微電子器件208之間的黏合材料402被部分地或完全地切斷至安裝膜400之層位,且通道210可至少延伸至安裝膜400之黏合材料402中。此外,如圖5C所示,具有拾取頭502之拾取工具500,包括延伸至拾取面504之真空通道(未展示),與能量場源600同時位於目標微電子器件208之上且緊鄰目標微電子器件,自能量場源產生能量場602。在此實施例中,能量場源600包含電磁場源,自該電磁場源發出磁場形式之能量場602。當拾取頭502之拾取面504上之真空向上拉動目標微電子器件208時,磁場602吸引鐵磁顆粒306,向下拉動安裝膜400以自目標微電子器件208之背面212釋放黏合材料402。磁場602可在目標微電子器件208之背面212上脈動地打開及關閉,以波動方式振盪或二者兼有,以便於自黏合材料402釋放。應注意,雖然顆粒306可基本上均勻地分佈在整個黏合材料402中,但亦可考慮顆粒可以對應於減薄之器件晶圓200之器件位置之間的長度、寬度及間隔之柵格圖案印刷至安裝膜上,或印刷至安裝膜400上之黏合材料402中。此種方法使安裝膜400上之黏合材料402及顆粒306之量最小化。該方法亦允許更局部地施加磁場602,且將顆粒306配置在器件柵格位置內,更密集地集中在對應於黏合材料402之彼等區域(例如,鄰近器件位置之周界)之柵格位置內,從而更難以自目標微電子器件208釋放以提供更大之向下拉力。Another method and apparatus for removing diced microelectronic devices (eg, semiconductor dies) from a carrier structure in accordance with an embodiment of the present invention is illustrated with reference to FIGS. 5A-5C . As shown in FIG. 5A , the thinned
在拾取之後,任何殘留之黏合材料402及任何嵌入之顆粒306保持黏附至目標微電子器件208之背面,在自安裝膜400拾取之後,可藉由噴霧去離子(DI)水或其他適合溶解黏合材料402之溶劑自每個目標微電子器件208之背面212清潔,接著將黏合劑材料鎖存在容器中,且回收顆粒306以供再次使用。After picking up, any remaining
參考圖6A至圖6C,描述根據本發明之實施例之用於自器件晶圓移除載體結構之方法及裝置。藉由上下文,已經證明,在減薄(例如,背面研磨、拋光、蝕刻)製程期間,約50 μm或更小之最終厚度之器件晶圓(即,在作用表面上製造積體電路並自其背面減薄之後)難以與用於支撐器件晶圓之載體晶圓分離。在將器件晶圓黏附至另一載體結構(例如安裝帶或膜)之後,習知之機械操作技術(諸如載體晶圓之邊緣夾緊及真空提昇)由於器件晶圓及載體晶圓之間的過度黏附而經常導致對器件晶圓、載體晶圓或兩者之損壞。一些習知之黏合-釋放技術提供了一些成功,諸如在機械移除載體晶圓之前,藉由掃描雷射束穿過載體晶圓,用電磁輻射加熱總成或加熱或以其他方式降解黏合劑;然而,不同之橫向分離之晶圓部分之間的黏合降解程度之不規則性可能導致器件晶圓、載體晶圓或兩者之應力相關之破裂。即使器件晶圓保持未損壞,藉由習知機械技術自器件晶圓機械移除部分(即,斷裂部分)載體晶圓即使並非不可能亦為不切實際的。Referring to FIGS. 6A-6C , a method and apparatus for removing a carrier structure from a device wafer according to an embodiment of the present invention is described. By way of context, it has been demonstrated that during the thinning (e.g., backgrinding, polishing, etching) process, device wafers with a final thickness of about 50 μm or less (i.e., on the active surface on which integrated circuits are fabricated and from which After backside thinning) is difficult to separate from the carrier wafer used to support the device wafer. After adhering the device wafer to another carrier structure (e.g. mounting tape or film), conventional mechanical manipulation techniques such as edge clamping and vacuum lifting of the carrier wafer due to excessive contact between the device wafer and the carrier wafer Sticking often results in damage to the device wafer, the carrier wafer, or both. Some known bond-release techniques have provided some success, such as heating the assembly with electromagnetic radiation or heating or otherwise degrading the adhesive by scanning a laser beam through the carrier wafer prior to mechanical removal of the carrier wafer; However, irregularities in the degree of adhesion degradation between different laterally separated wafer portions may lead to stress-related cracking of the device wafer, the carrier wafer, or both. Even if the device wafer remains undamaged, it is impractical, if not impossible, to mechanically remove portions (ie, fractured portions) of the carrier wafer from the device wafer by conventional mechanical techniques.
參考圖6A,例如半導體(例如矽)或玻璃材料之載體晶圓100在其主表面104上塗覆有黏合材料102。黏合材料102可包含熱固性或熱塑性材料,例如來自位於日本東京之DISCO 之HogoMax水溶性樹脂、來自位於美國密蘇里州羅拉市之Brewer Science公司之WaferBOND® HT-10.10及來自位於日本東京之信越化學工業株式會社之SPIS TA。鐵磁材料之顆粒106可在藉由例如旋塗或噴塗施加至主表面104之前以液體形式基本均勻地混合至黏合材料102中。或者,可將乾燥顆粒106分配至預先施加至主表面104上之接觸黏合劑上,接著藉由重力或氣流除去未黏附之顆粒106,並藉由旋塗、噴塗或作為滾塗之預成型黏附膜將黏合材料102施加至黏附之顆粒上。或者,顆粒106可以液體形式懸浮在黏合材料102中並分佈在主表面104上。顆粒106可例如具有在約1 μm及約25 μm之間的尺寸(例如直徑),例如約5 μm、約10 μm、約15 μm。通常,顆粒106可例如為黏合材料102之厚度的約一半。初始厚度為約600 μm至約775 μm之器件晶圓200接著藉由承載積體電路204之作用表面202黏附至黏合材料102。接著如上所述將器件晶圓200自背面206減薄至最終厚度。隨後,如圖6B所示,將總成倒置,並將減薄之器件晶圓200藉由其背面206黏附至另一載體結構,例如承載黏合材料(未展示)並支撐在膜框架404上之安裝膜400。此時,如圖6C所示,磁場形式之能量場602由磁場源(例如,電磁體)形式之能量源600產生,能量源置放在載體晶圓100附近(即,大約10 µm至大約25 µm)且在載體晶圓上方,且藉由磁場602對顆粒106之吸引,載體晶圓100被基本上自器件晶圓200上方之黏合材料102中拉出。磁場源600可在載體晶圓100上移動,例如如箭頭A1所示自一側移動至另一側以自黏合材料102剝離載體晶圓100,或者如箭頭A2所示以徑向剝離運動自載體晶圓100之中心徑向向邊緣108移動。自器件晶圓200釋放之載體晶圓100接著可僅藉由磁吸引來提昇,或者可施加來自真空卡盤(未展示)之真空或者使用邊緣夾持卡盤(若載體晶圓未損壞)來提昇載體晶圓100。磁場602可被快速地脈動以拉動及釋放顆粒106,從而促進載體晶圓100之釋放。應注意,磁性吸引之使用允許自器件晶圓200提昇部分載體晶圓(即,損壞段),而不藉由提昇機構實體接合部分載體晶圓,且因此無損壞器件晶圓200之風險。亦應注意,抗磁材料或非磁性導電材料可用於顆粒106,且時變振盪磁場可由位於安裝膜400下方並可橫向移動之電磁源產生,以藉由顆粒106之排斥自器件晶圓200提昇載體晶圓100,如先前關於圖4A至圖4D所述。Referring to FIG. 6A , a
參考圖7、圖8A、圖8B及圖8C,說明根據本發明之實施例之帶及卷軸總成之各種組態,帶及卷軸總成適用於帶之凹穴中攜帶之微電子器件的能量場輔助釋放。圖7說明帶及卷軸總成700,其包含安裝至中心轂704之兩個橫向間隔開之凸緣702,凸緣702之間的空間之尺寸適於容納纏繞在轂704周圍之分配帶706之寬度。分配帶706組態有凹陷在表面710中之一系列均勻縱向間隔之凹穴708,每個凹穴708組態有寬度、長度及深度以在其中接納且容納微電子器件208。覆蓋帶712被層壓(例如,用輕黏合劑黏附)在分配帶706之表面710上,覆蓋凹穴708之口部。分配帶706可用於取置操作,其中,拾取頭在覆蓋帶712自分配帶706之表面剝離之後隨著分配帶706前進而將每個微電子器件208自其凹穴708移除。通常,每個微電子器件208可僅藉由覆蓋帶712含有在凹穴708中,或者黏附至凹穴708之底表面上之黏合劑。當微電子器件208由拾取頭拾取時,前一種方法可能引起對準問題(例如,圍繞垂直Z軸)。後一種方法在拾取黏附至安裝膜上之微電子器件208時遭受與上述相同之缺陷,因為微電子器件208之不同部分以不同程度黏附至安裝膜之黏合劑上,導致拾取期間微電子器件208之不同部分之間的應力。與習知分配帶結構相比,根據本發明之實施例組態之分配帶可減輕(若未消除)此種應力。Referring to Figures 7, 8A, 8B and 8C, various configurations of tape and reel assemblies according to embodiments of the present invention are illustrated, which are suitable for powering microelectronic devices carried in pockets of the tape. Field assisted release. 7 illustrates a belt and
例如,如圖8A所示,分配帶706A可組態成具有縱向間隔開之凹穴708,每個凹穴之長度、寬度及深度足以容納微電子器件208,當微電子器件208黏附至與微電子器件之長度及寬度基本相同之底面716上之黏合材料714時,微電子器件凹入表面710之下。黏合材料714含有鐵磁材料、抗磁材料或諸如鋁或銅之其他非磁性導電材料之顆粒306。For example, as shown in FIG. 8A, dispensing
如圖8B所示之另一實例,分配帶706B可組態成具有縱向間隔開之凹穴708,每個凹穴之長度、寬度及深度足以容納微電子器件208,當微電子器件被接納在凹穴708中時,當微電子器件208黏附至位於微電子器件之相對端之預定位置下方的底面716上之黏合材料段714上時,微電子器件凹入表面710下方。黏合材料714可含有鐵磁材料、抗磁材料或諸如鋁或銅之其他非磁性導電材料之顆粒306。As another example shown in FIG. 8B, the dispensing
如圖8C所示之另一實例,分配帶706C可組態成具有縱向間隔開之凹穴708,每個凹穴之長度、寬度及深度足以容納微電子器件208,當微電子器件208被接納在凹穴708中時,當微電子器件黏附至自位於微電子器件之拐角之預期位置下方之底面716突出之基座720上之黏合材料段714上時,微電子器件凹入表面710下方。黏合材料714可含有鐵磁材料、抗磁材料或諸如鋁或銅之其他非磁性導電材料之顆粒306。分配帶706C可可選地設置有排出孔718,排出孔自底面716延伸至每個凹穴708下面的分配帶706C之下側。As another example shown in FIG. 8C, the dispensing
如以上參考圖4A至圖4D、圖5A至圖5C及圖6A至圖6C所述,鐵磁顆粒、抗磁顆粒或其他導電顆粒與適當之能量場源之結合使用可用於在拾取操作期間將分配帶706A、706B或706C拉離微電子器件(鐵磁顆粒被吸引至磁場),或將微電子器件208推離分配帶706A、706B或706C (抗磁顆粒或非磁性導電顆粒被適當磁場排斥)。當使用鐵磁顆粒時,可能希望允許圍繞容納被拾取之微電子器件208之凹穴708之分配帶部分回應於磁吸引而向下彎曲,而當使用鐵磁性或其他非磁性之導電顆粒時,可能希望防止分配帶向上彎曲或其他位移,例如藉由將分配帶706A、706B或706C之相對邊緣限制在拾取頭502下方之U形通道中,以方便拾取操作。As described above with reference to FIGS. 4A-4D , 5A-5C , and 6A-6C , the use of ferromagnetic, diamagnetic, or other conductive particles in combination with an appropriate energy field source can be used to The dispensing
參考圖9,拾取工具500之拾取頭502位於目標微電子器件208上方用於拾取操作,目標微電子器件208位於分配帶706C之凹穴708(為了清楚起見省略了凹穴側)中。拾取頭502配備有流體分配通道510及流體移除真空通道512,其可在拾取操作期間使用,以DI水或另一合適之溶劑溶解目標微電子器件208所黏附之黏合材料,排出孔718允許大量流體在微電子器件208下方流動並進入真空通道604,真空通道可併入位於目標微電子器件208下方之能量場源600中。此外,類似組態之拾取頭502可與分配帶706A及706B一起使用,以溶解黏合材料並清潔自一袋殘餘黏合材料及顆粒306拾取之每個目標微電子器件208。此外,雖然在帶及卷軸總成之分配帶之上下文中說明,但可考慮類似組態之拾取頭可用於溶解材料302、黏合材料402,並清潔自殘餘材料302、黏合材料402及顆粒306之安裝膜拾取之每個目標微電子器件208,如關於圖4A至圖4D及圖5A至圖5C所述。Referring to FIG. 9 , pick
參考圖10A及圖10B,說明在圖5B所示及所述之配置中,經切割之微電子器件208黏附至安裝膜400上之黏合材料402。然而,代替嵌入黏合材料402中之顆粒306,顆粒406包含鐵磁形狀記憶合金形式之磁性形狀記憶材料。磁性形狀記憶合金之一個實例為鎳-錳-鎵合金,而其他實例包括鐵-鈀及鎳-鐵-鎵合金。當經受磁場時,此種合金可能膨脹(例如伸長)或收縮。此種變形至少約為6%,且可接近約20%之量級,此取決於合金。黏合材料402之厚度可為例如約2 μm至約50 μm,例如約20 μm。如圖10A所示,當處於收縮狀態時,顆粒406完全位於黏合材料402之深度內,與目標微電子器件208之背面212之實體接觸最小或無實體接觸。然而,如圖10B所示,在拾取操作期間,拾取工具500之拾取頭502位於目標微電子器件208上方,且拾取面504緊鄰目標微電子器件,且拾取頭中之真空通道被致動。基本上同時,激活電磁體形式之能量場源600,以使磁場形式之局部能量場602作用在顆粒406上,使顆粒406垂直伸長超過黏合材料402之厚度,並藉由其背面212將微電子器件208推至黏合劑402上方(為清楚起見放大了距離)。為了增強黏合材料402之提昇效果,可能期望將安裝膜400保持在目標微電子器件208之位置處的固定垂直位置,例如藉由使用靠著安裝膜400下側置放之能量源600之周邊的周邊真空通道或多個真空通道來防止黏合材料402及安裝膜400之向上移位。在一種實施中,磁場602對於細長顆粒406可為恆定的,且在目標微電子器件208之下為靜止的。在另一實施中,磁場可固定在目標微電子器件208之下,但脈衝開啟及關閉以擴展及收縮顆粒406。在另一實施中,能量源600可包含多個可單獨致動之電磁體600A至600E,其在目標微電子器件208下之目標區域上相互橫向間隔開。可順序起始電磁體600A至600E,以在顆粒406之間引起自一側至另一側,或自微電子器件208周邊至中心,或自中心至周邊之波動,以促進目標微電子器件208自黏合材料402釋放。經考慮,可組態顆粒406以增強其之伸長特性,且可使用模板將顆粒406部分地置放至安裝膜400中,並呈現所期望之圖案,其對應於將要置放在安裝膜上之減薄之晶圓中的微電子器件位置之圖案,隨後將黏合材料402以液體形式或作為預成型膜分配至安裝膜400上。或者,黏合材料402可薄膜形式提供,其中顆粒406以所需圖案插入,且薄膜覆蓋有保護膜,在將薄膜形式之黏合材料402施加至安裝膜400之後,該保護膜將被剝離。利用此種方法,可優化給定微電子器件位置內之顆粒之數量及位置,且安裝膜之其他區域,例如器件位置之間的通道及器件位置之外之區域,可能無顆粒406。顆粒406之實例配置在圖12及圖13中說明,如下面更詳細地論述。Referring to FIGS. 10A and 10B , the
參考圖11A及圖11B,說明在圖5B所示及所述之配置中,經切割之微電子器件208黏附至安裝膜400上之黏合材料402。然而,代替嵌入在黏合材料402中之顆粒306,顆粒506包含細長引腳元件形式之鐵磁材料(例如,鐵、鎳、鈷或前述任一者的合金)。此種鐵磁材料可藉由曝露於磁場而被磁化,以呈現具有不同極性之相對端。如圖11A所示,磁化顆粒506可垂直於黏合材料402之主平面定向,且其長度基本上完全含有在黏合材料402之厚度內,與由黏合材料402支撐並黏附至黏合材料之微電子器件208之背面212之實體接觸最小或無實體接觸。黏合材料402之厚度可為例如約2 μm至約50 μm,例如約20 μm。然而,如圖11B所示,在拾取操作期間,拾取工具500之拾取頭502位於目標微電子器件208上方,且拾取面504緊鄰目標微電子器件,且拾取頭502中之真空通道(未展示)被致動。基本上同時地,電磁體形式之能量場源600被激活,以使磁場形式之局部能量場602作用在顆粒506上,磁場602之相似極性及顆粒506面向下朝向磁場602之末端向上排斥顆粒506,以藉由其背面212將目標微電子器件208提昇至黏合劑402上方(為清楚起見放大了距離)。為了增強提昇效果,期望將安裝膜400保持在目標微電子器件208之位置處的固定垂直位置,例如藉由使用靠著安裝膜400之下側置放之能量源600之周邊的周邊真空通道或多個真空通道來防止黏合材料402及安裝膜400之向上移位。在一種實施中,磁場602在目標微電子器件208之下可為恆定且靜止的。在另一實施中,磁場602可固定在目標微電子器件208之下,但磁場被脈衝開啟及關閉以推動及縮回顆粒506。在另一實施中,能量源600可包含多個可單獨致動之電磁體600A至600E (見圖10B),其在目標微電子器件208下之目標區域上相互橫向間隔開。可起始電磁體600A至600E以引起顆粒506之間自一側至另一側,或自微電子器件208周邊至中心,或自中心至周邊之波動,以促進目標微電子器件208自黏合材料402釋放。或者,如圖11B所示,能量場源600可在目標微電子器件208下橫向移動,如箭頭606所示,並根據需要激活。作為另一種選擇,且如圖11B之底部所示,能量源600可為靜止的,但由鐵磁材料覆蓋以屏蔽磁場,但對於橫向可移動之蓋610中之槽形孔608,蓋610可如箭頭612所示來回移動。經考慮,可使用電磁夾具將顆粒506磁化至期望之極性、間隔及定向,且使用夾具將顆粒部分地置放至安裝膜400中,並呈現所期望之圖案,其對應於將要置放在安裝膜上之減薄之器件晶圓200中的微電子器件位置之圖案,隨後將黏合材料402以液體形式抑或作為預成型膜分配至安裝膜400上。或者,黏合材料402可以薄膜形式提供,其中顆粒406被磁化並保持為所需圖案,且黏附膜覆蓋有保護膜,以便在將薄膜形式之黏合材料402施加至安裝膜400之後被剝離。利用此種方法,可優化減薄之器件晶圓200之給定微電子器件位置內的顆粒506之數量及位置,且黏合材料402及安裝膜400之其他區域,例如器件位置及器件位置外部之周邊晶圓區域之間的通道,可能無顆粒506。顆粒406之實例配置在圖12及圖13中說明,如下面更詳細地論述。Referring to FIGS. 11A and 11B , the
圖12及圖13描繪適用於載體結構(例如安裝膜400)上之黏合材料402的顆粒圖案之示意性實例配置。12 and 13 depict schematic example configurations of particle patterns suitable for use in
圖12說明對應於將要設置在安裝膜400上之減薄之器件晶圓200中的微電子器件位置之柵格狀陣列之微電子器件位置之黏合材料段402,其中每個器件位置與黏合材料段402對準地疊加,黏合材料段402可選地由通道210分開(為了清楚而誇大了寬度)。具體參考在圖10A及圖10B以及圖11A及圖11B之實施例中之使用,如圖12所示,分別為磁性形狀記憶合金材料及鐵磁材料形式之顆粒406及506可被圖案化,如圖所示鄰近每個黏合材料段402之周邊且在每個黏合材料段402之中心區域中。此類配置允許上述藉由適當之磁場位置來擴展或移動顆粒及在微電子器件208之周邊附近施加提昇力之能力,在微電子器件之周邊處過量之黏附已被證明係一個問題,同時將提昇力施加至微電子器件208之中心區域以消除微電子器件208中不同部分之間的剪切及彎曲應力。或者,磁場可首先施加至周邊區域,接著施加至中心區域。12 illustrates a segment of
圖13說明對應於將要設置在安裝膜400上之減薄之器件晶圓200中的微電子器件位置之柵格狀陣列之微電子器件位置之黏合材料段402,其中每個器件位置與黏合材料段402對準地疊加,該等段可選地由通道210分開(為了清楚而誇大了寬度)。具體參考在圖10及圖10B以及圖11A及圖11B之實施例中之使用,如圖13所示,分別以磁性形狀記憶合金材料及鐵磁材料之形式的顆粒406及506可被圖案化,如在黏合材料段402之寬度上延伸之平行顆粒行所示,平行行在段之長度上的不同縱向間隔位置處。此類配置允許上述能力藉由適當之磁場激活自黏合材料段402之一端至另一端選擇性地擴展或移動給定行之顆粒,並產生顆粒之脈衝波以自安裝結構提昇微電子器件208。或者,不同的、相鄰的顆粒行406、506可擴展或延伸,接著縮回,以放鬆微電子器件208對黏合材料402之黏合。13 illustrates a segment of
應注意,在圖10及圖10B以及圖11A及圖11B之實施例之上下文中,可最小化每個晶粒位置之顆粒406、506之數量,且選擇圖案以增強微電子器件208下之最有效區域處的提昇力。此外,此等顆粒406、506保留在黏合材料402中,而非潛在地轉移至微電子器件208。It should be noted that in the context of the embodiments of FIGS. 10 and 10B and FIGS. 11A and 11B , the number of
參考圖14,說明用於自安裝膜400拾取微電子器件208之裝置及方法之又一實施例。安裝膜400承載具有嵌入其上之鐵磁顆粒306之黏合材料402。如前所述,藉由將拾取工具500之拾取頭502置放在微電子器件208上並緊靠微電子器件,且激活真空通道(未展示)以將微電子器件208拉靠在拾取面504上,自黏合材料402拾取目標微電子器件208。為了增強顆粒306回應於來自能量源600之磁場形式之能量場602向下拉動黏合材料402並由此拉動安裝膜400之效果,包含非磁性材料並在其中心及拐角處具有支座元件802之支座壓板800緊鄰或接觸目標微電子器件208下之安裝膜400置放,使得磁場602向下拉動安裝膜400之支座元件802之間的部分。在一種實施中,支座壓板可形成或安裝至能量源600之上部表面。可脈動磁場602以自微電子器件208之背面212順序地拉動及釋放黏合材料402並拉伸安裝膜400以減少黏附。支座壓板800可與拾取頭502及能量源600一起在每個各別目標微電子器件208之下移動,或者如圖15所示,支座壓板800可包含支座元件802之陣列,其組態對應於器件晶圓200上之微電子器件位置之陣列,在切割之後自安裝膜400拾取微電子器件。Referring to FIG. 14, yet another embodiment of an apparatus and method for picking up a
參考圖15,支座壓板800'包括位於微電子器件位置之間的通道位置下方之支座元件802。如在圖14之情況下,向顆粒306施加磁場602,將在位於相鄰微電子器件208之通道角之間的相鄰支座元件802之間向下拉動安裝膜400,增強黏合材料402與微電子器件208之背面212之間的分離。此外,磁場602可被激活及去激活,以便拉開安裝膜400,拉伸安裝膜400,並放鬆黏合材料402與微電子器件208之黏合。Referring to FIG. 15, a standoff platen 800' includes a
本文所用術語「基板」係指並包括基礎材料或結構,在其上形成有額外材料。基板可為半導體基板、支撐結構上之基礎半導體層、金屬電極或其上形成有一或多種材料、層、結構或區域之半導體基板。半導體基板上之材料可包括但不限於半導體材料、絕緣材料、導電材料等。基板可為習知之矽基板或包含半導體材料層之其他體基板。如本文所使用,術語「體基板」係指且不僅包括矽晶圓,而且亦包括絕緣體上矽(「SOI」)基板,諸如藍寶石上矽(「SOS」)基板及玻璃上矽(「SOG」)基板、基礎半導體基礎上之矽及其他半導體或光電材料(諸如矽鍺、鍺、砷化鎵、氮化鎵及磷化銦)之磊晶層。基板可為摻雜之或未摻雜的。The term "substrate" as used herein means and includes a base material or structure upon which additional materials are formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate with one or more materials, layers, structures or regions formed thereon. Materials on the semiconductor substrate may include, but are not limited to, semiconductor materials, insulating materials, conductive materials, and the like. The substrate can be a conventional silicon substrate or other bulk substrates including semiconductor material layers. As used herein, the term "bulk substrate" refers to and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates. ) substrates, silicon on the basis of basic semiconductors and epitaxial layers of other semiconductor or optoelectronic materials (such as silicon germanium, germanium, gallium arsenide, gallium nitride and indium phosphide). The substrate can be doped or undoped.
如本文中所使用,術語「微電子器件」係指並包括,作為非限制性實例,半導體晶粒、藉由除了半導體活動之外的其他活動表現出功能性之晶粒、微機電系統(MEM)器件、包含多個晶粒之基板,包括習知晶圓及部分晶圓及如上所述之其他體基板,及包括多於一個晶粒位置之部分晶圓及基板。As used herein, the term "microelectronic device" means and includes, by way of non-limiting examples, semiconductor dies, dies exhibiting functionality by activities other than semiconductor activities, microelectromechanical systems (MEM ) devices, substrates comprising multiple dies, including conventional wafers and portions of wafers and other bulk substrates as described above, and portions of wafers and substrates comprising more than one die site.
如本文中所使用,術語「包含」、「包括」、「含有」、「特徵在於」及其語法等同表述係包含性或開放式術語,其不排除另外的、未列舉的要素或方法動作,而且亦包括更限制性之術語「由…組成」及「基本上由…組成」及其語法等同表述。As used herein, the terms "comprises," "comprising," "comprising," "characterized by," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, non-recited elements or method acts, Also included are the more restrictive terms "consisting of" and "consisting essentially of" and their grammatical equivalents.
如本文中所使用,關於材料、結構、特徵或方法動作之術語「可」表示此類術語預期用於實施本發明之實施例,且此類術語優先於更具限制性之術語「係」使用,以便避免應或必須排除可與其組合使用之其他相容材料、結構、特徵及方法之任何暗示。As used herein, the term "may" with respect to a material, structure, feature, or methodological action indicates that such term is contemplated for practicing an embodiment of the invention and that such term is used in preference to the more restrictive term "is". , in order to avoid any suggestion that other compatible materials, structures, features and methods which may be used in combination therewith should or must be excluded.
如本文中所使用,術語「縱向」、「垂直」、「橫向」及「層位」係指基板(例如,基礎材料、基礎結構、基礎組態等)之主平面,其中或其上形成一或多個結構及/或特徵,且不一定由地球重力場限定。「橫向」或「層位」方向為基本上平行於基板主平面之方向,而「縱向」或「垂直」方向為基本上垂直於基板主平面之方向。基板之主平面由與基板之其他表面相比具有相對較大面積之基板表面限定。As used herein, the terms "longitudinal", "vertical", "transverse" and "level" refer to the principal plane of a substrate (e.g. base material, base structure, base configuration, etc.) in or on which a or multiple structures and/or features, and not necessarily defined by the Earth's gravitational field. A "lateral" or "level" direction is a direction substantially parallel to the principal plane of the substrate, and a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the principal plane of the substrate. The main plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.
如本文中所使用,空間上相對之術語,諸如「在…之下」、「在…下面」、「下部」、「底部」、「在…之上」,「在…上方」、「上部」、「頂部」、「前部」、「後部」、「左」、「右」等,可用於便於描述,以描述如圖所示之一個元件或特徵與另一(些)元件或特徵之關係。除非另外指明,空間相對術語旨在涵蓋除附圖中描繪之定向之外的材料之不同定向。舉例而言,若附圖中之材料係倒置的,則描述為在其他元件或特徵之「上方」或「之上」或「上面」或「頂部」之元件將定向在其他元件或特徵之「下方」或「之下」或「下面」或「底部」。因此,術語「上方」可包括上方及下方之方向,此取決於使用該術語之上下文,此對於熟習此項技術者而言係顯而易見的。材料可以其他方式定向(例如,旋轉90度、倒置、翻轉),且本文中使用之空間相對描述符各別地解釋。As used herein, spatially relative terms such as "below", "beneath", "lower", "bottom", "above", "above", "upper" , "top", "front", "rear", "left", "right", etc. may be used for convenience of description to describe the relationship of one element or feature to another element or feature(s) as shown . Unless otherwise indicated, spatially relative terms are intended to encompass different orientations of materials in addition to the orientation depicted in the figures. For example, if material in a drawing is turned upside down, elements described as "above" or "on" or "above" or "top" other elements or features would then be oriented "below" the other elements or features " or "under" or "below" or "bottom". Thus, the term "above" can include an orientation of above as well as below, depending on the context in which the term is used, as will be apparent to those skilled in the art. Materials can be oriented in other ways (eg, rotated 90 degrees, inverted, turned over), and the spatially relative descriptors used herein are interpreted separately.
如本文中所使用,單數形式「一個」、「一種」及「該」亦旨在包括複數形式,除非上下文另外明確指出。As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.
如本文中所使用,術語「經組態以」及「組態」係指有助於以預定方式操作結構及裝置中之一或多者的至少一個結構及至少一個裝置中之一或多者的尺寸、形狀、材料組成、定向及配置。As used herein, the terms "configured and" and "configured" refer to one or more of at least one structure and at least one device that facilitates the operation of one or more of the structures and devices in a predetermined manner size, shape, material composition, orientation and configuration.
如本文中所使用,關於給定參數、特性或條件之術語「基本上」係指且包括達到熟習此項技術者將理解之以一定程度之變化(諸如在可接受之製造公差內)滿足給定參數、特性或條件之程度。舉例而言,取決於基本上滿足之特定參數、特性或條件,參數、特性或條件可滿足至少90.0%、滿足至少95.0%、滿足至少99.0%或甚至滿足至少99.9%。As used herein, the term "substantially" with respect to a given parameter, characteristic or condition means and includes such that a person skilled in the art will understand that the given parameter, characteristic or condition is met with a degree of variation, such as within acceptable manufacturing tolerances. The extent to which a parameter, characteristic or condition is specified. For example, depending on the particular parameter, characteristic or condition that is substantially satisfied, the parameter, characteristic or condition may be satisfied at least 90.0%, at least 95.0%, at least 99.0% or even at least 99.9%.
如本文中所使用,關於特定參數之數值之「約」或「大約」包括熟習此項技術者將理解之該數值及該數值之方差度在該特定參數之可接受公差內。舉例而言,關於數值之「約」或「大約」可包括在數值之90.0%至110.0%範圍內之另外之數值,諸如在數值之95.0%至105.0%範圍內、在數值之97.5%至102.5%範圍內、在數值之99.0%至101.0%範圍內、在該數值之99.5%至100.5%之範圍內,或在該數值之99.9%至100.1%之範圍內。As used herein, "about" or "approximately" with respect to a value of a particular parameter includes those skilled in the art will understand that the value and the degree of variance of the value are within acceptable tolerances for the particular parameter. For example, "about" or "approximately" with respect to a value may include other values within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0% of the value, within the range of 97.5% to 102.5% of the value %, within the range of 99.0% to 101.0% of the value, within the range of 99.5% to 100.5% of the value, or within the range of 99.9% to 100.1% of the value.
如本文中所使用,術語「層」及「膜」意指並包括存在於結構上之材料之層、片或塗層,該層或塗層在材料之各部分之間可為連續或不連續的,且可為保形或非保形的,除非另外指明。As used herein, the terms "layer" and "film" mean and include a layer, sheet, or coating of material present on a structure, which layer or coating may be continuous or discontinuous between portions of the material , and may be conformal or non-conformal unless otherwise indicated.
如本文中所使用,術語「包含」、「包括」、「含有」、「特徵在於」及其語法等同表述為包含步驟或開放式術語,其不排除另外的、未列舉的要素或方法步驟,而且亦包括更限制性之術語「由…組成」及「基本上由…組成」及其語法等同表述。As used herein, the terms "comprises," "comprising," "comprising," "characterized by," and their grammatical equivalents are expressions comprising steps or open-ended terms that do not exclude additional, non-recited elements or method steps, Also included are the more restrictive terms "consisting of" and "consisting essentially of" and their grammatical equivalents.
如本文中所使用,關於材料、結構、特徵或方法動作之術語「可」表示此類術語預期用於實施本發明之實施例,且此類術語優先於更具限制性之術語「係」使用,以便避免應或必須排除可與其組合使用之其他相容材料、結構、特徵及方法之任何暗示。As used herein, the term "may" with respect to a material, structure, feature, or methodological action indicates that such term is contemplated for practicing an embodiment of the invention and that such term is used in preference to the more restrictive term "is". , in order to avoid any suggestion that other compatible materials, structures, features and methods which may be used in combination therewith should or must be excluded.
如此處所使用,術語「記憶體器件」意謂且包括表現出儲存功能,但不一定限於儲存功能之微電子器件。換言之,且僅作為實例,術語「記憶體器件」意謂且不僅包括習知記憶體(例如,習知揮發性記憶體,諸如習知動態隨機存取記憶體(DRAM);習知非揮發性記憶體(諸如習知NAND記憶體),而且亦包括專用積體電路(ASIC)(例如,晶片上系統(SoC)),組合邏輯與記憶體之微電子器件及併入記憶體之圖形處理單元(GPU)。As used herein, the term "memory device" means and includes a microelectronic device that exhibits, but is not necessarily limited to, a memory function. In other words, and by way of example only, the term "memory device" means and does not only include conventional memory (eg, conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile Memory (such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units incorporated into memory (GPU).
在此使用諸如「第一」、「第二」等表示法對元件之任何引用並不限制此等元件之數量或順序,除非明確說明此種限制。相反,此等表示法在此可用作區分兩個或多個元件或一個元件之多個實例之方便方法。因此,對第一及第二元件之引用並不意味著在那裏可僅使用兩個元件,或者第一元件必須以某種方式在第二元件之前。此外,除非另有說明,一組元件可包含一或多個元件。Any reference to an element herein using a notation such as "first," "second," etc. does not limit the quantity or order of such elements, unless such a limitation is expressly stated. Rather, these notations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, references to first and second elements do not imply that only two elements can be used there or that the first element must precede the second element in some way. Also, unless stated otherwise, a set of elements may comprise one or more elements.
在實施例中,一種取置裝置包含:載體結構,用於在其上支撐經切割微電子器件;包括拾取頭之拾取工具,拾取頭可在支撐在載體結構上之經切割微電子器件之各別位置上方移動;及位於載體結構下方之能量源,其經組態及定位以發射與拾取頭基本對準之能量場,以吸引或排斥載體結構及支撐在其上之經切割微電子器件之間的材料顆粒。In an embodiment, a pick-and-place apparatus comprises: a carrier structure for supporting thereon a diced microelectronic device; a pick-up tool including a pick-up head capable of placing a pick-and-place on each of the diced microelectronic devices supported on the carrier structure. and an energy source positioned below the carrier structure configured and positioned to emit an energy field substantially aligned with the pick-up head to attract or repel the carrier structure and diced microelectronic devices supported thereon material particles between.
在實施例中,一種方法包含:提供載體結構,該載體結構具有黏附至其上表面之經切割微電子器件;將拾取工具之拾取頭定位在載體結構上之選定目標微電子器件上方;用拾取工具起始目標微電子器件之向上拾取。基本上在起始向上拾取之同時,激活能量源,以自載體結構下方發射能量場,並基本上與拾取頭對準,以執行以下操作之一:向上排斥目標微電子器件遠離載體結構,或基本上在目標微電子器件下方吸引載體結構之一或多個部分向下遠離微電子器件。In an embodiment, a method comprises: providing a carrier structure having a diced microelectronic device adhered to an upper surface thereof; positioning a pick head of a pick-up tool over a selected target microelectronic device on the carrier structure; The tool initiates an upward pick of the target microelectronic device. substantially simultaneously with the initiation of upward pick-up, activating the energy source to emit an energy field from below the carrier structure and substantially aligned with the pick-up head to either: repel the target microelectronic device upwardly away from the carrier structure, or One or more portions of the carrier structure are attracted downwardly and away from the microelectronic device substantially below the target microelectronic device.
在實施例中,一種方法包含:使用具有嵌入其中之顆粒之黏附膜,藉由承載積體電路之器件晶圓之作用表面將器件晶圓黏附至載體晶圓;自器件晶圓之背側減薄器件晶圓;藉由器件晶圓之背側將減薄之器件晶圓黏附至載體結構,以形成總成;在該總成附近施加能量場以使該等顆粒施加向上之原動力以將該載體晶圓與該器件晶圓分離,並將該載體晶圓自該器件晶圓移除。In an embodiment, a method comprises: adhering a device wafer to a carrier wafer by an active surface of the device wafer carrying integrated circuits using an adhesive film having particles embedded therein; Thin device wafer; adhering the thinned device wafer to a carrier structure by the backside of the device wafer to form an assembly; applying an energy field near the assembly so that the particles exert an upward motive force to the The carrier wafer is separated from the device wafer, and the carrier wafer is removed from the device wafer.
雖然已經結合附圖描述了某些說明性實施例,但熟習此項技術者將認識到並理解,本發明所涵蓋之實施例不限於本文明確說明及描述之彼等實施例。相反,在不脫離本發明所包含之實施例之範疇的情況下,可對本文描述之實施例進行許多添加、刪除及修改,諸如下文所主張之彼等實施例,包括法律等同表述。此外,來自一個所揭示實施例之特徵可與另一所揭示實施例之特徵組合,同時仍然涵蓋於本發明之範疇內。While certain illustrative embodiments have been described in conjunction with the drawings, those skilled in the art will recognize and understand that the embodiments encompassed by the invention are not limited to those specifically illustrated and described herein. On the contrary, many additions, deletions and modifications may be made to the embodiments described herein, such as those claimed below, including legal equivalents, without departing from the scope of the embodiments encompassed by this invention. Furthermore, features from one disclosed embodiment may be combined with features of another disclosed embodiment and still be within the scope of the invention.
100:載體晶圓
102:黏合材料
104:主表面
106:顆粒
108:邊緣
200:器件晶圓
202:作用表面
204:積體電路
206:背面
208:微電子器件
210:通道
212:背面
302:材料
306:顆粒
400:安裝膜
402:黏合材料
404:膜框架
406:顆粒
500:工具
502:拾取頭
504:面
506:顆粒
510:流體分配通道
512:流體移除真空通道
600:能量源/能量場源/磁場源
600A-600E:電磁體
602:磁場/能量場
604:真空通道/箭頭
608:槽形孔
610:蓋
612:箭頭
700:卷軸總成
702:凸緣
704:轂
706:分配帶
706A:分配帶
706B:分配帶
706C:分配帶
708:凹穴
710:表面
712:覆蓋帶
714:黏合材料
716:底面
718:排出孔
720:基座
800:支座壓板
800':支座壓板
802:支座元件
100: carrier wafer
102: Adhesive material
104: main surface
106: particles
108: edge
200: device wafer
202: Action surface
204: Integrated circuit
206: back
208: Microelectronic devices
210: channel
212: back
302: material
306: particles
400: Install the film
402: Adhesive material
404: Membrane frame
406: particles
500: tools
502: pick up head
504: face
506: particles
510: Fluid distribution channel
512: Fluid removal vacuum channel
600: Energy Source/Energy Field Source/
圖1為在晶粒拾取期間自黏附膜剝離之不均勻晶粒之顯微照片;Figure 1 is a photomicrograph of an inhomogeneous die peeled from an adhesive film during die pick-up;
圖2為來自不成功之晶粒拾取之安裝膜上之斷裂晶粒之顯微照片;Figure 2 is a photomicrograph of a fractured die on a mounting film from an unsuccessful die pick;
圖3為半導體晶粒中應力引起之裂紋之顯微照片;Figure 3 is a photomicrograph of stress-induced cracks in semiconductor crystal grains;
圖4A至圖4D示意性地說明根據本發明之方法及裝置之實施例,該方法及裝置用於製備用於切割晶圓、將晶圓切割為半導體晶粒,及在晶粒拾取期間,使用自安裝膜釋放之能量場輔助晶粒自經切割之晶圓拾取半導體晶粒;4A to 4D schematically illustrate an embodiment of a method and apparatus according to the present invention for preparing wafers for dicing, dicing the wafers into semiconductor dies, and during die pick-up using The energy field released from the mounting film assists the die to pick up the semiconductor die from the diced wafer;
圖5A至圖5C示意性地說明根據本發明之方法及裝置之另一實施例,該方法及裝置用於製備用於切割晶圓、將晶圓切割為半導體晶粒,及在晶粒拾取期間,使用自安裝膜釋放之能量場輔助晶粒自經切割之晶圓拾取半導體晶粒;5A to 5C schematically illustrate another embodiment of a method and apparatus according to the present invention for preparing wafers for dicing, dicing wafers into semiconductor dies, and during die pick-up. , using the energy field released from the mounting film to assist the die in picking up the semiconductor die from the diced wafer;
圖6A至圖6C示意性地說明根據本發明之用於在器件晶圓減薄之後自器件晶圓能量場輔助釋放載體晶圓之方法及裝置的實施例;6A-6C schematically illustrate an embodiment of a method and apparatus for energy field assisted release of a carrier wafer from a device wafer after device wafer thinning according to the present invention;
圖7為根據本發明之一或多個實施例組態以用於在晶粒拾取期間能量場輔助釋放晶粒之凹穴中載運帶承載半導體晶粒之卷軸的透視圖;7 is a perspective view of a spool carrying a semiconductor die on a carrier tape in a cavity configured for energy field assisted release of the die during die pick-up in accordance with one or more embodiments of the present invention;
圖8A、圖8B及圖8C為適用於結合在圖7所示類型之帶中用於在晶粒拾取期間半導體晶粒之能量場輔助釋放之凹穴之不同實施例的截面圖;8A, 8B and 8C are cross-sectional views of different embodiments of pockets suitable for incorporation in a tape of the type shown in FIG. 7 for energy field assisted release of semiconductor die during die pick-up;
圖9為用於在晶粒拾取期間自載體結構清潔及釋放半導體晶粒之裝置的示意性側視圖;9 is a schematic side view of an apparatus for cleaning and releasing semiconductor die from a carrier structure during die pick-up;
圖10A及圖10B示意性地說明用於自載體結構進行能量場輔助晶粒拾取之方法及裝置,該載體結構使用嵌入在載體結構上之黏附膜中之磁性形狀記憶顆粒,經切割之半導體晶粒黏附至該黏附膜上;10A and 10B schematically illustrate a method and apparatus for energy field assisted die picking from a carrier structure using magnetic shape memory particles embedded in an adhesive film on the carrier structure, diced semiconductor die. particles adhere to the adhesive film;
圖11A及圖11B示意性地說明用於自載體結構進行能量場輔助晶粒拾取之方法及裝置,該載體結構使用嵌入在載體結構上之黏附膜中之磁化引腳元件,經切割之半導體晶粒黏附至該黏附膜上;11A and 11B schematically illustrate a method and apparatus for energy field assisted die picking from a carrier structure using magnetized lead elements embedded in an adhesive film on the carrier structure, diced semiconductor die. particles adhere to the adhesive film;
圖12及圖13示意性地說明可黏附半導體晶粒之載體結構上之黏附膜之片段的頂部正視圖,其說明圖10A及圖10B之磁性形狀記憶合金顆粒及在圖11A及圖11B之方法及裝置中使用的黏附膜中之引腳元件形式之磁化顆粒的不同實例置放;12 and 13 schematically illustrate top elevation views of fragments of an adhesive film on a carrier structure to which semiconductor die can be adhered, illustrating the magnetic shape memory alloy particles of FIGS. 10A and 10B and the method of FIGS. 11A and 11B and placement of different examples of magnetized particles in the form of lead elements in the adhesive film used in the device;
圖14為根據本發明之實施例之在晶粒拾取期間位於目標晶粒下方且與拾取頭對準的可移動支座壓板之示意圖,該支座壓板用於增強安裝膜之黏附膜自目標晶粒之能量場輔助釋放;及14 is a schematic diagram of a movable standoff platen positioned under a target die and aligned with a pickup head during die picking to enhance adhesion of the mounting film from the target die in accordance with an embodiment of the present invention. Energy field assisted release of particles; and
圖15為根據本發明之另一實施例之晶圓級支座壓板之一部分的示意圖,該晶圓級支座壓板位於用於晶粒拾取之目標晶粒下方,該支座壓板用於增強安裝膜之黏附膜自目標晶粒之能量場輔助釋放。15 is a schematic diagram of a portion of a wafer-level standoff platen under a target die for die pick-up for enhanced mounting in accordance with another embodiment of the present invention. The adhesive film of the membrane is released assisted by the energy field of the target grain.
202:器件晶圓 202: Device wafer
204:積體電路 204: Integrated circuit
208:微電子器件 208: Microelectronic devices
212:背面 212: back
302:材料 302: material
306:顆粒 306: particles
400:安裝膜 400: Install the film
402:黏合材料 402: Adhesive material
404:膜框架 404: Membrane frame
500:工具 500: tools
502:拾取頭 502: pick up head
504:面 504: face
600:能量源/能量場源/磁場源 600: Energy Source/Energy Field Source/Magnetic Field Source
602:磁場/能量場 602: Magnetic Field/Energy Field
Claims (37)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202163161561P | 2021-03-16 | 2021-03-16 | |
US63/161,561 | 2021-03-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202238800A true TW202238800A (en) | 2022-10-01 |
Family
ID=83245761
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110120544A TW202238800A (en) | 2021-03-16 | 2021-06-07 | Apparatus and methods for energy field-assisted release of microelectronic devices from carrier structures |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN115083945A (en) |
TW (1) | TW202238800A (en) |
-
2021
- 2021-06-07 TW TW110120544A patent/TW202238800A/en unknown
- 2021-06-16 CN CN202110663856.7A patent/CN115083945A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
CN115083945A (en) | 2022-09-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102203790B1 (en) | Small or ultra-thin individual component placement | |
TW529095B (en) | Method of dividing wafer and manufacture of semiconductor device | |
US8080121B2 (en) | Method of bonding, thinning, and releasing wafer | |
TW493236B (en) | Method for manufacturing semiconductor devices | |
KR101617316B1 (en) | A method for bonding / de-bonding of device wafer and carrier wafer and apparatus for bonding/de-bonding | |
JP2008103494A (en) | Fixed jig, and method and apparatus for picking up chip | |
JP2008103493A (en) | Method and apparatus for picking up chip | |
US10679967B2 (en) | Systems enabling lower-stress processing of semiconductor device structures and related structures | |
TW201717266A (en) | Procedure of processing a workpiece and an apparatus designed for the procedure | |
US10269782B2 (en) | Apparatuses and methods for forming die stacks | |
TWI354325B (en) | ||
US20080044985A1 (en) | Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods | |
TW202238800A (en) | Apparatus and methods for energy field-assisted release of microelectronic devices from carrier structures | |
US11699677B2 (en) | Die-to-wafer bonding utilizing micro-transfer printing | |
TWI719161B (en) | Wafer processing method | |
JP2013219245A (en) | Method for manufacturing semiconductor device | |
TWI781582B (en) | Methods of cleaning and handling microelectronic devices and related tooling and assemblies | |
CN114582774A (en) | Apparatus and method for physical transfer of fragile microelectronic components |