TW202236644A - Front end integrated circuits incorporating differing silicon-on-insulator technologies - Google Patents

Abstract

SOI-based technology platforms are described that provide fully integrated front end integrated circuits (FEICs) that include switches, low-noise amplifiers (LNAs), and power amplifiers (PAs). The PAs can be built in a thick film region of the integrated circuit, resulting in a partially depleted silicon-on-insulator (PDSOI) PA, and the switches and LNAs can be built in a thin film region of the integrated circuit, resulting in fully depleted silicon-on-insulator (FDSOI) switches and LNAs. The resulting fully integrated FEIC includes PDSOI PAs with FDSOI switches and LNAs. Passive components can be built in the thick film region, the thin film region, or both regions.

Description

Front-end integrated circuits combining different silicon-on-insulator technologies

The present invention generally relates to front-end integrated circuits for radio frequency applications.

A front-end module (FEM) is an internal modeling group integrated with various functional components in a wireless front-end circuit for a wireless device. The front-end modules can be configured to handle various wireless protocols such as broadband cellular technologies (e.g., 3G, 4G, 5G, Long Term Evolution (LTE), etc.), wireless network connectivity technologies (e.g., Wi-Fi) , radio frequency (RF) signals from short-range wireless technologies (eg, BLUETOOTH®) and global positioning system (GPS) technology. Front-end modules usually include circuits and electrical components sufficient to receive and transmit radio frequency signals between the antenna and a digital baseband system. A particular FEM may include all the filters, low noise amplifiers (LNAs) and (several ) down-converting mixer. The FEM may also include a power amplifier (PA) and other circuitry for a transmitter that processes signals for transmission over the antenna. The FEM can be a surface mount technology (SMT) module, a multi-chip module (MCM), or the like. The FEM may include PA blocks, LNA blocks, input and output matching, MIPI standard digital control blocks, filters, duplexers, multiplexers, antenna switches, band selection switches, and the like. A front-end integrated circuit (FEIC) is a single semiconductor die that includes the functionality of a FEM.

According to some embodiments, the invention relates to a front-end integrated circuit comprising: a substrate; an insulator layer on top of the substrate; and a semiconductor layer on top of the insulator layer , the semiconductor layer forms a thin film region and a thick film region, the thin film region includes one or more fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) devices and one or more FDSOI switch devices, the thick The membrane region includes one or more partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) devices.

In some embodiments, the insulating layer is at least 100 nm thick. In some embodiments, the semiconductor layer in the thin film region is at least 5 nm thick and less than or equal to 50 nm thick. In some further embodiments, the semiconductor layer in the thick film region is at least about 50 nm thick and less than or equal to 180 nm thick.

In some embodiments, the insulating layer is a buried oxide layer. In some embodiments, the semiconductor layer in the thin film region is 1/4 the length of a gate of one or more FDSOI LNA devices. In some embodiments, the front-end IC further includes one or more passive devices built into the thin-film region of the semiconductor layer. In some embodiments, the front-end IC further includes one or more passive devices built into the thick film region of the semiconductor layer.

In some embodiments, localized thinning is used to form thin film regions of the semiconductor layer. In some embodiments, selective epitaxial growth is used to form thick film regions of the semiconductor layer.

According to several embodiments, the invention relates to a method for manufacturing a front-end integrated circuit. The method includes forming an insulating layer on top of a substrate. The method also includes forming a semiconductor layer on top of the insulating layer. The method also includes building a fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) device into the semiconductor layer. The method also includes embedding an FDSOI switching device in the semiconductor layer. The method also includes increasing a thickness of a portion of the semiconductor layer to form a thick film region of the semiconductor layer. The method also includes embedding a portion of a depleted silicon-on-insulator (PDSOI) power amplifier (PA) device in the thick film region of the semiconductor layer such that the FDSOI LNA device and the FDSOI switch device are in a thin film of the semiconductor layer region and the PDSOI PA device is in the thick film region.

In some embodiments, the insulating layer is at least about 100 nm thick. In some embodiments, the thin film region of the semiconductor layer is at least about 5 nm thick and less than or equal to about 50 nm thick. In some further embodiments, the thick film region of the semiconductor layer is at least about 50 nm thick and less than or equal to 180 nm thick.

In some embodiments, the thin film area of the semiconductor layer is 1/4 of the length of a gate of the FDSOI LNA device. In some embodiments, the method further includes embedding one or more passive devices in the thin film region of the semiconductor layer. In some embodiments, the method further includes building one or more passive devices in the thick film region of the semiconductor layer. In some embodiments, increasing the thickness includes using selective epitaxial growth.

According to several embodiments, the invention relates to a method for manufacturing a front-end integrated circuit. The method includes forming an insulating layer on top of a substrate. The method also includes forming a semiconductor layer on top of the insulating layer. The method also includes building a portion of a depleted silicon-on-insulator (PDSOI) power amplifier (PA) device into the semiconductor layer. The method also includes reducing a thickness of a portion of the semiconductor layer to form a thin film region of the semiconductor layer. The method also includes building a fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) device in the thin film region of the semiconductor layer. The method also includes embedding an FDSOI switching device in the thin film region of the semiconductor layer such that the PDSOI PA device is in a thick film region of the semiconductor layer and the FDSOI LNA device and the FDSOI switching device are in the semiconductor layer in the film region.

In some embodiments, the insulating layer is at least about 100 nm thick. In some embodiments, the thin film region of the semiconductor layer is at least about 5 nm thick and less than or equal to about 50 nm thick. In some further embodiments, the thick film region of the semiconductor layer is at least about 50 nm thick and less than or equal to 180 nm thick.

In some embodiments, the thin film area of the semiconductor layer is 1/4 of the length of a gate of the FDSOI LNA device. In some embodiments, the method further includes embedding one or more passive devices in the thin film region of the semiconductor layer. In some embodiments, the method further includes building one or more passive devices in the thick film region of the semiconductor layer. In some embodiments, reducing the thickness includes using localized thinning.

According to several embodiments, the invention relates to a method for manufacturing a front-end integrated circuit. The method includes forming an insulating layer on top of a substrate. The method also includes forming a semiconductor layer having a first thickness on top of the insulating layer. The method also includes increasing a thickness of a portion of the semiconductor layer to form a thick film region of the semiconductor layer, and the other portion of the semiconductor layer having the first thickness is a thin film region. The method also includes building a high voltage analog circuit into the thick film region. The method also includes building a low voltage analog circuit into the thin film region.

In some embodiments, the insulating layer is at least about 100 nm thick. In some embodiments, the thin film region of the semiconductor layer is at least about 5 nm thick and less than or equal to about 50 nm thick. In some further embodiments, the thick film region of the semiconductor layer is at least about 50 nm thick and less than or equal to 180 nm thick.

In some embodiments, the high voltage analog circuit includes a low dropout voltage regulator. In some embodiments, the high voltage analog circuit includes a high voltage power amplifier. In some embodiments, the method further includes building digital circuitry into the thin film region.

According to several embodiments, the invention relates to a method for manufacturing a front-end integrated circuit. The method includes forming an insulating layer on top of a substrate. The method also includes forming a semiconductor layer having a first thickness on top of the insulating layer. The method also includes reducing a thickness of a portion of the semiconductor layer to form a thin film region of the semiconductor layer, and the other portion of the semiconductor layer having the first thickness is a thick film region. The method also includes embedding a radio frequency (RF) device in the thick film region. The method also includes building analog or digital circuitry into the film region.

In some embodiments, the insulating layer is at least about 100 nm thick. In some embodiments, the thin film region of the semiconductor layer is at least about 5 nm thick and less than or equal to about 50 nm thick. In some further embodiments, the thick film region of the semiconductor layer is at least about 50 nm thick and less than or equal to 180 nm thick.

In some embodiments, the RF device in the thick film region includes a power amplifier (PA) device. In some further embodiments, the PA device includes a portion of a depleted silicon-on-insulator (PDSOI) PA device.

In some embodiments, the digital circuit includes logic gates.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, the disclosed embodiments may be practiced in a manner that achieves or optimizes one advantage or group of advantages as taught herein but not necessarily achieves other advantages as may be taught or implied herein.

Cross References to Related Applications

This application claims priority to U.S. Provisional Application No. 63/112,951, filed November 12, 2020, and entitled "FRONT END INTEGRATED CIRCUITS INCORPORATING DIFFERING SILICON-ON-INSULATOR TECHNOLOGIES," the entire contents of which are incorporated by reference are expressly incorporated herein.

Headings, if any, are provided herein for convenience only and do not necessarily affect the scope or meaning of claimed subject matter. overview

A front-end integrated circuit (FEIC) is a single semiconductor die that includes the functionality of a front-end module (FEM). In order to meet the increasing demands for higher performance, smaller size and lower cost, it would be desirable to develop a technology platform for a FEIC. Typically, analog circuits drive the implementation of chips used in FEICs, including components such as low-noise amplifiers (LNAs), switches, power amplifiers (PAs), passive devices, analog circuits (e.g., level shifters, summing devices, current mirrors, etc.), digital circuits (eg, logic gates), voltage regulators (eg, low dropout regulators), charge pumps, and the like. A fully integrated radio frequency (RF) FEIC, as the term is used herein, combines elements for both transmission and reception in a single die. These components include PAs, LNAs, and switches, and may include suitable passives, analog and digital circuits, voltage regulators, and the like.

Promising approaches for producing fully integrated RF FEICs include silicon-on-insulator (SOI) processing techniques. SOI is the fabrication of silicon semiconductor devices in a layered silicon-insulator-silicon substrate layer to reduce parasitic capacitance within the device, thereby improving performance. SOI processing techniques can enable improved characteristics of RF FEICs (eg, high bandwidth, low noise figure (NF) LNA performance, high linearity, power efficiency, small package footprint, low insertion loss, etc.). SOI can be distinguished from bulk processing technologies that include doped silicon wells extending deep into the substrate rather than stopping at an insulating layer above the substrate layer. Bulk transistors or devices include devices in which the source and drain are built into a silicon substrate and dopants are added to the substrate to tune its conductive properties. As device dimensions shrink (eg, below about 28 nm), bulk transistors become more complex, and it is advantageous to construct transistor systems using SOI technology.

SOI structures include a silicon film (eg, crystalline silicon) separated from a bulk substrate by a thin insulating layer (eg, buried oxide or BOX). The BOX layer is configured to improve isolation, reduce short channel effects, reduce leakage current, improve switching speed, etc. due at least in part to smaller drain body capacitance. In SOI wafers, the insulating layer (insulator) is usually a thermal silicon oxide (SiO2) layer, and the substrate is a silicon wafer. Depending on the type of application, the thickness of the silicon film can vary (eg, from less than about 50 nm to tens of microns). Likewise, the thickness of the BOX can vary depending on the application (eg, from tens of nanometers to microns). SOI manufacturing technologies include separation by implanted oxygen (SIMOX), bond and etch-back SOI (BESOI), epitaxial layer transfer (ELTRAN®), NANOCLEAVE®, SMART CUT ™ et al.

SOI technology can be implemented with Complementary Metal Oxide Semiconductor (CMOS). SOI CMOS involves building metal-oxide-semiconductor field-effect transistors (MOSFETs) on thin layers of semiconductors, such as silicon or germanium. The thin layer of semiconductor is separated from the substrate by an insulating layer (eg, buried oxide) to electrically isolate the device from the underlying semiconductor substrate and from each other. The thickness of the insulating layer of an SOI device can be anywhere between about 5 nm and about 400 nm, and the thickness of the semiconductor film can be anywhere between about 5 nm and about 240 nm.

MOSFETs on an SOI wafer include a channel depletion layer between the source and drain. Depending on the extent of the thickness of the channel depletion layer compared to the silicon film, SOI devices can be classified into two categories: partially depleted SOI (PDSOI) devices and fully depleted SOI (FDSOI) devices. PDSOI devices include devices in which the silicon film is thicker than the maximum gate depletion width and the device exhibits a floating body effect. FDSOI devices include devices where the silicon film is thin enough to deplete the entire film before reaching a critical condition.

FDSOI devices consist of an ultra-thin insulating layer (buried oxide or BOX) positioned on top of a substrate, and a very thin silicon film used to form a transistor channel. FDSOI devices typically use undoped or a lightly doped channel. Typically, the thin film silicon layer is between about 5 nm and about 50 nm thick, or typically about 1/4 of the gate length. Additionally, the insulating BOX layer can be thick (eg, between about 100 nm and about 400 nm) or it can be ultra-thin (eg, between about 5 nm and about 50 nm). For FDSOI devices, the silicon layer under the gate insulating layer is thin enough that it is completely depleted of mobile charge carriers, so the device is "fully depleted." In other words, during the switching of the FDSOI device from the off-state to the on-state, the depletion region reaches the buried oxide.

In FDSOI devices, the semiconductor film is so thin that the depletion region covers the entire film. In FDSOI devices, the gate oxide (GOX) supports less depletion charge than bulk devices, therefore, an increase in inversion charge occurs resulting in higher switching speeds. The depletion charge is suppressed by BOX limiting induced depletion capacitance and hence the substantial reduction in threshold swing, allowing the FDSOI MOSFET to operate at lower gate bias resulting in lower power operation.

Compared to FDSOI devices, PDSOI devices include a thicker silicon layer on top of the BOX layer. Typically, the top silicon layer is between about 50 nm and about 180 nm thick. The silicon below the channel is partially depleted of mobile charge carriers, so the resulting device is "partially depleted". Typically, the BOX layer is between about 100 nm and about 400 nm thick.

CMOS technology is one of the most promising candidates for fully integrating FEIC due to its high integration capability and lower cost. Typically, the most challenging devices to construct using CMOS technology are high power PA devices, which traditionally use laterally diffused MOSFETs (LDMOS) or extended drain MOSFETs (EDMOS) for high power applications at low frequencies. LDMOS and EDMOS PAs are generally easier to build using bulk or thick-film SOI technology. However, difficulties arise when the device size is small (eg, about 28 nm or smaller). For example, because the silicon film is really thin, fabrication typically requires etching through the BOX layer on the wafer. Thus, the resulting PA becomes comparable to a thick film or a bulk device rather than an FDSOI device. Existing CMOS technologies, whether bulk CMOS, thick-film SOI CMOS or thin-film SOI CMOS, have disadvantages in terms of integrating switches and LNAs with LDMOS PAs, or higher costs when integrating these components.

Accordingly, to address these and other issues, an SOI-based technology platform that provides a fully integrated FEIC including switches, LNAs, and PAs is described herein. PAs can lead to PDSOI PAs by being built in a thick film region of the IC, and switches and LNAs can lead to FDSOI switches and LNAs by being built in a thin film region of the IC. The resulting fully integrated FEIC includes PDSOI PA and FDSOI switches and LNA. Passive components can be built into thick film regions, thin film regions, or both. In some implementations, a FEIC includes one or more power amplifiers in the thick film region and RF circuitry in the thin film region. In some implementations, a FEIC includes high voltage analog circuits in thick film regions and low power analog circuits in thin film regions. In particular implementations, a FEIC includes an RF device implemented in the thick film region and analog and/or digital circuitry implemented in the thin film region.

Attempts to build a fully integrated FEIC have included building the devices (PA, LNA, switches) using bulk technology or using PDSOI technology. Attempts have also included building bulk LDMOS PAs (for example, by removing the BOX layer) and FDSOI LNAs and switches. Attempts have also included embedding PDSOI LDMOS PA and LDMOS LNA in a thick film region and embedding switches in a locally thinned thin film region.

Contrary to these attempts, disclosed herein is a fully integrated FEIC with FDSOI switches and LNAs in addition to PDSOI PAs. In the disclosed embodiments, contrary to the above attempts, the BOX layer is not removed. Alternatively, the switch and LNA are built in a thin film region and the PA is built in a thick film region. This can be done by starting from a thin film, building the switches and LNAs, building up a thick film region (e.g. using selective epitaxial growth or SEG), and building the PA into the built up thick film region . This can also be done by starting from a thick film, building the PA into the thick film region, using local thinning to create a thin film region, and building the switch and LNA into the formed thin film region. This can also be done by making a BOX layer and a thin film layer, increasing the thickness of a part of the thin film region to create a thick film region, and then building the FDSOI LNA and switching device into the thin film region and the PDSOI PA device into the thick film completed in the area. This can also be done by making a BOX layer and a thick film layer, reducing the thickness of a part of the thick film region to create a thin film region, and then building the PDSOI PA device into the thick film region and the FDSOI LNA and switching device Finished in the thin film area.

Thus, the disclosed FEIC is a fully integrated CMOS front-end integrated circuit with improved performance and lower cost. Some embodiments of the resulting structures of the disclosed FEICs include a thin film region with one or more FDSOI switches and one or more FDSOI LNAs and a thick film with one or more PDSOI PAs (eg, LDMOS PA or EDMOS PA) area. In the disclosed FEIC, passive components can be built in the thick film region (with the PA), the thin film region (with the switch and the LNA), or both. In some embodiments, the disclosed FEIC includes one or more devices in the thick film region that form a high voltage analog circuit, which may include a high voltage power amplifier and/or low dropout voltage regulator. In some embodiments, the disclosed FEIC includes an RF device (eg, a PA) in the thick film region and low voltage analog and/or digital circuits in the thin film region.

Advantageously, the disclosed FEIC reduces parasitics of the PA relative to bulk implementations. This results in higher active device performance for FEIC and other ultimate performance advantages. Another advantage of the disclosed FEIC is that no part of the buried oxide layer needs to be removed to build the device (eg, PA) into the thick film region. Thus, the integrated circuit in the thick film region may have a thicker silicon film or layer relative to a particular implementation of the integrated circuit with the FDSOI PA or PA in a thin film region. Thus, in the thick film region, there is a more robust performance of the active device and a higher performance of the passive device. This improvement reveals the overall performance of the FEIC. Front-end integrated circuit structure

FIG. 1A illustrates a fully integrated front-end integrated circuit 100a (FEIC) fabricated using silicon-on-insulator (SOI) processing technology. FEIC 100a includes a substrate 102 (e.g., a handle wafer) and an insulating layer 104 (e.g., buried oxide (BOX)) on top of substrate 102, and an active device layer on top of insulating layer 104 or silicon layer 106 (for example, a silicon film such as crystalline silicon). In some embodiments, BOX layer 104 may have a thickness between about 100 nm and about 400 nm. The silicon layer 106 forms a thick film region 108a and a thin film region 108b. In some embodiments, thick film region 108a may have a thickness between about 50 nm and about 180 nm. In some embodiments, the thin film region 108b may have a thickness between about 5 nm and about 50 nm thick. In certain embodiments, thick film region 108a is at least about twice as thick as thin film region 108b, or at least about 2.5 times thicker and/or less than or equal to about 20 times thicker, or at least about 5 times thicker and/or Less than or equal to about 15 times thicker.

A portion of a depleted SOI (PDSOI) power amplifier (PA) device 110 is formed in the thick film region 108a. A fully depleted SOI (FDSOI) low noise amplifier (LNA) device 120 and a FDSOI switching device 130 are formed in the thin film region 108b. PDSOI PA device 110, FDSOI LNA device 120, and FDSOI switch device 130 may each include an n-MOSFET and/or a p-MOSFET.

PDSOI PA device 110 includes a MOSFET having a gate structure with a gate conductor 112 (eg, polysilicon) and a gate insulating layer 119 (eg, oxide). One or more spacers may also be used. PDSOI PA device 110 includes a source diffusion 114 and a drain diffusion 116 . In a particular implementation, source diffusion 114 and/or drain diffusion 116 may extend through the depth of silicon layer 106 to reach or nearly reach insulating layer 104 . In some embodiments, drain diffusion 116 can be configured such that PDSOI PA device 110 is a laterally diffused MOSFET (LDMOS) or an extended drain MOSFET (EDMOS). PDSOI PA device 110 includes a channel 118 below gate insulating layer 119 and between source diffusion 114 and drain diffusion 116 . Channel 118 may be doped to achieve targeted performance characteristics. Channel 118 can be configured to have a thickness such that the depletion layer partially covers the space below gate insulating layer 119 when PDSOI PA device 110 is in the on state. Thus, the PDSOI PA device 110 is partially depleted due at least in part to being built into the thick film region 108a.

The FDSOI LNA device 120 is similar to the PDSOI PA device 110 in that it includes a gate having a gate conductor 122 and a gate insulating layer 129, a source diffusion 124, a drain diffusion 126 and an insulating layer on the gate. One channel 128 below layer 129 . In the FDSOI LNA device 120, the channel 128 is configured to have a thickness such that the depletion layer covers the space below the gate insulating layer 129 when the FDSOI LNA device 120 is in the on state. Thus, the FDSOI LNA device 120 is completely depleted due at least in part to being built into the thin film region 108b. In some embodiments, channel 128 is undoped or lightly doped.

The FDSOI switch device 130 is similar to the FDSOI LNA device 120 in that it includes a gate having a gate conductor 132 and a gate insulating layer 139, a source diffusion 134, a drain diffusion 136 and an insulating layer on the gate. One channel 138 below layer 139 . Channel 138 is configured to have a thickness such that a depletion layer covers the space below gate insulating layer 139 when FDSOI switching device 130 is in the on state. Thus, the FDSOI switching device 130 is completely depleted due at least in part to being built into the thin film region 108b. In some embodiments, channel 138 is undoped or lightly doped.

FEIC 100a includes a substrate 102 , an insulating layer 104 on top of substrate 102 , and a semiconductor layer 106 on top of insulating layer 104 . The semiconductor layer 106 forms a thin film region 108b and a thick film region 108a. Thin film region 108b includes one or more FDSOI LNA devices 120 and one or more FDSOI switching devices 130 . The thick film region 108a includes one or more PDSOI PA devices 110 . Accordingly, the semiconductor layer 106 is thinner in the LNA device 120 and the switching device 130 than in the PA device 110 .

FIG. 1B illustrates another fully integrated FEIC 100b fabricated using SOI processing techniques. FEIC 100b includes the same structure as FEIC 100a in that it includes a substrate 102 , an insulating layer 104 on top of substrate 102 , and a semiconductor layer 106 on top of insulating layer 104 . The semiconductor layer 106 forms a thin film region 108b and a thick film region 108a. The thick film region 108a contains various thick film devices 140 . In some embodiments, the thick film device 140 may include analog circuits (eg, high voltage PA, LDO, high voltage breakdown, ESD protection, charge pump, high power switch, power control unit, etc.). The thin film region 108b contains various thin film devices 150 . In some embodiments, thin film device 150 may include analog circuits (eg, low power analog circuits, level shifters, summing devices, current mirrors, etc.) and/or digital circuits (eg, logic gates). Thus, the semiconductor layer 106 is thicker in the region of the thin film device 150 than it is in the region of the thick film device 140 . In some embodiments, thick film region 108a of FEIC 100b is used for high voltage analog circuitry. In such embodiments, the membrane region 108b may be used for RF circuitry. In a particular embodiment, thick film region 108a of FEIC 100b is used for RF circuitry (eg, PA), and thin film region 108b is used for analog (eg, low power analog circuitry) and/or digital circuitry (eg, logic gates).

2A, 2B, 2C, and 2D illustrate an exemplary FEIC 200 at various stages in a manufacturing process. FEIC 200 is similar to FEIC 100a, 100b in that it includes a substrate 102 and an insulating layer 104 on substrate 102 . The substrate 102 can be a silicon support wafer or a handle wafer. The insulating layer 104 may be a buried oxide such as silicon dioxide. In some embodiments, insulating layer 104 may have a thickness between about 100 nm and about 400 nm.

In FIG. 2A , FEIC 200 includes an active or silicon layer 206 of substantially uniform thickness. The silicon layer 206 can be a silicon film. The thickness of silicon layer 206 may be suitable for constructing FDSOI devices. For example, silicon layer 206 may be between about 5 nm and about 50 nm thick, or about 1/4 the length of a gate of a FDSOI device to be built in silicon layer 206 .

In FIG. 2B , FEIC 200 includes a FDSOI LNA device 220 and a FDSOI switching device 230 . FDSOI LNA device 220 is similar to FDSOI LNA device 120 of FIG. 1A in that it includes a gate structure having a gate conductor 222 over a gate insulating layer 229, a source diffusion 224, a drain diffusion 226 and a channel 228. FDSOI switching device 230 is similar to FDSOI switching device 130 of FIG. 1A in that it includes a gate structure having a gate conductor 232 over a gate insulating layer 239, a source diffusion 234, a drain diffusion 236 and a channel 238. It should be understood that although a single FDSOI LNA device 220 is shown, a plurality of FDSOI LNA devices may be built into the silicon layer 206 . It should also be understood that although a single FDSOI switching device 230 is shown, a plurality of FDSOI switching devices may be built into the silicon layer 206 .

In FIG. 2C, FEIC 200 includes a build-up region 207 that increases the thickness of silicon film 206 in a target region. Build-up portion 207 may be constructed on silicon film 206 using any suitable process. One example of a process for building up silicon films is selective epitaxial growth (SEG). For example, using SEG, a portion of silicon layer 206 that does not contain any FDSOI devices can be built up.

Build-up portion 207 results in thick film region 208a of silicon layer 206 that is thicker than thin film region 208b of silicon layer 206 . The resulting thickness of the thick film region 208a may be suitable for constructing a PDSOI device. For example, the thickness of silicon layer 206 in thick film region 208a may be between about 50 nm and about 180 nm. This build-up portion 207 is shown as a cross-hatched portion on top of the silicon layer 206 , but it should be understood that the resulting increase in thickness of the silicon film 206 does not necessarily result in an additional layer on top of the silicon layer 206 . In fact, the additional thickness of build-up portion 207 represents an increase in the thickness of silicon layer 206 itself.

In FIG. 2D , FEIC 200 includes a PDSOI PA device 210 built into thick film region 208 a of silicon layer 206 . PDSOI PA device 210 is similar to PDSOI PA device 110 of FIG. 1A in that it includes a gate structure having a gate conductor 212 over a gate insulating layer 219, a source diffusion 214, a drain diffusion 216 and a well 218. The PDSOI PA device 210 can be an LDMOS PA device or an EDMOS PA device. It should be understood that although a single PDSOI PA device 210 is shown, a plurality of PDSOI PA devices may be built into the silicon layer 206 . FEIC 200 may include passive devices in either or both of thick film region 208a and thin film region 208b.

By way of example, one suitable method for fabricating FEIC 200 includes forming insulating layer 104 on top of substrate 102 . The method includes forming a semiconductor layer 206 on top of the insulating layer 104 . The method includes building the FDSOI LNA device 220 into the semiconductor layer 206 . The method includes building the FDSOI switching device 230 into the semiconductor layer 206 . The method includes increasing a thickness of a portion of the semiconductor layer 206 to form a thick film region 208 a of the semiconductor layer 206 . The method includes building the PDSOI PA device 210 in the thick film region 208a of the semiconductor layer 206 such that the FDSOI LNA device 220 and the FDSOI switching device 230 are in the thin film region 208b of the semiconductor layer 206 and the PDSOI PA device 210 is in the thick film region 208a of the semiconductor layer 206. In the membrane region 208a.

Figures 3A, 3B, 3C and 3D illustrate a variation of the procedure for building the FEIC 200 described with respect to Figures 2A-2D. In this variation, FEIC 200 begins with a thin silicon layer 206, as shown in FIG. 3A. In FIG. 3B, the build-up region 207 of the FEIC is formed prior to forming the devices in the thin film region 208b. Build-up portion 207 may be constructed on silicon film 206 using any suitable process, such as SEG. Build-up portion 207 results in thick film region 208a of silicon layer 206 that is thicker than thin film region 208b of silicon layer 206 . The resulting thickness of thick film region 208a may be suitable for constructing a PDSOI device, eg, between about 50 nm and about 180 nm. This build-up portion 207 is shown as a cross-hatched portion on top of the silicon layer 206 , but it should be understood that the resulting increase in thickness of the silicon film 206 does not necessarily result in an additional layer on top of the silicon layer 206 . In fact, the additional thickness of build-up portion 207 represents an increase in the thickness of silicon layer 206 itself. Once thick film region 208a is formed, devices 210, 220, 230 may be built into thick film region 208a and thin film region 208b, as described herein with respect to FIGS. 2B and 2D. FIG. 3C shows that source diffusions 214 , 224 , 234 and drain diffusions 216 , 226 , 236 can be formed along with channels 218 , 228 , 238 . In some embodiments, after these have been formed, the gate insulating layers 219, 229, 239 shown in FIG. 3D between the respective source and drain diffusions may be formed with a gate insulating layer formed over the respective gate insulating layers. Gate conductors 212 , 222 , 232 . In a particular embodiment, the mask used to construct the gate insulating layer 219 may be shared with the masks used for the gate insulating layers 229 , 239 . Similarly, the mask used to construct gate conductor 212 may be shared with the masks used for gate conductors 222,232.

4A, 4B, 4C, and 4D illustrate another exemplary FEIC 300 at various stages in a manufacturing process. FEIC 300 is similar to FEIC 100a in that it includes a substrate 102 and an insulating layer 104 on substrate 102 . The substrate 102 can be a silicon support wafer or a handle wafer. The insulating layer 104 may be a buried oxide such as silicon dioxide. In some embodiments, insulating layer 104 may have a thickness between about 100 nm and about 400 nm.

In FIG. 4A , FEIC 300 includes an active or silicon layer 306 of substantially uniform thickness. The silicon layer 306 can be a silicon film. The thickness of silicon layer 306 may be suitable for constructing PDSOI devices. For example, silicon layer 306 may be between about 50 nm and about 180 nm thick.

In FIG. 4B , FEIC 300 includes a PDSOI PA device 310 built into silicon layer 306 . PDSOI PA device 310 is similar to PDSOI PA device 110 of FIG. 1A in that it includes a gate structure having a gate conductor 312 over a gate insulating layer 319, a source diffusion 314, a drain diffusion 316 and a well 318. The PDSOI PA device 310 can be an LDMOS PA device or an EDMOS PA device. It should be understood that although a single PDSOI PA device 310 is shown, a plurality of PDSOI PA devices may be built into the silicon layer 306 .

In FIG. 4C , FEIC 300 includes a region 307 representing a portion of silicon layer 306 that has been removed to reduce the thickness of silicon layer 306 in a target region. Removed portion 307 may be removed from silicon film 306 using any suitable procedure. One example of a procedure for removing a portion of a silicon film is localized thinning. For example, using localized thinning, a portion of silicon layer 306 that does not contain any PDSOI devices can be removed.

The removed portion 307 results in a thick film region 308a of the silicon layer 306 that is thicker than a thin film region 308b of the silicon layer 306 . The resulting thickness of thin film region 308b may be suitable for constructing FDSOI devices. For example, the thickness of silicon layer 306 in thin film region 308b may be between about 5 nm and about 50 nm, or about 1/4 of the gate length of a FDSOI device to be built in thin film region 308b.

In FIG. 4D , FEIC 300 includes a FDSOI LNA device 320 and a FDSOI switching device 330 . FDSOI LNA device 320 is similar to FDSOI LNA device 120 of FIG. 1A in that it includes a gate structure having a gate conductor 322 over a gate insulating layer 329, a source diffusion 324, a drain diffusion 326 and a channel 328. FDSOI switching device 330 is similar to FDSOI switching device 130 of FIG. 1A in that it includes a gate structure having a gate conductor 332 over a gate insulating layer 339, a source diffusion 334, a drain diffusion 336, and a Channel 338. It should be understood that although a single FDSOI LNA device 320 is shown, a plurality of FDSOI LNA devices may be built into the silicon layer 306 . It should also be understood that although a single FDSOI switching device 330 is shown, a plurality of FDSOI switching devices may be built into the silicon layer 306 . FEIC 300 may include passive devices in either or both thick film region 308a and thin film region 308b.

By way of example, one suitable method for fabricating FEIC 300 includes forming insulating layer 104 on top of substrate 102 . The method also includes forming a semiconductor layer 306 on top of the insulating layer 104 . The method also includes embedding the PDSOI PA device 310 in the semiconductor layer 306 . The method also includes reducing the thickness of a portion of the semiconductor layer 306 to form a thin film region 308b of the semiconductor layer 306 . The method also includes embedding the FDSOI LNA device 320 in the thin film region 308b of the semiconductor layer 306 . The method also includes embedding the FDSOI switching device 330 in the thin film region 308 b of the semiconductor layer 306 . PDSOI PA device 310 is in thick film region 308 a of semiconductor layer 306 , and FDSOI LNA device 320 and FDSOI switching device 330 are in thin film region 308 b of semiconductor layer 306 .

Figures 5A, 5B, 5C, and 5D illustrate a variation of the procedure for building the FEIC 300 described with respect to Figures 4A-4D. In this variation, FEIC 300 begins with a thick silicon layer 306, as shown in Figure 5A. In FIG. 5B , FEIC 300 includes a region 307 representing a portion of silicon layer 306 that has been removed to reduce the thickness of silicon layer 306 in a target region. Removed portion 307 may be removed from silicon film 306 using any suitable procedure, such as localized thinning. The removed portion 307 results in a thick film region 308a of the silicon layer 306 that is thicker than the thin film region 308b of the silicon layer 306 . The resulting thickness of thin film region 308b may be suitable for constructing an FDSOI device, eg, between about 5 nm and about 50 nm, or about 1/4 of the gate length of a FDSOI device to be built in thin film region 308b. Once the thin film region 308b is formed, the devices 310, 320, 330 may be built into the thick film region 308a and the thin film region 308b, as described herein with respect to FIGS. 4B and 4D. FIG. 5C shows that source diffusions 314 , 324 , 334 and drain diffusions 316 , 326 , 336 can be formed along with channels 318 , 328 , 338 . In some embodiments, after these have been formed, the gate insulating layers 319, 329, 339 shown in FIG. 5D between the respective source and drain diffusions may be formed with a gate insulating layer formed over the respective gate insulating layers. Gate conductors 312 , 322 , 332 . In a particular embodiment, the mask used to construct the gate insulating layer 319 may be shared with the masks used for the gate insulating layers 329 , 339 . Similarly, the mask used to construct gate conductor 312 may be shared with the masks used for gate conductors 322,332. Manufacturing front-end integrated circuits

6A illustrates an integration for constructing a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device, a fully depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device, and a FDSOI switching device. A method 600 of a front end integrated circuit (FEIC). 2A-2D illustrate an example of an FEIC fabricated corresponding to the steps of method 600 .

At block 605, a substrate having a buried oxide (BOX) layer and a thin film silicon layer is prepared. For example, the substrate with the BOX layer and thin film silicon may be in the form of a silicon-on-insulator (SOI) wafer. The preparation of the SOI wafer may occur in a separate process such that the step at block 605 involves receiving or providing the SOI wafer, rather than requiring fabrication of the SOI wafer. Fabrication may also include any steps performed to prepare structures to enable active devices to be built into thin-film silicon layers. An example of FEIC at block 605 is shown in FIG. 2A.

The substrate can be a handle wafer. The BOX layer can be any suitable insulating layer, such as a thermal silicon oxide (SiO2). The thin film silicon layer can be a thin film deposited on the BOX, such as crystalline silicon. The thickness of the BOX layer can be anywhere between about 5 nm and about 400 nm, and can be at least about 100 nm and/or less than or equal to about 200 nm, and typically between about 5 nm and about 50 nm. It is sometimes called a thick BOX layer compared to a thin or ultra-thin BOX layer. The thickness of the thin-film silicon layer can be between about 5 nm and about 50 nm, or about 1/4 the length of the gate of an active device to be built in the thin-film silicon layer. Any suitable procedure can be used to fabricate SOI wafers, including ion implant separation (SIMOX), bonding and etch back SOI (BESOI), epitaxial layer transfer (ELTRAN®), NANOCLEAVE®, SMART CUT™, etc.

At block 610, one or more FDSOI LNA devices and one or more FDSOI switch devices are built into the thin film silicon layer. The channels between the source and drain diffusions of these active devices can be constructed undoped or can be lightly doped. Thin-film silicon is so thick that the channel is completely empty when the active device is in the on state. An example of FEIC at block 610 is shown in FIG. 2B .

At block 615, the thickness of a region of thin film silicon is increased to create a thick film region that does not include any FDSOI active devices. Thus, a region of thin-film silicon that has not been subjected to a process of thickening the silicon layer may be referred to as a thin-film region of the silicon layer that includes one or more FDSOI LNA devices and one or more FDSOI switch devices. The thickness of the resulting thick film region can be between about 50 nm and about 180 nm. FIG. 2C shows an example of FEIC at block 615.

An epitaxial deposition process, or epitaxy, can be used to increase the thickness of the silicon layer. These procedures can be used to grow a silicon layer (eg, crystalline silicon) over a silicon film (eg, crystalline silicon) or a substrate. Selective epitaxial growth (SEG) is one such exemplary process that may be used to grow silicon on exposed silicon regions of a silicon film. Areas where silicon growth is not desired can be masked by a dielectric film (usually silicon dioxide or silicon nitride). Epitaxial growth can involve the condensation of liquid or gaseous precursors to form a film on a substrate. For example, the gaseous precursors can be obtained by chemical vapor deposition and/or laser ablation.

At block 620, one or more PDSOI PA devices are built into the thick film region. The one or more PDSOI PA devices can be LDMOS and/or EDMOS PA devices. The thickness of the thick film silicon is such that when the active device is in the on state, the channel is partially empty. An example of FEIC at block 620 is shown in FIG. 2D . Optionally, at block 625, passive devices may be built into thin film regions, thick film regions, or both thin film and thick film regions.

Method 600 provides many advantages. For example, LDMOS PA devices and EDMOS PA devices on SOI have fewer parasitics associated with implementations using bulk technology. This results in better or improved active device performance. As another example, the buried oxide layer can be a thick BOX layer rather than an ultra-thin layer to achieve the desired performance characteristics. This results in more robust active device performance, higher power capability, and improved passive device performance. As another example, the resulting FEIC has the advantages of both FDSOI active devices (eg, switching devices and LNA devices) as well as PDSOI active devices (eg, PA devices).

FIG. 6B illustrates a method 650 for constructing an integrated FEIC with a PDSOI PA device, a FDSOI LNA device, and a FDSOI switch device. 3A-3D illustrate an example of an FEIC fabricated corresponding to the steps of method 650 . It should be noted that method 650 is substantially similar to method 600 described with respect to FIG. 6A , and thus shares the advantages of method 600 . One difference between methods 600 and 650 is an order of method steps such that method 650 prepares the substrate prior to building the device. In particular, method 650 switches the order of building the device in a thin film region and increasing the thickness of a portion of the thin film region to create a thick film region. Accordingly, the description of method 650 will be abbreviated in reliance on the description of method 600 to provide details of method 650 .

At block 655, a substrate is prepared having a BOX layer and a thin-film silicon layer, and may be in the form of an SOI wafer, for example. An example of FEIC at block 655 is shown in FIG. 3A.

At block 660, the thickness of a region of thin film silicon is increased to create a thick film region. Thus, a region of thin-film silicon that has not been subjected to a procedure to thicken the silicon layer can be referred to as a thin-film region of the silicon layer. The thickness of the resulting thick film region can be between about 50 nm and about 180 nm. An example of FEIC at block 660 is shown in FIG. 3B .

At block 665, one or more FDSOI LNA devices and one or more FDSOI switch devices are built into the thin film region of the silicon layer. The channels between the source and drain diffusions of these active devices can be constructed undoped or can be lightly doped. Thin-film silicon is so thick that the channel is completely empty when the active device is in the on state. At block 670, one or more PDSOI PA devices are built into the thick film region. The one or more PDSOI PA devices can be LDMOS and/or EDMOS PA devices. The thickness of the thick film silicon is such that when the active device is in the on state, the channel is partially empty. Optionally, at block 675, passive devices may be built into thin film regions, thick film regions, or both thin film and thick film regions.

An example of the FEIC at blocks 665 and 670 is shown in FIGS. 3C and 3D . It should be understood that while blocks 665 and 670 indicate that the device is built in the thin film region and then in the thick film region, other implementations of the method 650 include partially embedding the device in both the thin film region and the thick film region ( For example, as shown in FIG. 3C ), and then complete the device in both regions (eg, as shown in FIG. 3D ). In some embodiments, a common mask can be used to complete the device, as described herein. This also applies to method 600, where the device is partially built into the thin film region and the thick film region, and then done in a single step, possibly using a common mask in some instances.

FIG. 7A illustrates a method 700 for constructing an integrated FEIC with a PDSOI PA device, a FDSOI LNA device, and a FDSOI switch device. 4A-4D illustrate an example of an FEIC fabricated corresponding to the steps of method 500 .

At block 505, a substrate having a buried oxide (BOX) layer and a thick film silicon layer is prepared. For example, the substrate with BOX layers and thick film silicon may be in the form of a silicon-on-insulator (SOI) wafer. The preparation of the SOI wafer may occur in a separate process such that the step at block 505 involves receiving or providing the SOI wafer, rather than requiring fabrication of the SOI wafer. Fabrication may also include any steps performed to prepare structures to enable active devices to be built into thick film silicon layers. An example of FEIC at block 505 is shown in FIG. 4A.

The substrate can be a handle wafer. The BOX layer can be any suitable insulating layer, such as a thermal silicon oxide (SiO2). The thin film silicon layer can be a thin film deposited on the BOX, such as crystalline silicon. The thickness of the BOX layer can be anywhere between about 5 nm and about 400 nm, and can be at least about 100 nm and/or less than or equal to about 200 nm, and typically between about 5 nm and about 50 nm. It is sometimes called a thick BOX layer compared to a thin or ultra-thin BOX layer. The thickness of the thick film silicon layer may be between about 50 nm and about 180 nm. Any suitable procedure can be used to fabricate SOI wafers, including ion implant separation (SIMOX), bonding and etch back SOI (BESOI), epitaxial layer transfer (ELTRAN®), NANOCLEAVE®, SMART CUT™, etc.

At block 510, one or more PDSOI PA devices are built into the thick film silicon layer. The one or more PDSOI PA devices can be LDMOS and/or EDMOS PA devices. The thickness of the thick film silicon is such that when the active device is in the on state, the channel is partially empty. An example of FEIC at block 510 is shown in FIG. 4B.

At block 515, the thickness of a region of thin film silicon is reduced to produce a thin film region that does not include any PDSOI active devices. Accordingly, a region of thick-film silicon that has not been subjected to a process of thinning the silicon layer can be referred to as a thick-film region of the silicon layer that includes one or more PDSOI PA devices. The thickness of the resulting thin film region can be between about 5 nm and about 50 nm thick, or typically about 1/4 the length of the gate of an active device to be built in the thin film region. An example of FEIC at block 515 is shown in FIG. 4C.

Thinning of the thick film silicon layer may include any suitable procedure for localized thinning. For example, thinning may include mechanical grinding, chemical mechanical planarization, wet etching, atmospheric downstream plasma dry chemical etching (ADP DCE), and the like.

At block 510, one or more FDSOI LNA devices and one or more FDSOI switch devices are built into the thin film region. The channels between the source and drain diffusions of these active devices can be constructed undoped or can be lightly doped. The thickness of the membrane region is such that the channel is completely empty when the active device is in the on state. An example of FEIC at block 520 is shown in FIG. 4D . Optionally, at block 525, passive devices may be built into thin film regions, thick film regions, or both thin film and thick film regions.

Method 500 provides many advantages. For example, LDMOS PA devices and EDMOS PA devices on SOI have fewer parasitics associated with implementations using bulk technology. This results in better or improved active device performance. As another example, the buried oxide layer can be a thick BOX layer rather than an ultra-thin layer to achieve the desired performance characteristics. This results in more robust active device performance, higher power capability, and improved passive device performance. As another example, the resulting FEIC has the advantages of both FDSOI active devices (eg, switching devices and LNA devices) as well as PDSOI active devices (eg, PA devices). Additionally, method 500 may be less expensive than method 400 because thinning is generally a less expensive procedure than epitaxial growth or deposition.

FIG. 7B illustrates a method 750 for constructing an integrated FEIC with a PDSOI PA device, a FDSOI LNA device, and a FDSOI switch device. 5A-5D illustrate an example of an FEIC fabricated corresponding to the steps of method 750 . It should be noted that method 750 is substantially similar to method 700 described with respect to FIG. 7A , and thus shares the advantages of method 700 . One difference between methods 700 and 750 is an order of method steps such that method 750 prepares the substrate prior to building the device. In particular, method 750 switches the order of building the device in the thick film region and reducing the thickness of a portion of the thick film region to create the thin film region. Accordingly, the description of method 750 will be abbreviated in reliance on the description of method 700 to provide details of method 750 .

At block 755, a substrate is prepared having a BOX layer and a thick film silicon layer, and for example the substrate may be in the form of an SOI wafer. An example of FEIC at block 755 is shown in FIG. 5A.

At block 760, the thickness of a region of thick film silicon is reduced to create a thin film region. Therefore, a region of thick-film silicon that has not been subjected to a process of thinning the silicon layer can be referred to as a thick-film region of the silicon layer. The thickness of the resulting thin film regions can be between about 5 nm and about 50 nm. An example of FEIC at block 760 is shown in FIG. 5B.

At block 765, one or more PDSOI PA devices are built into the thick film region. The one or more PDSOI PA devices can be LDMOS and/or EDMOS PA devices. The thickness of the thick film silicon is such that when the active device is in the on state, the channel is partially empty. At block 770, one or more FDSOI LNA devices and one or more FDSOI switch devices are built into the thin film region of the silicon layer. These active devices can be constructed without doping the channel between the source and drain diffusions of these active devices or can be lightly doped. Thin-film silicon is so thick that the channel is completely empty when the active device is in the on state. Optionally, at block 775, passive devices may be built into thin film regions, thick film regions, or both thin film and thick film regions.

5C and 5D show examples of FEIC at blocks 765 and 770 . It should be understood that while blocks 765 and 770 indicate that the device is embedded in the thick film region and then in the thin film region, other embodiments of the method 750 include partially embedding the device in both the thin film region and the thick film region (eg, as shown in FIG. 5C ), and then complete the device in both regions (eg, as shown in FIG. 5D ). In some embodiments, a common mask can be used to complete the device, as described herein. This also applies to method 600, where the device is partially built into the thin film region and the thick film region, and then done in a single step, possibly using a common mask in some instances.

Additionally, it should be understood that the methods 600, 650, 700, 750 may be used to prepare the FEIC 100b depicted in Figure IB. A modification to methods 600, 650, 700, 750 would be to swap the steps for preparing a particular PDSOI PA device, FDSOI LNA device, and/or FDSOI switch with other circuits described with respect to FIG. 1B. Additional Examples and Terms

This disclosure describes various features, no single one of which is solely responsible for the advantages described herein. It will be appreciated that various features described herein may be combined, modified or omitted, as would be apparent to those of ordinary skill in the art. Other combinations and subcombinations than those specifically described herein will be apparent to the skilled artisan and are intended to form a part of the present invention. Various methods are described herein in conjunction with various flowchart steps and/or stages. It will be understood that in many cases certain steps and/or stages may be combined together such that multiple steps and/or stages shown in a flow diagram can be performed as a single step and/or stage. Also, certain steps and/or stages may be divided into additional sub-components for separate execution. In some instances, the order of steps and/or stages may be rearranged and certain steps and/or stages may be omitted entirely. Furthermore, the methods described herein are to be understood as open-ended such that additional steps and/or stages of the methods shown and described herein may also be performed.

Unless the context clearly requires otherwise, throughout this description and throughout the claims, the words "comprise/comprising" and the like shall be construed as an inclusive rather than an exclusive or exhaustive meaning; That is, the meaning of "including but not limited to". As used generally herein, the word "coupled" refers to two or more elements, either directly connected or connected through one or more intermediate elements. In addition, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portion of this application. Where the context permits, words in the above detailed description using the singular or the plural may also include the plural or the singular respectively. The word "or" in reference to a list of two or more items includes all of the following constructions of the word: any of the items in the list, all of the items in the list and any combination of items in the list . The word "exemplary" is used herein exclusively to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

The present invention is not intended to be limited to the implementations shown herein. Various modifications to the implementations described in this disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention provided herein can be applied to other methods and systems and are not limited to those described above, and the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the novel methods and systems described herein may be embodied in many other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the invention. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.

100a: Fully integrated front-end integrated circuit (FEIC) 100b: Fully integrated front-end integrated circuit (FEIC) 102: Substrate 104: insulating layer/buried oxide (BOX) layer 106: Silicon layer/semiconductor layer 108a: thick film region 108b: Membrane area 110: Partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device 112: gate conductor 114: Source Diffusion 116: Drain Diffusion 118: channel 119: gate insulating layer 120: Fully depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device 122: gate conductor 124: Source Diffusion 126: Drain Diffusion 128: channel 129: gate insulation layer 130: Fully depleted silicon-on-insulator (FDSOI) switching device 132: gate conductor 134: Source Diffusion 136: Drain Diffusion 138: channel 139: Gate insulating layer 140: thick film device 150: thin film device 200: Front-end integrated circuit (FEIC) 206: Silicon layer/silicon film/semiconductor layer 207:Additional area/additional part 208a: thick film region 208b: Membrane area 210: Partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device 212: gate conductor 214: Source Diffusion 216: Drain Diffusion 218: well/channel 219: Gate insulating layer 220: Fully depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device 222: gate conductor 224: Source Diffusion 226: Drain Diffusion 228: channel 229: Gate insulating layer 230: Fully Depleted Silicon-on-Insulator (FDSOI) Switching Devices 232: gate conductor 234: source diffusion 236: Drain Diffusion 238: channel 239: Gate insulating layer 300: Front-end integrated circuit (FEIC) 306: Silicon layer/silicon film/semiconductor layer 307: area/removed part 308a: thick film region 308b: Membrane area 310: Partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device 312: gate conductor 314: Source Diffusion 316: Drain Diffusion 318: well/channel 319: gate insulation layer 320: Fully Depleted Silicon-on-Insulator (FDSOI) Low Noise Amplifier (LNA) Device 322: gate conductor 324: source diffusion 326: Drain Diffusion 328: channel 329: gate insulation layer 330: Fully Depleted Silicon-on-Insulator (FDSOI) Switching Devices 332: gate conductor 334: source diffusion 336: Drain Diffusion 338: channel 339: gate insulation layer 600: method 605: block 610: block 615: block 620: block 625: block 650: method 655: block 660: block 665: block 670: block 675: block 700: method 750: method 755: block 760: block 765: block 770: block 775: block

FIG. 1A illustrates a fully integrated front-end integrated circuit (FEIC) fabricated using silicon-on-insulator (SOI) processing technology.

FIG. 1B illustrates another fully integrated FEIC fabricated using SOI processing technology.

2A, 2B, 2C and 2D illustrate an exemplary FEIC at different stages in a process.

Figures 3A, 3B, 3C and 3D illustrate a variation of the procedure for constructing the FEIC described with respect to Figures 2A-2D.

4A, 4B, 4C, and 4D illustrate another exemplary FEIC at various stages in a process.

Figures 5A, 5B, 5C and 5D illustrate a variation of the procedure for constructing the FEIC described with respect to Figures 4A-4D.

6A and 6B are diagrams for constructing a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device, a fully depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device, and a FDSOI switching device. One way to integrate FEIC.

7A and 7B illustrate additional methods for constructing an integrated FEIC with a PDSOI PA device, a FDSOI LNA device, and a FDSOI switch device.

100a: Fully integrated front-end integrated circuit (FEIC)

102: Substrate

104: insulating layer/buried oxide (BOX) layer

106: Silicon layer/semiconductor layer

108a: thick film region

108b: Membrane area

110: Partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device

112: gate conductor

114: Source Diffusion

116: Drain Diffusion

118: channel

119: gate insulating layer

120: Fully depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device

122: gate conductor

124: Source Diffusion

126: Drain Diffusion

128: channel

129: gate insulation layer

130: Fully depleted silicon-on-insulator (FDSOI) switching device

132: gate conductor

134: Source Diffusion

136: Drain Diffusion

138: channel

139: Gate insulating layer

Claims (40)

A front-end integrated circuit, comprising: a substrate; an insulating layer on top of the substrate; and a semiconductor layer on top of the insulating layer, the semiconductor layer forming a thin film region and a thick film region, the thin film region comprising one or more fully depleted silicon-on-insulator (FDSOI) low noise amplifiers (LNAs) device and one or more FDSOI switching devices, the thick film region includes one or more partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) devices. A front-end integrated circuit as claimed in claim 1, wherein the insulating layer is at least 100 nm thick. The front end integrated circuit of claim 1, wherein the semiconductor layer in the thin film region is at least 5 nm thick and less than or equal to 50 nm thick. The front end integrated circuit of claim 3, wherein the semiconductor layer in the thick film region is at least about 50 nm thick and less than or equal to 180 nm thick. The front-end integrated circuit of claim 1, wherein the insulating layer is a buried oxide layer. The front end integrated circuit of claim 1, wherein the semiconductor layer in the thin film region is 1/4 of a gate length of the one or more FDSOI LNA devices. The front-end integrated circuit according to claim 1, further comprising one or more passive devices built in the thin film region of the semiconductor layer. The front end integrated circuit of claim 1, further comprising one or more passive devices built in the thick film region of the semiconductor layer. The front end integrated circuit of claim 1, wherein the thin film region of the semiconductor layer is formed using local thinning. The front end integrated circuit of claim 1, wherein the thick film region of the semiconductor layer is formed using selective epitaxial growth. A method for manufacturing a front-end integrated circuit, the method comprising: forming an insulating layer on top of a substrate; forming a semiconductor layer on top of the insulating layer; Embedding a fully depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device in the semiconductor layer; embedding an FDSOI switching device in the semiconductor layer; increasing a thickness of a portion of the semiconductor layer to form a thick film region of the semiconductor layer; and Embedding a portion of a depleted silicon-on-insulator (PDSOI) power amplifier (PA) device in the thick film region of the semiconductor layer such that the FDSOI LNA device and the FDSOI switch device are in a thin film region of the semiconductor layer and the PDSOI PA devices are in this thick film region. The method of claim 11, wherein the insulating layer is at least about 100 nm thick. The method of claim 11, wherein the thin film region of the semiconductor layer is at least about 5 nm thick and less than or equal to about 50 nm thick. The method of claim 13, wherein the thick film region of the semiconductor layer is at least about 50 nm thick and less than or equal to 180 nm thick. The method of claim 11, wherein the thin film region of the semiconductor layer is 1/4 of a gate length of the FDSOI LNA device. The method of claim 11, further comprising building one or more passive devices in the thin film region of the semiconductor layer. The method of claim 11, further comprising building one or more passive devices in the thick film region of the semiconductor layer. The method of claim 11, wherein increasing the thickness comprises using selective epitaxial growth. A method for manufacturing a front-end integrated circuit, the method comprising: forming an insulating layer on top of a substrate; forming a semiconductor layer on top of the insulating layer; Embedding a portion of a depleted silicon-on-insulator (FDSOI) power amplifier (PA) device into the semiconductor layer; reducing a thickness of a portion of the semiconductor layer to form a thin film region of the semiconductor layer; embedding a fully depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device in the thin-film region of the semiconductor layer; and Embedding an FDSOI switching device in the thin film region of the semiconductor layer such that the PDSOI PA device is in a thick film region of the semiconductor layer and the FDSOI LNA device and the FDSOI switching device are in the thin film region of the semiconductor layer middle. The method of claim 19, wherein the insulating layer is at least about 100 nm thick. The method of claim 19, wherein the thin film region of the semiconductor layer is at least about 5 nm thick and less than or equal to about 50 nm thick. The method of claim 21, wherein the thick film region of the semiconductor layer is at least about 50 nm thick and less than or equal to 180 nm thick. The method of claim 19, wherein the thin film region of the semiconductor layer is 1/4 of a gate length of the FDSOI LNA device. The method of claim 19, further comprising building one or more passive devices into the thin film region of the semiconductor layer. The method of claim 19, further comprising building one or more passive devices in the thick film region of the semiconductor layer. The method of claim 19, wherein reducing the thickness comprises using localized thinning. A method for manufacturing a front-end integrated circuit, the method comprising: forming an insulating layer on top of a substrate; forming a semiconductor layer having a first thickness on top of the insulating layer; increasing a thickness of a portion of the semiconductor layer to form a thick film region of the semiconductor layer, and the other portion of the semiconductor layer having the first thickness is a thin film region; embedding high voltage analog circuitry in the thick film region; and A low voltage analog circuit is built into the membrane area. The method of claim 27, wherein the insulating layer is at least about 100 nm thick. The method of claim 27, wherein the thin film region of the semiconductor layer is at least about 5 nm thick and less than or equal to about 50 nm thick. The method of claim 29, wherein the thick film region of the semiconductor layer is at least about 50 nm thick and less than or equal to 180 nm thick. The method of claim 27, wherein the high voltage analog circuit comprises a low dropout voltage regulator. The method of claim 27, wherein the high voltage analog circuit comprises a high voltage power amplifier. The method according to claim 27, further comprising building digital circuits into the thin film region. A method for manufacturing a front-end integrated circuit, the method comprising: forming an insulating layer on top of a substrate; forming a semiconductor layer having a first thickness on top of the insulating layer; reducing a thickness of a portion of the semiconductor layer to form a thin film region of the semiconductor layer, and the other portion of the semiconductor layer having the first thickness is a thick film region; embedding a radio frequency (RF) device in the thick film region; and Analog or digital circuitry is built into the membrane region. The method of claim 34, wherein the insulating layer is at least about 100 nm thick. The method of claim 34, wherein the thin film region of the semiconductor layer is at least about 5 nm thick and less than or equal to about 50 nm thick. The method of claim 34, wherein the thick film region of the semiconductor layer is at least about 50 nm thick and less than or equal to 180 nm thick. The method of claim 34, wherein the RF device in the thick film region comprises a power amplifier (PA) device. The method of claim 38, wherein the PA device comprises a portion of a depleted silicon-on-insulator (PDSOI) PA device. The method of claim 34, wherein the digital circuit comprises logic gates.

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