TW202236601A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure includes a substrate, a gate, a bit line, a capping layer, a first spacer, an insulated layer, a second spacer and a spin-coating dielectric layer. The gate and the bit line is located on the substrate. The gate is located between the substrate and the bit line. The capping layer is located on the bit line. The first spacer is located on a sidewall of the gate, a sidewall of the bit line and a sidewall of the capping layer. The insulated layer is located on an upper portion of the first spacer. The second spacer is located under a bottom surface of the insulated layer and extends downwardly. The insulated layer, the first spacer and the second spacer defines an air gap. The spin-coating dielectric layer is among the first spacer, the air gap and the second spacer. The spin-coating dielectric layer is lower than a bottom surface of the bit line.

Description

Semiconductor structures and methods of forming them

The present disclosure relates to a semiconductor structure and a method for forming the semiconductor structure.

Generally speaking, an air gap is usually applied in the bit line process to reduce the parasitic capacitance between the bit lines. In a conventional air gap process, the sacrificial layer between the first spacer and the second spacer is removed by wet etching or plasma cleaning to form the air gap. In the conventional air gap process, the opening of the air gap is formed in the upper half of the air gap, and after the opening is formed, the opening of the air gap is sealed with nitride (such as silicon nitride). However, the structure in which the opening of the air gap is formed in the upper half of the air gap may allow the nitride closing the opening to flow into the interior of the air gap, resulting in nitride in the air gap, resulting in a reduced effect of the air gap on reducing parasitic capacitance.

One technical aspect of the present disclosure is a semiconductor structure.

According to an embodiment of the present disclosure, a semiconductor structure includes a substrate, a gate, a bit line, a capping layer, a first spacer, an insulating layer, a second spacer, and a spin-on dielectric layer. The gate and bit lines are located on the substrate. The gate is located between the substrate and the bit line. The overlay is on the bitlines. The first spacer is located on the sidewalls of the gate, the bit line and the upper cover layer. An insulating layer is on the upper portion of the first spacer. The second spacer is located on the bottom surface of the insulating layer and extends downward. The insulating layer, the first spacer and the second spacer define an air gap. A spin-on dielectric layer is located between the first spacer, the air gap, and the second spacer. The spin-on dielectric layer is below the bottom surface of the bitlines.

In an embodiment of the present disclosure, the top of the air gap is higher than the top surface of the bit line.

In an embodiment of the present disclosure, the first spacer, the air gap, and the second spacer are parallel to each other in a vertical direction.

In an embodiment of the present disclosure, the above-mentioned substrate has an active area and shallow trench isolation next to the active area. The active area is located under the gate and the first spacer.

In an embodiment of the present disclosure, the above-mentioned semiconductor structure further includes a semiconductor layer. The semiconductor layer is on the spin-on dielectric layer, the shallow trench isolation, and the active region. The semiconductor layer extends to the sidewall of the insulating layer.

One technical aspect of the present disclosure is a method for forming a semiconductor structure.

According to an embodiment of the present disclosure, a method for forming a semiconductor structure includes: forming a photoresist on a first spacer on a substrate, wherein the first spacer is located on the sidewalls of the gate, the bit line, and the upper cap layer, and the bit The line is located between the gate and the upper cover layer; an insulating layer is formed on the top surface of the photoresist and the sidewall of the first spacer; the bottom of the insulating layer and the photoresist are etched to make the remaining insulating layer and the photoresist along the first spacer setting; forming a second spacer on the photoresist; etching the bottom of the second spacer and the bottom of the photoresist to expose the bottom of the first spacer; removing the photoresist between the first spacer and the second spacer To form an air gap, wherein there is an opening between the bottom of the first spacer and the second spacer, the opening is located below the bit line; and a spin-on dielectric layer is formed on the bottom of the first spacer, so that the spin-on dielectric A layer is located in the opening.

In an embodiment of the present disclosure, the method further includes etching a spin-on dielectric layer outside the opening and on the bottom of the first spacer.

In an embodiment of the present disclosure, the above-mentioned substrate has an active area and shallow trench isolation next to the active area. The above method further includes etching the bottom of the first spacer and the STI and the active region thereunder.

In an embodiment of the present disclosure, the above method further includes forming a semiconductor layer on the shallow trench isolation and the active region, wherein the semiconductor layer is located on the spin-on dielectric layer.

In an embodiment of the present disclosure, the method further includes anisotropically etching the photoresist after etching the bottom of the insulating layer and the photoresist, so that the sidewall of the photoresist is closer to the first spacer than the sidewall of the insulating layer.

In the above embodiments of the present disclosure, there is an air gap between the first spacer and the second spacer of the semiconductor structure, and the opening of the air gap is located below the bit line and between the bottom of the first spacer and the second spacer. between. Additionally, a spin-on dielectric layer of the semiconductor structure can be formed on the bottom of the first spacer such that the spin-on dielectric layer can be located in the opening below the bit line. That is to say, the design that the opening of the air gap is located below the bit line can make the spin-on dielectric layer flow into the opening of the air gap from the bottom of the first spacer, so as to achieve the effect of closing the opening. Compared with the conventional technology, the air gap of the semiconductor structure does not have the nitride backfilled inside, so the air gap can effectively reduce the parasitic capacitance.

The embodiments disclosed below provide many different implementations, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present case. Of course, these examples are only examples and are not intended to be limiting. In addition, the present case may repeat element symbols and/or letters in various instances. This repetition is for the purposes of brevity and clarity and does not in itself dictate a relationship between the various implementations and/or configurations discussed.

Spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein for convenience of description to describe The relationship of one element or feature to another element or feature as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 shows a cross-sectional view of a semiconductor structure 100 according to an embodiment of the present disclosure. Referring to FIG. 1 , the semiconductor structure 100 includes a substrate 110 , a gate 120 , a bit line 130 , a capping layer 140 , a first spacer 150 a , an insulating layer 160 , a second spacer 150 b and a spin-on dielectric layer 180 . The gate 120 and the bit line 130 of the semiconductor structure 100 are located on the substrate 110 . Moreover, the gate 120 of the semiconductor structure 100 is located between the substrate 110 and the bit line 130 . In this embodiment, the gate 120 of the semiconductor structure 100 may include doped polysilicon, metal, conductive metal nitride and combinations thereof, but the present disclosure is not limited thereto. The upper cap layer 140 of the semiconductor structure 100 is located on the bit line 130 . The material of the upper cap layer 140 of the semiconductor structure 100 may include nitride (such as silicon nitride), but this disclosure is not limited thereto.

The first spacer 150 a of the semiconductor structure 100 is located on the sidewall 122 of the gate 120 , the sidewall 132 of the bit line 130 and the sidewall 142 of the upper cap layer 140 . The insulating layer 160 of the semiconductor structure 100 is on the upper portion of the first spacer 150a. The second spacer 150b of the semiconductor structure 100 is located on the bottom surface 162 of the insulating layer 160 and extends downward from the bottom surface 162 of the insulating layer 160 along the vertical direction D1. The bottom surface 162 of the insulating layer 160 of the semiconductor structure 100 , the first spacer 150 a and the second spacer 150 b define an air gap 170 . The spin-on dielectric layer 180 of the semiconductor structure 100 is located between the first spacer 150a, the air gap 170 and the second spacer 150b. The spin-on dielectric layer 180 of the semiconductor structure 100 is lower than the bottom surface 134 of the bit line 130 .

In this embodiment, the top 172 of the air gap 170 of the semiconductor structure 100 is higher than the top surface 136 of the bit line 130 of the semiconductor structure 100 , and the bottom 174 of the air gap 170 is lower than the bottom surface 134 of the bit line 130 . That is to say, the overall height of the air gap 170 of the semiconductor structure 100 is greater than the overall height of the bit line 130 of the semiconductor structure 100, so the air gap 170 of the semiconductor structure 100 can provide a sufficient spacing effect, so that adjacent bits of the semiconductor structure 100 The undesired parasitic capacitance between the element lines 130 can be reduced.

Specifically, there is an air gap 170 between the first spacer 150 a and the second spacer 150 b of the semiconductor structure 100 , and the bottom 174 of the air gap 170 is located below the bottom surface 134 of the bit line 130 . In addition, the spin-on dielectric layer 180 of the semiconductor structure 100 can be formed on the bottom 152a of the first spacer 150a, such that the spin-on dielectric layer 180 can be located under the bit line 130 and at the bottom of the second spacer 150b. and the bottom 152a of the first spacer 150a. That is, the design of the bottom 174 of the air gap 170 below the bottom surface 134 of the bit line 130 allows the spin-on dielectric layer 180 to be formed on the bottom 152a of the first spacer 150a and formed on the bottom 174 of the air gap 170. below, to achieve the effect of closing the air gap 170. Compared with the conventional technology, the air gap 170 of the semiconductor structure 100 does not have the nitride backfilled therein, so the air gap 170 of the semiconductor structure 100 can effectively provide the effect of reducing parasitic capacitance.

In this embodiment, the first spacer 150a, the air gap 170 and the second spacer 150b of the semiconductor structure 100 are parallel to each other in the vertical direction D1. The substrate 110 of the semiconductor structure 100 has an active region 112 and a shallow trench isolation 114 beside the active region 112 . The active region 112 of the substrate 110 is located under the gate 120 of the semiconductor structure 100 and the first spacer 150a. The shallow trench isolation 114 of the substrate 110 can provide an isolation effect. In addition, the semiconductor structure 100 further includes a semiconductor layer 190 . The material of the semiconductor layer 190 of the semiconductor structure 100 may include polysilicon, but this disclosure is not limited thereto. The semiconductor layer 190 of the semiconductor structure 100 is located on the spin-on dielectric layer 180 , the shallow trench isolation 114 of the substrate 110 and the active region 112 . Moreover, the semiconductor layer 190 of the semiconductor structure 100 extends to the sidewall 164 of the insulating layer 160 .

In the following description, a method for forming the semiconductor structure 100 will be described. The described component connection relationship and materials will not be repeated, but will be described first.

FIG. 2 shows a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. A method of forming a semiconductor structure includes the following steps. First in step S1, a photoresist is formed on the first spacer on the substrate, wherein the first spacer is located on the gate, the bit line and the sidewall of the upper cover layer, and the bit line is located between the gate and the upper cover layer . Next in step S2, an insulating layer is formed on the top surface of the photoresist and the sidewall of the first spacer. Then in step S3, the bottom of the insulating layer and the photoresist are etched, so that the remaining insulating layer and photoresist are arranged along the first spacer. Subsequently in step S4, a second spacer is formed on the photoresist. Then in step S5, the bottom of the second spacer and the bottom of the photoresist are etched to expose the bottom of the first spacer. Then in step S6, remove the photoresist between the first spacer and the second spacer to form an air gap, wherein there is an opening between the bottom of the first spacer and the second spacer, and the opening is located below the bit line . Then in step S7, a spin-on dielectric layer is formed on the bottom of the first spacer so that the spin-on dielectric layer is located in the opening. In the following description, the above-mentioned steps will be described in detail.

3 to 11 are cross-sectional views of different stages of the method of forming the semiconductor structure 100 . Referring to FIG. 3, the photoresist 200 is formed on the first spacer 150a on the substrate 110 of the semiconductor structure 100, wherein the first spacer 150a is located on the sidewall 122 of the gate 120, the sidewall 132 of the bit line 130 and the upper cap layer. 140 on the side wall 142. Moreover, the bit line 130 of the semiconductor structure 100 is located between the gate 120 and the upper cap layer 140 . Next, an insulating layer 160 is formed on the top surface 202 of the photoresist 200 and the sidewall 154a of the first spacer 150a. In detail, the insulating layer 160 is formed on the upper portion of the sidewall 154 a of the first spacer 150 a and the top surface 202 of the photoresist 200 , and the insulating layer 160 may be U-shaped.

Referring to FIG. 3 and FIG. 4 at the same time, then, the bottom of the insulating layer 160 and the photoresist 200 of the semiconductor structure 100 are etched, so that the remaining insulating layer 160 and the photoresist 200 are arranged along the first spacer 150a, and the remaining photoresist 200 A U-shape may be formed on the first spacer 150a. Please refer to FIG. 5, the forming method of the semiconductor structure 100 further includes etching the photoresist 200 anisotropically after etching the bottom of the insulating layer 160 and the photoresist 200, so that the sidewall 204 of the photoresist 200 is higher than the sidewall 164 of the insulating layer 160 close to the first spacer 150a. That is, after anisotropic etching, the thickness of the photoresist 200 on the sidewall 154a of the first spacer 150a is smaller than the thickness of the insulating layer 160 on the sidewall 154a of the first spacer 150a.

Referring to FIG. 6 , next, the second spacer 150 b is formed on the photoresist 200 . The second spacer 150b is disposed along the photoresist 200, and the sidewall 152b of the second spacer 150b is aligned with the sidewall 164 of the insulating layer 160 in the vertical direction D1. Referring to FIG. 6 and FIG. 7 at the same time, the bottom of the second spacer 150b and the bottom of the photoresist 200 of the semiconductor structure 100 are etched to expose the bottom 152a of the first spacer 150a. In detail, when etching the bottom of the second spacer 150b and the bottom of the photoresist 200 of the semiconductor structure 100, the bottom 152a of the first spacer 150a can be used as an etching stop layer, so that the etching stays at the bottom of the first spacer 150a. 152a on.

Referring to FIG. 7 and FIG. 8 at the same time, then, the photoresist 200 between the first spacer 150 a of the semiconductor structure 100 and the second spacer 150 b of the semiconductor structure 100 is removed to form the air gap 170 . In addition, there is an opening O between the bottom 152 a of the first spacer 150 a and the bottom 154 b of the second spacer 150 b of the semiconductor structure 100 . The opening O is located below the bottom surface 134 of the bit line 130 .

Referring to FIG. 8 and FIG. 9 at the same time, next, a spin-on dielectric layer 180 is formed on the bottom 152 a of the first spacer 150 a of the semiconductor structure 100 , so that the spin-on dielectric layer 180 is located in the opening O. The design of the opening O of the air gap 170 below the bottom surface 134 of the bit line 130 allows the spin-on dielectric layer 180 to flow from the bottom 152a of the first spacer 150a into the bottom 152a of the first spacer 150a and the second spacer 150b. In the opening O between the bottom ends 154b of , in order to achieve the effect of closing the air gap 170 . The material of the spin-on dielectric layer 180 of the semiconductor structure 100 may include a spin-on dielectric material, but this disclosure is not limited thereto.

Please refer to FIG. 10. Next, the method for forming the semiconductor structure 100 further includes forming the spin-on dielectric layer 180 on the bottom 152a of the first spacer 150a, and then etching the spin-on dielectric layer outside the bottom 174 of the air gap 170. 180, and etch the spin-on dielectric layer 180 on the bottom 152a of the first spacer 150a. Referring to FIG. 11 , the substrate 110 of the semiconductor structure 100 has an active region 112 and a shallow trench isolation 114 beside the active region 112 . The forming method of the semiconductor structure 100 further includes etching the bottom 152 a of the first spacer 150 a and the active region 112 and the shallow trench isolation 114 thereunder.

Returning to FIG. 1 , next, the method of forming the semiconductor structure 100 further includes etching the bottom 152 a of the first spacer 150 a and the active region 112 and the shallow trench isolation 114 therebelow, and then forming the active region 112 and the shallow trench on the substrate 110 A semiconductor layer 190 is formed on the trench isolation 114 , wherein the semiconductor layer 190 of the semiconductor structure 100 is located on the sidewall of the spin-on dielectric layer 180 , and the semiconductor layer 190 extends to the sidewall 164 of the insulating layer 160 . In this way, the structure shown in Figure 1 can be obtained.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. It should be appreciated by those skilled in the art that they may readily use the present disclosure as a basis for designing or modifying other processes and structures, so as to achieve the same purposes and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

100: Semiconductor Structures 110: Substrate 112: active zone 114:Shallow trench isolation 120: Gate 122: side wall 130: bit line 132: side wall 134: bottom surface 136: top surface 140: upper cover layer 142: side wall 150a: first spacer 152a: Bottom 154a: side wall 150b: second spacer 152b: side wall 154b: Bottom 160: insulating layer 162: Bottom 164: side wall 170: air gap 172: top 174: bottom 180:Spin-coated dielectric layer 190: semiconductor layer 200: photoresist 202: top surface 204: side wall D1: vertical direction O: open

One embodiment of the present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. FIG. 2 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. FIG. 3 to FIG. 11 illustrate cross-sectional views at different stages of the formation method of the semiconductor structure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100: Semiconductor Structures

110: Substrate

112: active area

114:Shallow trench isolation

120: Gate

122: side wall

130: bit line

132: side wall

134: bottom surface

136: top surface

140: upper cover layer

142: side wall

150a: first spacer

152a: Bottom

154a: side wall

150b: second spacer

152b: side wall

160: insulating layer

162: Bottom

164: side wall

170: air gap

172: top

174: bottom

180:Spin-coated dielectric layer

190: semiconductor layer

D1: vertical direction

Claims (10)

A semiconductor structure comprising: a substrate; A gate and a bit line are located on the substrate, wherein the gate is located between the substrate and the bit line; a capping layer located on the bit line; a first spacer located on the sidewalls of the gate, the bit line and the upper cap layer; an insulating layer located on the upper portion of the first spacer; a second spacer, located on the bottom surface of the insulating layer and extending downward, wherein the insulating layer, the first spacer and the second spacer define an air gap; and A spin-on dielectric layer is located between the first spacer, the air gap and the second spacer, and is lower than the bottom surface of the bit line. The semiconductor structure of claim 1, wherein a top of the air gap is higher than a top surface of the bit line. The semiconductor structure of claim 1, wherein the first spacer, the air gap, and the second spacer are parallel to each other in a vertical direction. The semiconductor structure of claim 1, wherein the substrate has an active region and a shallow trench isolation next to the active region, and the active region is located under the gate and the first spacer. The semiconductor structure as described in Claim 4, further comprising: A semiconductor layer is located on the spin-on dielectric layer, the shallow trench isolation and the active region, and extends to the sidewall of the insulating layer. A method for forming a semiconductor structure, comprising: A photoresist is formed on a first spacer on a substrate, wherein the first spacer is located on sidewalls of a gate, a bit line and an upper cover layer, and the bit line is located between the gate and the gate Between the upper cover layer; forming an insulating layer on a top surface of the photoresist and sidewalls of the first spacer; etching a bottom of the insulating layer and the photoresist so that the remaining insulating layer and the photoresist are disposed along the first spacer; forming a second spacer on the photoresist; etching the bottom of the second spacer and the bottom of the photoresist to expose a bottom of the first spacer; removing the photoresist between the first spacer and the second spacer to form an air gap, wherein there is an opening between the bottom of the first spacer and the second spacer, the opening is located at the position below the element line; and A spin-on dielectric layer is formed on the bottom of the first spacer such that the spin-on dielectric layer is located in the opening. The method as described in Claim 6, further comprising: The spin-on dielectric layer is etched outside the opening and on the bottom of the first spacer. The method according to claim 7, wherein the substrate has an active area and a shallow trench isolation next to the active area, the method further comprising: Etching the bottom of the first spacer and the STI thereunder and the active region. The method as described in claim item 8 further includes: A semiconductor layer is formed on the shallow trench isolation and the active region, wherein the semiconductor layer is located on the spin-on dielectric layer. The method as described in Claim 6, further comprising: After etching the bottom of the insulating layer and the photoresist, anisotropically etch the photoresist so that the sidewall of the photoresist is closer to the first spacer than the sidewall of the insulating layer.

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