TW202236282A - Storage device - Google Patents

Abstract

A storage device includes a first interconnection, a second interconnection, a memory cell connected between the first and second interconnections and including a variable resistance element and a switching element that is connected in series to the variable resistance element, and a control circuit configured to exercise control of a read operation to read data stored in the memory cell. The control circuit exercises control in such a manner as to set the first interconnection which has been charged with a first voltage and the second interconnection which has been charged with a second voltage into floating states, to set the switching element into an on-state by discharging the second interconnection set into the floating state to thereby increase a voltage applied to the memory cell, and to read the data stored in the memory cell in a state in which the switching element is set into the on-state.

Description

storage device

[CROSS-REFERENCE TO RELATED APPLICATIONS]

This application is based on and claims the benefit of priority of Japanese Patent Application No. 2021-037466 filed on March 9, 2021, and U.S. Patent Application No. 17/462449 filed on August 31, 2021, which The entire contents of the application are incorporated herein by reference.

The embodiments described herein generally relate to a storage device.

A non-volatile storage device including a plurality of memory cells is proposed, each of which includes a variable resistance memory element (for example, a magnetoresistive effect element) and a switch element connected in series.

Embodiments provide a storage device capable of reliably performing a read operation.

In general, according to one embodiment, a storage device includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction, the second direction being the same as the first The direction crosses; the memory unit is connected between the first interconnection and the second interconnection and includes a variable resistance memory element and a switching element, and the switching element is connected between the first end of the memory unit and the second interconnection. The second terminals are connected in series to the variable resistance memory element, the first terminal and the second terminal are respectively connected to the first interconnection and the second interconnection; and a control circuit, It is configured to control the read operation to read the data stored in the memory unit. The control circuit controls in such a manner that the first interconnect charged to a first voltage and the second interconnect charged to a second voltage are set to a floating state by The second interconnect set to the floating state discharges thereby increasing a voltage applied to the memory cell to set the switching element to an on state, and when the switching element is set to The data stored in the memory unit is read in the on state.

Embodiments will be explained hereinafter with reference to the drawings.

FIG. 1 is a block diagram showing an overall schematic configuration of a storage device (for example, a non-volatile storage device) according to an embodiment. Note that a magnetic storage device will be described hereinafter as an example of a storage device.

A magnetic storage device according to an embodiment of the present invention includes a memory cell array section 100 , a control circuit 200 and a detection circuit 300 .

FIG. 2A is a perspective view schematically showing the configuration of the memory cell array section 100 .

The memory cell array segment 100 includes: a plurality of word lines (also referred to herein as first interconnects) 10 disposed on a base area (not shown) and extending in the X direction, the base area Including a semiconductor substrate (not shown); a plurality of bit lines (also referred to herein as second interconnects) 20 extending in the Y direction; and a plurality of memory cells 30 connected to the plurality of word between the bit line 10 and the plurality of bit lines 20 .

Note that the X direction, the Y direction, and the Z direction shown in the drawings are directions intersecting each other. More specifically, the X direction, the Y direction, and the Z direction are orthogonal to each other.

When writing data into or reading data from the memory unit 30 , the word line 10 and the bit line 20 respectively supply predetermined signals to each memory unit 30 . Although word line 10 is on the lower layer side and bit line 20 is on the upper layer side in FIG. 2A , word line 10 may be on the upper layer side and bit line 20 may be on the lower layer side.

Each memory unit 30 includes: a magnetoresistance effect element 40, which is a variable resistance memory element; and a selector (ie, a switch element 50) connected in series to the magnetoresistance effect element 40 to select the magnetoresistance effect Element 40.

Although the magnetoresistance effect element 40 is located on the lower layer side and the selector 50 is located on the upper layer side in FIG. 2A, the magnetoresistance effect element 40 may be located on the upper layer side and the selector 50 may be located on the lower layer side, as shown in FIG. 2B. .

FIG. 3 is a cross-sectional view schematically showing the arrangement of the magnetoresistance effect element 40 .

In the embodiment of the present invention, a magnetic tunnel junction (magnetic tunnel junction, MTJ) element is used as the magnetoresistance effect element 40 . The magnetoresistance effect element 40 includes: a storage layer, that is, a first magnetic layer 41 ; a reference layer, that is, a second magnetic layer 42 ; and a tunneling barrier layer, that is, a nonmagnetic layer 43 .

The storage layer 41 is a ferromagnetic layer with a variable magnetization direction. Variable magnetization direction means that the magnetization direction changes with respect to a write current. The reference layer 42 is a ferromagnetic layer with a fixed magnetization direction. Fixed magnetization direction means that the magnetization direction does not change with respect to a predetermined write current. The tunnel barrier layer 43 is an insulating layer disposed between the storage layer 41 and the reference layer 42 .

When the magnetization direction of the storage layer 41 is parallel to the magnetization direction of the reference layer 42 , the magnetoresistance effect element 40 is in a low-resistance state in which the resistance of the magnetoresistance effect element 40 is relatively low. When the magnetization direction of the storage layer 41 is antiparallel to the magnetization direction of the reference layer 42 , the magnetoresistance effect element 40 is in a high resistance state in which the resistance of the magnetoresistance effect element 40 is relatively high. Therefore, the magnetoresistive element 40 can store binary data in response to the resistance state (low resistance state or high resistance state). In addition, a low-resistance state or a high-resistance state can be set in the magnetoresistance effect element 40 according to the direction of the write current.

Although the magnetoresistive effect element 40 shown in FIG. 3 has a bottom free structure in which the storage layer 41 is located on the lower layer side and the reference layer 42 is located on the upper layer side, it is also applicable to have a structure in which the storage layer 41 is located on the upper layer side and the reference layer 42 Magneto-resistive effect elements of the top free structure on the lower layer side.

FIG. 4 is a cross-sectional view schematically showing the configuration of the selector 50 .

The selector 50 includes a lower electrode 51 , an upper electrode 52 and a selector material layer, that is, a switch material layer 53 , and the switch material layer 53 is disposed between the lower electrode 51 and the upper electrode 52 . The selector 50 is a two-terminal switching element exhibiting nonlinear current-voltage characteristics. When the voltage applied across the two terminals is lower than the threshold voltage, the selector 50 is set to a high resistance state (such as a non-conductive state), and when the voltage applied across the two terminals is equal to or higher than the threshold voltage, the selector 50 is selected The device 50 is set to a low resistance state (eg, a conductive state).

FIG. 5 schematically shows the relationship between the voltage applied across the memory cell 30 and the current through the memory cell 30 .

When the voltage applied to the memory cell 30 increases to a level equal to or higher than the threshold voltage Vth, the selector 50 transitions to a low resistance state (on state); and when the voltage applied to the memory cell 30 decreases to a low When maintaining the level of the voltage Vhold, the selector 50 turns into a high resistance state (off state). When the voltage applied to the memory unit 30 is equal to the holding voltage Vhold, the holding current Ihold passes through the memory unit 30 . Applying a voltage equal to or higher than the threshold voltage Vth between one word line 10 and one bit line 20 turns the selector 50 into an on state and enables data to be written to the devices connected in series to the selector 50. The magnetoresistance effect element 40 reads data from the magnetoresistance effect element 40 .

Next, the read operation performed by the storage device according to the embodiment of the present invention will be described with reference to the circuit diagram shown in FIG. 6 and the timing diagrams shown in FIGS. 7A to 7C .

The storage device mainly operates under the control of the control circuit 200 shown in FIG. 1 . That is, the write operation of writing data into the magnetoresistance effect element 40 and the read operation of reading data stored in the magnetoresistance effect element 40 are mainly performed under the control of the control circuit 200 .

As shown in FIG. 6, one end of the switch circuit 61 and one end of the switch circuit 62 are connected to each word line 10, the global word line (global word line, GWL) 63 is connected to the other end of the switch circuit 61, and the voltage The supply line 64 is connected to the other end of the switching circuit 62 . One end of the switch circuit 71 and one end of the switch circuit 72 are connected to each bit line 20, a global bit line (GBL) 73 is connected to the other end of the switch circuit 71, and a voltage supply line 74 is connected to the switch circuit The other end of 72. A fixed voltage Vdd/2 is applied to each of the voltage supply lines 64 and 74 .

A global word line (GWL) control circuit 210 is connected to the global word line 63 , and a global bit line (GBL) control circuit 220 is connected to the global bit line 73 . The control circuit 200 shown in FIG. 1 includes a global word line control circuit 210 and a global bit line control circuit 220 .

The detection circuit 300 includes a constant current source 310 and a sense amplifier (sense amplifier, S/A) 320, and the read enable transistor 81 and the clamp transistor 82 are connected between the detection circuit 300 and the global word line 63 between.

The read operation will be specifically explained later with reference to FIGS. 7A to 7C . FIG. 7A shows the voltage VGWL of the global word line 63 and the voltage VGBL of the global bit line 73 . FIG. 7B shows the read enable signal REN applied to the gate of the transistor 81 . FIG. 7C shows the current Icell passing through the memory cell 30 , that is, the current passing through the magnetoresistive element 40 and the selector 50 connected in series.

Each of the voltage VGWL of the global word line 63 and the voltage VGBL of the global bit line 73 are maintained at Vdd/2 before the start of the read operation. In addition, the read enable signal REN is at a low level and the current Icell passing through the memory cell 30 is zero.

When the read operation starts at time t1, the control circuit 200 controls the selected word line 10 connected to the read target memory cell (also referred to as the selected memory cell) 30 and connected to the read target The selected bit line 20 of the memory cell 30 is charged.

Specifically, the global word line control circuit 210 charges the global word line 63 with the first voltage, and the global bit line control circuit 220 charges the global bit line 73 with the second voltage. In an embodiment of the present invention, both the first voltage and the second voltage are Vdd, so that the first voltage is equal to the second voltage. At this time, the switch circuit 61 connected to the selected word line 10 and the switch circuit 71 connected to the selected bit line 20 are set to an on state. On the other hand, the switch circuit 62 connected to the selected word line 10 is set to the OFF state, and the switch circuit 72 connected to the selected bit line 20 is set to the OFF state. Accordingly, selected wordline 10 and selected bitline 20 are each charged with voltage Vdd. That is, the voltage to charge the selected word line 10 is equal to the voltage to charge the selected bit line 20 .

In addition, the switch circuit 61 connected to each unselected word line 10 is set to an off state, and the switch circuit 62 connected to each unselected word line 10 is set to an on state. In addition, the switch circuit 71 connected to each unselected bit line 20 is set to an off state, and the switch circuit 72 connected to each unselected bit line 20 is set to an on state. Therefore, the voltage of each of unselected word lines 10 and 20 is Vdd/2.

After charging the selected word line 10 and the selected bit line 20 with the voltage Vdd as described above, the control circuit 200 proceeds in such a manner as to set the selected word line 10 and the selected bit line 20 to a floating state. control.

Specifically, at time t2, global wordline control circuit 210 sets global wordline 63 to a floating state and global bitline control circuit 220 sets global bitline 73 to a floating state. Therefore, the selected word line 10 and the selected bit line 20 are set to a floating state.

After setting the selected word line 10 and the selected bit line 20 to the floating state as described above, the control circuit 200 controls to start discharging the selected bit line 20 at time t3. The voltage applied to the selected memory cell 30 is thereby increased and the selector 50 of the selected memory cell 30 is turned on.

Specifically, by causing the global bit line control circuit 220 to discharge the global bit line 73, the voltage of the selected bit line 20 is gradually decreased to Vss (eg, zero volts).

In addition, in the embodiment of the present invention, at time t3, the control signal from the control circuit 200 controls the read enable signal REN to be set at a high level and the control transistor 81 is turned on. This turns the constant current source 310 into a state capable of supplying a constant current to the selected memory cell 30 . Note that the timing at which the read enable signal REN transitions to a high level does not necessarily match the timing at which the discharge to the selected bit line 20 starts, and the read enable signal REN can actually detect the stored state in the detection circuit 300 Before the data in the magneto-resistance effect element 40 transitions to a high level.

When the voltage difference between the voltage of the global word line 63 and the voltage of the global bit line 73 reaches the threshold voltage Vth at time t4 (that is, the voltage between the voltage of the selected word line 10 and the voltage of the selected bit line 20 When the voltage difference reaches the threshold voltage Vth), the selector 50 of the selected memory cell 30 is turned from the off state to the on state. Therefore, the on-current is supplied from the constant current source 310 to the serially connected magnetoresistance effect element 40 and the selector 50 of the selected memory cell 30, and the voltage of the word line 10 (ie, the voltage of the global word line 63) is selected. decreasing gradually.

When the voltage of the global word line 63 drops, the voltage difference between the voltage of the global word line 63 and the voltage of the global bit line 73 (this difference is equal to the voltage of the selected word line 10 and the voltage of the selected bit line 20 The voltage difference between them) reaches the hold voltage Vhold, that is, the voltage applied to the selected memory cell 30 reaches the hold voltage Vhold at time t5. At this time, the control signal from the control circuit 200 controls the read enable signal REN to maintain a high level, and controls the transistor 81 to be set in an on state. Therefore, the turn-on current is continuously supplied from the constant current source 310 to the selector 50 of the selected memory cell 30 . For this reason, the selector 50 of the selected memory cell 30 is not set to the OFF state and maintained in the ON state. That is, after the selector 50 is set to the ON state at time t4, the ON current continues to pass through the selector 50 .

The control circuit 200 controls in the following manner: wherein the selector 50 of the selected memory cell 30 is set to an ON state and wherein the voltage applied to the selected memory cell 30 (which is equal to the voltage applied to the selected word line 10 and the voltage applied to The difference between the voltages of the selected bit line 20) is maintained at the holding voltage Vhold to read the data stored in the magnetoresistance effect element 40 of the selected memory cell 30 (the data corresponding to the low resistance state or the data corresponding to the high resistance state). data corresponding to the state).

Specifically, the sense amplifier 320 detects the cell current Icell passing through the selected memory cell 30 , thereby determining the data stored in the magnetoresistance effect device 40 . As shown in FIG. 7C , the turn-on current (illustrated as holding current Ihold1 ) through the selected memory cell 30 when the magnetoresistance effect element 40 is in the low resistance state is higher than when the magnetoresistance effect element 40 is in the high resistance state. The turn-on current (shown as the hold current Ihold2 ) through the selected memory cell 30 . Therefore, the detection circuit 300 including the sense amplifier 320 detects the resistance state of the magneto-resistance effect element 40 based on the on-current (which is equal to the on-current through the selected memory cell 30 ) through the selector 50 , thereby determining the storage state. The data in the magnetoresistance effect element 40. The detection circuit 300 including the sense amplifier 320 detects the magnetoresistive effect element 40 in a state in which the ON current through the selector 50 is maintained at a constant value and the voltage applied to the selected memory cell 30 is maintained at the hold voltage Vhold resistance state.

Note that the method of determining the data stored in the magnetoresistive effect element 40 is not limited to the method described above (that is, detecting the passage of the selected memory cell 30 in a state where the voltage applied to the selected memory cell 30 is maintained at the hold voltage Vhold). The method of holding the current Ihold of the memory unit 30), and other determination methods can also be applied.

As described so far, according to an embodiment of the present invention, by charging the selected word line 10 and the selected bit line 20 and discharging the selected bit line 20 set to the floating state and increasing the voltage applied to the selected memory cell 30 to set the selector 50 to the ON state. Therefore, it is possible to reliably set the selector 50 to the ON state and reliably read data stored in the magnetoresistance effect element 40 in the state in which the selector 50 is set to the ON state.

In addition, the constant current source 310 supplies a constant current to the selected memory cell 30 until the voltage applied to the selected memory cell 30 (ie, the voltage applied between the selected word line 10 and the selected bit line 20 ) reaches the holding voltage Vhold. Pass current. Therefore, data stored in the magnetoresistance effect element 40 can be reliably read in a state in which the selector 50 is set to the ON state without turning the selector 50 into the OFF state.

8A to 8C are timing diagrams illustrating another example of a read operation performed by a storage device according to an embodiment of the present invention.

The read operation shown in FIGS. 8A-8C is substantially similar to the read operation shown in FIGS. 7A-7C described above. However, the read operation shown in FIGS. 8A to 8C differs from the read operation shown in FIGS. 7A to 7C in the following respects. In the read operation shown in FIGS. 7A to 7C , the global word line 63 and the global word line 63 and the global Bit line 73 transitions to a floating state. In contrast, in the read operation shown in FIGS. 8A to 8C , the global word line 63 is charged with the voltage Vdd and the global bit line 73 is charged with the voltage Vdd/2. The global word line 63 and the global bit line 73 transition to a floating state. That is, in the read operation shown in FIGS. 8A to 8C , the first voltage is different from the second voltage. Note that the first voltage and the second voltage are not limited to the values in the example of the read operation shown in FIGS. 7A to 7C or the values in the example of the read operation shown in FIGS. 8A to 8C as long as the first The difference between the first voltage and the second voltage may be less than the threshold voltage Vth.

In the example of the read operation shown in FIGS. 8A to 8C , similar to the read operation shown in FIGS. 7A to 7C , effects similar to those of the embodiment described above can be produced, and similar The data stored in the magnetoresistance effect element 40 can be reliably read in a state where the selector 50 is set to the on state.

Although magnetoresistive elements are used as variable resistance memory elements in the above-described embodiments, other variable resistance memory elements may be used.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in various other forms; moreover, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The appended claims and their equivalents are intended to cover such forms or modifications as come within the scope and spirit of the disclosure.

10: word line/first interconnect 20: bit line/second interconnect 30: memory unit/target memory unit 40:Magnetoresistive effect element 41: first magnetic layer/storage layer 42:Second magnetic layer/reference layer 43: Non-magnetic layer/Tunneling barrier layer 50: Switching element/selector 51: Lower electrode 52: Upper electrode 53: switch material layer 61, 62, 71, 72: switch circuit 63:Global character line 64, 74: voltage supply line 73:Global bit line 81:Read enabling transistor/transistor 82: clamping transistor 100: memory cell array segment 200: control circuit 210: Global word line (GWL) control circuit 220: Global bit line (GBL) control circuit 300: detection circuit 310: constant current source 320: sense amplifier Icell: current/cell current Ihold, Ihold1, Ihold2: holding current REN: read enable signal t1, t2, t3, t4, t5: time Vdd, VGBL, VGWL: voltage Vdd/2: fixed voltage/voltage Vhold: hold voltage Vth: threshold voltage X, Y, Z: direction

FIG. 1 is a block diagram showing an overall schematic configuration of a storage device according to an embodiment. FIG. 2A is a perspective view schematically showing a configuration of a memory cell array section in a storage device according to an embodiment. 2B is a perspective view schematically showing the configuration of a modification of the memory cell array section of the storage device according to the embodiment. 3 is a cross-sectional view schematically showing the configuration of a magnetoresistance effect element of the storage device according to the embodiment. 4 is a cross-sectional view schematically showing the configuration of a selector in the storage device according to the embodiment. Fig. 5 schematically shows the relationship between the voltage applied across the memory cell and the current passing through the memory cell. FIG. 6 is a circuit diagram illustrating a read operation performed by a storage device according to an embodiment. 7A to 7C are timing diagrams illustrating an example of a read operation performed by a storage device according to an embodiment. 8A to 8C are timing diagrams illustrating another example of a read operation performed by a storage device according to an embodiment.

10: word line/first interconnect

20: bit line/second interconnect

30: memory unit/target memory unit

61, 62, 71, 72: switch circuit

63:Global character line

64, 74: voltage supply line

73:Global bit line

81:Read enabling transistor/transistor

82: clamping transistor

210: global word line (GWL) control circuit

220: global bit line (GBL) control circuit

300: detection circuit

310: constant current source

320: sense amplifier

REN: read enable signal

Claims (20)

A storage device comprising: a first interconnect extending in a first direction; a second interconnect extending in a second direction that intersects the first direction; A memory unit connected between the first interconnection and the second interconnection and including a variable resistance memory element and a switch element, the switch element is at the first end and the second end of the memory unit connected in series to the variable resistance memory element, the first terminal and the second terminal are respectively connected to the first interconnection and the second interconnection; and a control circuit configured to control a read operation to read data stored in the memory unit, wherein The control circuit controls in such a manner that the first interconnect charged to a first voltage and the second interconnect charged to a second voltage are set to a floating state by The second interconnect set to the floating state discharges thereby increasing a voltage applied to the memory cell to set the switching element to an on state, and when the switching element is set to The data stored in the memory unit is read in the on state. The storage device as claimed in claim 1, wherein The switching element transitions to the ON state when a voltage applied across the memory cell is equal to or higher than a threshold voltage, and transitions to the ON state when the voltage applied across the memory cell is lower than a holding voltage. In an off state, the holding voltage is lower than the threshold voltage and higher than zero voltage. The storage device as described in claim 2, wherein A difference between the first voltage and the second voltage is less than the threshold voltage. The storage device as described in claim 2, wherein When reading the data stored in the memory cell, the difference between the voltage applied to the first interconnection and the voltage applied to the second interconnection is equal to the holding voltage. The storage device as claimed in claim 1, wherein The first voltage is equal to the second voltage. The storage device as claimed in claim 1, wherein The first voltage is different from the second voltage. The storage device as claimed in claim 1, wherein The control circuit performs control to continuously pass an on-current to the switching element after setting the switching element to the on state. The storage device as described in claim 7, further comprising: A constant current source supplies the on-current to the switching element. The storage device as described in claim 1, further comprising: The detection circuit detects the resistance state of the variable resistance memory element based on the on-current passing through the switch element. The storage device as claimed in item 9, wherein The detection circuit detects the resistance state of the variable resistance memory element when the on-current is maintained at a constant value. The storage device as claimed in claim 1, wherein The variable resistance memory element is a magnetoresistance effect element. A storage device comprising: a plurality of bit lines, including a first bit line and a second bit line; a plurality of word lines, including a first word line and a second word line; A plurality of memory cells located between the bit line and the word line, each of the plurality of memory cells includes a variable resistance element and a switch element, the variable resistance element and the switch element connected in series between a first end connected to one of the plurality of bit lines and a second end connected to one of the plurality of word lines; control circuits; and detection circuit, where during a read operation, reading data stored in a target memory cell, the target memory cell being one of the plurality of memory cells located between the first bit line and the first word line between, The control circuit sets the first bit line and the first word line to float when the first bit line is at a first voltage and the first word line is at a second voltage state, After setting the first bit line and the first word line to a floating state, the control circuit discharges the first bit line to the switching element of the target memory cell supplying a constant current to turn on the switching element of the target memory cell, and When the voltage difference between the first word line and the first bit line is at a holding voltage less than a threshold voltage and greater than zero voltage and the constant voltage is continuously supplied to the switching element of the target memory cell When the current is flowing, the detection circuit detects the current passing through the target memory unit and determines the data stored in the target memory unit based on the detected current. The storage device as claimed in claim 12, wherein The switching element is turned into an on state when the voltage applied across the memory cell is equal to or higher than the threshold voltage, and when the voltage applied across the memory cell is lower than the holding voltage transition to the disconnected state. The storage device as claimed in claim 13, wherein A difference between the first voltage and the second voltage is less than the threshold voltage. The storage device as claimed in claim 12, wherein The first voltage is equal to the second voltage. The storage device as claimed in claim 12, wherein The first voltage is different from the second voltage. The storage device as claimed in claim 12, wherein The control circuit continuously supplies the constant current to the switching element after the switching element is turned on. The storage device as claimed in claim 12, wherein The detection circuit determines that data having a first value is stored in the target memory cell when the detected current is higher than a reference level, and when the detected current is lower than the reference level Data with a second value is stored in the target memory unit. The storage device as claimed in claim 12, wherein During the read operation on the target memory cell, a fixed voltage is applied to the second bit line and the second word line. The storage device as claimed in claim 19, wherein The fixed voltage is equal to half of the first voltage.

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