TW202232617A - Precision reconstruction for panel-level packaging - Google Patents

Abstract

Panel level packaging (PLP) with high positional accuracy of dies. The PLP bonds dies accurately to die bonding regions of an alignment panel. High accuracy is achieved by providing die bonding regions with local alignment marks. Accurate die bonding on the alignment carrier results in a reconstructed wafer with accurate positioning of dies. The dies of the reconstructed wafer can be scanned by a die location check (DLC) scan based on sub-blocks of dies, enabling high DLC throughput. The DLC scan generates a DLC file with coordinate points of sub-blocks of the reconstructed wafer. Also, a laser direct imaging (LDI) file can be generated using sub-block circuit files aligned to the DLC file. The use of sub-block circuit files facilitates high throughput in generating the LDI file with high accuracy due to the reconstructed wafer being formed using the alignment carrier with local alignment marks.

Description

Precise Refactoring Methods for Panel Level Packaging

The present application relates to precise reconfiguration of panel level packaging devices. In particular, the present application relates to the bonding of dies on panels for high precision panel level packaging.

Panel-level packaging (PLP) for devices has attracted a great deal of interest in recent years. This is because of the larger die volume that can be packaged in parallel compared to traditional wafer-level or substrate-level packaging techniques. PLP involves joining or bonding individual dies on a large panel or carrier for die bonding. For example, the dies are arranged on a panel or carrier in a matrix, with rows and columns of dies. The molding compound wraps the die to form a mold panel or reconstituted wafer. Depending on its size, the carrier can accommodate significantly more dies than the wafer, eg, 3 to 5 times or more dies than the wafer. This increases packaging yield and reduces cost. After the dies are packaged, the reconstituted wafer is sawn or diced to divide the dies.

However, conventional techniques for forming reconstituted wafers result in inaccurate positioning of dies within the reconstituted wafer. The inaccuracy may be due, for example, to inaccurate alignment of the die to the carrier. In addition, bound dies may move during processing, such as molding, further exacerbating inaccuracies in die positioning within the reconstructed wafer. Due to misalignment of dies in the reconstituted wafer, downstream processing, such as forming traces to complete the packaging process and sawing the reconstituted wafer to divide it into individual packages, may be misaligned. This misalignment of downstream processes results in lower yields.

Therefore, based on the foregoing discussion, it is desirable to provide accurate positioning of dies in reconstituted wafers to increase throughput.

Embodiments of the present application generally relate to panel level packaging devices. In particular, the present application relates to precise reconfiguration for panel level packaging.

In one embodiment, a method for die location inspection (DLC) includes providing a reconstituted wafer having a die block encapsulated in a molding compound. The die block includes a plurality of dies arranged in rows and columns to form a die matrix of the block. The plurality of dies includes aligned dies and active dies. The method also includes scanning the reconstituted wafer. The scanning includes scanning the die block. The method also includes processing the scan information of the die block. The process includes identifying the location of the aligned dies of the die block, assigning one of the aligned dies of the die block as the origin of the Cartesian coordinate system of the die block, wherein the die is scanned A block includes scanning a die block one sub-block at a time, wherein each sub-die block includes dies arranged in a sub-block matrix that includes fewer dies than a matrix of the die block. grains, and assigning coordinate points to sub-blocks of the grains in the Cartesian coordinate system.

In another embodiment, a method for bonding dies for panel level processing includes providing an alignment panel having a bonding surface including a die for bonding dies thereon particle binding region. The bound face includes local alignment marks. The bonded face includes a panel adhesive film for facilitating bonding of the die to the die bonding area. The method also includes bonding the selected die to the selected die bonding area, including aligning the selected die with the selected die bonding area using the local alignment marks of the selected die bonding area, and When the selected die is aligned with the selected die binding region, the selected die is bound to the selected die binding region.

These and other advantages and features of the embodiments disclosed herein will become apparent by reference to the following description and drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and may exist in various combinations and permutations.

Embodiments generally relate to panel level packaged devices, such as panel level packaged semiconductor devices or integrated circuits (ICs). In particular, the present application relates to high precision bonding of on-panel dies or devices for panel-level packaging.

FIG. 1 shows a simplified top view of a semiconductor wafer 100 . The wafer may be a lightly doped p-type silicon wafer. Other types of wafers may also be used. For example, the wafers may be silicon carbide (SiC) wafers, gallium nitride (GaN) wafers, gallium arsenide (GaAs) wafers, or indium phosphide (InP) wafers. Devices 110 are formed in parallel on the active surface of wafer 100 . The active surface may be the upper surface of wafer 100 . The passive surface may be the lower surface of the wafer.

The devices 110 are arranged in rows along a first direction (x) and in columns along a second direction (y). After processing of the wafer is complete, the wafer is diced along a dicing or saw line 180 using a wafer saw. For example, the wafer is diced along a first scribe line 180 ₁ in the x-direction and along a second scribe line 180 ₂ in the y-direction to separate the devices 110 of the wafer 100 into individual devices or dies 110 .

2a to 2d show simplified cross-sectional views of the process for processing a processed wafer 200. FIG. Referring to Figure 2a, a cross-sectional view of a processed wafer 200 is shown. Process wafer 200 includes a top or active wafer surface 201 and a bottom or passive wafer surface 202 . By way of example, to simplify the description, the cross-sectional view of the processed wafer 200 includes three dies 210 . It should be understood that the cross-sectional views may include other numbers of dies 210 as well as other elements not shown, eg, portions of the dies at the wafer edge. Process wafer 200 may be an imported process wafer from an external supplier. For example, a packaging supplier may receive processed wafer 200 from an external supplier such as a wafer processing facility.

In one embodiment, bare wafers are processed to form processed wafers 200 . For example, processing includes forming circuit elements or components of die 210 on the surface of the wafer. The circuit elements may include active and passive circuit elements. Active elements may include, for example, transistors, diodes, and triodes, while passive elements include voltage elements, capacitors, resistors, and inductors. Other types of active and passive elements may also be included. Circuit elements can be formed using a range of processes, such as doping (eg, implantation or diffusion), deposition (eg, oxidation, chemical vapor deposition (CVD), electroplating, and sputtering), and patterning (eg, lithography and etching) . Other techniques may also be employed to form circuit elements.

A BEOL dielectric with multiple interconnect levels with wires coupled to via contacts is formed on the die substrate. For example, BEOL dielectrics cover the surface of die substrates with circuit elements. In one embodiment, the BEOL dielectric includes a low-k dielectric or dielectric layer that isolates wires of different interconnect levels. The low-k dielectric layer may also include an ultra-low-k dielectric layer. The low-k dielectrics or dielectric layers may be collectively referred to as low-k dielectrics or dielectric layers and ultra-low-k dielectrics or dielectric layers. Other types of dielectric layers may also be useful. The circuit elements and BEOL dielectric are shown simply as part of the processed wafer 200 . The top of the BEOL may be the active processing wafer surface 201 .

The top of the BEOL dielectric may include a pad. In one embodiment, the pad layer includes die bond pads 240 . The die bond pads 240 may be, for example, aluminum (Al) die bond pads 240 . Other types of die bond pads 240, such as copper (Cu), nickel (Ni), palladium (Pd), gold (Au), chromium (Cr), or combinations or alloys thereof, including Al-Cu, may also be useful.

Die bond pads 240 may be covered by passivation layer 242 . Passivation layer 242 may be a passivation stack having multiple dielectric layers. For example, the passivation stack may include a combination of dielectric layers, such as silicon oxide and silicon nitride layers. Other types of dielectric layers may also be useful.

Passivation layer 242 may include pad openings 244 to expose die bond pads 240 . As shown, the pad openings 244 are smaller than the die bond pads 240 . For example, the top surface of the passivation layer 242 is above the top surface of the die bond pad 240 , and the pad opening 244 is smaller than the die bond pad 240 . As shown, the passivation layer 242 covers the edge portion of the die bond pad 240 . For example, the pad openings 244 may be formed by anisotropic etching such as reactive ion etching (RIE). Other types of etching can also be used to form the pad openings. The exposed portion of the top of the BEOL dielectric, passivation layer 242 and bond pads 240 may be collectively referred to as active handle wafer surface 201 . In some cases, actively processed wafer surface 201 may include the top of the BEOL dielectric and die bond pads 240 , but no passivation layer 242 .

In Figure 2b, the processed wafer 200 is further processed. In one embodiment, further processing of the processed wafer 200 includes forming a buffer layer 260 on the actively processed wafer surface 201 . For example, the buffer layer 260 is a wafer-level buffer layer 260 formed on the surface 201 of the active processing wafer. Wafer level buffer layer 260 is a dielectric buffer layer. The buffer layer 260 may include, for example, epoxy, polyimide, polybenzoxazole, or other types of dielectric materials. The thickness of the buffer layer 260 may be about 10-100 um, about 15-100 um, about 20-100 um, about 25-100 um, about 45-100 um, or about 60-100 um. Other thicknesses of buffer layer 260 may also be useful.

In a preferred embodiment, buffer layer 260 prevents or reduces chipping or cracking of the BEOL dielectric from wafer dicing processes, such as dicing to separate wafer 200 into individual dies 210 . The buffer layer 260 can be tuned to have or to have Young's modulus and fracture strength to reduce or prevent chipping or cracking of the BEOL dielectric during wafer dicing. In one embodiment, the Young's modulus of the buffer layer 260 is about 10,000-25,000 MPa, about 14,000-25,000 MPa, about 15,000-25,000 MPa, about 16,000-25,000 MPa, about 15,000-25,000 MPa, or, about 20,000- 25,000MPa. As for the breaking strength, it may be about 45-150 MPa, about 70-150 MPa, about 70-120 MPa, about 70-105 MPa, about 80-120 MPa, or about 90-120 MPa. The coefficient of thermal expansion (CTE) of the buffer layer 260, for example, may be about 6-20 ppm/K. The buffer layer 260 may have temperature stability in the range of -65-+300°C.

In one embodiment, the buffer layer 260 is a composite buffer layer 260 that includes a base buffer layer with filler particles. In one embodiment, the base buffer layer includes an organic polymer matrix material. For example, the base buffer layer may include thermosets or thermoplastics such as polyimides, epoxies, and other types of polymers. In one embodiment, the base buffer layer includes a resin, such as epoxy or cyanate. Preferably, the base buffer layer is a low viscosity resin, such as biphenyl epoxy resin. Of course, other types of base buffer layers may also be useful.

In one embodiment, the filler is inorganic based. For example, the filler can be silicon dioxide (SiO ₂ ), amorphous aluminum oxide (α-Al ₂ O ₃ ), or a combination thereof. Other types of fillers are also possible. For example, the filler can be organic-based or inorganic-based or a combination of organic-based fillers. For example, the fillers may be spherical fillers. The filler for composite buffer layer 260 is a non-uniformly sized filler ranging in diameter from about 0.5-12 um or about 0.5-10 um. Other sized fillers or shaped fillers may also be useful.

Buffer layer 260 may be formed on actively processed wafer surface 201 using various techniques. For example, the buffer layer 260 may be formed by spin coating or lamination. Other techniques, such as suture coating, may also be useful. The technique used to form the buffer layer 260 may depend on the type of buffer layer.

Referring to FIG. 2 c , the buffer layer 260 on the actively processed wafer surface 201 of the processed wafer 201 is patterned to form via openings 262 . The via openings 262 expose the die bond pads 240 . In one embodiment, the via openings 262 are formed by laser etching. Via openings 262 may also be formed by other processes. As shown, the via opening 262 may have a sloped or tapered sidewall profile. The sidewalls of the via openings 262 may also be non-sloped. Additionally, as shown, the bottom of via opening 262 is smaller than die bond pad 240 . Preferably, the bottom of via opening 262 is located approximately or as close as possible to the central portion of die bond pad 240 .

After via openings 262 are formed in buffer layer 260, process wafer 200 is diced into individual dies 210, as shown in FIG. 2d. For example, process wafer 200 is sawed at dicing line 280 to divide wafer 200 into individual dies 210 .

Figure 3a shows a simplified top view of an embodiment of an alignment carrier or panel 304 used in a PLP. For example, the top view may be aligned with the top surface 305 of the carrier on which the die is bound for the PLP. For example, top surface 305 may be referred to as the binding surface of alignment panel 304 . The opposite surface of the top surface 305 is aligned with the bottom surface 306 of the carrier 304 . Bottom surface 306 may be referred to as the unbonded surface of alignment panel 304 . As shown, the alignment panel 304 is rectangular. Alignment panel 304 may be formed in other shapes.

In a preferred embodiment, the alignment panel 304 is formed from a material with a low coefficient of expansion (CTE) to minimize linear changes during temperature changes. For example, alignment panel 304 may be formed of a material having a CTE equal to or lower than 8 ppm/K. Also, the material should be strong enough to withstand handling during bonding. Furthermore, the material should preferably be magnetic so that the alignment panel 304 can be held securely during the grinding process as part of the overall bonding process. For example, low CTE materials may include Alloy 42 (CTE 3-4.5 ppm/K) and Alloy 46 (CTE 7-8 ppm/K). Alignment panel 304 may also be formed using other types of low CTE materials. It is also useful to form alignment panel 304 using other materials, as well as materials with other CTEs, including materials with CTEs above 8 ppm/K. The dimensions of the alignment panel 304 may be approximately 700 mm by 700 mm. It may also be useful to provide alignment panels 304 with other sizes (larger or smaller).

In one embodiment, the bonding surface 305 of the alignment panel 304 includes an active region 314 having a die bonding region 330 . The die-bonding regions 330 may be arranged in a matrix form with rows and columns of the die-bonding regions 330 in the first (row) and second (column) directions. For example, the row direction is the x direction and the column direction is the y direction.

As shown, the die bond regions 330 in the active region 314 are arranged as a block or matrix. The pitch of the die-bonded regions within a block is the same. For example, the pitch (row pitch) of adjacent die-bonding regions 330 in the row direction of the block is the same; the pitch (column pitch) of the adjacent die-bonding regions 330 in the column direction of the block is the same. The line spacing and column spacing can be the same or different from each other.

In some embodiments, the die bond regions 330 of the alignment panel 304 may be arranged in multiple blocks. For example, the die bond areas 330 of the alignment panel 304 may be arranged in 4 separate blocks of the die bond areas 330, eg, a 2x2 block matrix or arrangement. Other numbers of blocks or permutations of blocks may also be useful. For example, the alignment panel 304 may include an odd number of blocks arranged in a row or column format. For example, the blocks are physically separated by block spacing. For example, adjacent blocks are separated by a block spacing. The block pitch is greater than the grain pitch (the spacing of rows and columns between grains) within a block. Where the alignment panel 304 includes only one block, the block may be used to refer to all die bonding areas 330 of the alignment panel 304, or to all dies within one block of the alignment panel 304 having multiple blocks Binding area 330.

The die is bound to the die bound region 330 of the block. In one embodiment, die bond region 330 includes local alignment marks or fiducials 350 . Local alignment marks 350 aid in aligning the dies to bind them to die attach area 338 of die bonding area 330 . For example, each die bonding area 330 includes its own local alignment mark 350 that is used to align and bond one or more dies to the die attach area 338 . The die attach region 338 may be, for example, the die or the profile of the die when bonded thereto. As shown, the local alignment marks 350 have a circular shape. Local alignment marks 350 may also be of other shapes. Preferably, all local alignment marks 350 have the same shape. It will be appreciated, however, that not all local alignment marks 350 need to have the same shape.

In one embodiment, the local alignment marks 350 are preferably located outside the die attach area 338 . For example, a local alignment mark 350, as shown, surrounds the die attach region 338. In some cases, local alignment marks 350 are disposed within die attach region 338 . In this case, the local alignment marks 350 are not visible after die bonding because the die will cover them. In other embodiments, local alignment marks 350 may be provided inside and outside of die attach region 338 . Providing local alignment marks 350 outside the die attach area 338 facilitates post-bonding inspection as they are visible after die bonding.

The die bonding area 330 can accommodate a single die or multiple dies, such as a multi-chip module (MCM). For example, each die bond region 330 may include a plurality of die attach regions 338 . In the case of MCM, providing local alignment marks 350 outside the die attach area of the multiple dies advantageously enables the local alignment marks 350 to be used collectively to bond multiple dies to die bonding area 330. If local alignment marks 350 are provided within the die attach area 338 of one of the dies, additional local alignment marks 350 may need to be provided for use in bonding other dies of the MCM into the die attach area 330. within their respective die attach regions 338 .

In one embodiment, the local alignment marks 350 may be detected by a collinear vision camera for alignment. Such cameras may be described, for example, in US Pat. No. 16/814,961, which is incorporated herein by reference for all purposes. Local alignment marks 350 may be formed on die bond regions 330 of alignment panel 304 using, for example, laser drilling. Other techniques for forming local alignment marks 350 may also be useful. Preferably, the local alignment marks 350 are shallow marks that can be easily removed by grinding to recover the alignment panel 304 . For example, when a die is no longer in production, the local alignment marks 350 can be removed and a new die bond formed for another or different type of die.

Providing local alignment marks 350 for each die bonding region 330 improves the positional accuracy of die bonding compared to the conventional calculation of die bonding positions based on global alignment marks. Furthermore, by providing local alignment marks 350, the effects of panel deformation or other positioning errors are minimized, increasing the accuracy of die positioning on the alignment panel 304, thereby increasing yield and scalability.

The die bond area 330 of the block includes an aligned die bond area 336 and an active die bond area 331 . The active die binding area 331 accommodates the active die. For example, active dies are ordinary dies that are sold for use. Aligned die bond regions 336 are similar to active die bond regions 331, except that they are designated for alignment die. For example, alignment die bonding region 336 houses alignment dies for alignment purposes. Aligned dies may be normal dies or active dies, such as dies bonded in active die bonding region 331 . For example, the alignment die may be a moving die for alignment purposes.

Alternatively, the alignment die may be used exclusively for alignment purposes. It may be advantageous to provide specific aligned dies because they can be easily distinguished from normal or active dies. In this case, the aligned die cannot be used for normal use. Preferably, the active surface of the alignment die is treated with features that are easily detected by the alignment camera. These features of the aligned die create contrast in the alignment image, making it easy to detect or distinguish from the active die.

In one embodiment, the block includes at least 2 aligned die bond regions 336 . It may also be useful to provide the block with other numbers of aligned die bond regions 336 . As shown, the block includes 4 aligned die bond regions 336 _1-4 . The number of aligned die bond regions may depend on, for example, the application. Aligned die bond regions 336 are located in the block to facilitate determination of the die location of the die in the block of reconstituted wafer by a die location inspection (DLC) process for further processing.

In one embodiment, the alignment die bond regions 336 _1-4 are located at the corner die bond regions of the block. For example, aligned die bond regions 336 _1-4 correspond to the first and last die bond regions 330 of the first and last rows and first and last columns of the block. It may also be useful to provide aligned die bond regions 336 elsewhere in the block. Where the alignment panel 304 includes multiple blocks, each block preferably has the same alignment of the alignment die bond regions 336 . It will be appreciated, however, that different blocks of alignment panel 304 may have different arrangements of alignment die bond regions 336 , including the number and location of alignment die bond regions 336 .

FIG. 3b shows a simplified top view of a portion of another embodiment of the alignment panel 304 . As shown, adjacent die bond regions 330 of the alignment panel 304 abut each other. This arrangement enables local alignment marks 350 to be shared by adjacent die bond regions 330 . Sharing local alignment marks 350 between adjacent die bond regions 330 reduces the footprint of die bond regions 336 , enabling alignment panel 304 to fit more die bond regions 330 .

As mentioned above, the alignment panel 304 is formed of a metallic material with local alignment marks 350 . Using a metallic material is advantageous as it allows the use of a magnetic stage to hold the alignment panel 304 securely in place for processing. For example, a magnetic stage can be used to hold the alignment panel 304 securely in place for grinding the molding compound.

In other embodiments, the alignment panel 304 may be formed of glass or other type of transparent material. Local alignment marks 350 may be formed on transparent alignment panel 304 . In other cases, the local alignment marks 350 may be independent of the transparent alignment panel 304 . For example, the local alignment marks 350 may be formed on a separate sheet of marks, such as paper or resin, and may be attached to the bottom or passive surface of the transparent alignment panel 304 . The use of separate local alignment marks 350 eliminates the need for a marking process on the alignment panel 304, thereby significantly reducing manufacturing costs.

Light from the camera module of the die bonder can penetrate transparent alignment panel 304 to detect local alignment marks 350 on the marker sheet. The use of separate local alignment marks 350 can be easily achieved, eliminating the need for a marking process on the alignment panel 304. Furthermore, providing the local alignment marks 350 separate from the transparent alignment panel 304 is advantageous because it avoids the need to mass produce the glass alignment panels 304 with the local alignment marks 350 . Since the glass alignment panel 304 is fragile and the marking process is expensive, the cost can be significantly reduced.

Figures 4a to 4d illustrate an embodiment of a process for preparing an alignment panel. Referring to Figure 4a, an exposed alignment panel 404 is provided. Alignment panel 404 includes opposing top surfaces 405 and bottom surfaces 406 . Alignment panel 404 may be formed of a low CTE material, such as Alloy 42 or Alloy 46. Other types of materials may also be used to form alignment panel 404 . For a 700 mm x 700 mm panel, the thickness of the alignment panel 404 may be approximately 2 mm. Alignment panel 404 may also be of other thicknesses. For example, the thickness may depend on the size and material of the alignment panel 404 .

In Figure 4b, the top surface or bonding surface 405 of the alignment panel 404 is prepared. In one embodiment, panel preparation includes grinding the top surface 405 to create a thickness parallel to the alignment panel 404 . The grinding process ensures the flatness of the alignment panel 404 and produces a scratch-free top or active surface 405 . In some embodiments, the bottom or non-bonding surface 406 may be similarly ground to ensure that it is free of dents and burrs. In some embodiments, the binding surface 405 of the alignment panel 404 may be hardened to prevent scratch formation or panel discoloration.

Referring to FIG. 4c , local alignment marks 450 are formed on alignment panel 404 . The local alignment marks 450 may be formed based on the CAD design file of the alignment panel 404 . In one embodiment, the local alignment marks 450 are formed by laser drilling. Local alignment marks 450 may also be formed by other techniques. For example, local alignment marks 450 may be formed using mechanical drilling, etching, or other material removal processes. In a preferred embodiment, the local alignment marks 450 are formed using a high precision system to ensure accurate hole-to-hole throwing. The hole-to-hole spacing depends, for example, on the die size and layout of the alignment panel 404 . Preferably, the local alignment marks 450 are shallow to facilitate recycling by removing them, eg, by grinding. The local alignment marks 450 may be approximately 25 um deep. Local alignment marks 450 may also be of other depths.

As shown in Figure 4d, tape 422 is applied on the active surface 405 of the alignment panel 404. For example, tape 422 may be referred to as panel tape. Panel tape 422 is applied on the active surface 405 of the alignment panel 404 in preparation for die bonding. For example, panel tape 422 covers active surface 405 . In one embodiment, the panel tape 422 is a thermal or heat release tape. Other types of panel tape can also be used to facilitate die bonding. The panel tape 422 should be transparent enough to allow the camera of the binding tool to detect the local alignment marks 450. For example, the panel tape 422 may be transparent or translucent to enable the camera's light to penetrate the panel tape 422 and detect the local alignment marks 450 . Furthermore, the tack of the panel tape 422 should be strong enough to hold the die in place once aligned and placed thereon by the bonding tool. After the panel tape 422 is applied, the alignment carrier 404 is ready for die bonding.

Figures 5a to 5b illustrate an embodiment of pattern matching of AutoCAD (CAD) files to die and alignment panels. Referring to Figure 5a, an image of the die 510 of the alignment panel and an image of the die bonding area 530 are shown, eg captured by an alignment module of a bonding tool.

With respect to die 510 , the active surface includes die features 512 . The die features 512 of the active surface of the die 510 may be via openings in the buffer layer. A corresponding CAD die file 513 for die 510 is shown. For example, CAD die file 513 contains information related to die 510 . For example, CAD die file 513 includes CAD die feature 514 corresponding to die feature 512 on die 510 . The information contained in the CAD die file 513 is based on green data. For example, green data refers to design data. In one embodiment, the CAD die file includes the coordinate locations of the die features 512 . The coordinate location of the die feature 512 may be the center point of the die feature 512 . For example, the file may be a text file that includes coordinate locations corresponding to the centers of die features 512 .

In some cases, there may be different files containing die feature information. For example, there may be a design file containing the shape of the feature and a coordinate file containing the coordinates of the grain features within the grain. For example, the coordinates file may be a text file containing coordinates corresponding to the center points of the die features 512 . The coordinate file may be referred to as a CAD grain file 513 .

In one embodiment, CAD die reference points 516 are defined. Preferably, at least 2 CAD die reference points 516 are defined. As shown, the CAD die reference points 516 include 2 die reference points. For example, the first and second CAD die reference points are vertically aligned. Other arrangements or numbers of CAD die reference points 516 are also possible. CAD die reference points 516 are used for alignment purposes. By using 2 or more CAD die reference points 516, translational and angular (rotational) alignment can be achieved. The location of the CAD die reference point 516 may be arbitrarily chosen by, for example, the designer of the die 510 . The locations of CAD die reference points 516 may be identified based on their relative positions to CAD die features 514 , including the contours or corners of die 510 .

As for die bonding area 530 , it includes local alignment marks 550 . A corresponding CAD panel file 533 is shown aligned to the die bond area 530 on the panel. For example, CAD panel file 533 is the CAD file for the panel object, which is die bound area 530 . For example, CAD panel file 533 contains information related to die bond area 530 . CAD panel file 533 includes CAD panel features 537 . The CAD panel features 537 are located within the CAD die bonding area, which corresponds to the location of the local alignment marks 550 of the die bonding area 530 .

Similarly, there may be different files that contain panel feature information. For example, there might be a design file containing the shape of the feature and a coordinate file containing the coordinates of the panel feature within the die bound area. The coordinate file is, for example, a text file containing coordinates corresponding to center points of panel features, such as local alignment marks 550 . The coordinate file may be referred to as the CAD panel file 533 .

In one embodiment, a CAD panel reference point 539 is defined. Preferably, at least 2 CAD panel reference points 539 are defined. CAD panel reference point 539 is used for alignment purposes. As shown, the CAD panel file 533 includes 2 CAD panel reference points 539. Translation and angular (rotational) alignment can be achieved by using 2 or more CAD panel reference points 539. In one embodiment, the location of the CAD panel reference point 539 is selected to correspond to the location of the CAD die reference point 516 for die bond alignment. The positions of CAD panel reference points 539 may be identified based on their relative positions to CAD panel features 537 .

In Figure 5b, CAD die file 513 is best suited for die 510. For example, CAD die feature 514 is the die feature 512 that best fits die 510 . This results in a die 510 having a CAD die reference point 516 being positioned on the die 510 based on the CAD die file 513 . Similarly, the CAD panel file 533 is the closest match to the die bond area 530 on the alignment panel. For example, CAD panel features 537 are best suited to align local alignment marks 550 on the panel. This results in the die bond area 530 having a CAD panel reference point 539 . The CAD panel reference point 539 is positioned on the die bonding area 530 of the alignment panel based on the CAD panel file 533 . When the CAD die reference point 516 is aligned with the CAD panel reference point 539 , the die 510 is aligned with the die bonding area 530 .

Figure 5c shows a simplified diagram of the die bonder aligning the die for bonding to the alignment carrier. As shown, the alignment carrier 504 is mounted on the stage of a die bonder (not shown). A bonding head (not shown) of the die bonder picks up the die 510 for bonding to the alignment carrier 504 . The camera 596 of the die bonder extends into position for aligning the die 510 with the carrier 504 . In one embodiment, the cameras 596 are collinear up and down cameras. For example, camera 596 is looking up and imaging the active surface of die 510 and looking down and imaging alignment carrier 504 under the same line of sight. Camera images of die 510 and alignment carrier 504 are shown. For example, a camera image of die 510 shows die features 510 , while a camera image aligned with carrier 504 shows die bond regions 530 with local alignment marks 550 .

The die binder includes memory that stores CAD die files 513 and CAD panel files 533 . The CAD die file 513 is best suited for the image of the die 510, while the CAD panel file 533 is best suited for the die bonding area 530 of the alignment panel (as shown in Figure 5b). In one embodiment, the bond head of the die bonder positions the die 510 over the alignment panel 504 such that the CAD die reference point 516 is aligned with the CAD panel reference point 539, indicating that the die 510 is aligned with Die bond regions 530 on panel 504 are aligned. When die 510 is aligned with die bonding area 530 , camera 596 retracts, enabling the bonding head to move vertically downward to bond die 510 to die bonding area 530 .

In one embodiment, a block of alignment panel 504 is die-bonded to the die-bonding area one die at a time. For example, the first die is bound to the first die binding region of the block of the alignment panel 504 . The first die and the first die bonding region may be referred to as the selected die and the selected die bonding region. Binding the selected die includes the die binder picking up the selected die, aligning the selected die with the selected die binding area, and binding the selected die to the selected die binding area. After the selected die is bound to the selected die binding area, the die binder will determine whether there are other die binding areas in the block that need to be processed. If there is, the die binder picks up the next selected die to bind to the next selected die binding area of the block. The Next Selected Die and Next Selected Die Binding Area become Selected Die and Selected Die Binding Area. The process of binding the selected die to the selected die binding area is repeated until all the die binding areas of the block have been processed. After the block processing is completed, the die binder will determine whether there are other blocks aligned with the panel 504 that need to be processed. If so, the die binder processes the remaining blocks until all of the blocks aligned with panel 504 have been processed.

As described above, the alignment panel 504 includes local alignment marks 550 formed thereon with high precision at predetermined positions. Local alignment marks 550 and die features 512 (eg via openings) are used as fiducials and are matched with the corresponding CAD files (CAD die file 513 and CAD panel file 533) for die 510 and alignment panels 504 reference. The binder has upward and downward cameras to align the die 510 with the panel 504 with the same line of sight. Various features enable die 510 to be precisely bonded to alignment panels with high yield and high placement accuracy of 3 um, XY repeatability of +/-0.5 um, and theta repeatability of +/- ^004o . Additionally, pre- and post-bind checks can be easily performed. In addition, high precision and high throughput increase yield and simplify downstream processing of reconstituted wafers, thereby reducing manufacturing costs and increasing yield.

6a-6e are simplified cross-sectional views depicting embodiments of a process for forming a reconstituted wafer and preparing the reconstituted wafer for further processing. Referring to FIG. 6a , the alignment panel 604 includes a panel binding surface 605 and a panel non-binding surface 606 . Panel bond surface 605 includes local alignment marks 650 for die bond areas thereon. Panel tape 622 is applied to panel binding surface 605 . Die 610 is bonded to the die bonding area of alignment panel 604 by a die bonder. As previously described, the die bonder uses local alignment marks 650 to align and bond the die 610 to the die bond area. Panel tape 622 attaches die 610 to the die bond area of alignment panel 604 .

As shown, alignment panel 604 includes a die 610 . Die 610 includes alignment die 612 and active die 611 . For example, the alignment die 612 may be located at the corner die bond regions of the block. Accordingly, the simplified cross-sectional view illustrates the first row, last row, first column, or last column of die 610 of the block.

Referring to Figure 6b, the alignment panel 604 combined with the die 610 is subjected to a molding process. For example, molding compound 670 is formed over alignment panel 604 , covering it and die 610 . Mold compound 670 and die 610 may be referred to as a molded panel or reconstituted wafer 665, while molded panel 665 and alignment panel 604 may be referred to as a panel assembly or reconstituted wafer assembly. The molding compound 670 may be in the form of powder/granule, liquid or film. In one embodiment, compression molding is performed to form molding compound 670 . Other techniques for forming molding compound 670 may also be useful. The molding process is a high temperature process. For example, the alignment panel 604 with the die 610 is subjected to high temperature and pressure, eg, about 150-180°C and 240-320TF. The material of the alignment carrier 604 can withstand the conditions of the molding process without deformation, warping or damage. In addition, due to the low CTE material of the alignment carrier 604, linear changes due to temperature changes are minimized.

As shown in Figure 6c, the top surface of the molding compound 670 of the reconstituted wafer 665 is ground using, for example, a grinder 608. The grinder 608 includes, for example, a grinding wheel for grinding the top surface of the molding compound 670 . The surface of the molding compound 670 may be ground such that the reconstituted wafer 665 has a desired or defined height and ensures a uniform thickness to relieve stress.

Referring to FIG. 6d , the reconstituted wafer 665 is released from the alignment panel 604 . In one embodiment, releasing the reconstituted wafer 665 from the alignment panel 604 includes subjecting the reconstituted wafer components to a high temperature process, eg, about 210 degrees Celsius. The high temperature peel process causes the panel tape 622 to lose its adhesive properties, thereby enabling the reconstituted wafer 665 to be separated from the tape 622 and alignment panel 604 . For example, the peeling process may include peeling the panel tape 622 from the alignment panel 604 and then peeling the panel tape 622 from the reconstituted wafer 665 . Alternatively, the release process may release the reconstituted wafer 665 from the panel tape 622 and then peel the panel tape 622 from the alignment panel 604 . Other techniques for releasing reconstituted wafer 665 from reconstituted wafer components may also be useful.

In one embodiment, the released reconstituted wafer 665 is mounted on a carrier substrate 694, as shown in Figure 6e. Carrier substrate 694 serves as a substrate for downstream processing of reconstituted wafer 665 . For example, carrier substrate 694 should be rigid enough to support reconstituted wafer 665 for downstream processing, such as forming interconnects or conductive traces on reconstituted wafer 665, carrier substrate 694 may be formed of metal. For example, carrier substrate 694 may be similar to alignment panel 604 except that local alignment marks 650 are not required. Other types of materials may also be used to form carrier substrate 694 .

Carrier tape 623 is applied to a surface, such as the top surface. For example, carrier tape 623 may be a thermal or thermal release tape. Other types of tape may also be used to facilitate bonding of reconstituted wafer 665 to carrier substrate 694 . Reconstituted wafer 665 is attached to carrier substrate 694 using carrier tape 623 . In one embodiment, the active surface of the reconstituted wafer 665 is exposed (face up). For example, the passive surface of reconstituted wafer 665 is bound to carrier substrate 694 . The carrier substrate 694 with the reconstituted wafer 665 may be referred to as a carrier reconstituted wafer element.

Figures 7a to 7c depict an embodiment of a Die Location Check (DLC) process on a reconstituted wafer. Referring to Figure 7a, a carrier reconstituted wafer assembly is shown. The carrier reconstituted wafer assembly includes a reconstituted wafer 765 mounted face-up on a carrier substrate (not shown). Reconstituted wafer 765 includes die 710 with molding compound 770 . The active surface of die 710 is visible. As shown, the dies 710 of the reconstituted wafer 765 are arranged in four blocks 715. Blocks 715 are arranged in a 2x2 block matrix arrangement. The die 710 of each block 715 includes an alignment die 712 and an active die 711 . Alignment die 712 may be used for alignment purposes only or may be active die 711 for alignment purposes. Each block 715 may include 4 alignment dies 712 _1-4 . In one embodiment, alignment dies 712 _1-4 are located at the corners of block 715 . Alignment die 712 may also be positioned at other locations.

Referring to Figure 7b, the DLC process scans the reconstituted wafer 765. In one embodiment, the DLC employs multiple cameras to scan the reconstructed wafer 765. In one embodiment, the DLC scan employs the first and second cameras (Camera A and Camera B) to scan the reconstructed wafer 765. As shown, camera A scans the first camera area 792 of the reconstructed wafer 765 (left half); camera B scans the second camera area 794 of the reconstructed wafer 765 (right half). For example, camera A scans all of the first and second blocks 715 _1-2 on the left half of the reconstructed wafer 765 and camera B scans the third and fourth blocks 715 ₃ on the right half of the reconstructed wafer 765 _-4 for all.

The DLC scan identifies the aligned die 712 of each block 715 to determine the zero or origin (0,0) on a Cartesian coordinate system. In one embodiment, the zero point is the alignment die 712 ₁ at the upper left corner of the block 715 . For example, the zero point is the alignment die 712 ₁ at the upper left corner of each block 715 . The zero point can also be set at other locations in block 715 . Preferably, the zero point of each block 715 is located at the same location. It may also be useful to locate the zero or origin of different blocks 715 at different locations.

In _one embodiment, the zero point is based on the point on the alignment die 7121. The zero point may correspond to, for example, the center point _of alignment die 7121. For example, the scan can determine the corner of the alignment die 7121, and the center _of the corner can be the zero point. It may also be useful to provide zeros corresponding to other locations or features _of alignment die 7121.

As shown in Figure 7c, the DLC process scans the entirety of each block 715 of the reconstituted wafer 765. For example, in this case, each camera scans blocks 715 in its respective camera area, which includes a plurality of blocks 715, at a rate of one block 715 at a time. In each block 715, the camera images multiple dies 710 at a time. For example, each camera images one sub-block 718 of die 710 of block 715 at a time. For example, the scan pattern of block 715 may be left-to-right and top-to-bottom. Other scan modes for scanning blocks may also be useful. The scan produces a complete image of each block 715.

The image size of the sub-block 718 may be, for example, about 14×10 mm. _An image showing sub-block 7181 is provided. The image shows sub-block _718i in more detail. Illustratively, sub-block _718i includes 12 dies 710 arranged in a 3x4 matrix. Other image sizes for sub-block 718 may also be useful. For example, the image size may be selected to accommodate other numbers of dies 710 . Sub-block 718 ₁ includes an origin-aligned die 712 _{1 located in the upper left corner of block 715 1 .} For example, sub-block 718 ₁ is the first sub-block of first block 715 ₁ .

As shown, the aligned die ₇₁₂₁ is different from the active die 711. For example, aligned die features are different from active die features. As shown, alignment die 712 ₁ includes 2 large alignment die features (large vias) with smaller alignment die features (smaller vias) arranged along a line therebetween. Other arrangements of alignment die features may also be useful. As for the active die 711, they each include 2 rows of active die features (vias). The vias of the active die 711 are smaller _than the vias of the aligned die 7121. Other arrangements of grains or grain features may also be useful.

The origin aligned with die 712 ₁ forms the zero point of block 715 ₁ . For example, the x and y coordinates of the zero point aligned with die _712i are (0,0) corresponding to the Cartesian system of block _715i . In _one embodiment, the zero point corresponds to the center point of the alignment die 7121. It is also useful to provide zeros corresponding to other locations _of the alignment die 7121. For example, the zero point may be determined by using other alignment die features or offsets _of alignment die features of alignment die 7121.

Sub-block 718 ₁ includes sub-block reference point 719 . Sub-block reference points 719 may be defined using a CAD sub-block file, similar to the CAD die file depicted in FIG. The die features of die 710 are located in the CAD die file based on the green data. For example, the spacing of the grains, the size of the grains, and the location of the grain features are all based on green materials. For example, sub-block reference point 719 is a virtual sub-block reference point for sub-block 718 ₁ . The location of the sub-block reference point 719 can be predefined in the CAD sub-block file. The location of the sub-block reference point 719 may be based on one or more characteristics of one or more dies of the sub-block 718 ₁ . As shown, the sub-block reference point 719 is offset from the zero point or alignment die 712 _{1 at the upper left corner of the sub-block 718 1 .}

In one embodiment, the sub-block reference point 719 of the sub-block 718 ₁ includes the first and second reference points. As shown, the first and second reference points are arranged vertically. For example, the second reference point is offset from the first reference point. The use of at least two sub-block reference points 719 enables translational and angular alignment. Other arrangements of first and second reference points may also be useful. Similar to the die reference point, the sub-block reference point 719 is a virtual sub-block reference point.

In _one embodiment, the coordinate points of sub-block 7121 are defined. Subblock coordinate points can be arbitrarily defined. For example, a sub-block coordinate point may be defined by selecting a die feature of one of the dies 710 of the sub-block 718 ₁ . The sub-block coordinate points may be offset from the zero point of block 715 . In some cases, the sub-block coordinate point may be _one of the sub-block reference points 719 of sub-block 718i. In other cases, the sub-block coordinate point may be the zero point of sub _- block 7181. In this case, the sub-block coordinate point of sub-block 718 ₁ does not deviate from the zero point of sub-block 718 ₁ .

As discussed, the scan generates images of sub-block 718 of block 715 . The coordinate points of the other sub-blocks 718 of block 715 are generated relative to the zero or origin. Determining the coordinate points of the other sub-blocks is similar to generating the coordinate points of the first sub-block 718 ₁ .

In one embodiment, the zero point is determined based on the _first sub-block 718i. Based on the zero point, the positions of other sub-blocks can be determined. For example, using the green profile, the spacing of other sub-blocks can be determined. For example, the center of the upper left die of each sub-block may be the sub-block coordinate point of each sub-block of that block. It may also be useful to choose another location for the subblock coordinate points. The sub-block coordinate points may be referred to as indexed nominal coordinate points because they are determined based on the green data about the zero point.

In one embodiment, the CAD sub-block file is the best-fit sub-block image. A best fit is performed on each subplot. The best fit may result in an offset of the nominal coordinate point relative to the index of each sub-block. The virtual sub-block reference points are also offset. This produces a DLC file, which is a map of blocks, containing sub-block coordinate points and their virtual sub-block reference points.

In one embodiment, one DLC file is generated for each block. The material contained in a DLC file may be in DLC format. For example, the DLC file of block 715 is used to generate an LDI file for downstream laser direct imaging (LDI) processing, such as forming traces on block 715 of reconstructed wafer 765 . For example, LDI files can be read by LDI tools, such as laser direct imagers.

The image of sub-block 718 ₁ shown in FIG. 7c is the first sub-block of the first block 715 ₁ . In particular, the first sub-block 718 ₁ includes an alignment die 712 _{1 that is the zero of the first block 715 1 .} Other sub-blocks of the block can have different arrangements. For example, the alignment die 712 may be located at a different location on the sub-block or the sub-block may not include the alignment die.

Figure 7d shows images of different arrangements of sub-blocks 718 of the block. As shown, each arrangement of sub-blocks 718 is a 3x4 matrix. An image of the regular sub-block _718G and the first, second, third and fourth corner sub-blocks 718 _1-4 are shown. The first corner sub-block 718 ₁ includes a first aligned die 712 ₁ disposed in the upper left corner of the sub-block, and the active die 711 is disposed elsewhere in the sub-block. The second corner sub-block 718 ₂ includes a second aligned die 712 ₂ disposed in the lower left corner of the sub-block matrix and an active die 711 disposed elsewhere in the sub-block. The third corner sub-block 718 ₃ includes a third aligned die 712 ₃ disposed in the upper right corner of the sub-block matrix and an active die 711 disposed elsewhere in the sub-block. The _fourth corner subblock 7184 includes a _fourth alignment die 7124 disposed in the lower right corner of the subblock matrix and an active die 711 disposed elsewhere in the subblock. As for general sub-block _718G , it does not include any alignment die 712, only active die 711.

One of the corner blocks 718 _1-4 is selected to align die 712 as the zero point for block 715. For example, the first aligned die 712 ₁ of the first corner sub-block 718 ₁ may be selected as the zero point of the block 715 . The coordinate points of the other sub-blocks 718 are relative to the zero point.

The block 715 includes aligned dies 712 at the corners of the block 715 as depicted in FIG. 7d. However, other arrangements of alignment dies 712 for block 715 may also be useful. In such cases, the arrangement of dies 710 of sub-block 718 may vary based on the arrangement of aligned dies 712 of block 715 as described in FIG. 7d.

Figures 8a to 8c illustrate an embodiment of generating a circuit file for forming conductive traces on a reconstituted wafer. In Figure 8a, an image of the _first sub-block 8181 of the reconstructed wafer is shown. For example, sub-block 818 ₁ includes a 3×4 matrix of dies 810 . Illustratively, sub-block 818 ₁ includes origin-aligned die 812 ₁ and active die 811 . As shown, origin-aligned die 812 ₁ is a dedicated alignment die 812 with different characteristics than active die 811 . Alternatively, the aligned die ₈₁₂₁ may be the active die 811. As mentioned above, the coordinate points of all sub-blocks of a block are generated relative to the origin and provided in the DLC file. Additionally, virtual subblock reference points 819 may be provided from the subblock CAD file.

Referring to Figure 8b, a circuit file 817i corresponding to the _first sub-block of the die is shown. For example, the circuit file corresponds to the first subblock with origin-aligned die. The circuit file includes the circuits for the dies of the sub-blocks. In one embodiment, the circuit file is based on green or design data. For example, the placement of the circuit is based on the designed die pitch and location and the die characteristics of the sub-block.

The circuit file for the first sub-block includes locations 813 to align the die. As shown, no circuit pattern is provided for aligning the dies. For the circuit file of the sub-block, the die is not aligned, and there will be a circuit pattern of the die where the die is aligned. In some cases, the location 813 for aligning the die may be at other locations on the sub-block. In this case, no circuitry is provided at location 813 where the die is aligned. The circuit of the circuit file for the die of the sub-block is not adapted. For example, according to the green material, the circuit is located in the circuit file. The circuit file includes sub-block circuit reference points 849 . As shown, the sub-block circuit reference points 849 include first and second sub-block reference points. It may also be useful to provide other numbers of sub-block circuit reference points 849. The sub-block circuit reference point 849 corresponds to the sub-block reference point on the DLC file.

In Figure 8c, the LDI file is generated. As shown, the circuit files for the first sub-block are aligned and appended to the first sub-block _818i . For example, the sub-block circuit reference point 849 of the first corner sub-block circuit file 817 ₁ is aligned to the first sub-block reference point 819 of the first sub-block 818 ₁ of the DLC file. Alignment and appending of the sub-block's circuit file is performed on all sub-blocks of the block. For example, according to the sub-block coordinates in the DLC file, align and attach the corresponding circuit file. This generates an LDI file, which is used for downstream processing, eg, generating traces on alignment vectors. LDI files are in a format readable by the LDI tool.

Figure 8d shows a different arrangement of the sub-block circuit file 817. As shown, the sub-block circuit file 817 includes a general sub-block circuit file _817G and a corner sub-block circuit file 817i- ₄ . The first corner sub-dice circuit file _817i includes a _first aligned die location 813i in the upper left corner. The _second corner sub-dice circuit file 8172 includes a _second aligned die location 8132 in the lower left corner. The _third corner sub-block circuit file 8173 includes a _third aligned die location 8133 in the upper right corner. The _fourth corner sub-block circuit file 8174 includes a _fourth aligned die location 8134 in the lower right corner. There is no circuit pattern provided for the aligned die locations of the sub-block circuit files 817 _1-4 . For the generic sub-block circuit file _817G , it includes circuit patterns for all die locations.

As described in Figure 8d, a sub-block circuit file 817 is used to include die aligned blocks at the corners of the blocks. However, other arrangements of aligned dice of the blocks may also be useful. In this case, the circuit arrangement of the sub-block circuit file 817 may differ from that described in Figure 8d, depending on the alignment of the die arrangement of the blocks.

9a-9e show simplified cross-sectional views of a carrier reconstituted wafer assembly illustrating an embodiment of a process for forming traces on a reconstituted wafer. Referring to Figure 9a, a carrier reconstituted wafer assembly is shown. The carrier reconstituted wafer assembly includes a reconstituted wafer 965 attached to a carrier substrate 994 with carrier tape 923 . The reconstituted wafer includes die 910 encapsulated in molding compound 970 . As shown, a simplified cross-sectional view of reconstituted wafer 965 is a row or column of blocks of dies 910 , including aligned dies 912 and active dies 911 . For example, a row or column can be the last or first row or column of a block. Alignment die 912 is located at the end of a row or column of blocks. Die 910 includes features as vias 962 in buffer layer 960 to expose die bond pads of die 910 . Illustratively, the features of the aligned die 912 are different from the features of the active die 911 . In other embodiments, the alignment die 912 may be the same as the active die 911 .

In Figure 9b, a conductive or metal layer 980 is formed. For example, the conductive layer 980 may be a copper (Cu) layer. Other types of conductive layers can also be formed. As shown, conductive layer 980 fills vias 962 of die 910 . The conductive layer 980 may be formed by, for example, an electroplating process. Other techniques may also be employed to form conductive layer 980 . The conductive layer 980 may be referred to as a conductive filling layer 980 .

In one embodiment, a metal seed layer 981 is formed on the reconstituted wafer 965 and a conductive fill layer 980 fills the vias 962 . The seed layer may be, for example, a titanium (Ti) layer formed by sputtering. Other types of seed layers or techniques for forming seed layers may also be useful.

Referring to FIG. 9c, after formation of the seed layer 981, after removal of the excess conductive layer 980, a thin film 982 is formed over the surface of the reconstituted wafer 965. For example, thin film 982 covers seed layer 981 . In one embodiment, the film is a laser-imageable film, such as a photoresist. In one embodiment, the laser-imageable film 982 is a film 982 laminated to the surface of the reconstituted wafer 965 . Other types or techniques for forming the laser-imageable film 982 may also be useful.

Film 982 is patterned to form openings 984 as shown in FIG. 9d. In one embodiment, the pattern of patterned dry film 982 corresponds to a circuit pattern or trace to be formed on reconstituted wafer 965 . In one embodiment, the dry film 982 is patterned by an LDI tool using laser direct imaging (LDI). For example, LDI tools use a laser to expose dry films. The exposure has the desired pattern. For example, the desired pattern is based on an LDI file. For example, the LDI file is generated as described in Figure 8c. In one embodiment, the LDI file is used to form the traces of the active die 911 of the block. The LDI file can be used to form other types of interconnects, such as redistribution layers (RDLs), for the active die 911 of the block. The exposed dry film 982 is developed to form openings 984 therein.

Referring to Figure 9e, the process continues to form conductive traces 986 that fill openings 984 in dry film 982. The conductive traces 986 include, for example, Cu or a Cu alloy. Other types of conductive traces 986 may also be useful. In one embodiment, the conductive traces 986 are formed by electroplating. The plating process fills the openings 984 in the dry film 982 . The plating process is slowly stopped below the height of the dry film 982 . The plating process forms conductive traces 986 in the openings 984 of the dry film 982 . As shown, dry film 982 is patterned to expose seed layer 981, eg, near the edge of reconstituted wafer 965. This facilitates the electroplating process.

After the conductive traces 986 are formed, the dry film 982 is removed, as shown in Figure 9f. Exposed portions of seed layer 981 are removed. For example, the seed layer 981 can be removed using dry etching. Other types of etching processes may also be employed to remove exposed portions of seed layer 981 . After removing the exposed portion of the seed layer 981, the process may continue. For example, the process may continue to singulate the reconstituted wafer 965 into individual packages.

Alternatively, the process may continue to form additional metal layers of the RDL structure over die 910 . For example, the dry film, exposure and electroplating processes can be repeated until the RDL structure is completed. The reconstituted wafer 965 may be diced into individual packages.

Figures 10a-10b show simplified cross-sectional and top views of an exemplary embodiment of a package with conductive traces. Referring to Figure 10a, a top view 1007a of the package 1007 and a cross-sectional view 1007b along A-A' are shown. As shown, package 1007 includes a single die 1011 . For example, package 1007 is a single die package with one die 1011 . Die 1011 is encapsulated by molding compound 1070 . As shown, the passive surface (without buffer layer 1060 ) and side surfaces of die 1011 and the side surfaces of buffer layer 1060 are protected by molding compound 1070 . As for the active surface of die 1011 , it is protected by buffer layer 1060 . Other arrangements of packages 1007 may also be useful.

The buffer layer 1060 includes via openings filled with conductive fillers 1080 . The conductively filled via openings may be referred to as via contacts. In one embodiment, the conductive traces 1086 are disposed over the via contacts. For example, the pattern of conductive traces 1086 is defined by an LDI file. In one embodiment, portions of conductive traces 1086 above the conductive vias form annular rings 1089 . An annular ring 1089 surrounds the circumference of the through-hole contact. In one embodiment, the width W of the annular ring 1089 is formed with high precision or tolerance. For example, the width W of the annular ring 1089 may be approximately 15 um. Other widths of annular ring 1089 may also be useful. This allows for a more compact layout of the die 1011, resulting in a smaller package footprint.

FIG. 10b shows a top view 1007a and a cross-sectional view 1007b along AA' of another embodiment of the package 1007 . Package 1007 is a multi-die package. As shown, the multi-die package 1007 includes first and second dies 1011 _1-2 . It may also be useful to provide the multi-die package 1007 with other numbers of dies 1011 . Dies 1011 _1-2 are wrapped with molding compound 1070 . As shown, the passive and side surfaces of die 1011 and buffer layer 1060 are protected by molding compound 1070 . As for the active surface of die 1011 _1-2 , it is protected by buffer layer 1060. Other arrangements of packaging may also be useful.

The buffer layer 1060 includes via openings filled with conductive fillers 1080 . Conductive filled vias may be referred to as via contacts. In one embodiment, the conductive traces 1086 are disposed over the via contacts. For example, the pattern of conductive traces 1086 is defined by an LDI file. The pattern of conductive traces includes interconnections between the first and second dies 1011 _1-2 . For example, conductive traces 1086 may be interconnected through contacts of the first and second dies 1011 _1-2 . In one embodiment, portions of conductive traces 1086 over the via contacts form annular rings 1089 . An annular ring 1089 surrounds the circumference of the via contacts. In one embodiment, the width W of the annular ring 1089 is formed with high precision or tolerance. For example, the width W of the annular ring 1089 is about 15 um. This enables a more compact layout of the die 1011 _1-2 , resulting in a smaller package footprint.

Figures 11a to 11b illustrate an embodiment of defining dicing or sawing lines for a reconstituted wafer. Referring to Figure 11a, a grid of dicing or saw lines 1173 is generated for the die blocks of the reconstituted wafer.

Wire grid 1173 is created using the average x and y values of die 1110 for each row and column of die 1110 of block 1115 . For example, the grid of saw lines 1173 is created using the average x and y values of adjacent rows and columns of die 1110 of block 1115 . In one embodiment, the average x and y values are based on x and y measurements of the rows and columns of the die 1110 of the block 1115 . xwire 1187 is based on the measured y value of the die 1110 of the adjacent die row and y wire 1188 is based on the measured x value of the die 1110 of the adjacent die column. In one embodiment, xwire fiducial point 1177 is based on the measured y value of die 1110 of an adjacent die row and y wire fiducial point 1178 is based on the measured x value of die 1110 of an adjacent die column. The x datum 1177 and the y datum 1178 define the x saw line 1187 and the y saw line 1188 of the block 1115 , forming a saw line grid 1173 . The wire grid 1173 may be referred to as a dynamic wire grid, for example, since the pitch may vary according to the measurements of the rows and columns of the die 1110 .

In one embodiment, the wire mesh 1173 is the block 1115 that best fits the die 1110 . In one embodiment, the wire grid 1173 is best adapted to the block 1115. The x wire reference point 1177 and the y wire reference point 1178 are determined relative to the origin of the block 1115 . The x and y wire reference points 1177 , 1178 are provided in the e-map file at block 1115 . The e-map file can be merged with the circuit pattern into the LDI file to form fiducials for the saw line during the trace making process. Physical saw line fiducials on the reconstituted wafer may be identified by the saw tool during singulation of the reconstituted wafer.

In another embodiment, the wire grid 1173 may be based on measurements of sub-blocks of the block 1115 . For example, based on the subblock coordinate points for each subblock, the average x and y values for each row and column can be extrapolated to generate a grid of saw lines 1173 . The wire mesh 1173 is then best fitted to block 1115 to generate x and y wire fiducials 1177, 1178, which are provided in the e-map file at block 1115.

Referring to FIG. 11b, another embodiment of saw lines for determining blocks 1115 of reconstituted wafers. Block 1115 includes dies 1110 arranged in rows and columns. For example, the dies 1110 of the block 1115 are arranged in a 3x4 matrix. Matrices of other sizes may also be useful. As shown, dies 1110 include alignment dies 1112 disposed at corner locations of blocks 1115 . The remaining locations of block 1115 include active die 1111 .

In one embodiment, the saw wire is determined based on an averaging technique. For example, the averaging technique is used when a saw line is located between adjacent rows or adjacent columns of a die. The averaging technique includes generating an x-average line 1197 and a y-average line 1198 for each column and row of the die. A mean line is generated using the centers of all grains 1110 . For example, the centers of the grains 1110 in each row are connected in the row or x-direction to form the row or x-mean line 1197; the centers of the grains 1110 in each column are connected in the column or y-direction to form the column or y-mean line 1198.

In one embodiment, the number of x saw lines 1187 is equal to the number of rows in block 1115 plus one, and the number of y saw lines 1188 is equal to the number of columns in block 1115 plus one. In one embodiment, the x wires 1187 are parallel to each other and the y wires 1188 are parallel to each other. Since the average x and y lines are based on the actual measured positions of the die 1110 of the block 1115, the x and y saw lines 1187, 1188 may have variable pitches. The x and y line datum points 1177 and 1178 are provided in the e-map file. e-map files can be incorporated into LDI files along with circuit patterns to form fiducials for saw lines during trace fabrication. The physical wire fiducials on the reconstituted wafer can be identified by the dicing tool during the dicing process of the reconstituted wafer.

In another embodiment, the wire mesh 1173 may be based on measurements of sub-blocks of the block 1115 . For example, based on the sub-block coordinate points for each sub-block, the mean lines 1197 and 1198 of the die 1110 may be extrapolated to generate the saw line reference points 1177 and 1178 .

The present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics of the present disclosure. Accordingly, the foregoing embodiments are to be considered in all respects to be illustrative and not restrictive of the invention described herein. Therefore, the protection scope of the present invention is defined by the scope of the patent application, and includes the meaning of the scope of the patent application and all changes which are covered by the equivalent scope.

100: semiconductor wafer 110: device/die 180: dicing line/saw line 180 ₁ : first dicing line 180 ₂ : second dicing line 200: process wafer 201: top or active wafer surface 202: bottom or Passive Wafer Surface 210: Die 240: Die Bond Pad 242: Passivation Layer 244: Pad Opening 260: Buffer Layer 262: Via Opening 280: Cut Line 304: Alignment Panel/Alignment Carrier 305: Top face/bond face 306: bottom face 314: active area 330: die bond area 331: active die bond area 336: die bond area 336 _1-4 : aligned die bond area 338: die Attachment Area 350: Local Alignment Marks 404: Alignment Panel/Alignment Carrier 405: Top Surface/Binding Surface/Active Surface 406: Bottom Surface 42: Alloy 422: Tape/Panel Tape 450: Local Alignment Mark 46: Alloy 504: Alignment Carrier/Alignment Panel 510: Die 512: Die Feature 513: CAD Die File 514: CAD Die Feature 516: CAD Die Reference Point 530: Die Binding Area 533: CAD Panel File 537 :CAD Panel Features 539:CAD Panel Reference Points 550:Local Alignment Marks 596:Camera 604:Align Panels 605:Panel Bound Surfaces 606:Panel Unbound Surfaces 608:grinders 610:die 611:active die 612: Align Die 622: Panel Tape 623: Carrier Tape 650: Local Alignment Marks 665: Reconstituted Wafer/Mold Panel 670: Molding Compound 694: Carrier Substrate 710: Die 711: Active Die 712, 712 ₁ , 712 ₂ ,712 ₃ ,712 ₄ : Align Die 715,715 ₁ ,715 ₂ ,715 ₃ ,715 ₄ : Block 718,718 ₁ ,718 ₂ ,718 ₃ ,718 ₄ ,718 _G : Sub-block 719 : Sub-block reference point 765 : Reconstituted Wafer 770: Molding Compound 792: First Camera Area 794: Second Camera Area 810: Die 811: Active Die 812: Aligned Die 812 ₁ : Origin Aligned Die 813: Aligned Die Die Location 813 ₁ : First Aligned Die Location 813 ₂ : Second Aligned Die Location 813 ₃ : Third Aligned Die Location 813 ₄ : Fourth Aligned Die Location 817: Subblock Circuit File 817 ₁ : First corner sub-block circuit file 817 ₂ : Second corner sub-block circuit file 817 ₃ : Third corner sub-block circuit file 817 ₄ : Fourth corner sub-block circuit file 817 _G : General sub-block circuit file 818 ₁ : Sub-block /first sub-block 819: sub-block reference point 849: sub-block circuit reference point 910: die 911: active die 912: alignment die 923: carrier tape 960: buffer layer 962: via 965: reconstituted die Round 970: Molded Plastic 980 : conductive layer/conductive fill layer 981: seed layer/metal seed layer 982: thin film/dry film 984: opening 986: conductive trace 994: carrier substrate 1007: package 1007a: top view 1007b: cross-sectional view 1011, 1011 ₁ , 1011 ₂ : Die 1060: Buffer Layer 1070: Molding Compound 1080: Conductive Filler 1086: Conductive Trace 1089: Ring 1110: Die 1111: Active Die 1112: Alignment Die 1115: Block 1173: Saw Wire Grid 1177 :x line reference point 1178: y line reference point 1187: x line 1188: y line 1197: x average line 1198: y average line

Figure 1 shows a simplified top view of a semiconductor wafer; Figures 2a to 2d illustrate an embodiment of processing a processed wafer; Figure 3a shows a simplified top view of an alignment panel in one embodiment; Figure 3b shows a simplified top view of a portion of an alignment panel in another embodiment; Figures 4a to 4d illustrate an embodiment of a process for preparing an alignment panel; Figures 5a to 5b illustrate an embodiment of matching the pattern of the CAD file to the die and alignment panels; Figure 5c is a simplified illustration of an embodiment of aligning a die with an alignment panel for bonding; 6a-6e illustrate simplified cross-sectional views of embodiments of processes for forming a reconstituted wafer and preparing the reconstituted wafer for further processing; 7a-7c show images depicting embodiments of a die location inspection (DLC) process on a reconstituted wafer; Figure 7d shows images of different arrangements of sub-blocks; Figures 8a-8c illustrate an embodiment of generating a laser direct imaging file for forming traces on the reconstructed wafer; Figure 8d shows different arrangements of sub-block circuit files; 9a-9f show simplified cross-sectional views illustrating embodiments of a process for forming traces on a reconstituted wafer; Figures 10a-10b show simplified top views of embodiments of packages with traces; and Figures 11a to 11b illustrate an embodiment of generating wire fiducials for dicing a reconstituted wafer.

710: Die

711: Active Die

712 ₁ : Align Die

715,715 ₁ ,715 ₂ ,715 ₃ ,715 ₄ : block

718,718 ₁ : Subblock

719: Subblock reference point

765: Reconstructed Wafer

770: Molding compound

792: First camera area

794:Second camera area

Claims (20)

A method for die location inspection (DLC) comprising: A reconstituted wafer providing a die block encapsulated in a molding compound, the die block comprising a plurality of dies arranged in rows and columns to form a die matrix of the die block, wherein a plurality of the dies The grains include aligned grains and active grains; scanning the reconstituted wafer, wherein the scanning includes scanning the die block; and processing the scan information of the die block, wherein the processing includes: identifying the aligned die location of the die block, determining one of the aligned grains of the grain block as the origin of the Cartesian coordinate system of the grain block, Wherein scanning the die block includes scanning the die block by scanning one sub-block at a time, wherein each die block includes dies arranged in a sub-block matrix, the sub-block matrix includes more than the die block a grain matrix with a smaller number of grains, and Coordinate points are assigned to the block of crystal particles in the Cartesian coordinate system. The method of claim 1, wherein the coordinate points of the sub-blocks of the die are relative to the origin. The method of claim 2, wherein the sub-block matrix for each sub-block of the die is the same. The method of claim 1, wherein the grain block includes a locally aligned grain, and the location of the locally aligned grain in the Cartesian coordinate system is a coordinate point of the grain block . The method of claim 1, wherein the reconstituted wafer includes a plurality of die blocks encapsulated in the molding compound. The method of claim 1, wherein the reconstituted wafer includes a plurality of die blocks encapsulated in the molding compound, the die blocks arranged in a block matrix. The method of claim 1, wherein the reconstructed wafer includes 4 blocks arranged in a 2x2 block matrix. The method of claim 6, wherein scanning the reconstructed wafer comprises: scanning the reconstructed wafer with first and second cameras covering at least first and second regions of the reconstructed wafer, wherein the first camera covers a first region of a first block having a matrix of blocks, and the second camera covers a second area of a second block having a matrix of blocks; and processing scan information of the first block and the second block in parallel identifying the aligned die positions of the first block and the second block, designating one of the aligned grains of the first block and the second block as the origin of the Cartesian coordinate system of the first block and the second block, wherein scanning the first and second blocks includes scanning sub-blocks of dies in the first and second blocks one sub-block at a time, and Sub-blocks of grains are assigned coordinate points in a Cartesian coordinate system. The method of claim 1, wherein assigning coordinate points to sub-blocks of die includes defining sub-block reference points for sub-blocks of die, wherein: the sub-block reference points are located at predetermined positions of each grain block, and The sub-block reference point is the coordinate point of the grain block relative to the origin. The method of claim 1, further comprising generating a laser direct imaging (LDI) file for downstream processing of the traces of the reconstructed wafer. The method of claim 9, wherein generating the LDI file comprises: Provides a CAD circuit sub-block file that includes: CAD circuit information for the die of a CAD sub-block, according to the design position of the die of the die block of the reconstructed wafer, and a CAD sub-block reference point, the CAD sub-block reference point corresponding to the coordinate point of each sub-block of the die; and The CAD subblock reference points of the CAD circuit subblock file are aligned with the coordinate points of the die block to generate an LDI file. The method of claim 1, wherein providing the reconstituted wafer comprises: An alignment panel is provided having a bonding face, the bonding face including a die bonding area for bonding dies, wherein the bonding face includes local alignment marks, wherein the bonding face includes a bonding face for facilitating the die Panel adhesive film bonded to the die bonding area; Align the selected die with the selected die binding area using the local alignment marks of the selected die binding area; when the selected die is aligned to the selected die bond region, binding the selected die to the selected die bond region; and The die combined with the alignment panel is encapsulated with molding compound to form the reconstituted wafer. The method of claim 1, wherein scanning the reconstructed wafer further comprises: determining the positions of all dies of the reconstructed wafer relative to the origin in the Cartesian coordinate system; compute the x-saw line in the x-direction of the Cartesian coordinate system between two adjacent rows of grains; and Calculate the y-saw line in the y-direction of the Cartesian coordinate system between two adjacent columns of grains. The method of claim 13, wherein determining the locations of all dies of the reconstituted wafer comprises: calculating the x-mean line for each row of grains in the grain block; setting an x-saw line fiducial point at the midpoint of two adjacent x-mean lines, the x-saw line fiducial point corresponding to the x-saw line of the reconstructed wafer; calculating the y-mean line for each column of grains in the grain block; and A ysawline fiducial point is placed at the midpoint of two adjacent ysaw lines, the ysawline fiducial point corresponding to the ysawline of the reconstructed wafer. The method of claim 13, wherein determining the locations of all dies of the reconstituted wafer comprises: Generate a dynamic saw-line mesh using the average x-value of all grains and the average y-value of all grains in Cartesian coordinates; and A dynamic wire mesh is optimally fitted to the reconstituted wafer by die position. A method of bonding die for panel-level processing, comprising: An alignment panel is provided having a bonding surface, the bonding surface including a die bonding area for bonding the die, wherein the bonding surface includes local alignment marks, wherein the bonding surface includes a a panel adhesive film with the die bound to the die bound region; and Bind selected grains to selected grain binding areas, including: aligning the selected die with the selected die bond region using the local alignment marks of the selected die bond region, and When the selected die is aligned with the selected die bond, bind the selected die to the selected die bond area. The method of claim 16, wherein aligning the selected die to the selected die bonding area comprises: providing a CAD grain file having grain features corresponding to the selected grain features on the selected grain surface and a defined CAD grain reference point; providing a CAD panel file with panel features corresponding to the local alignment marks of the selected die binding area and a CAD panel reference point defined; Image the surface of the selected die using the selected die feature through the camera model, and adapt the CAD die file to the surface of the selected die; using local alignment marks to image the selected die-bound area and to best fit the CAD panel file to the selected die-bound area; and The selected die is aligned with the selected die binding area by aligning the CAD die reference point of the best fit selected die with the CAD panel reference point that best fits the selected die binding area. The method of claim 17, wherein: CAD die reference points include first and second CAD die reference points; and The CAD panel reference points include first and second CAD panel reference points, wherein providing the first and second CAD die reference points and the first and second panel reference points enables translation and angular alignment of the selected die. particle binding region. The method of claim 16, wherein binding the selected die to the selected die binding region comprises: bind the next selected die to the next selected die binding region of the alignment panel; and Repeat binding the next selected die to the next selected die binding area until all the die binding areas aligned to the panel are bound to the die. The method of claim 19, further comprising wrapping the die bound to the die binding area of the alignment panel with a molding compound to form a reconstituted wafer.

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