TW202230674A - A terminal and package used in electronic product - Google Patents

A terminal and package used in electronic product Download PDF

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Publication number
TW202230674A
TW202230674A TW109147107A TW109147107A TW202230674A TW 202230674 A TW202230674 A TW 202230674A TW 109147107 A TW109147107 A TW 109147107A TW 109147107 A TW109147107 A TW 109147107A TW 202230674 A TW202230674 A TW 202230674A
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TW
Taiwan
Prior art keywords
contact
terminal
extension
plastic
contact point
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TW109147107A
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Chinese (zh)
Inventor
王忠寶
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王忠寶
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Application filed by 王忠寶 filed Critical 王忠寶
Priority to TW109147107A priority Critical patent/TW202230674A/en
Priority to CN202111281261.1A priority patent/CN114023732A/en
Publication of TW202230674A publication Critical patent/TW202230674A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A terminal of electronic product and a semiconductor package is disclosed, said terminal includes a conductor, said terminal also enables to include either an opening which is situated at a suitable place on said terminal or an extending portion, in case that a portion of encapsulant received in said opening so as to be coupled with the terminal more securely, then it prevents said terminal from the damage of peeling off caused by external force; when a chip is electrically connected to said terminal by a conductive mean such as a bump, and the tin of said bump is placed in said opening, a solder material such as solder ball coupled with both the lower surface of terminal and the tin of said bump, it can avoid the problem of IMC(intermetallic compound) occurred between said solder ball and said bump, then the reliability of the semiconductor package is enhanced.

Description

一種電子裝置的端點及封裝體 Endpoint and package of an electronic device

一種供電子裝置用的端點,尤指用於半導體的封裝體。 A terminal for an electronic device, especially a package for a semiconductor.

如圖7A~圖7B所示,是無引腳扁平封裝體(QFN)結構,其中,圖7A是俯視圖,圖7B是圖7A切割線CC的剖視圖,封裝體1A包含有:端點3、晶片20、導電件18及塑料60,端點3是框架(lead frame)的一部分,是由C7025系列的銅金屬製成,該端點3具有接點3A、延伸部3C及晶片座(die pad)3P,延伸部3C與接點3A相鄰設置並能電連通,接點3A具有上表面31、下表面32及側邊33,延伸部3C具有上表面31、下表面3C2及側邊33,其中,接點3A及延伸部3C的上表面31是齊平的,依據設計準則:接點3A最小的厚度Ta為127微米(μm),接點3A最小的寬度W是200微米,而二接點3A最小的間隙S是150微米,而延伸部3C最小的厚度Tc是接點3A厚度Ta的一半,也就是64微米,使接點3A下表面32凸出於延伸部3C下表面3C2,並使接合區域3S相對應的下表面3C2區域是懸空的,而距延伸部3C上表面31未端約200微米的區域內,是供導電件18接合的區域3S,且已知塑料60最小的厚度T6是200微米;晶片20,其上表面21具連接墊(bond pad)24,並藉黏膠40與晶片座3P接合;導電件18,實施為導電線,並分別與晶片20連接墊24及接點3A上表面31電連通,使晶片20與接點3A電連通;塑料60,其為絕緣體與端點3接合並包覆晶片20及導電件18,並令接點3A及晶片座3P的下表面32裸露於封裝體1A外;由於電子裝置除了需品質好成本低外,也被要求體積要更薄及更小,經多年的發展,封裝體1A已不易藉框架達到上述的需求,說明如下:1)降低厚度難: 如圖7B所示,封裝體1A厚度是由接點3A及塑料60的厚度Ta、T6疊加組成,使封裝體1A因具有接點3A厚度Ta無法降到最低,再如圖7C所示,是將圖7B接點3A厚度Ta降為30微米的剖視圖,接點3A側邊33與塑料60接合的面積明顯的被降低,當錫Tn與接點3A接合且受外力拉扯時,塑料60與接點3A上表面31及側邊33接合處,易產生剝離的損壞;2)延伸部限制多:如圖7B所示,當長度L過長時,在導電件18與延伸部3C接合過程中,延伸部3C會因剛性不足而產生振動,造成導電件18接合強度不足的損壞,據此,長度L需小於2,500微米,再如圖7C所示,當接點3A厚度Ta降為30微米,而延伸部3C厚度Tc僅為15微米時,因厚度太薄使剛性更不足而無法與導電件18接合,令端點3無法具有延伸部3C;由上述得,需優化封裝體1A以滿足電子裝置的需求。 As shown in FIGS. 7A to 7B , it is a leadless flat package (QFN) structure, wherein FIG. 7A is a top view, and FIG. 7B is a cross-sectional view of the cutting line CC in FIG. 7A . The package body 1A includes: a terminal 3, a chip 20. Conductor 18 and plastic 60, the terminal 3 is a part of the lead frame, which is made of C7025 series copper metal, the terminal 3 has a contact 3A, an extension 3C and a die pad 3P, the extension part 3C is arranged adjacent to the contact 3A and can be electrically connected, the contact 3A has an upper surface 31, a lower surface 32 and a side 33, and the extension 3C has an upper surface 31, a lower surface 3C2 and a side 33, wherein , the top surface 31 of the contact 3A and the extension 3C are flush, according to the design criteria: the minimum thickness Ta of the contact 3A is 127 microns (μm), the minimum width W of the contact 3A is 200 microns, and the two contacts The minimum gap S of 3A is 150 microns, and the minimum thickness Tc of the extension 3C is half of the thickness Ta of the contact 3A, that is, 64 microns, so that the lower surface 32 of the contact 3A protrudes from the lower surface 3C2 of the extension 3C, and makes The region 3C2 of the lower surface corresponding to the bonding region 3S is suspended, and the region about 200 microns from the end of the upper surface 31 of the extension portion 3C is the region 3S for the bonding of the conductive member 18, and the minimum thickness T6 of the plastic 60 is known is 200 microns; the chip 20 has a bonding pad 24 on its upper surface 21 and is bonded to the chip seat 3P by an adhesive 40; the conductive member 18 is implemented as a conductive wire, and is connected to the chip 20 with the bonding pads 24 and 3P respectively. The upper surface 31 of the point 3A is electrically connected, so that the chip 20 and the contact point 3A are electrically connected; the plastic 60 is an insulator that is joined to the terminal point 3 and covers the chip 20 and the conductive member 18, and makes the contact point 3A and the lower part of the chip seat 3P. The surface 32 is exposed outside the package body 1A; in addition to the need for high quality and low cost, electronic devices are also required to be thinner and smaller in size. After years of development, the package body 1A is no longer able to meet the above requirements by means of a framework. The description is as follows : 1) It is difficult to reduce the thickness: As shown in FIG. 7B , the thickness of the package body 1A is formed by the superposition of the thicknesses Ta and T6 of the contact 3A and the plastic 60 , so that the thickness Ta of the package body 1A cannot be minimized due to the contact 3A. As shown in FIG. 7C , it is The cross-sectional view of reducing the thickness Ta of the contact 3A to 30 μm in FIG. 7B , the area where the side edge 33 of the contact 3A and the plastic 60 are joined is significantly reduced. When the tin Tn is joined to the contact 3A and pulled by an external force, the plastic 60 is connected to the contact. The joint of the upper surface 31 and the side edge 33 of the point 3A is prone to peeling damage; 2) The extension has many restrictions: as shown in FIG. 7B, when the length L is too long, during the bonding process of the conductive member 18 and the extension 3C, The extension portion 3C will vibrate due to insufficient rigidity, resulting in damage to the conductive member 18 due to insufficient bonding strength. Accordingly, the length L needs to be less than 2,500 μm. As shown in FIG. 7C , when the thickness Ta of the contact 3A is reduced to 30 μm, and When the thickness Tc of the extension portion 3C is only 15 μm, the rigidity is too thin and the conductive member 18 cannot be joined, so that the terminal 3 cannot have the extension portion 3C; from the above, the package body 1A needs to be optimized to meet the requirements of the electronic device demand.

優化習用封裝體的方法之一是令端點具有開孔,該開孔可供容置塑料等材料,並令塑料崁在端點內,使端點可更穩固的與塑料接合;另一方法是令端點具有延伸部,延伸部除了可增加與塑料的接合面積,使端點可更穩固的與塑料接合外,並使導電件與延伸部接合時,藉延伸部下表面不是懸空的特徵,使導電件可更穩固的與延伸部接合。 One of the ways to optimize the conventional package is to make the terminals have openings, which can accommodate materials such as plastic, and make the plastic embedded in the terminals, so that the terminals can be more firmly bonded to the plastic; another method The end point has an extension part, the extension part can not only increase the bonding area with the plastic, so that the end point can be more firmly bonded with the plastic, and when the conductive part is connected with the extension part, the lower surface of the extension part is not suspended. The conductive member can be more firmly connected with the extension portion.

3、30:端點 3, 30: Endpoint

10、15、1A:封裝體 10, 15, 1A: Package body

18、28:導電件 18, 28: Conductive parts

20:晶片 20: Wafer

21、31、81、91:上表面 21, 31, 81, 91: upper surface

24:連接墊 24: Connection pad

2a:銅柱 2a: copper pillar

2b:錫金屬 2b: Tin metal

32、3C2、3E2、62、82、92:下表面 32, 3C2, 3E2, 62, 82, 92: lower surface

33:側邊 33: Side

34:開孔 34: Opening

38:導電層 38: Conductive layer

3A、3B:接點 3A, 3B: Contacts

3C、3E、3Ea:延伸部 3C, 3E, 3Ea: Extensions

3P:晶片座 3P: Chip holder

3S:接合區域 3S: junction area

40:黏膠 40: Viscose

60:塑料 60: plastic

68、88、98:凹部 68, 88, 98: Recess

70、75:線路 70, 75: Line

80:載板 80: carrier board

8C、8D:元件 8C, 8D: Components

90、95:絕緣層 90, 95: insulating layer

CC:切割線 CC: cutting line

D:深度 D: depth

F:外來物 F: foreign object

L:長度 L: length

PC:電路板 PC: circuit board

S、Se、St:間隙 S, Se, St: Clearance

Tn:錫 Tn: Tin

T3、T6、Ta、Tc、Tp:厚度 T3, T6, Ta, Tc, Tp: Thickness

W:寬度 W: width

Y:開度 Y: opening

圖1A~圖1C:封裝體的俯視圖、底視圖及剖視圖 1A to 1C : top view, bottom view and cross-sectional view of the package body

圖2A~圖2D:端點及載板剖視圖 Figures 2A to 2D: Cross-sectional views of terminals and carrier

圖3~圖3E1、圖4A~圖4C及圖5A~圖5C:封裝體製造流程剖視圖 FIGS. 3 to 3E1 , 4A to 4C and 5A to 5C : cross-sectional views of the package manufacturing process

圖6A~圖6D:封裝體剖視圖 6A to 6D: Cross-sectional views of the package body

圖7A~圖7C:習用封裝體的俯視圖及剖視圖 7A to 7C : a top view and a cross-sectional view of a conventional package

如圖1A~圖1C所示實施例,圖1A是封裝體俯視圖,圖1B是圖 1A切割線CC的剖視圖,圖1C是封裝體底視圖,封裝體10包含有:端點30、晶片20、導電件18及塑料60,該端點30是導體可由銅或鎳等導電材料製成,或由鎳及銅、錫及銅、錫及鎳、鎳及金、鎳及銀、鎳及鈀及金等不同材料堆疊製成,該端點30具有接點3B,並令端點30更是可具有延伸部3E或開孔34,接點3B具有上表面31、下表面32及側邊33,其厚度T3是30微米,寬度W是200微米,而二接點3B間的間隙S是150微米,該開孔34可設置在接點3B或延伸部3E的任何位置,並可設計成圓形或橢圓形或多邊形等形狀,用以容置塑料60或錫或鎳等材料,該延伸部3E具有上表面31、下表面3E2及側邊33,其設置在接點3B周緣並能電連通,且延伸部3B上表面31及下表面3E2,分別與接點3B上表面31及下表面32是齊平的,另外,接點3B及延伸部3E的下表面32、3E2不是易被氧化的銅金屬,而是由不易被氧化的金屬組成,如:鎳或錫等金屬;晶片20,其上表面21具有連接墊24,晶片20與黏膠40接合並設置在接點3B周緣,並可依需求令晶片20設置在端點30表面(參閱圖4B);導電件18,實施為導電線,其分別與晶片20連接墊24及接點3B上表面31電連通,或經由延伸部3E上表面31與接點3B上表面31電連通,使晶片20與接點3B電連通;塑料(molding compound)60,是為包覆晶片20及導電件18而設計的絕緣體,塑料60與端點30接合並包覆晶片20及導電件18,並使接點3B及延伸部3E的下表面32、3E2,及黏膠40裸露於封裝體10外;由上述說明,封裝體10相比於圖7B~圖7C習用封裝體1A,具有下列優點:1)延伸部限制少:手機等消費性產品,會將電子元件妥善的包封在外殼內,用以避免電子元件因外來物造成電性短路,經分析發現,封裝體10藉導電材料與電路板(PC_參閱圖4C)接合後,該導電材料可實施為錫Tn,而具導電性的外來物F必需小於150微米才能穿過二錫Tn的間隙St,即使外物F可進到延伸部3E周緣,當二延伸部3E的間隙Se大於150微米時,更可降低二延伸部3E造成電性短路的風險, 或當間隙Se小於150微米時,可令塑料60具有凹部(68_參閱圖4C),用以加大二延伸部3E間的距離,甚至使該距離可大於二延伸部的間隙Se,或在封裝體10的周緣塗佈絕緣膠,使外來物F無法穿過二錫Tn間隙St,以上方法,均可減少延伸部3E造成電性短路的風險,甚至使風險趨近於零而可忽略,使延伸部3E可裸露於封裝體10外,另外,當導電件18與延伸部3E的接合區域3S接合時,因延伸部3E可與載板(80_參閱圖4B)接合,使導電件18不會因剛性不足而造成接合強度不足的損壞,使延伸部3E不受長度L的限制;2)端點及封裝體厚度更薄:藉端點30具有開孔34,令塑料60的一部分容置於開孔34內,使塑料60如圖釘般的釘在端點30內,並使接點3B能與塑料60更穩固的接合,或藉端點30具有延伸部3E,使端點30可增加與塑料60的接合面積及強度,並使接點3B更穩固的與塑料60接合,令設置開孔34或延伸部3E,均可使錫Tn受外力拉扯時,減少接點3B與塑料60間造成剝離的損壞,使接點3B厚度T3可小於30或15或5微米,相比習用接點3A厚度Ta可顯著的減薄;由上述說明可知,封裝體10更能符合電子裝置需求。 The embodiment shown in FIG. 1A to FIG. 1C, FIG. 1A is a top view of the package body, and FIG. 1B is a diagram of 1A is a cross-sectional view of the cutting line CC, and FIG. 1C is a bottom view of the package body. The package body 10 includes: a terminal 30, a chip 20, a conductive member 18 and a plastic 60. The terminal 30 is a conductor and can be made of conductive materials such as copper or nickel. , or made of stacks of different materials such as nickel and copper, tin and copper, tin and nickel, nickel and gold, nickel and silver, nickel and palladium and gold, the terminal 30 has a contact 3B, and the terminal 30 is more It can have an extension 3E or an opening 34, the contact 3B has an upper surface 31, a lower surface 32 and a side 33, the thickness T3 is 30 microns, the width W is 200 microns, and the gap S between the two contacts 3B is 150 microns, the opening 34 can be set at any position of the contact 3B or the extension 3E, and can be designed into a circular, oval or polygonal shape to accommodate plastic 60 or materials such as tin or nickel, the extension The portion 3E has an upper surface 31, a lower surface 3E2 and a side edge 33, which are arranged on the periphery of the contact 3B and can be electrically connected, and the upper surface 31 and the lower surface 3E2 of the extension portion 3B are respectively connected with the upper surface 31 and the lower surface of the contact 3B. 32 is flush, in addition, the lower surfaces 32 and 3E2 of the contact 3B and the extension 3E are not easily oxidized copper metal, but are composed of metals that are not easily oxidized, such as: nickel or tin and other metals; the wafer 20, The upper surface 21 has connection pads 24, the chip 20 is bonded with the adhesive 40 and arranged on the periphery of the contact 3B, and the chip 20 can be arranged on the surface of the terminal 30 according to the requirements (refer to FIG. 4B); the conductive member 18 is implemented as a conductive Wires, which are in electrical communication with the connection pads 24 of the chip 20 and the upper surface 31 of the contact 3B, respectively, or are in electrical communication with the upper surface 31 of the contact 3B through the upper surface 31 of the extension 3E, so that the chip 20 and the contact 3B are electrically connected; plastic ( molding compound) 60, which is an insulator designed for wrapping the chip 20 and the conductive member 18. The plastic 60 is bonded to the terminal 30 and wraps the chip 20 and the conductive member 18, and makes the contact 3B and the lower surface 32 of the extension 3E. , 3E2, and the adhesive 40 are exposed outside the package body 10; from the above description, the package body 10 has the following advantages compared with the conventional package body 1A shown in FIGS. , the electronic components will be properly encapsulated in the casing to avoid electrical short circuits caused by foreign objects. After analysis, it is found that after the package body 10 is joined to the circuit board (PC_see FIG. 4C ) by means of conductive materials, the The conductive material can be implemented as tin Tn, and the conductive foreign matter F must be smaller than 150 microns to pass through the gap St between the two tin Tn, even if the foreign matter F can enter the periphery of the extension 3E, when the gap Se between the two extensions 3E When the thickness is larger than 150 microns, the risk of electrical short circuit caused by the two extensions 3E can be reduced. Or when the gap Se is less than 150 μm, the plastic 60 can have a concave portion (68_refer to FIG. 4C ) to increase the distance between the two extending portions 3E, and even make the distance larger than the gap Se between the two extending portions, or The periphery of the package body 10 is coated with insulating glue, so that the foreign matter F cannot pass through the two-tin Tn gap St. The above methods can reduce the risk of electrical short circuit caused by the extension 3E, and even make the risk approach zero and can be ignored. The extension portion 3E can be exposed outside the package body 10. In addition, when the conductive member 18 is bonded to the bonding region 3S of the extension portion 3E, the extension portion 3E can be bonded to the carrier board (80_, see FIG. 4B ), so that the conductive member 18 The lack of rigidity will not cause the damage of insufficient bonding strength, so that the extension part 3E is not limited by the length L; 2) The thickness of the terminal and the package body is thinner: the terminal 30 has the opening 34, so that a part of the plastic 60 can accommodate Placed in the opening 34, the plastic 60 is nailed into the end 30 like a nail, so that the contact 3B can be more firmly joined with the plastic 60, or the end 30 has an extension 3E, so that the end 30 can be Increase the bonding area and strength with the plastic 60, and make the contact 3B more firmly bonded with the plastic 60, so that the opening 34 or the extension 3E can make the tin Tn be pulled by external force, reducing the contact 3B and the plastic 60. The thickness T3 of the contact 3B can be less than 30 or 15 or 5 microns, which can be significantly thinner than the thickness Ta of the conventional contact 3A. It can be seen from the above description that the package body 10 can better meet the requirements of electronic devices.

如圖2A~圖2D所示實施例剖視圖,是以圖1B端點30為基礎發展而得的端點,各端點30至少具有接點3B,接點3B具有上表面31、下表面32及側邊33,首先,如圖2A所示,端點30更是具有延伸部3E及開孔34,延伸部3E與接點3B相鄰設置並能電連通,且開孔34設置在延伸部3E,用以供容置塑料或錫或導電件(28_參閱圖3B),一載板80,其具有上表面81及下表面82,載板80可由銅等導電材料組成,或由環氧樹脂等絕緣材料組成,或由不同層數的導電及絕緣材料堆疊組成(參閱圖2B~圖2D),本例實施為銅,且接點3B及延伸部3E的下表面32、3E2與載板80上表面81接合;接著,如圖2B所示,端點30更是具有開孔34,一導體或塑料(60)容置於開孔34內並與接點3B接合,導體可實施為錫Tn或鎳或銅等導電材料,且塑料或導體表面可凸 出或齊平或凹設於接點3B上表面31或下表面32,一載板80,其至少具有上表面81、下表面82及凹部88,接點3B下表面32與載板80上表面81接合,而凹部88用以容置錫Tn等導體,載板80由二導電的元件8C堆疊組成,該導電元件8C可由銅或其他導電材料製成;接著,如圖2C所示,端點30更是具有導電層38,導電層38可由金或鎳或銀或錫等適用的金屬組成,或由不同的導電材料堆疊組成,如鎳及金、鎳及鈀及金、鈀及金等等,導電層38可設置在接點3B或延伸部(未繪示)的上表面31或下表面32,並令導電層38成為接點3B或延伸部的上表面31或下表面的一部分,導電層38具有保護端點30表面不被氧化,或不被化學溶劑侵蝕,或提升與其他導體接合品質的功效,一載板80,其具有上表面81、下表面82及凹部88,接點3B下表面32與載板80上表面81接合,凹部88的深度D可大於1或10或20微米,用以容置塑料或環氧樹脂等的絕緣材料,載板80由導電的元件8C及絕緣的元件8D堆疊組成,該絕緣元件8D可由環氧樹脂或其他絕緣材料組成;接著,如圖2D所示,載板80,其具有上表面81及下表面82,並由二導電的元件8C,及一絕緣的元件8D堆疊組成,該端點30具有接點3B、延伸部3E及絕緣層90,其中,接點3B及延伸部3E的下表面32、3E2與載板80上表面81接合,而絕緣層90實施為環氧樹脂或防焊油墨(solder mask)或其他絕緣材料,其設置在載板80上表面81並與接點3B及延伸部3E接合,並令接點3B或延伸部3E上表面31的一部分不與絕緣層90接合,用以供電連通用,或可在絕緣層90上表面91再堆疊至少一線路(70_參閱圖6C)或絕緣層,使端點30具有至少二層導電層的結構;由圖2A~圖2D說明可知,端點30與載板80組合的結構,可視為一組件並可被生產、儲存及使用。 The cross-sectional views of the embodiment shown in FIGS. 2A to 2D are endpoints developed based on the endpoints 30 in FIG. 1B , each endpoint 30 has at least a contact 3B, and the contact 3B has an upper surface 31 , a lower surface 32 and On the side 33, first, as shown in FIG. 2A, the end point 30 has an extension part 3E and an opening 34, the extension part 3E is arranged adjacent to the contact 3B and can be electrically connected, and the opening 34 is arranged in the extension part 3E , for accommodating plastic or tin or conductive parts (28_ refer to FIG. 3B), a carrier board 80, which has an upper surface 81 and a lower surface 82, the carrier board 80 can be composed of conductive materials such as copper, or epoxy resin It is composed of other insulating materials, or is composed of different layers of conductive and insulating materials stacked (refer to FIG. 2B to FIG. 2D ). In this embodiment, copper is used, and the lower surfaces 32 and 3E2 of the contact 3B and the extension 3E are connected to the carrier board 80 . The upper surface 81 is joined; then, as shown in FIG. 2B, the terminal 30 has an opening 34, and a conductor or plastic (60) is accommodated in the opening 34 and is joined to the contact 3B. The conductor can be implemented as tin Tn or conductive materials such as nickel or copper, and the surface of the plastic or conductor can be convex Out or flush or recessed on the upper surface 31 or the lower surface 32 of the contact 3B, a carrier board 80 has at least an upper surface 81, a lower surface 82 and a recess 88, the lower surface 32 of the contact 3B and the upper surface of the carrier board 80 81 is joined, and the concave portion 88 is used to accommodate conductors such as tin, Tn, etc. The carrier board 80 is composed of two conductive elements 8C stacked, and the conductive elements 8C can be made of copper or other conductive materials; then, as shown in FIG. 2C, the terminal 30 further has a conductive layer 38, the conductive layer 38 can be composed of suitable metals such as gold, nickel, silver or tin, or a stack of different conductive materials, such as nickel and gold, nickel and palladium and gold, palladium and gold, etc. , the conductive layer 38 can be disposed on the upper surface 31 or the lower surface 32 of the contact 3B or the extension (not shown), and make the conductive layer 38 become a part of the upper surface 31 or the lower surface of the contact 3B or the extension, conductive The layer 38 has the effect of protecting the surface of the terminal 30 from being oxidized, or not being eroded by chemical solvents, or improving the quality of bonding with other conductors. The lower surface 32 is joined to the upper surface 81 of the carrier board 80, and the depth D of the recess 88 can be greater than 1 or 10 or 20 microns to accommodate insulating materials such as plastic or epoxy resin. The carrier board 80 is composed of conductive elements 8C and insulating materials. Then, as shown in FIG. 2D, the carrier board 80, which has an upper surface 81 and a lower surface 82, is composed of two conductive elements 8C, And an insulating element 8D is stacked, the terminal 30 has a contact 3B, an extension 3E and an insulating layer 90, wherein the lower surfaces 32 and 3E2 of the contact 3B and the extension 3E are joined to the upper surface 81 of the carrier board 80, The insulating layer 90 is implemented as epoxy resin or solder mask or other insulating material, which is disposed on the upper surface 81 of the carrier board 80 and is joined to the contact 3B and the extension 3E, and makes the contact 3B or the extension 3E A part of the upper surface 31 of the insulating layer 90 is not bonded to the insulating layer 90 for power supply connection, or at least one circuit (see FIG. 6C ) or insulating layer can be stacked on the upper surface 91 of the insulating layer 90, so that the terminal 30 has at least one circuit. The structure of the two-layer conductive layer; as shown in FIGS. 2A to 2D , the combination of the terminal 30 and the carrier 80 can be regarded as a component and can be produced, stored and used.

如圖3A~圖3D及圖3A~圖3E1所示,是封裝體製作流程的剖視圖,首先,如圖3A所示,提供一端點30及載板80,該端點30及載板80的特 徵與符號與圖2A的端點30相同,請參閱圖2A說明,且端點30依產品需求可具有或不具有延伸部3E;接著,如圖3B所示,先提供晶片20及導電件28,晶片20上表面21具有連接墊24,並設置在端點30表面,導電件28實施為以錫金屬為主要材料的凸塊(bump),其一部分容置於開孔34內,並分別與晶片20連接墊24及延伸部3E電連通,並經由延伸部3E上表面31與接點3B上表面31電連通,使晶片20與接點3B電連通,然後將塑料60設置在載板80上表面81,其與端點30接合並包覆晶片20及導電件28,另外,導電件28可置換以銅及錫金屬為主要材料的銅凸塊(copper pillar bump_參閱圖6A);接著,如圖3C所示,將載板80移除,使導電件28的一部分、接點3B下表面32及延伸部3E下表面3E2裸露於大氣中,至此,封裝體10就已形成,同時,使塑料60與接點3B及延伸部3E呈並列設置,而可忽略接點3B及延伸部3E的厚度,使封裝體10的厚度就是塑料60的厚度;接著,如圖3D所示,依產品需求,可提供一實施為防焊油墨或其他絕緣材料的絕緣層90,其與塑料60下表面62接合,並至少令接點3B下表面32可裸露於大氣中,供對外電連通用,藉絕緣層90可使接點3B及延伸部3E更穩固的與塑料60接合,並能避免延伸部3E造成電性短路的損壞;接著,如圖3C1所示,依產品需求,在完成圖3B的步驟,且載板80上表面81實施為導電的元件(8C_參閱圖2B)時,將部分的載板80移除,令未被移除的載板80轉換成線路70,且線路70可與接點3B電連通或不電連通;接著,如圖3D1所示,提供一實施為防焊油墨或環氧樹脂或其他絕緣材料的絕緣層90,絕緣層90設置在塑料60下表面62並與線路70接合,令一部分的線路70未被絕緣層90包覆,可供錫接合或對外電連通用,至此,封裝體15就已形成;接著,如圖3E1所示,可再依需求,在絕緣層90下表面92再堆疊至少一第二線路75或第二絕緣層95,使端點30具有多層線路的結構。 3A to 3D and 3A to 3E1 are cross-sectional views of the manufacturing process of the package. First, as shown in FIG. 3A, a terminal 30 and a carrier 80 are provided. The characteristics of the terminal 30 and the carrier 80 are provided. The features and symbols are the same as those of the terminal 30 in FIG. 2A , please refer to the description of FIG. 2A , and the terminal 30 may or may not have the extension 3E according to product requirements; then, as shown in FIG. 3B , the chip 20 and the conductive member 28 are provided first. , the upper surface 21 of the chip 20 has connection pads 24 and is arranged on the surface of the terminal 30, the conductive member 28 is implemented as a bump with tin metal as the main material, a part of which is accommodated in the opening 34, and is respectively connected with The connection pads 24 of the wafer 20 are electrically connected to the extension portion 3E, and are electrically connected to the upper surface 31 of the contact point 3B through the upper surface 31 of the extension portion 3E, so that the wafer 20 is electrically connected to the contact point 3B, and then the plastic 60 is placed on the carrier board 80 The surface 81, which is bonded to the terminal 30 and covers the chip 20 and the conductive member 28, in addition, the conductive member 28 can replace copper and tin metal as the main material of the copper bump (copper pillar bump_refer to FIG. 6A); then, As shown in FIG. 3C, the carrier board 80 is removed so that a part of the conductive member 28, the lower surface 32 of the contact 3B and the lower surface 3E2 of the extension 3E are exposed to the atmosphere. At this point, the package body 10 has been formed. The plastic 60 is arranged side by side with the contact 3B and the extension 3E, and the thickness of the contact 3B and the extension 3E can be ignored, so that the thickness of the package body 10 is the thickness of the plastic 60; then, as shown in FIG. 3D, according to product requirements , an insulating layer 90 implemented as solder resist ink or other insulating material can be provided, which is bonded to the lower surface 62 of the plastic 60, and at least the lower surface 32 of the contact 3B can be exposed to the atmosphere for external electrical connection. The layer 90 can make the contact 3B and the extension 3E more firmly bonded to the plastic 60, and can prevent the extension 3E from causing electrical short-circuit damage; then, as shown in FIG. 3C1, according to product requirements, the step of FIG. 3B is completed. , and when the upper surface 81 of the carrier board 80 is implemented as a conductive element (8C_refer to FIG. 2B ), a part of the carrier board 80 is removed, so that the unremoved carrier board 80 is converted into a circuit 70, and the circuit 70 can be connected with Contact 3B is electrically connected or not; then, as shown in FIG. 3D1, an insulating layer 90 implemented as solder mask ink or epoxy resin or other insulating material is provided, the insulating layer 90 is provided on the lower surface 62 of the plastic 60 and is connected to the lower surface 62 of the plastic 60. The circuit 70 is bonded, so that a part of the circuit 70 is not covered by the insulating layer 90, which can be used for tin bonding or external electrical connection. At this point, the package body 15 has been formed; then, as shown in FIG. The lower surface 92 of the insulating layer 90 is further stacked with at least one second circuit 75 or a second insulating layer 95 , so that the terminal 30 has a multi-layer circuit structure.

如圖4A~圖4C所示,是封裝體製作流程的剖視圖,首先,如 圖4A所示,提供端點30及載板80,該載板80由導電的元件8C及絕緣的元件8D堆疊組成,並具有上表面81、下表面82及凹部88,其中,凹部88位於上表面81,使凹部88的底部與上表面81間具有一深度D,而元件8D可置換成元件8C,該端點30具有接點3B、延伸部3E及晶片座3P,並分別具有上表面31及下表面32、3E2,其下表面32、3E2實施為鎳或錫,且分別與載板80上表面81接合,一延伸部3E與接點3B相鄰設置並能電連通,而另一接點(3B_未繪示)與延伸部3Ea相鄰設置並能電連通,接點3B或延伸部3Ea的上表面31可設置導電層38,也可依需求令端點30不具有延伸部3E、3Ea;接著,如圖4B所示,先提供晶片20,晶片20藉黏膠40與晶片座3P接合後,導電件18分別與晶片20連接墊24、接點3B及延伸部3Ea接合,使晶片20與接點3B電連通,接著,塑料60與端點30接合並包覆晶片20及導電件18,且塑料60的一部分容置於載板80凹部88內;接著,如圖4C所示,將載板80移除,至此,封裝體10就已形成,並令塑料60具有凹部68,該凹部68的深度可大於1或10或20微米,使塑料60下表面62凸出於接點3B下表面32、延伸部3E下表面3E2及晶片座39下表面32,並令接點3B、延伸部3E及晶片座3P的下表面32、3E2裸露於凹部68的底部;塑料60凹部68的功效說明如下:1)減少電性短路風險:當封裝體10藉錫Tn與電路板PC端點接合後,因錫Tn的一部分容置於凹部68內,使封裝體10與電路板PC間的厚度Tp得以降低,藉此,除了使可穿過二錫Tn間的間隙(St_參閱圖1C),到達延伸部3E、3Ea周緣的外來物F是更小且更少外,更可藉凹部68的深度加大二延伸部3E、3Ea間的距離,該距離甚至可大於間隙(St),據此,二延伸部3E、3Ea間因外來物F造成電性短路的風險將更低,進而可忽略該風險;2)減少電性斷路風險:因錫Tn的一部分容置於塑料60凹部68,使錫Tn崁在塑料60內,而能更穩固的與接點3B接合,當錫Tn受外力左右拉扯時,可降低接點3B受外力的拉扯,進而可降低接點3B與塑料60間 產生剝離,以及造成接點3B與導電件18間電性斷路的損壞;3)最薄的封裝體厚度:藉接點3B及延伸部3E、3Ea裸露於凹部68底部的特徵,使接點3B及延伸部3E、3Ea均與塑料60呈並列設置,而可忽略接點3B等元件的厚度(T3),使封裝體10的厚度僅由塑料60厚度T6組成,也就是目前已知最薄的厚度200微米;4)降低導電件材料用量:增加凹部68的深度,或不具有晶片座3P,或令黏膠40與載板80凹部88的底部接合,使黏膠40與塑料60下表面62齊平,均使接點3B及延伸部3Ea更靠近晶片20連接墊24,可達到減少導電件18長度的用量及成本,並能提升生產效率。 As shown in FIG. 4A to FIG. 4C, it is a cross-sectional view of the package manufacturing process. First, as shown in FIG. 4A~FIG. 4C As shown in FIG. 4A, a terminal 30 and a carrier 80 are provided. The carrier 80 is composed of a stack of conductive elements 8C and insulating elements 8D, and has an upper surface 81, a lower surface 82 and a recess 88, wherein the recess 88 is located on the upper side The surface 81 has a depth D between the bottom of the recess 88 and the upper surface 81, and the element 8D can be replaced with an element 8C. The end point 30 has a contact 3B, an extension 3E and a wafer holder 3P, and has an upper surface 31 respectively. and the lower surfaces 32, 3E2, the lower surfaces 32, 3E2 are implemented with nickel or tin, and are respectively connected with the upper surface 81 of the carrier board 80, an extension 3E is adjacent to the contact 3B and can be electrically connected, and the other is connected The point (3B_ is not shown) is disposed adjacent to the extension portion 3Ea and can be electrically connected. The contact 3B or the upper surface 31 of the extension portion 3Ea can be provided with a conductive layer 38, or the terminal 30 can be provided without the extension portion 3E as required. 3Ea; then, as shown in FIG. 4B , the chip 20 is provided first, and after the chip 20 is bonded to the chip seat 3P by the adhesive 40 , the conductive members 18 are respectively bonded to the connection pads 24 , the contacts 3B and the extension 3Ea of the chip 20 , so that the The chip 20 is in electrical communication with the contact 3B, and then, the plastic 60 is bonded to the terminal 30 and covers the chip 20 and the conductive member 18, and a part of the plastic 60 is accommodated in the recess 88 of the carrier plate 80; then, as shown in FIG. 4C , remove the carrier board 80, so far, the package body 10 has been formed, and the plastic 60 has a recess 68, the depth of the recess 68 can be greater than 1 or 10 or 20 microns, so that the lower surface 62 of the plastic 60 protrudes from the contact The lower surface 32 of 3B, the lower surface 3E2 of the extension part 3E and the lower surface 32 of the wafer seat 39, and the lower surfaces 32 and 3E2 of the contact 3B, the extension part 3E and the wafer seat 3P are exposed at the bottom of the recessed part 68; The effects are described as follows: 1) Reduce the risk of electrical short circuit: after the package body 10 is joined to the terminal of the circuit board PC by the tin Tn, a part of the tin Tn is accommodated in the concave portion 68, so that the gap between the package body 10 and the circuit board PC is reduced. The thickness Tp is reduced, thereby, in addition to making it possible to pass through the gap between the two tin Tn (St_ refer to FIG. 1C ), the foreign matter F reaching the periphery of the extension parts 3E, 3Ea is smaller and less, and the concave part can be used. The depth of 68 increases the distance between the two extension parts 3E, 3Ea, and the distance can even be larger than the gap (St), accordingly, the risk of electrical short circuit between the two extension parts 3E, 3Ea caused by the foreign object F will be lower, and then This risk can be ignored; 2) reduce the risk of electrical disconnection: since a part of the tin Tn is accommodated in the concave portion 68 of the plastic 60, the tin Tn is embedded in the plastic 60, and can be more firmly bonded to the contact 3B, when the tin Tn receives When the external force pulls left and right, the pulling of the contact 3B by the external force can be reduced, and the distance between the contact 3B and the plastic 60 can be reduced. 3) The thinnest package thickness: the contact 3B and the extension parts 3E, 3Ea are exposed at the bottom of the recess 68 by virtue of the feature that the contact 3B is exposed at the bottom of the recess 68, so that the contact 3B and the extension parts 3E, 3Ea are arranged side by side with the plastic 60, and the thickness (T3) of the components such as the contact 3B can be ignored, so that the thickness of the package body 10 is only composed of the thickness T6 of the plastic 60, which is the thinnest known so far. The thickness is 200 microns; 4) Reduce the amount of conductive material: increase the depth of the concave portion 68, or do not have the chip seat 3P, or make the adhesive 40 and the bottom of the concave portion 88 of the carrier 80 join, so that the adhesive 40 is connected to the lower surface 62 of the plastic 60 By being flush, the contacts 3B and the extension portions 3Ea are brought closer to the connection pads 24 of the chip 20 , which can reduce the amount and cost of the length of the conductive member 18 and improve the production efficiency.

如圖5A~圖5C所示,是封裝體製作流程的剖視圖,首先,如圖5A所示,提供端點30及載板80,該載板80由導電的元件8C及絕緣的元件8D堆疊組成,並具有上表面81、下表面82及凹部88,其中,凹部88位於上表面81,使凹部88的底部與上表面81間具有一深度D,該端點30具有接點3B及延伸部3E,並分別具有上表面31及下表面32、3E2,其下表面下表面32、3E2實施為鎳或錫,並分別與載板80上表面81接合,同時,一接點3B與延伸部3E相鄰設置並能電連通;接著,如圖5B所示,先提供晶片20,其設置在端點30表面,導電件28分別與晶片20連接墊24、接點3B及延伸部3E接合,使晶片20與接點3B電連通,接著,塑料60與端點30接合並包覆晶片20及導電件28,且塑料60的一部分容置於載板80凹部88內;接著,如圖5C所示,將載板80移除,至此,封裝體10就已形成,並令塑料60具有凹部68,該凹部68的深度可大於1或10或20微米,使塑料60下表面62凸出於接點3B、延伸部3E的下表面32、3E2,並令接點3B及延伸部3E的下表面32、3E2裸露於凹部68的底部,且凹部68開度Y的寬度是小於接點3B下表面32寬度(W_參閱圖1A),或可令一部分的載板80元件8C容置於凹部68內與接點3B下表面32接合;塑料60凹部68具降低接點3B剝離風險,說明如下:1)當一導電材料容置於凹 部68內時,其可實施為錫Tn或元件8C,在導電材料受外力拉扯時,因凹部68開度Y小於接點3B下表面32,令凹部68呈梯形狀,使導電材料可更穩固的容置於凹部68內與接點3B接合,以及減少接點3B受外力的拉扯,進而可降低接點3B與塑料60間剝離的風險;2)不論凹部68是否呈梯形狀,只要一部分的接點3B下表面32與塑料60接合時,使接點3B被卡在塑料60內,都可降低受外力拉扯造成剝離的風險,據此,使端點30厚度(T3_參閱圖1B)可如薄膜,可小於7或3或1微米,使端點30的用料及製作成本得以有效降低。 As shown in FIGS. 5A to 5C , which are cross-sectional views of the package fabrication process, first, as shown in FIG. 5A , the terminals 30 and the carrier 80 are provided, and the carrier 80 is composed of a stack of conductive elements 8C and insulating elements 8D , and has an upper surface 81, a lower surface 82 and a recess 88, wherein the recess 88 is located on the upper surface 81, so that there is a depth D between the bottom of the recess 88 and the upper surface 81, and the endpoint 30 has a contact 3B and an extension 3E , and have an upper surface 31 and a lower surface 32, 3E2 respectively, the lower surface and the lower surface 32, 3E2 are implemented as nickel or tin, and are respectively connected with the upper surface 81 of the carrier board 80, at the same time, a contact 3B and the extension 3E are connected Next, as shown in FIG. 5B, the chip 20 is provided first, which is arranged on the surface of the terminal 30, and the conductive members 28 are respectively connected with the connection pads 24, the contacts 3B and the extension parts 3E of the chip 20, so that the chip 20 is in electrical communication with the contact 3B, then, the plastic 60 is bonded to the terminal 30 and covers the chip 20 and the conductive member 28, and a part of the plastic 60 is accommodated in the recess 88 of the carrier board 80; then, as shown in FIG. 5C, The carrier board 80 is removed, so far, the package body 10 has been formed, and the plastic 60 has a concave portion 68, the depth of the concave portion 68 can be greater than 1 or 10 or 20 microns, so that the lower surface 62 of the plastic 60 protrudes from the contact 3B , the lower surfaces 32, 3E2 of the extension 3E, and the lower surfaces 32, 3E2 of the contact 3B and the extension 3E are exposed at the bottom of the recess 68, and the width of the opening Y of the recess 68 is smaller than the width of the lower surface 32 of the contact 3B (W_refer to FIG. 1A ), or a part of the components 8C of the carrier board 80 can be accommodated in the recess 68 to engage with the lower surface 32 of the contact 3B; the plastic 60 recess 68 reduces the risk of peeling of the contact 3B, as follows: 1) When a conductive material is contained in the concave When the conductive material is pulled by external force, the opening Y of the concave portion 68 is smaller than the lower surface 32 of the contact 3B, so that the concave portion 68 has a trapezoidal shape, so that the conductive material can be more stable is accommodated in the concave portion 68 to engage with the contact 3B, and reduce the pulling of the contact 3B by external force, thereby reducing the risk of peeling between the contact 3B and the plastic 60; 2) No matter whether the concave portion 68 is trapezoidal or not, as long as a part of the When the lower surface 32 of the contact 3B is engaged with the plastic 60, the contact 3B is stuck in the plastic 60, which can reduce the risk of peeling caused by pulling by external force. For example, the thin film can be smaller than 7 or 3 or 1 micron, so that the material and manufacturing cost of the terminal 30 can be effectively reduced.

如圖6A~圖6B所示實施例,圖6A是封裝體剖視圖,圖6B是封裝體與錫Tn接合後的剖視圖,該封裝體10包含有:端點30、晶片20、塑料60及導電件28,該端點30具有接點3B及開孔34,接點3B具有上表面31、下表面32及側邊33,而開孔34設置在接點3B;晶片20,上表面21具有連接墊24;導電件28,實施為銅凸塊,其具有銅柱2a及錫金屬2b,銅柱2a與晶片20連接墊24接合,而錫金屬2b容置於開孔34內,但不與端點30接合;依需求,可令錫金屬2b與接點3B電連通(參閱圖3C),或可令端點30無開孔34,使錫金屬2b與接點3B上表面31接合,或令開孔34內具有錫,使導電件28可不具有錫金屬2b用以降低成本;塑料60,其為絕緣體與端點30接合並包覆晶片20及導電件28,且塑料60的一部分容置於開孔34內,並令導電件28的一部分及接點3B下表面32,裸露於塑料60下表面62;如圖6B所示,一導電材料與接點3B下表面32接合,該導電材料可實施為錫Tn,使錫Tn可直接與導電件28電連通,並使導電件28與接點3B電連通;由上述說明可得下列優點;1)品質更好:錫Tn直接與導電件28的錫金屬2b接合,使導電件28與錫Tn間無不同金屬的介面,進而不會產生金屬間化合物,可避免因阻抗改變造成電性的衰減或損壞;2)接合性更好:錫Tn與導電件28的錫金屬2b接合,令錫Tn如圖釘般釘在塑料60內,使接點3B更穩固的與塑料60及錫Tn接合,可降低錫Tn被拉 扯而造成接點3B與塑料60間剝離的損壞,據此,接點3B厚度(T3)可實施得更薄,如:小於10或5或1微米,並可藉更薄的接點3B,減少封裝體10厚度,以及達到接點3B及塑料60用料更少及成本更低的功效。 6A to FIG. 6B , FIG. 6A is a cross-sectional view of the package body, and FIG. 6B is a cross-sectional view of the package body after bonding with tin Tn. The package body 10 includes: terminals 30 , chips 20 , plastics 60 and conductive parts 28, the terminal 30 has a contact 3B and an opening 34, the contact 3B has an upper surface 31, a lower surface 32 and a side edge 33, and the opening 34 is arranged at the contact 3B; the wafer 20, the upper surface 21 has connection pads 24; The conductive member 28 is implemented as a copper bump, which has a copper pillar 2a and a tin metal 2b, the copper pillar 2a is bonded to the connection pad 24 of the chip 20, and the tin metal 2b is accommodated in the opening 34, but not connected to the terminal 30 bonding; according to requirements, the tin metal 2b can be electrically connected to the contact 3B (refer to FIG. 3C), or the terminal 30 can be made without the opening 34, so that the tin metal 2b can be connected with the upper surface 31 of the contact 3B, or can be opened The hole 34 has tin, so that the conductive member 28 may not have the tin metal 2b to reduce the cost; the plastic 60 is an insulator bonded to the terminal 30 and covers the chip 20 and the conductive member 28, and a part of the plastic 60 is accommodated in the opening In the hole 34, part of the conductive member 28 and the lower surface 32 of the contact 3B are exposed on the lower surface 62 of the plastic 60; as shown in FIG. 6B, a conductive material is bonded to the lower surface 32 of the contact 3B, and the conductive material can be implemented It is tin Tn, so that the tin Tn can be directly electrically connected with the conductive member 28, and the conductive member 28 is electrically connected with the contact 3B; the following advantages can be obtained from the above description; 1) The quality is better: the tin Tn is directly connected to the conductive member 28 The tin metal 2b is bonded, so that there is no interface of different metals between the conductive member 28 and the tin Tn, so that no intermetallic compound is generated, which can avoid electrical attenuation or damage caused by impedance changes; 2) Better bonding: tin Tn and The tin metal 2b of the conductive member 28 is joined, so that the tin Tn is nailed into the plastic 60 like a thumbtack, so that the contact 3B is more firmly joined with the plastic 60 and the tin Tn, which can reduce the pulling of the tin Tn Therefore, the thickness (T3) of the contact 3B can be made thinner, for example, less than 10 or 5 or 1 μm, and a thinner contact 3B can be used to The thickness of the package body 10 is reduced, and the effect of using less material and lower cost for the contacts 3B and the plastic 60 is achieved.

如圖6C所示實施例是封裝體剖視圖,封裝體10的晶片20、黏膠40、塑料60及導電件18特徵及符號,與圖1B所示的相同,請參閱圖1B說明,該端點30除了具有接點3B及延伸部3E外,更是具有絕緣層90及線路70,延伸部3E與接點3B相鄰設置並能電連通,且其下表面32、3E2不是易被氧化的銅金屬,而是由不易被氧化的金屬組成,如:鎳或錫等金屬,該絕緣層90與接點3B及延伸部3E接合,並使接點3B及延伸部3E的下表面32、3E2裸露於絕緣體90凹部98的底部,該凹部98是由載板的凹部(88_參閱圖2C)形成的,依需求也可令絕緣體90不具有凹部98,該線路70設置在絕緣層90上表面91並與接點3B電連通,或可在絕緣層90上表面91設置第二絕緣層並與線路70接合,使線路70的一部分裸露第二絕緣層外,該晶片20設置在端點30表面,藉黏膠40與端點30接合,並藉導電件18與線路70電連通,使晶片20與接點3B電連通,該塑料60與端點30接合並包覆晶片20及導電件18,並令接點3B及延伸部3E的下表面32、3E2裸露於封裝體10外,使接點3B可對外電連通;由上述說明可知,設置絕緣層90及線路70,使端點30與習用二層線路的電路板結構相同,但不需如習用電路板在絕緣層90下表面92需再設置一防焊層(未繪示),用以包覆延伸部3E下表面3E2,使下表面3E2不裸露封裝體10外,據此,封裝體10因不需設置防焊層而可達到降低成本及減少厚度的功效。 The embodiment shown in FIG. 6C is a cross-sectional view of the package body. The features and symbols of the chip 20 , the adhesive 40 , the plastic 60 and the conductive member 18 of the package body 10 are the same as those shown in FIG. 1B . Please refer to FIG. 1B for description. 30 not only has the contact 3B and the extension part 3E, but also has an insulating layer 90 and a line 70. The extension part 3E is arranged adjacent to the contact 3B and can be electrically connected, and its lower surfaces 32 and 3E2 are not easily oxidized copper. The insulating layer 90 is connected to the contact 3B and the extension 3E, and the lower surfaces 32 and 3E2 of the contact 3B and the extension 3E are exposed. At the bottom of the concave portion 98 of the insulator 90, the concave portion 98 is formed by the concave portion (88_refer to FIG. 2C) of the carrier board, and the insulator 90 can also not have the concave portion 98 according to requirements, and the circuit 70 is disposed on the upper surface 91 of the insulating layer 90. And it is electrically connected with the contact 3B, or a second insulating layer can be provided on the upper surface 91 of the insulating layer 90 and bonded with the circuit 70, so that a part of the circuit 70 is exposed outside the second insulating layer, and the wafer 20 is arranged on the surface of the terminal 30, The adhesive 40 is bonded to the terminal 30, and the conductive member 18 is electrically connected to the circuit 70, so that the chip 20 is electrically connected to the contact 3B. The plastic 60 is bonded to the terminal 30 and covers the chip 20 and the conductive member 18, and The lower surfaces 32 and 3E2 of the contact point 3B and the extension portion 3E are exposed outside the package body 10, so that the contact point 3B can be electrically connected to the outside; it can be seen from the above description that the insulating layer 90 and the line 70 are provided, so that the terminal 30 and the conventional two The circuit board structure of the layered circuit is the same, but it is not necessary to provide a solder mask (not shown) on the lower surface 92 of the insulating layer 90 as in the conventional circuit board to cover the lower surface 3E2 of the extension part 3E, so that the lower surface 3E2 The outside of the package body 10 is not exposed. Accordingly, the package body 10 does not need to be provided with a solder mask, thereby achieving the effects of reducing cost and reducing thickness.

本發明實施例僅例示性說明本發明的原理及其功效,而非用於限制本發明的。任何熟悉此技術的人士皆可在不違背本發明的精神及範疇下,對上述實施例進行修飾或改變。因此,舉凡所屬技術領域中具有通常知識者在未脫離本發明的所揭示的精神與技術思想下所完成的一切等效 修飾或改變,仍應由本發明的權利要求所涵蓋。 The embodiments of the present invention merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalents accomplished by those with ordinary knowledge in the technical field without departing from the disclosed spirit and technical idea of the present invention Modifications or changes should still be covered by the claims of the present invention.

10:封裝體 10: Package body

20:晶片 20: Wafer

21、31:上表面 21, 31: upper surface

24:連接墊 24: Connection pad

28:導電件 28: Conductive parts

2a:銅柱 2a: copper pillar

2b:錫金屬 2b: Tin metal

30:端點 30: Endpoint

32、62:下表面 32, 62: lower surface

33:側邊 33: Side

34:開孔 34: Opening

3B:接點 3B: Contact

60:塑料 60: plastic

Claims (23)

一種端點及載板,其特徵是: A terminal and a carrier board, characterized in that: 所述載板,具有上表面、下表面及凹部,且上表面是由導電的元件組成,凹部位於上表面並具有一深度;及 The carrier plate has an upper surface, a lower surface and a recess, and the upper surface is composed of conductive elements, and the recess is located on the upper surface and has a depth; and 所述端點,具有接點,接點具有上表面、下表面及側邊,且下表面與載板上表面接合。 The end point has a contact point, the contact point has an upper surface, a lower surface and a side edge, and the lower surface is joined to the upper surface of the carrier. 如申請專利範圍第1項所述之端點及載板,端點更是具有延伸部,其具有上表面、下表面及側邊,其中,接點及延伸部的下表面是由不易被氧化金屬組成,延伸部與接點相鄰設置並能電連通,且下表面與載板上表面接合。 According to the end point and the carrier board described in the first item of the patent application scope, the end point further has an extension portion, which has an upper surface, a lower surface and a side edge, wherein the lower surface of the contact point and the extension portion is made of a material that is not easily oxidized. It is composed of metal, the extension part is arranged adjacent to the contact point and can be electrically connected, and the lower surface is joined with the upper surface of the carrier board. 如申請專利範圍第1項所述之端點及載板,端點更是具有開孔,開孔可設置在端點的任何位置。 According to the end point and the carrier plate as described in item 1 of the scope of the application, the end point has an opening, and the opening can be arranged at any position of the end point. 一種端點及載板,其特徵是: A terminal and a carrier board, characterized in that: 所述載板,具有上表面及下表面,且上表面是由導電的元件組成;及 The carrier board has an upper surface and a lower surface, and the upper surface is composed of conductive elements; and 所述端點,具有接點及開孔,接點具有上表面、下表面及側邊,且下表面與載板上表面接合,開孔設置在端點的任何位置。 The end point has a contact point and an opening, the contact point has an upper surface, a lower surface and a side edge, and the lower surface is joined to the upper surface of the carrier, and the opening hole is arranged at any position of the end point. 如申請專利範圍第4項所述之端點及載板,端點更是具有延伸部,其具有上表面、下表面及側邊,其中,接點及延伸部的下表面是由不易被氧化金屬組成,延伸部與接點相鄰設置並能電連通,且下表面與載板上表面接合。 According to the end point and the carrier board described in claim 4, the end point further has an extension portion, which has an upper surface, a lower surface and a side edge, wherein the lower surface of the contact point and the extension portion is made of a material that is not easily oxidized. It is composed of metal, the extension part is arranged adjacent to the contact point and can be electrically connected, and the lower surface is joined with the upper surface of the carrier board. 一種端點及載板,其特徵是: A terminal and a carrier board, characterized in that: 所述載板,具有上表面及下表面,且上表面是由導電的元件組成;及 The carrier board has an upper surface and a lower surface, and the upper surface is composed of conductive elements; and 所述端點,具有接點及延伸部,接點及延伸部均具有上表面、下表面 及側邊,其中,接點及延伸部的下表面是由不易被氧化金屬組成,延伸部與接點相鄰設置並能電連通,且各下表面與載板上表面接合。 The end point has a contact point and an extension part, and both the contact point and the extension part have an upper surface and a lower surface and the side, wherein the lower surfaces of the contacts and the extension parts are made of metal that is not easily oxidized, the extension parts are adjacent to the contacts and can be electrically connected, and each lower surface is joined to the upper surface of the carrier. 如申請專利範圍第6項所述之端點及載板,端點更是具有絕緣層,其具有上表面及下表面,並設置在載板上表面,絕緣層與接點及延伸部接合,使一部分的接點或延伸部上表面裸露於絕緣層上表面外。 According to the terminal and the carrier as described in item 6 of the scope of the patent application, the terminal further has an insulating layer, which has an upper surface and a lower surface, and is disposed on the upper surface of the carrier, and the insulating layer is joined to the contact and the extension portion, A part of the upper surface of the contact or extension is exposed outside the upper surface of the insulating layer. 如申請專利範圍第7項所述之端點及載板,端點更是具有線路,其設置在絕緣層上表面,並與接點電連通。 According to the terminal and the carrier as described in claim 7, the terminal further has a circuit, which is arranged on the upper surface of the insulating layer and is in electrical communication with the contact. 一種端點,具有接點、延伸部、絕緣層及線路,其特徵是: An end point, which has a contact, an extension, an insulating layer and a circuit, and is characterized by: 所述接點,其具有上表面、下表面及側邊,其中,下表面是由不易被氧化金屬組成; The contact has an upper surface, a lower surface and a side edge, wherein the lower surface is composed of a metal that is not easily oxidized; 所述延伸部,其具有上表面、下表面及側邊,其中,下表面是由不易被氧化金屬組成,延伸部與接點相鄰設置並能電連通; the extension part has an upper surface, a lower surface and a side edge, wherein the lower surface is composed of a metal that is not easily oxidized, and the extension part is arranged adjacent to the contact and can be electrically connected; 所述絕緣層,具有上表面及下表面,絕緣層與接點及延伸部接合,使接點及延伸部的下表面裸露於絕緣層下表面,並使一部分的接點或延伸部上表面裸露於絕緣層上表面;及 The insulating layer has an upper surface and a lower surface, and the insulating layer is joined to the contacts and the extension parts, so that the lower surfaces of the contacts and the extension parts are exposed on the lower surface of the insulating layer, and part of the upper surfaces of the contacts or the extension parts are exposed on the upper surface of the insulating layer; and 所述線路,其設置在絕緣層上表面,並與接點電連通。 The circuit is arranged on the upper surface of the insulating layer and is in electrical communication with the contact point. 如申請專利範圍第9項所述之端點,絕緣層下表面具有凹部,並令接點及延伸部的下表面裸露於凹部的底部。 As described in the end point of claim 9, the lower surface of the insulating layer has a concave portion, and the lower surfaces of the contact point and the extension portion are exposed at the bottom of the concave portion. 一種封裝體,具有端點、晶片、導電件及塑料,其特徵是: An encapsulation body, comprising a terminal, a chip, a conductive member and a plastic, is characterized in that: 所述端點,具有接點,接點具有上表面、下表面及側邊; the end point has a joint, and the joint has an upper surface, a lower surface and a side; 所述晶片,上表面具有連接墊; The wafer has connection pads on the upper surface; 所述導電件,導電件與晶片連接墊接合,並與接點上表面電連通,使晶片與端點電連通;及 the conductive member, the conductive member is engaged with the chip connection pad, and is in electrical communication with the upper surface of the contact point, so that the chip and the terminal point are electrically connected; and 所述塑料,下表面具有凹部,塑料與端點接合並包覆晶片及導電件, 並令接點下表面裸露於塑料凹部的底部供對外電連通,使塑料下表面凸出接點下表面一深度。 The plastic has a concave portion on the lower surface, and the plastic is joined to the terminal and covers the chip and the conductive member, The lower surface of the contact is exposed at the bottom of the plastic concave portion for external electrical connection, so that the lower surface of the plastic protrudes from the lower surface of the contact by a depth. 如申請專利範圍第11項所述之封裝體,端點更是具有延伸部,延伸部與接點相鄰設置並能電連通,其具有上表面、下表面及側邊,其中,接點及延伸部的下表面是由不易被氧化金屬組成,且下表面裸露於塑料凹部的底部。 According to the package described in claim 11, the end point further has an extension part, the extension part is arranged adjacent to the contact point and can be electrically connected, and has an upper surface, a lower surface and a side edge, wherein the contact point and The lower surface of the extension part is made of metal that is not easily oxidized, and the lower surface is exposed at the bottom of the plastic recess. 如申請專利範圍第11項所述之封裝體,端點更是具有開孔,開孔設置在端點的任何位置,用以容置塑料的一部分或錫金屬等材料。 For the package described in item 11 of the scope of the patent application, the end points are further provided with openings, and the openings are arranged at any positions of the end points for accommodating a part of plastic or tin metal and other materials. 如申請專利範圍第13項所述之封裝體,導電件的一部分容置於開孔內,且不與端點接合,而封裝體更是具有一導電材料,該導電材料與接點或延伸部的下表面接合,並與容置於開孔內的導電件接合,使導電件與接點電連通。 According to the package described in claim 13, a part of the conductive member is accommodated in the opening and is not connected to the terminal, and the package further has a conductive material, and the conductive material is connected to the contact or the extension portion. The lower surface of the contactor is engaged with the conductive member accommodated in the opening, so that the conductive member is electrically communicated with the contact point. 如申請專利範圍第11項所述之封裝體,塑料凹部開度的寬度小於接點下表面的寬度。 According to the package described in claim 11, the width of the opening of the plastic recess is smaller than the width of the lower surface of the contact. 如申請專利範圍第11項所述之封裝體,接點下表面的一部分與塑料接合。 The package body described in claim 11, wherein a portion of the lower surface of the contact is bonded to plastic. 一種封裝體,具有端點、晶片、導電件及塑料,其特徵是: An encapsulation body, comprising a terminal, a chip, a conductive member and a plastic, is characterized in that: 所述端點,具有接點及開孔,接點具有上表面、下表面及側邊,開孔設置在端點的任何位置,用以容置塑料或錫金屬等材料; The end point has a contact point and an opening, the contact point has an upper surface, a lower surface and a side edge, and the opening hole is arranged at any position of the end point to accommodate materials such as plastic or tin metal; 所述晶片,上表面具有連接墊; The wafer has connection pads on the upper surface; 所述導電件,其與晶片連接墊接合,並與接點上表面電連通,使晶片與端點電連通;及 the conductive member, which is engaged with the die attach pad and is in electrical communication with the upper surface of the contact, so that the die is in electrical communication with the terminal; and 所述塑料,其與端點接合並包覆晶片及導電件,並令接點下表面裸露於塑料供對外電連通。 The plastic is bonded to the terminal and covers the chip and the conductive member, and the lower surface of the contact is exposed to the plastic for external electrical communication. 如申請專利範圍第17項所述之封裝體,端點更是具有延伸部,延伸部與接點相鄰設置並能電連通,其具有上表面、下表面及側邊,其中,接點及延伸部的下表面是由不易被氧化金屬組成,且下表面裸露於塑料外。 According to the package described in claim 17, the end point further has an extension portion, the extension portion is disposed adjacent to the contact point and can be electrically connected, and has an upper surface, a lower surface and a side edge, wherein the contact point and The lower surface of the extension part is made of metal that is not easily oxidized, and the lower surface is exposed to the outside of the plastic. 如申請專利範圍第17項所述之封裝體,導電件的一部分容置於開孔內,且不與端點接合,而封裝體更是具有一導電材料,該導電材料與接點或延伸部的下表面接合,並與容置於開孔內的導電件接合,使導電件與接點電連通。 According to the package body described in claim 17, a part of the conductive member is accommodated in the opening and is not connected to the terminal, and the package body further has a conductive material, and the conductive material is connected to the contact point or the extension part. The lower surface of the contactor is engaged with the conductive member accommodated in the opening, so that the conductive member is electrically communicated with the contact point. 一種封裝體,具有晶片、導電件、端點及塑料,其特徵是: A package body has a chip, a conductive member, a terminal and a plastic, and is characterized by: 所述端點,具有接點及延伸部,延伸部與接點相鄰設置並能電連通,且均具有上表面、下表面及側邊,其中,接點及延伸部下表面是由不易被氧化金屬組成; The end point has a contact point and an extension part, the extension part is adjacent to the contact point and can be electrically connected, and each has an upper surface, a lower surface and a side, wherein the contact point and the lower surface of the extension part are not easily oxidized. metal composition; 所述晶片,上表面具有連接墊; The wafer has connection pads on the upper surface; 所述導電件,其與晶片連接墊接合,並與接點上表面電連通,使晶片與端點電連通;及 the conductive member, which is engaged with the die attach pad and is in electrical communication with the upper surface of the contact, so that the die is in electrical communication with the terminal; and 所述塑料,其與端點接合並包覆晶片及導電件,並令接點及延伸部的下表面裸露於封裝體,使接點可對外電連通。 The plastic is bonded to the terminal and covers the chip and the conductive member, and exposes the lower surface of the contact point and the extension part to the package body, so that the contact point can be electrically connected to the outside. 如申請專利範圍第20項所述之封裝體,端點更是具有絕緣層,其具有上表面及下表面,絕緣層與接點及延伸部接合,使一部分的接點或延伸部上表面裸露於絕緣層上表面,並使接點及延伸部的下表面裸露於絕緣層下表面,且令晶片設位在絕緣層上表面。 According to the package described in item 20 of the scope of the patent application, the terminal is further provided with an insulating layer, which has an upper surface and a lower surface, and the insulating layer is joined to the contact and the extension, so that a part of the upper surface of the contact or the extension is exposed on the upper surface of the insulating layer, the lower surfaces of the contacts and the extension part are exposed on the lower surface of the insulating layer, and the chip is positioned on the upper surface of the insulating layer. 如申請專利範圍第21項所述之封裝體,絕緣層下表面具有凹部,並令接點及延伸部的下表面裸露於凹部的底部。 According to the package described in claim 21, a lower surface of the insulating layer has a concave portion, and the lower surfaces of the contacts and the extension portion are exposed at the bottom of the concave portion. 如申請專利範圍第21項所述之封裝體,端點更是具有線路,線路設置在絕緣層上表面並與接點電連通。 According to the package body described in the claim 21, the end point is further provided with a circuit, and the circuit is arranged on the upper surface of the insulating layer and is electrically connected with the contact point.
TW109147107A 2020-12-31 2020-12-31 A terminal and package used in electronic product TW202230674A (en)

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