TW202230674A - A terminal and package used in electronic product - Google Patents
A terminal and package used in electronic product Download PDFInfo
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- TW202230674A TW202230674A TW109147107A TW109147107A TW202230674A TW 202230674 A TW202230674 A TW 202230674A TW 109147107 A TW109147107 A TW 109147107A TW 109147107 A TW109147107 A TW 109147107A TW 202230674 A TW202230674 A TW 202230674A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
一種供電子裝置用的端點,尤指用於半導體的封裝體。 A terminal for an electronic device, especially a package for a semiconductor.
如圖7A~圖7B所示,是無引腳扁平封裝體(QFN)結構,其中,圖7A是俯視圖,圖7B是圖7A切割線CC的剖視圖,封裝體1A包含有:端點3、晶片20、導電件18及塑料60,端點3是框架(lead frame)的一部分,是由C7025系列的銅金屬製成,該端點3具有接點3A、延伸部3C及晶片座(die pad)3P,延伸部3C與接點3A相鄰設置並能電連通,接點3A具有上表面31、下表面32及側邊33,延伸部3C具有上表面31、下表面3C2及側邊33,其中,接點3A及延伸部3C的上表面31是齊平的,依據設計準則:接點3A最小的厚度Ta為127微米(μm),接點3A最小的寬度W是200微米,而二接點3A最小的間隙S是150微米,而延伸部3C最小的厚度Tc是接點3A厚度Ta的一半,也就是64微米,使接點3A下表面32凸出於延伸部3C下表面3C2,並使接合區域3S相對應的下表面3C2區域是懸空的,而距延伸部3C上表面31未端約200微米的區域內,是供導電件18接合的區域3S,且已知塑料60最小的厚度T6是200微米;晶片20,其上表面21具連接墊(bond pad)24,並藉黏膠40與晶片座3P接合;導電件18,實施為導電線,並分別與晶片20連接墊24及接點3A上表面31電連通,使晶片20與接點3A電連通;塑料60,其為絕緣體與端點3接合並包覆晶片20及導電件18,並令接點3A及晶片座3P的下表面32裸露於封裝體1A外;由於電子裝置除了需品質好成本低外,也被要求體積要更薄及更小,經多年的發展,封裝體1A已不易藉框架達到上述的需求,說明如下:1)降低厚度難:
如圖7B所示,封裝體1A厚度是由接點3A及塑料60的厚度Ta、T6疊加組成,使封裝體1A因具有接點3A厚度Ta無法降到最低,再如圖7C所示,是將圖7B接點3A厚度Ta降為30微米的剖視圖,接點3A側邊33與塑料60接合的面積明顯的被降低,當錫Tn與接點3A接合且受外力拉扯時,塑料60與接點3A上表面31及側邊33接合處,易產生剝離的損壞;2)延伸部限制多:如圖7B所示,當長度L過長時,在導電件18與延伸部3C接合過程中,延伸部3C會因剛性不足而產生振動,造成導電件18接合強度不足的損壞,據此,長度L需小於2,500微米,再如圖7C所示,當接點3A厚度Ta降為30微米,而延伸部3C厚度Tc僅為15微米時,因厚度太薄使剛性更不足而無法與導電件18接合,令端點3無法具有延伸部3C;由上述得,需優化封裝體1A以滿足電子裝置的需求。
As shown in FIGS. 7A to 7B , it is a leadless flat package (QFN) structure, wherein FIG. 7A is a top view, and FIG. 7B is a cross-sectional view of the cutting line CC in FIG. 7A . The
優化習用封裝體的方法之一是令端點具有開孔,該開孔可供容置塑料等材料,並令塑料崁在端點內,使端點可更穩固的與塑料接合;另一方法是令端點具有延伸部,延伸部除了可增加與塑料的接合面積,使端點可更穩固的與塑料接合外,並使導電件與延伸部接合時,藉延伸部下表面不是懸空的特徵,使導電件可更穩固的與延伸部接合。 One of the ways to optimize the conventional package is to make the terminals have openings, which can accommodate materials such as plastic, and make the plastic embedded in the terminals, so that the terminals can be more firmly bonded to the plastic; another method The end point has an extension part, the extension part can not only increase the bonding area with the plastic, so that the end point can be more firmly bonded with the plastic, and when the conductive part is connected with the extension part, the lower surface of the extension part is not suspended. The conductive member can be more firmly connected with the extension portion.
3、30:端點 3, 30: Endpoint
10、15、1A:封裝體 10, 15, 1A: Package body
18、28:導電件 18, 28: Conductive parts
20:晶片 20: Wafer
21、31、81、91:上表面 21, 31, 81, 91: upper surface
24:連接墊 24: Connection pad
2a:銅柱 2a: copper pillar
2b:錫金屬 2b: Tin metal
32、3C2、3E2、62、82、92:下表面 32, 3C2, 3E2, 62, 82, 92: lower surface
33:側邊 33: Side
34:開孔 34: Opening
38:導電層 38: Conductive layer
3A、3B:接點 3A, 3B: Contacts
3C、3E、3Ea:延伸部 3C, 3E, 3Ea: Extensions
3P:晶片座 3P: Chip holder
3S:接合區域 3S: junction area
40:黏膠 40: Viscose
60:塑料 60: plastic
68、88、98:凹部 68, 88, 98: Recess
70、75:線路 70, 75: Line
80:載板 80: carrier board
8C、8D:元件 8C, 8D: Components
90、95:絕緣層 90, 95: insulating layer
CC:切割線 CC: cutting line
D:深度 D: depth
F:外來物 F: foreign object
L:長度 L: length
PC:電路板 PC: circuit board
S、Se、St:間隙 S, Se, St: Clearance
Tn:錫 Tn: Tin
T3、T6、Ta、Tc、Tp:厚度 T3, T6, Ta, Tc, Tp: Thickness
W:寬度 W: width
Y:開度 Y: opening
圖1A~圖1C:封裝體的俯視圖、底視圖及剖視圖 1A to 1C : top view, bottom view and cross-sectional view of the package body
圖2A~圖2D:端點及載板剖視圖 Figures 2A to 2D: Cross-sectional views of terminals and carrier
圖3~圖3E1、圖4A~圖4C及圖5A~圖5C:封裝體製造流程剖視圖 FIGS. 3 to 3E1 , 4A to 4C and 5A to 5C : cross-sectional views of the package manufacturing process
圖6A~圖6D:封裝體剖視圖 6A to 6D: Cross-sectional views of the package body
圖7A~圖7C:習用封裝體的俯視圖及剖視圖 7A to 7C : a top view and a cross-sectional view of a conventional package
如圖1A~圖1C所示實施例,圖1A是封裝體俯視圖,圖1B是圖
1A切割線CC的剖視圖,圖1C是封裝體底視圖,封裝體10包含有:端點30、晶片20、導電件18及塑料60,該端點30是導體可由銅或鎳等導電材料製成,或由鎳及銅、錫及銅、錫及鎳、鎳及金、鎳及銀、鎳及鈀及金等不同材料堆疊製成,該端點30具有接點3B,並令端點30更是可具有延伸部3E或開孔34,接點3B具有上表面31、下表面32及側邊33,其厚度T3是30微米,寬度W是200微米,而二接點3B間的間隙S是150微米,該開孔34可設置在接點3B或延伸部3E的任何位置,並可設計成圓形或橢圓形或多邊形等形狀,用以容置塑料60或錫或鎳等材料,該延伸部3E具有上表面31、下表面3E2及側邊33,其設置在接點3B周緣並能電連通,且延伸部3B上表面31及下表面3E2,分別與接點3B上表面31及下表面32是齊平的,另外,接點3B及延伸部3E的下表面32、3E2不是易被氧化的銅金屬,而是由不易被氧化的金屬組成,如:鎳或錫等金屬;晶片20,其上表面21具有連接墊24,晶片20與黏膠40接合並設置在接點3B周緣,並可依需求令晶片20設置在端點30表面(參閱圖4B);導電件18,實施為導電線,其分別與晶片20連接墊24及接點3B上表面31電連通,或經由延伸部3E上表面31與接點3B上表面31電連通,使晶片20與接點3B電連通;塑料(molding compound)60,是為包覆晶片20及導電件18而設計的絕緣體,塑料60與端點30接合並包覆晶片20及導電件18,並使接點3B及延伸部3E的下表面32、3E2,及黏膠40裸露於封裝體10外;由上述說明,封裝體10相比於圖7B~圖7C習用封裝體1A,具有下列優點:1)延伸部限制少:手機等消費性產品,會將電子元件妥善的包封在外殼內,用以避免電子元件因外來物造成電性短路,經分析發現,封裝體10藉導電材料與電路板(PC_參閱圖4C)接合後,該導電材料可實施為錫Tn,而具導電性的外來物F必需小於150微米才能穿過二錫Tn的間隙St,即使外物F可進到延伸部3E周緣,當二延伸部3E的間隙Se大於150微米時,更可降低二延伸部3E造成電性短路的風險,
或當間隙Se小於150微米時,可令塑料60具有凹部(68_參閱圖4C),用以加大二延伸部3E間的距離,甚至使該距離可大於二延伸部的間隙Se,或在封裝體10的周緣塗佈絕緣膠,使外來物F無法穿過二錫Tn間隙St,以上方法,均可減少延伸部3E造成電性短路的風險,甚至使風險趨近於零而可忽略,使延伸部3E可裸露於封裝體10外,另外,當導電件18與延伸部3E的接合區域3S接合時,因延伸部3E可與載板(80_參閱圖4B)接合,使導電件18不會因剛性不足而造成接合強度不足的損壞,使延伸部3E不受長度L的限制;2)端點及封裝體厚度更薄:藉端點30具有開孔34,令塑料60的一部分容置於開孔34內,使塑料60如圖釘般的釘在端點30內,並使接點3B能與塑料60更穩固的接合,或藉端點30具有延伸部3E,使端點30可增加與塑料60的接合面積及強度,並使接點3B更穩固的與塑料60接合,令設置開孔34或延伸部3E,均可使錫Tn受外力拉扯時,減少接點3B與塑料60間造成剝離的損壞,使接點3B厚度T3可小於30或15或5微米,相比習用接點3A厚度Ta可顯著的減薄;由上述說明可知,封裝體10更能符合電子裝置需求。
The embodiment shown in FIG. 1A to FIG. 1C, FIG. 1A is a top view of the package body, and FIG. 1B is a diagram of
1A is a cross-sectional view of the cutting line CC, and FIG. 1C is a bottom view of the package body. The
如圖2A~圖2D所示實施例剖視圖,是以圖1B端點30為基礎發展而得的端點,各端點30至少具有接點3B,接點3B具有上表面31、下表面32及側邊33,首先,如圖2A所示,端點30更是具有延伸部3E及開孔34,延伸部3E與接點3B相鄰設置並能電連通,且開孔34設置在延伸部3E,用以供容置塑料或錫或導電件(28_參閱圖3B),一載板80,其具有上表面81及下表面82,載板80可由銅等導電材料組成,或由環氧樹脂等絕緣材料組成,或由不同層數的導電及絕緣材料堆疊組成(參閱圖2B~圖2D),本例實施為銅,且接點3B及延伸部3E的下表面32、3E2與載板80上表面81接合;接著,如圖2B所示,端點30更是具有開孔34,一導體或塑料(60)容置於開孔34內並與接點3B接合,導體可實施為錫Tn或鎳或銅等導電材料,且塑料或導體表面可凸
出或齊平或凹設於接點3B上表面31或下表面32,一載板80,其至少具有上表面81、下表面82及凹部88,接點3B下表面32與載板80上表面81接合,而凹部88用以容置錫Tn等導體,載板80由二導電的元件8C堆疊組成,該導電元件8C可由銅或其他導電材料製成;接著,如圖2C所示,端點30更是具有導電層38,導電層38可由金或鎳或銀或錫等適用的金屬組成,或由不同的導電材料堆疊組成,如鎳及金、鎳及鈀及金、鈀及金等等,導電層38可設置在接點3B或延伸部(未繪示)的上表面31或下表面32,並令導電層38成為接點3B或延伸部的上表面31或下表面的一部分,導電層38具有保護端點30表面不被氧化,或不被化學溶劑侵蝕,或提升與其他導體接合品質的功效,一載板80,其具有上表面81、下表面82及凹部88,接點3B下表面32與載板80上表面81接合,凹部88的深度D可大於1或10或20微米,用以容置塑料或環氧樹脂等的絕緣材料,載板80由導電的元件8C及絕緣的元件8D堆疊組成,該絕緣元件8D可由環氧樹脂或其他絕緣材料組成;接著,如圖2D所示,載板80,其具有上表面81及下表面82,並由二導電的元件8C,及一絕緣的元件8D堆疊組成,該端點30具有接點3B、延伸部3E及絕緣層90,其中,接點3B及延伸部3E的下表面32、3E2與載板80上表面81接合,而絕緣層90實施為環氧樹脂或防焊油墨(solder mask)或其他絕緣材料,其設置在載板80上表面81並與接點3B及延伸部3E接合,並令接點3B或延伸部3E上表面31的一部分不與絕緣層90接合,用以供電連通用,或可在絕緣層90上表面91再堆疊至少一線路(70_參閱圖6C)或絕緣層,使端點30具有至少二層導電層的結構;由圖2A~圖2D說明可知,端點30與載板80組合的結構,可視為一組件並可被生產、儲存及使用。
The cross-sectional views of the embodiment shown in FIGS. 2A to 2D are endpoints developed based on the
如圖3A~圖3D及圖3A~圖3E1所示,是封裝體製作流程的剖視圖,首先,如圖3A所示,提供一端點30及載板80,該端點30及載板80的特
徵與符號與圖2A的端點30相同,請參閱圖2A說明,且端點30依產品需求可具有或不具有延伸部3E;接著,如圖3B所示,先提供晶片20及導電件28,晶片20上表面21具有連接墊24,並設置在端點30表面,導電件28實施為以錫金屬為主要材料的凸塊(bump),其一部分容置於開孔34內,並分別與晶片20連接墊24及延伸部3E電連通,並經由延伸部3E上表面31與接點3B上表面31電連通,使晶片20與接點3B電連通,然後將塑料60設置在載板80上表面81,其與端點30接合並包覆晶片20及導電件28,另外,導電件28可置換以銅及錫金屬為主要材料的銅凸塊(copper pillar bump_參閱圖6A);接著,如圖3C所示,將載板80移除,使導電件28的一部分、接點3B下表面32及延伸部3E下表面3E2裸露於大氣中,至此,封裝體10就已形成,同時,使塑料60與接點3B及延伸部3E呈並列設置,而可忽略接點3B及延伸部3E的厚度,使封裝體10的厚度就是塑料60的厚度;接著,如圖3D所示,依產品需求,可提供一實施為防焊油墨或其他絕緣材料的絕緣層90,其與塑料60下表面62接合,並至少令接點3B下表面32可裸露於大氣中,供對外電連通用,藉絕緣層90可使接點3B及延伸部3E更穩固的與塑料60接合,並能避免延伸部3E造成電性短路的損壞;接著,如圖3C1所示,依產品需求,在完成圖3B的步驟,且載板80上表面81實施為導電的元件(8C_參閱圖2B)時,將部分的載板80移除,令未被移除的載板80轉換成線路70,且線路70可與接點3B電連通或不電連通;接著,如圖3D1所示,提供一實施為防焊油墨或環氧樹脂或其他絕緣材料的絕緣層90,絕緣層90設置在塑料60下表面62並與線路70接合,令一部分的線路70未被絕緣層90包覆,可供錫接合或對外電連通用,至此,封裝體15就已形成;接著,如圖3E1所示,可再依需求,在絕緣層90下表面92再堆疊至少一第二線路75或第二絕緣層95,使端點30具有多層線路的結構。
3A to 3D and 3A to 3E1 are cross-sectional views of the manufacturing process of the package. First, as shown in FIG. 3A, a terminal 30 and a
如圖4A~圖4C所示,是封裝體製作流程的剖視圖,首先,如
圖4A所示,提供端點30及載板80,該載板80由導電的元件8C及絕緣的元件8D堆疊組成,並具有上表面81、下表面82及凹部88,其中,凹部88位於上表面81,使凹部88的底部與上表面81間具有一深度D,而元件8D可置換成元件8C,該端點30具有接點3B、延伸部3E及晶片座3P,並分別具有上表面31及下表面32、3E2,其下表面32、3E2實施為鎳或錫,且分別與載板80上表面81接合,一延伸部3E與接點3B相鄰設置並能電連通,而另一接點(3B_未繪示)與延伸部3Ea相鄰設置並能電連通,接點3B或延伸部3Ea的上表面31可設置導電層38,也可依需求令端點30不具有延伸部3E、3Ea;接著,如圖4B所示,先提供晶片20,晶片20藉黏膠40與晶片座3P接合後,導電件18分別與晶片20連接墊24、接點3B及延伸部3Ea接合,使晶片20與接點3B電連通,接著,塑料60與端點30接合並包覆晶片20及導電件18,且塑料60的一部分容置於載板80凹部88內;接著,如圖4C所示,將載板80移除,至此,封裝體10就已形成,並令塑料60具有凹部68,該凹部68的深度可大於1或10或20微米,使塑料60下表面62凸出於接點3B下表面32、延伸部3E下表面3E2及晶片座39下表面32,並令接點3B、延伸部3E及晶片座3P的下表面32、3E2裸露於凹部68的底部;塑料60凹部68的功效說明如下:1)減少電性短路風險:當封裝體10藉錫Tn與電路板PC端點接合後,因錫Tn的一部分容置於凹部68內,使封裝體10與電路板PC間的厚度Tp得以降低,藉此,除了使可穿過二錫Tn間的間隙(St_參閱圖1C),到達延伸部3E、3Ea周緣的外來物F是更小且更少外,更可藉凹部68的深度加大二延伸部3E、3Ea間的距離,該距離甚至可大於間隙(St),據此,二延伸部3E、3Ea間因外來物F造成電性短路的風險將更低,進而可忽略該風險;2)減少電性斷路風險:因錫Tn的一部分容置於塑料60凹部68,使錫Tn崁在塑料60內,而能更穩固的與接點3B接合,當錫Tn受外力左右拉扯時,可降低接點3B受外力的拉扯,進而可降低接點3B與塑料60間
產生剝離,以及造成接點3B與導電件18間電性斷路的損壞;3)最薄的封裝體厚度:藉接點3B及延伸部3E、3Ea裸露於凹部68底部的特徵,使接點3B及延伸部3E、3Ea均與塑料60呈並列設置,而可忽略接點3B等元件的厚度(T3),使封裝體10的厚度僅由塑料60厚度T6組成,也就是目前已知最薄的厚度200微米;4)降低導電件材料用量:增加凹部68的深度,或不具有晶片座3P,或令黏膠40與載板80凹部88的底部接合,使黏膠40與塑料60下表面62齊平,均使接點3B及延伸部3Ea更靠近晶片20連接墊24,可達到減少導電件18長度的用量及成本,並能提升生產效率。
As shown in FIG. 4A to FIG. 4C, it is a cross-sectional view of the package manufacturing process. First, as shown in FIG. 4A~FIG. 4C
As shown in FIG. 4A, a terminal 30 and a
如圖5A~圖5C所示,是封裝體製作流程的剖視圖,首先,如圖5A所示,提供端點30及載板80,該載板80由導電的元件8C及絕緣的元件8D堆疊組成,並具有上表面81、下表面82及凹部88,其中,凹部88位於上表面81,使凹部88的底部與上表面81間具有一深度D,該端點30具有接點3B及延伸部3E,並分別具有上表面31及下表面32、3E2,其下表面下表面32、3E2實施為鎳或錫,並分別與載板80上表面81接合,同時,一接點3B與延伸部3E相鄰設置並能電連通;接著,如圖5B所示,先提供晶片20,其設置在端點30表面,導電件28分別與晶片20連接墊24、接點3B及延伸部3E接合,使晶片20與接點3B電連通,接著,塑料60與端點30接合並包覆晶片20及導電件28,且塑料60的一部分容置於載板80凹部88內;接著,如圖5C所示,將載板80移除,至此,封裝體10就已形成,並令塑料60具有凹部68,該凹部68的深度可大於1或10或20微米,使塑料60下表面62凸出於接點3B、延伸部3E的下表面32、3E2,並令接點3B及延伸部3E的下表面32、3E2裸露於凹部68的底部,且凹部68開度Y的寬度是小於接點3B下表面32寬度(W_參閱圖1A),或可令一部分的載板80元件8C容置於凹部68內與接點3B下表面32接合;塑料60凹部68具降低接點3B剝離風險,說明如下:1)當一導電材料容置於凹
部68內時,其可實施為錫Tn或元件8C,在導電材料受外力拉扯時,因凹部68開度Y小於接點3B下表面32,令凹部68呈梯形狀,使導電材料可更穩固的容置於凹部68內與接點3B接合,以及減少接點3B受外力的拉扯,進而可降低接點3B與塑料60間剝離的風險;2)不論凹部68是否呈梯形狀,只要一部分的接點3B下表面32與塑料60接合時,使接點3B被卡在塑料60內,都可降低受外力拉扯造成剝離的風險,據此,使端點30厚度(T3_參閱圖1B)可如薄膜,可小於7或3或1微米,使端點30的用料及製作成本得以有效降低。
As shown in FIGS. 5A to 5C , which are cross-sectional views of the package fabrication process, first, as shown in FIG. 5A , the
如圖6A~圖6B所示實施例,圖6A是封裝體剖視圖,圖6B是封裝體與錫Tn接合後的剖視圖,該封裝體10包含有:端點30、晶片20、塑料60及導電件28,該端點30具有接點3B及開孔34,接點3B具有上表面31、下表面32及側邊33,而開孔34設置在接點3B;晶片20,上表面21具有連接墊24;導電件28,實施為銅凸塊,其具有銅柱2a及錫金屬2b,銅柱2a與晶片20連接墊24接合,而錫金屬2b容置於開孔34內,但不與端點30接合;依需求,可令錫金屬2b與接點3B電連通(參閱圖3C),或可令端點30無開孔34,使錫金屬2b與接點3B上表面31接合,或令開孔34內具有錫,使導電件28可不具有錫金屬2b用以降低成本;塑料60,其為絕緣體與端點30接合並包覆晶片20及導電件28,且塑料60的一部分容置於開孔34內,並令導電件28的一部分及接點3B下表面32,裸露於塑料60下表面62;如圖6B所示,一導電材料與接點3B下表面32接合,該導電材料可實施為錫Tn,使錫Tn可直接與導電件28電連通,並使導電件28與接點3B電連通;由上述說明可得下列優點;1)品質更好:錫Tn直接與導電件28的錫金屬2b接合,使導電件28與錫Tn間無不同金屬的介面,進而不會產生金屬間化合物,可避免因阻抗改變造成電性的衰減或損壞;2)接合性更好:錫Tn與導電件28的錫金屬2b接合,令錫Tn如圖釘般釘在塑料60內,使接點3B更穩固的與塑料60及錫Tn接合,可降低錫Tn被拉
扯而造成接點3B與塑料60間剝離的損壞,據此,接點3B厚度(T3)可實施得更薄,如:小於10或5或1微米,並可藉更薄的接點3B,減少封裝體10厚度,以及達到接點3B及塑料60用料更少及成本更低的功效。
6A to FIG. 6B , FIG. 6A is a cross-sectional view of the package body, and FIG. 6B is a cross-sectional view of the package body after bonding with tin Tn. The
如圖6C所示實施例是封裝體剖視圖,封裝體10的晶片20、黏膠40、塑料60及導電件18特徵及符號,與圖1B所示的相同,請參閱圖1B說明,該端點30除了具有接點3B及延伸部3E外,更是具有絕緣層90及線路70,延伸部3E與接點3B相鄰設置並能電連通,且其下表面32、3E2不是易被氧化的銅金屬,而是由不易被氧化的金屬組成,如:鎳或錫等金屬,該絕緣層90與接點3B及延伸部3E接合,並使接點3B及延伸部3E的下表面32、3E2裸露於絕緣體90凹部98的底部,該凹部98是由載板的凹部(88_參閱圖2C)形成的,依需求也可令絕緣體90不具有凹部98,該線路70設置在絕緣層90上表面91並與接點3B電連通,或可在絕緣層90上表面91設置第二絕緣層並與線路70接合,使線路70的一部分裸露第二絕緣層外,該晶片20設置在端點30表面,藉黏膠40與端點30接合,並藉導電件18與線路70電連通,使晶片20與接點3B電連通,該塑料60與端點30接合並包覆晶片20及導電件18,並令接點3B及延伸部3E的下表面32、3E2裸露於封裝體10外,使接點3B可對外電連通;由上述說明可知,設置絕緣層90及線路70,使端點30與習用二層線路的電路板結構相同,但不需如習用電路板在絕緣層90下表面92需再設置一防焊層(未繪示),用以包覆延伸部3E下表面3E2,使下表面3E2不裸露封裝體10外,據此,封裝體10因不需設置防焊層而可達到降低成本及減少厚度的功效。
The embodiment shown in FIG. 6C is a cross-sectional view of the package body. The features and symbols of the
本發明實施例僅例示性說明本發明的原理及其功效,而非用於限制本發明的。任何熟悉此技術的人士皆可在不違背本發明的精神及範疇下,對上述實施例進行修飾或改變。因此,舉凡所屬技術領域中具有通常知識者在未脫離本發明的所揭示的精神與技術思想下所完成的一切等效 修飾或改變,仍應由本發明的權利要求所涵蓋。 The embodiments of the present invention merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalents accomplished by those with ordinary knowledge in the technical field without departing from the disclosed spirit and technical idea of the present invention Modifications or changes should still be covered by the claims of the present invention.
10:封裝體 10: Package body
20:晶片 20: Wafer
21、31:上表面 21, 31: upper surface
24:連接墊 24: Connection pad
28:導電件 28: Conductive parts
2a:銅柱 2a: copper pillar
2b:錫金屬 2b: Tin metal
30:端點 30: Endpoint
32、62:下表面 32, 62: lower surface
33:側邊 33: Side
34:開孔 34: Opening
3B:接點 3B: Contact
60:塑料 60: plastic
Claims (23)
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TW109147107A TW202230674A (en) | 2020-12-31 | 2020-12-31 | A terminal and package used in electronic product |
CN202111281261.1A CN114023732A (en) | 2020-12-31 | 2021-11-01 | Frame and packaging body of electronic device |
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TW109147107A TW202230674A (en) | 2020-12-31 | 2020-12-31 | A terminal and package used in electronic product |
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TW109147107A TW202230674A (en) | 2020-12-31 | 2020-12-31 | A terminal and package used in electronic product |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN114023732A (en) |
TW (1) | TW202230674A (en) |
-
2020
- 2020-12-31 TW TW109147107A patent/TW202230674A/en unknown
-
2021
- 2021-11-01 CN CN202111281261.1A patent/CN114023732A/en active Pending
Also Published As
Publication number | Publication date |
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CN114023732A (en) | 2022-02-08 |
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