TW202230381A - Operation method for a memory device - Google Patents

Abstract

An operation method for a memory device is provided. The operation method includes: increasing an adjacent word line voltage to a first adjacent word line voltage during a pre-turn on period; and increasing the adjacent word line voltage from the first adjacent word line voltage to a second adjacent word line voltage after the pre-turn on period is finished; wherein the first adjacent word line voltage is lower than the second adjacent word line voltage; the adjacent word line voltage is applied to at least one adjacent word line, and the at least one adjacent word line is adjacent to a selected word line.

Description

How to operate a memory device

The present invention relates to an operation method of a memory device, in particular, to a read operation method of the memory device.

For three-dimensional (3D) memory devices, after many read cycles of a selected word line (eg, after 100K read cycles), adjacent word lines of the selected word line may encounter read Take the problem of read disturbance.

After analysis, it can be known that when the pre-turn-on period of the target word line is turned off, if the pass voltage (Vpass) of the target word line is lower than the target word line If the critical value is exceeded, the down-coupling effect will occur. This will cause a large channel potential difference between the target word line and its neighboring word lines, and a high vertical electronic field on its neighboring word lines. As a result, hot carrier injection is more likely to occur, which in turn causes read disturb.

According to an example of the present application, an operation method of a memory device is proposed, which includes: during a pre-on period, the voltage of an adjacent word line rises to a voltage of a first adjacent word line; and after the pre-on period ends, the The adjacent word line voltage rises from the first adjacent word line voltage to a second adjacent word line voltage. The first adjacent word line voltage is lower than the second adjacent word line voltage. The adjacent word line voltage is applied to at least one adjacent word line that is adjacent to a selected word line.

According to another example of the present application, an operation method of a memory device is proposed, including: during a pre-on period, a voltage of a selected word line rises to a voltage of a first selected word line, and the voltage of the selected word line The voltage from the first selected word line drops in multiple steps, and when the voltage drops in multiple steps, the number of steps is more than two.

According to yet another example of the present application, an operation method of a memory device is proposed, including: during a pre-on period, a selected word line voltage rises to a first selected word line voltage; and from a first timing to a In the second time sequence, the voltage of the selected word line decreases with a smooth curve from the voltage of the first selected word line.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

The technical terms in this specification refer to the common terms in the technical field. If some terms are described or defined in this description, the interpretations of these terms are subject to the descriptions or definitions in this description. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

Please refer to FIG. 1, which shows a functional block diagram of a memory device according to an embodiment of the present application. The memory device 100 includes a controller 110 and a memory array 120 . The controller 110 is coupled to the memory array 120 . The controller 110 controls operations of the memory array 120, such as read operations and the like.

FIG. 2 shows a three-dimensional (3D) circuit diagram of the memory array 120 according to an embodiment of the present invention. The memory array 120 includes: a plurality of string select lines (SSL) (SSL0_0~SSL2_3), a plurality of redundant word lines (DWLT1, DWLT0, DWLB1, DWLB0), a plurality of word lines (WL0~WLN-1, N is a positive integer), a plurality of bit lines (BL0~BL3), a plurality of global select lines (GSL0~GSL3), and a plurality of memory cells. It should be known that Figure 2 is an example, and this case is not limited to this.

Generally speaking, the memory array 120 includes a plurality of memory blocks. Each memory block includes, by way of example and not limitation, 4 sub-blocks. As shown in FIG. 2, the sub-blocks SB0-SB3 can be independently selected by the string selection lines SSL0_0-SSL2_3 and the global selection lines GSL0-GSL3, respectively.

FIG. 3 shows a waveform diagram of a read operation of the memory device according to the first embodiment of the present application. VBL is the bit line voltage; VSWL is the selected word line voltage; VUWL is the unselected word line voltage; VAWL is the adjacent word line voltage; VSSL is the string select line voltage; and VGSL is the global select line voltage. In the following description, the word line WLn (n is an integer between 0 and N-1) is used as the "selected word line (target word line)", and is adjacent to the selected word line WLn The word lines WLn+1 and WLn-1 are called "adjacent word lines". The selected word line voltage VSWL is applied to the selected word line, and the adjacent word line voltage VAWL is applied to the adjacent word line.

In the first embodiment of the present application, during the pre-on period, the bit line voltage VBL is at a low voltage (also referred to as a reference voltage) (such as, but not limited to, 0V), and during the read period, the bit line voltage VBL transitions to a high voltage (T34), and at the end of the read period (T37), the bit line voltage VBL transitions to a low voltage.

In the first embodiment of the present invention, during the pre-on period, the selected word line voltage VSWL rises to the first selected word line voltage VSWL1 at the timing T31 and falls at the timing T32. During reading, the selected word line voltage VSWL has multi-level voltages (also called multi-level increasing voltages): the first level voltage (ie the second selected word line voltage VSWL2) is and the second-level voltage (ie, the third selected word line voltage VSWL3 ) rises from the first-level voltage (ie, the second selected word line voltage VSWL2 ) at the timing T35 . At timing T36, the selected word line voltage VSWL rises from the third selected word line voltage VSWL3 to the first selected word line voltage VSWL1. At the end of the read period, the selected word line voltage VSWL transitions to a low voltage (timing T37). The second selected word line voltage VSWL2 and the third selected word line voltage VSWL3 are read voltages.

In the first embodiment of the present application, during the pre-on period, the unselected word line voltage VUWL rises at time sequence T31; when the read period ends, the unselected word line voltage VUWL transitions to a low voltage.

In the first embodiment of the present application, during the pre-on period, the adjacent word line voltage VAWL rises to the first adjacent word line voltage VAWL1 at the time sequence T31. After the pre-on period ends, the adjacent word line voltage VAWL rises from the first adjacent word line voltage VAWL1 to the second adjacent word line voltage VAWL2 at timing T33. At the end of the read period, the adjacent word line voltage VAWL transitions to a low voltage. The first adjacent word line voltage VAWL1 is lower than the second adjacent word line voltage VAWL2; the second adjacent word line voltage VAWL2 is the same as the unselected word line voltage VUWL.

In the first embodiment of the present application, during the pre-on period, the voltage of the adjacent word line (the first adjacent word line voltage VAWL1 ) is lower than the selected word line voltage VSWL of the selected word line, which can reduce the Vertical electric field on adjacent word lines during pre-on.

In the first embodiment of the present application, the timing ( T33 ) when the adjacent word line voltage VAWL rises to the second adjacent word line voltage VAWL2 is later than the end of the pre-on period, which can reduce the number of adjacent words in the read period. The horizontal electric field on the element line.

In the first embodiment of the present application, the value of the voltage VAWL1 of the first adjacent word line, for example, but not limited to, is greater than the threshold voltage of the memory cell on the adjacent word line, and may be between 2V and 5V .

In the first embodiment of the present case, the value of the second adjacent word line voltage VAWL2 is related to the pass voltage (Vpass). For example, the value of the second adjacent word line voltage VAWL2, such as but not limited to, is a sufficiently high pass voltage (Vpass), which may be between 6V~9V (or 6V~10V).

In the first embodiment of the present case, during the pre-on period, the string selection line voltage VSSL (indicated by the curve L31 ) of the selected sub-block and the string selection line voltage VSSL (indicated by the curve L32 ) of the unselected sub-block are in the timing sequence T31 goes up. Also, at the end of the pre-on period, the string select line voltage VSSL (indicated by the curve L32 ) of the unselected sub-blocks drops at timing T32. At the end of the read period, the string select line voltage VSSL (indicated by curve L31 ) of the selected sub-block drops. During the read period, the string select line voltage VSSL (indicated by curve L32 ) of the unselected sub-blocks remains low.

In the first embodiment of the present application, during the pre-on period, the overall selection line voltage VGSL of the selected sub-blocks (indicated by the curve L33 ) and the overall selection line voltage VGSL of the unselected sub-blocks (indicated by the curve L34 ) are in the timing sequence T31 goes up. Also, at the end of the pre-on period, the overall select line voltage VGSL of the unselected sub-blocks (indicated by curve L34 ) drops at timing T32. At the end of the read period, the overall select line voltage VGSL (indicated by curve L33 ) of the selected sub-block drops. During the reading period, the overall select line voltage VGSL (indicated by curve L34 ) of the unselected sub-blocks remains low.

FIG. 4 shows a comparison diagram of the horizontal electric field and the vertical electric field of the prior art and the first embodiment of the present application. Curve L41 represents at the end of the pre-on period, in the conventional memory device (the read operation of the first embodiment of the present application is not applied), the selected word line WLn and the adjacent word lines WLn-1, WLn Horizontal electric field plot between +1 channel and ONO (oxide-nitride-oxide). The curve L42 represents when the adjacent word line voltage VAWL rises to the second adjacent word line voltage VAWL2 (time sequence T33), in the conventional memory device (the read operation of the first embodiment of the present application is not applied), Graph of the horizontal electric field between the channel of the selected word line WLn and the adjacent word lines WLn-1, WLn+1 and ONO.

Curve L43 represents at the end of the pre-on period, in the conventional memory device (the read operation of the first embodiment of the present application is not applied), between the selected word line WLn and the adjacent word lines WLn-1, WLn Plot of vertical electric field between ONO and gate at +1. Curve L44 represents when the adjacent word line voltage VAWL rises to the second adjacent word line voltage VAWL2 (time sequence T33), in the conventional memory device (the read operation of the first embodiment of the present application is not applied), Plot of vertical electric field between ONO and gate at selected word line WLn and adjacent word lines WLn-1, WLn+1.

Curve L45 represents the horizontal electric field curve between the channel of the selected word line WLn and the adjacent word lines WLn-1, WLn+1 and ONO in the first embodiment of the present application at the end of the pre-on period. The curve L46 represents that when the adjacent word line voltage VAWL rises to the second adjacent word line voltage VAWL2 (time sequence T33), in the first embodiment of the present application, the selected word line WLn and the adjacent word line WLn -1. The horizontal electric field curve between the channel of WLn+1 and ONO.

Curve L47 represents the vertical electric field curve between ONO and gate at the selected word line WLn and adjacent word lines WLn-1, WLn+1 in the first embodiment of the present case at the end of the pre-on period picture. The curve L48 represents that when the adjacent word line voltage VAWL rises to the second adjacent word line voltage VAWL2 (time sequence T33), in the first embodiment of the present application, the selected word line WLn and the adjacent word line WLn -1. The vertical electric field curve between the ONO and the gate at WLn+1.

Comparing the curve L43 and the curve L47, it can be seen that the read operation of the first embodiment of the present application can effectively reduce the vertical electric field of the adjacent word line, thereby reducing the read disturbance.

FIG. 5 is a graph showing the relationship between the variation of the threshold voltage and the number of readings in the prior art and the first embodiment of the present application. It can be seen from FIG. 5 that the first embodiment of the present application can reduce the variation of the threshold voltage, thereby reducing the read disturbance.

6A and 6B show waveforms of two read operations of the memory device according to the second embodiment of the present application. In FIGS. 6A and 6B , the waveforms of the bit line voltage VBL, the unselected word line voltage VUWL, the string select line voltage VSSL and the global select line voltage VGSL are in principle the same or similar to the bit lines in FIG. 3 . The waveforms of the voltage VBL, the unselected word line voltage VUWL, the string select line voltage VSSL and the overall select line voltage VGSL are omitted here.

Please refer to Figure 6A. In the second embodiment of the present application, during the pre-on period, the selected word line voltage VSWL rises to the first selected word line voltage VSWL601 at the time sequence T601 and drops with a multi-stage voltage at the time sequence T602 (also called multi-stage voltage). lower voltage). The selected word line voltage VSWL drops from the first selected word line voltage VSWL601 to the second selected word line voltage VSWL 602 at the time sequence T602, and the selected word line voltage VSWL decreases from the second selected word line voltage VSWL at the time sequence T603. The voltage VSWL602 drops to the third selected word line voltage VSWL603, the selected word line voltage VSWL drops from the third selected word line voltage VSWL603 to a low voltage at the time sequence T604, and the selected word line voltage VSWL drops from the third selected word line voltage VSWL603 to the low voltage at the time sequence T605. The low voltage rises to the first selected word line voltage VSWL601. The sequences 603, 604 and 605 are in the read period. At the end of the read period (T606), the selected word line voltage VSWL transitions to a low voltage. The second selected word line voltage VSWL602 and the third selected word line voltage VSWL603 can also be used as read voltages.

Please refer to Figure 6A. In the second embodiment of the present case, the adjacent word line voltage VAWL rises at the beginning of the pre-on period and falls at the end of the read period.

Please refer to Figure 6B. In the second embodiment of the present application, during the pre-on period, the selected word line voltage VSWL rises to the first selected word line voltage VSWL611 at the time sequence T611 and decreases in multiple steps at the time sequence T612. The selected word line voltage VSWL drops from the first selected word line voltage VSWL611 to the second selected word line voltage VSWL612 at the time sequence T612, and the selected word line voltage VSWL decreases from the second selected word line voltage VSWL at the time sequence T613. The voltage VSWL612 drops to the third selected word line voltage VSWL613, and the selected word line voltage VSWL drops from the third selected word line voltage VSWL613 to a low voltage at timing T614. The multi-step drop of the selected word line voltage VSWL of FIG. 6B is similar to the multi-step drop of the selected word line voltage VSWL of FIG. 6A.

The selected word line voltage VSWL rises from the low voltage to the fourth selected word line voltage VSWL 614 at timing T615. The selected word line voltage VSWL rises from the fourth selected word line voltage VSWL 614 to the fifth selected word line voltage VSWL 615 at timing T616. The selected word line voltage VSWL rises from the fifth selected word line voltage VSWL 615 to the first selected word line voltage VSWL 611 at timing T617. The multi-step rise of the selected word line voltage VSWL (during the read period) in FIG. 6B is similar to the multi-step rise of the selected word line voltage VSWL (during the read period) in FIG. 3 .

At the end of the read period (T618), the selected word line voltage VSWL transitions to a low voltage. The second selected word line voltage VSWL612, the third selected word line voltage VSWL613, the fourth selected word line voltage VSWL614 and the fifth selected word line voltage VSWL615 can also be used as read voltages.

The waveform of the adjacent word line voltage VAWL in FIG. 6B is the same as or similar to the waveform of the adjacent word line voltage VAWL in FIG. 6A, so its details are omitted here.

In the second embodiment of the present application, the first selected word line voltage /VSWL611 is higher than the highest threshold voltage of the plurality of memory cells of the selected word line WLn, for example, the first selected word line voltage VSWL601 / VSWL611 can be between 6V~10V.

In the second embodiment of the present case, during the multi-step drop, the second selected word line voltage VSWL602/VSWL612 is lower than the first selected word line voltage VSWL601/VSWL611, and the third selected word line voltage VSWL603/ VSWL613 It is lower than the second selected word line voltage VSWL602/VSWL612, and the rest can be deduced by analogy.

In the second embodiment of the present case, during the multi-order descent, the stages are at least more than 2 stages.

FIG. 7 shows a comparison diagram of the horizontal electric field and the vertical electric field between the prior art and the second embodiment of the present application. Curve L71 represents at the end of the pre-on period, in the conventional memory device (the read operation of the second embodiment of this case is not applied), the selected word line WLn and the adjacent word lines WLn-1, WLn A graph of the horizontal electric field between the channel at +1 and the ONO; the curve L72 represents at the time sequence T605/T615, in the prior art memory device (the read operation of the second embodiment of this case is not applied), when the selected Graph of the horizontal electric field between the channel and ONO at word line WLn and adjacent word lines WLn-1, WLn+1. Curve L73 represents at the end of the pre-on period, in the conventional memory device (the read operation of the second embodiment of the present application is not applied), the selected word line WLn and the adjacent word lines WLn-1, WLn The vertical electric field curve between the ONO and the gate at +1; the curve L74 represents at the time sequence T605/T615, in the conventional memory device (the read operation of the second embodiment of this case is not applied), when the Graph of vertical electric field between ONO and gate at selected word line WLn and adjacent word lines WLn-1, WLn+1. Curve L75 represents the level between the channel and ONO at the selected word line WLn and the adjacent word lines WLn-1, WLn+1 in the memory device of the second embodiment of the present application at the end of the pre-on period The electric field curve diagram; the curve L76 represents the channel and ONO at the selected word line WLn and the adjacent word lines WLn-1, WLn+1 in the memory device of the second embodiment of the present case at the time sequence T605/T615 The horizontal electric field curve between. Curve L77 represents at the end of the pre-on period, in the memory device of the second embodiment of the present application, between the ONO and the gate at the selected word line WLn and the adjacent word lines WLn-1 and WLn+1. The vertical electric field curve diagram; the curve L78 represents at the time sequence T605/T615, in the memory device of the second embodiment of this case, the ONO and ONO at the selected word line WLn and adjacent word lines WLn-1, WLn+1 Plot of vertical electric field between gates.

Comparing the curves L71 and L75, it can be seen that the read operation of the second embodiment of the present application can effectively reduce the horizontal electric field on the selected word line WLn, thereby reducing the read disturbance. Comparing the curves L73 and L77, it can be seen that the read operation of the second embodiment of the present application can effectively reduce the vertical electric field of the selected word line WLn, thereby reducing the read disturbance.

FIG. 8 is a graph showing the relationship between the variation of the threshold voltage and the number of readings in the prior art and the second embodiment of the present application. It can be seen from FIG. 8 that the second embodiment of the present application can reduce the variation of the threshold voltage, thereby reducing the read disturbance.

FIG. 9 shows a waveform diagram of a read operation of the memory device according to the third embodiment of the present application. In FIG. 9, the waveforms of the bit line voltage VBL, the unselected word line voltage VUWL, the adjacent word line VAWL, the string select line voltage VSSL and the overall select line voltage VGSL are in principle the same or similar to those shown in FIG. 6A or The waveforms of the bit line voltage VBL, the unselected word line voltage VUWL, the adjacent word line VAWL, the string select line voltage VSSL and the global select line voltage VGSL in FIG. 6B are omitted here.

In the third embodiment of the present application, during the pre-on period, the selected word line voltage VSWL rises to the first selected word line voltage VSWL91 at the time sequence T91. From the time sequence T92 to the time sequence T93, the selected word line voltage VSWL drops from the first selected word line voltage VSWL91 to a low voltage with a smooth curve. In a possible embodiment of the present application, the smooth curve is, for example, but not limited to, a straight line.

In the third embodiment of the present application, the time interval between the time sequence T92 and the time sequence T93 is greater than 1 μs, for example, between 1 μs and 10 μs.

In the third embodiment of the present application, during the reading period, the selected word line voltage VSWL has multiple levels of voltages: the first level voltage (ie, the second selected word line voltage VSWL92 ) is from a low voltage at time sequence T94 rising; and the second-level voltage (ie, the third selected word line voltage VSWL93 ) rises from the first-level voltage (ie, the second selected word line voltage VSWL92 ) at timing T95 . At timing T96, the selected word line voltage VSWL rises to the first selected word line voltage VSWL91. At the end of the read period, the selected word line voltage VSWL transitions to a low voltage (timing T97). The second selected word line voltage VSWL92 and the third selected word line voltage VSWL93 are read voltages.

FIG. 10 shows a comparison diagram of the horizontal electric field and the vertical electric field of the prior art and the third embodiment of the present application. The curve L101 represents at the end of the pre-on period, in the conventional memory device (the read operation of the third embodiment of this case is not applied), the selected word line WLn and the adjacent word lines WLn-1, WLn Plot of the horizontal electric field between the channel at +1 and the ONO. The curve L102 represents at the end of the pre-on period, in the conventional memory device (the read operation of the third embodiment of this case is not applied), the selected word line WLn and the adjacent word lines WLn-1, WLn Plot of vertical electric field between ONO and gate at +1. The curve L103 represents the horizontal electric field curve between the channel and ONO at the selected word line WLn and the adjacent word lines WLn-1 and WLn+1 in the memory device of the third embodiment at the time sequence T93 picture. The curve L104 represents the vertical electric field between the ONO and the gate at the selected word line WLn and the adjacent word lines WLn-1 and WLn+1 in the memory device of the third embodiment of the present case at the time sequence T93 Graph.

Comparing these curves L101 to L104, it can be seen that the read operation of the third embodiment of the present application can effectively reduce the horizontal electric field and the vertical electric field of the selected word line WLn, thereby reducing the read disturbance.

FIG. 11 is a graph showing the relationship between the variation of the threshold voltage and the number of readings in the prior art and the third embodiment of the present application. It can be seen from FIG. 11 that the third embodiment of the present application can reduce the variation of the threshold voltage, thereby reducing the read disturbance.

The above-mentioned first to third embodiments may be implemented independently or in combination. That is, the first and second embodiments may be implemented in combination; alternatively, the first and third embodiments may be implemented in combination. This is all within the spirit of this case.

It can be seen from the above description that the above-mentioned embodiments of the present application can effectively reduce the abnormal read disturbance of the selected word line.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Memory device 110: Controller 120: Memory array SSL0_0~SSL2_3: String selection line DWLT1, DWLT0, DWLB1, DWLT1: redundant word lines WL0~WLN-1: word line BL0~BL3: bit lines GSL0~GSL3: Overall selection line VBL: bit line voltage VSWL: selected word line voltage VUWL: Unselected word line voltage VAWL: Adjacent word line voltage VSSL: String Select Line Voltage VGSL: Overall Select Line Voltage VSWL1: The voltage of the first selected word line VSWL2: The second selected word line voltage VSWL3: The third selected word line voltage VAWL1: first adjacent word line voltage VAWL2: Second Adjacent Word Line Voltage T31~T37: Timing BL: bit line SSL0~SSL2: String selection line GSL: Overall Selection Line L31~L34, L41~L48: Curve T601~T618: Timing VSWL601: The voltage of the first selected word line VSWL602: The second selected word line voltage VSWL603: The third selected word line voltage VSWL611: The first selected word line voltage VSWL612: Second selected word line voltage VSWL613: The third selected word line voltage VSWL614: Fourth selected word line voltage VSWL615: Fifth selected word line voltage L71~L78: Curve T91~T97: Timing VSWL91: The voltage of the first selected word line VSWL92: The second selected word line voltage VSWL93: The third selected word line voltage L101~L104: Curve

FIG. 1 is a functional block diagram of a memory device according to an embodiment of the present invention. FIG. 2 shows a three-dimensional (3D) circuit diagram of a memory array according to an embodiment of the present application. FIG. 3 shows a waveform diagram of a read operation of the memory device according to the first embodiment of the present application. FIG. 4 shows a comparison diagram of the horizontal electric field and the vertical electric field of the prior art and the first embodiment of the present application. FIG. 5 is a graph showing the relationship between the variation of the threshold voltage and the number of readings in the prior art and the first embodiment of the present application. 6A and 6B show waveforms of two read operations of the memory device according to the second embodiment of the present application. FIG. 7 shows a comparison diagram of the horizontal electric field and the vertical electric field between the prior art and the second embodiment of the present application. FIG. 8 is a graph showing the relationship between the variation of the threshold voltage and the number of readings in the prior art and the second embodiment of the present application. FIG. 9 shows a waveform diagram of a read operation of the memory device according to the third embodiment of the present application. FIG. 10 shows a comparison diagram of the horizontal electric field and the vertical electric field of the prior art and the third embodiment of the present application. FIG. 11 is a graph showing the relationship between the variation of the threshold voltage and the number of readings in the prior art and the third embodiment of the present application.

VBL: bit line voltage

VSWL: selected word line voltage

VUWL: Unselected word line voltage

VAWL: Adjacent word line voltage

VSSL: String Select Line Voltage

VGSL: Overall Select Line Voltage

VSWL1: The voltage of the first selected word line

VSWL2: The second selected word line voltage

VSWL3: The third selected word line voltage

VAWL1: first adjacent word line voltage

VAWL2: Second Adjacent Word Line Voltage

T31~T37: Timing

L31~L34: Curve

BL: bit line

SSL0~SSL2: String selection line

WL0~WLN-1: word line

DWLT1, DWLT0, DWLB1, DWLT1: redundant word lines

GSL: Overall Selection Line

Claims (10)

A method of operating a memory device, comprising: during a pre-on period, an adjacent word line voltage rises to a first adjacent word line voltage; and After the pre-on period ends, the adjacent word line voltage rises from the first adjacent word line voltage to a second adjacent word line voltage; wherein the voltage of the first adjacent word line is lower than the voltage of the second adjacent word line, The adjacent word line voltage is applied to at least one adjacent word line that is adjacent to a selected word line. The operating method of a memory device as claimed in claim 1, wherein, During the pre-on period, the adjacent word line is lower than a selected word line voltage of the selected word line. The operating method of a memory device as claimed in claim 1, wherein, the first adjacent word line voltage is greater than a threshold voltage of a plurality of memory cells on the at least one adjacent word line; and The second adjacent word line voltage is related to a pass voltage. The operation method of the memory device as claimed in claim 1, further comprising: During the pre-on period, a selected word line voltage rises to a first selected word line voltage, and The voltage of the selected word line drops from the voltage of the first selected word line in multiple steps. When the voltage of the selected word line drops in multiple steps, the number of steps is more than two. The operation method of the memory device as claimed in claim 1, further comprising: During the pre-on period, a selected word line voltage rises to a first selected word line voltage; and From a first time sequence to a second time sequence, the voltage of the selected word line decreases with a smooth curve from the voltage of the first selected word line. A method of operating a memory device, comprising: during a pre-on period, a selected word line voltage rises to a first selected word line voltage, and The voltage of the selected word line drops from the voltage of the first selected word line in multiple steps. When the voltage of the selected word line drops in multiple steps, the number of steps is more than two. The operating method of a memory device as claimed in claim 6, wherein, During a read period, the selected word line voltage drops from a first selected word line voltage to a second selected word line voltage; and During the read period, the selected word line voltage drops from the second selected word line voltage to a third selected word line voltage, The second selected word line voltage and the third selected word line voltage are used as a plurality of read voltages. The operation method of the memory device of claim 6, wherein the voltage of the first selected word line is higher than a highest threshold voltage of a plurality of memory cells of a selected word line. A method of operating a memory device, comprising: During a pre-on period, a selected word line voltage rises to a first selected word line voltage; and From a first time sequence to a second time sequence, the voltage of the selected word line decreases with a smooth curve from the voltage of the first selected word line. The operating method of a memory device as claimed in claim 9, wherein a time interval between the first timing sequence and the second timing sequence is greater than a predetermined time.

Images