TW202227836A - High efficiency measuring method to measure power supply rejection ratio of audio power amplifier - Google Patents

Abstract

A high efficiency measuring method to measure a power supply rejection ratio of an audio power amplifier is provided that includes steps outlined below. (S1) N under-measuring frequency points are selected to assign random initial phases on corresponding frequency portion. (S2) Frequency signals under-detection are integrated and superimposed to a DC operation voltage. (S3) Whether a voltage of an under-test chip power terminal matches an operation criteria is determined such that step (S4) is performed when the voltage matches the operation criteria and step (S2) is performed when the voltage does not match the operation criteria. (S4) An input signal spectrum diagram illustrated. (S5) A signal of an under-test chip output terminal is retrieved to generate an amplitude value of the attenuated frequency portion. (S6) An output signal frequency spectrum diagram is illustrated to determine whether the amplitude value satisfies a requirement. Comparing to a current technology, the present invention greatly shortens the test time and saves the cost due to additional test hardware.

Description

An efficient method for measuring the noise rejection ratio of audio power amplifier chip power supply

The invention relates to the technical field of chips, in particular to an efficient measurement method for the noise suppression ratio of an audio power amplifier chip power supply.

Speaker driving power chips used in mobile communication devices such as mobile phones need to provide excellent sound quality. The functions of mobile phones are complex, including circuits with various functions. These circuits operate by coupling various voltage fluctuations into the power supply. The components in the audio frequency band (20Hz~20000Hz) of these noises will add noise to the final output audio signal through the power supply, affecting the sound quality.

For GSM mobile phones, the time-division multiplexing (TDMA) time interval sharing technology adopted will send a radio frequency signal with a width of 1/8 time interval (0.5769ms) every 4.615ms to establish contact with the base station. A periodic perturbation of 1/0.004615 = 216.7Hz will string into the power supply. This frequency and its higher-order harmonics fall right in the sensitive range of human hearing, which affects the sound quality. This is one of the main sources of noise.

In addition, the fluctuation of the driving current output by the audio power amplifier circuit itself will also cause the fluctuation of the power supply voltage, forming another source of noise.

At present, the digital waveform storage space configured in the programmable power supply of the tester is mainly used to measure the power supply rejection ratio of the audio power amplifier chip. However, the built-in AC signal generation mechanism of the programmable power supply has insurmountable shortcomings. Its digital waveform storage depth is limited, and different data needs to be reloaded for different test frequencies, which increases the test time. In addition, its controllable sampling frequency generator cannot be well synchronized with the analog signal collector used to capture the output signal of the chip under test, and it cannot use discrete Fourier analysis to process the data, so it can only be obtained by searching for the maximum and minimum voltage values. peak. However, the peak voltage of the time-domain signal will be contaminated by other signals of non-observed frequencies, resulting in measurement errors and ultimately affecting the measurement accuracy.

In order to overcome the deficiencies of the prior art, the present invention provides an efficient method for measuring the noise suppression ratio of audio power amplifier chip power supply.

In order to achieve the above purpose, a high-efficiency measurement method for the noise rejection ratio of audio power amplifier chip power supply is designed, which includes the following steps:

(S1) Select N measured frequency points, and use the software to assign a random initial phase to each frequency component corresponding to the N measured frequency points, where N is a positive integer greater than or equal to 1;

(S2) Make the program-controlled voltage source of the chip tester provide the DC working voltage, so that the analog signal generator integrates the multiple frequency signals to be investigated, and then superimposes it on the DC working voltage by means of AC coupling;

(S3) Determine whether the voltage of the power supply terminal of the tested chip meets the working conditions of the tested chip, if so, go to step (S4), if not, return to step (S2);

(S4) Detect the actual signal loaded into the power terminal of the chip under test after being superimposed by the analog signal generator, and draw the input signal spectrum diagram;

(S5) causing the analog signal collector to grab the signal at the output end of the chip under test to obtain the amplitudes of the attenuated frequency components of each of the N measured frequency points in the Fourier-transformed spectrum;

(S6) Draw the output signal spectrogram, and judge whether the amplitude of each N measured frequency points meets the requirements.

The measurement circuit for performing the steps (S1) to (S6) includes the chip under test, an analog signal generator, an analog signal collector, and a digital signal processor, and the positive input pin of the chip under test is connected to the first capacitor one end of the first capacitor, the other end of the first capacitor is connected to the common ground of the system, the negative input pin of the chip under test is connected to one end of the second capacitor, the other end of the second capacitor is connected to the common ground of the system, and the ground pin of the chip under test is connected to The system common ground terminal, the negative output pin of the chip under test is connected to the negative terminal of the analog signal collector, the positive output pin of the tested chip is connected to the positive terminal of the analog signal collector, and the negative terminal of the analog signal collector and the other end of the positive terminal are both connected In the digital signal processor, the power pins of the tested chip are respectively connected to one end of the third capacitor, one end of the fourth capacitor and one end of the program control voltage source, the other end of the third capacitor is connected to the analog signal generator, and the other end of the fourth capacitor Connect to the common ground terminal GND of the system.

，其中

，則每個頻率分量的VP=0.0625V，Vpp=0.125V，N個頻率分量在時域的幅值疊加最大為VACmax=N×0.125，判斷VACmax與0.5Vpp的大小，從而判斷被測晶片U電源端的電壓是否符合被測晶片工作條件。 The judgment method in the step (S3) is as follows: the coupling voltage after the coupling in the step (S2)

,in

, then the VP of each frequency component is 0.0625V, Vpp=0.125V, and the maximum amplitude superposition of N frequency components in the time domain is VACmax=N×0.125, and the size of VACmax and 0.5Vpp is judged to judge the measured chip U Whether the voltage of the power supply terminal meets the working conditions of the chip under test.

In the step (S3), the working condition of the wafer U under test is that the fluctuation range of the working voltage of the wafer U under test does not exceed 0.5Vpp.

The VDC is the DC working voltage provided by the program-controlled voltage source, VAC is the AC voltage component, VP is the peak value of the AC voltage, Vpp is the peak value of the AC voltage, rp is the random initial phase in step S1, PI is the pi coefficient, and fk is the The frequency of the measured frequency point.

In the step ( S6 ), it is judged whether the amplitude value of each measured frequency point is lower than -84dBV to determine whether the amplitude value meets the requirements.

Compared with the prior art, the present invention has the following beneficial effects:

1. The present invention can complete the workload of multiple rounds of traditional testing methods by performing one round of testing, greatly reducing the testing time;

2. The analog signal generator can also be applied to other test items, saving the cost of adding test hardware;

3. By analyzing the spectrogram, the pros and cons of the test results can be more clearly and intuitively reflected;

4. For frequency points that are not relevant to the audio test, even if there are spectral peaks, they can be eliminated to avoid misjudgment.

Regarding the features, implementation and effects of this case, a preferred embodiment is described in detail as follows in conjunction with the drawings.

The present invention will be further described below according to the accompanying drawings.

Example 1:

Please refer to FIG. 1A and FIG. 1B at the same time. FIG. 1A is a flowchart of an efficient method 100 for measuring the power noise rejection ratio of an audio power amplifier chip according to an embodiment of the present invention. FIG. 1B is a schematic structural diagram of a measurement circuit 200 for implementing the high-efficiency measurement method 100 according to an embodiment of the present invention.

In this embodiment, two audio power amplifier chips: the first chip under test U1 and the second chip under test U2 are respectively measured for the power noise suppression ratio. The measurement method specifically includes the following steps:

In step (S1), select N measured frequency points f1=216.7Hz, f2=433.4Hz, f3=1000Hz, f4=2000Hz, and use the software to assign a random initial value to each frequency component corresponding to the N measured frequency points. phase, where N is a positive integer greater than or equal to 1, in this example N is 4;

In step (S2), the program-controlled voltage source of the chip testing machine provides a DC working voltage of 4.2V, and the analog signal generator integrates multiple frequency signals to be investigated, and then superimposes the DC working voltage through AC coupling. superior;

，VDC=4.2V，其中

，則每個頻率分量的VP=0.0625V，Vpp=0.125V，4個頻率分量在時域的幅值疊加最大為VACmax=4×0.125=0.5Vpp，符合被測晶片工作條件。 In step ( S3 ), it is judged whether the voltage of the power terminal of the chip under test meets the working conditions of the chip under test. If yes, go to step (S4), if not, go back to step (S2). Coupling voltage after coupling in step (S2)

, VDC=4.2V, where

, then the VP of each frequency component is 0.0625V, Vpp=0.125V, and the maximum amplitude superposition of the four frequency components in the time domain is VACmax=4×0.125=0.5Vpp, which is in line with the working conditions of the tested chip.

In step (S4), the actual signal loaded into the power terminal of the chip under test after being superimposed by the analog signal generator is detected, and a spectrum diagram of the input signal is drawn;

In step (S5), the analog signal collector grabs the signal at the output end of the chip under test, and obtains the amplitudes of the attenuated frequency components of each of the N measured frequency points in the Fourier-transformed spectrum;

In step ( S6 ), a spectrogram of the output signal is drawn to determine whether the amplitudes of the N measured frequency points meet the requirements. In one embodiment, in step ( S6 ), it is determined whether the amplitude of each measured frequency point is lower than -84dBV to determine whether the amplitude meets the requirement.

In step (S3), VDC is the DC working voltage provided by the program-controlled voltage source, VAC is the AC voltage component, VP is the peak value of the AC voltage, Vpp is the peak value of the AC voltage, rp is the random initial phase in step S1, and PI is the pi coefficient. , this embodiment selects PI=3.1415926, and fk is the frequency of the measured frequency point. The specific method for judging whether the voltage of the power supply terminal of the wafer U under test conforms to the working conditions of the wafer under test is that the fluctuation range of the working voltage of the wafer U under test does not exceed 0.5Vpp.

The measurement circuit 200 from steps ( S1 ) to ( S6 ) includes the wafer U under test (which can be the first wafer under test U1 or the second wafer under test U2 ), an analog signal generator ASG, an analog signal collector ASC, Digital signal processor DSP, the positive input pin IN+ of the chip U under test is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the system common ground GND, and the negative input pin IN- of the chip U under test is connected One end of the second capacitor C2, the other end of the second capacitor C2 is connected to the system common ground terminal GND, the ground pin GNDP of the tested chip U is connected to the system common ground terminal GND, and the negative output pin OUT of the tested chip U is connected to the analogy The negative pole of the signal collector ASC (marked with '-' under ASC in Figure 1), the positive output pin OUT+ of the chip U under test is connected to the positive pole of the analog signal collector ASC (marked with '+' under ASC in Figure 1) ), the negative terminal of the analog signal collector ASC and the other terminal of the positive terminal are connected to the digital signal processor DSP, and the power supply pin VBAT of the chip U under test is connected to one end of the third capacitor C3, one end of the fourth capacitor C4 and one end of the program control voltage source DPS respectively. The other end of the third capacitor C3 is connected to the analog signal generator ASG, and the other end of the fourth capacitor C4 is connected to the system common ground GND.

In this embodiment, the model of the analog signal generator ASG is MIXI_AWG, and the model of the analog signal collector ASC is MIXI_DTZ.

The actual signals of the first tested chip U1 and the second tested chip U2 are superimposed by the analog signal generator and loaded into the power terminal of the tested chip as shown in Figure 2, and the input signal spectrum is shown in Figure 3. The first The spectrum diagram of the output signal of the chip U1 under test is shown in FIG. 4 , and the spectrum diagram of the output signal of the second chip U2 under test is shown in FIG. 5 . The ordinate Vnoise in Figure 2 is the AC peak voltage superimposed on the input end of the power supply of the chip under test, and the ordinate Vout in Figures 3 and 4 is the peak AC voltage at the output end of the power supply of the chip under test.

The power supply noise suppression ratio of high-fidelity audio power amplifier chips generally cannot be lower than -60dB, that is, the amplitude of the measured frequency point is lower than -84dBV, indicating that the power supply noise needs to be suppressed and attenuated by at least 1000 times, which meets the requirements for use.

As can be seen from Figure 4, the amplitudes of the frequency components of the four measured frequency points are all lower than -84dBV, indicating that the power noise suppression ratio of the first measured chip U1 for the four measured frequencies is better than -60dB, which meets the requirements. .

As can be seen from Figure 5, the signal amplitude of the measured frequency point with f1=216.7Hz is -70dBV, which exceeds -84dBV, indicating that the second measured chip U2 has poor noise suppression effect on the power supply side at 216.7Hz, which does not meet the Require.

Although the specific embodiments of the present invention are described above, those skilled in the art should understand that these are only examples, and various changes or modifications can be made to these embodiments without departing from the principle and essence of the present invention .

100: Efficient Measurement Methods S1~S6: Steps 200: Measuring circuit ASG: Analog Signal Generator ASC: Analog Signal Collector C1: first capacitor C2: second capacitor C3: the third capacitor C4: Fourth capacitor DPS: Program Controlled Voltage Source DSP: Digital Signal Processor GND: system common ground GNDP: ground pin IN+: positive input pin IN-: negative input pin OUT+: Positive output pin OUT-: negative output pin U: wafer under test U1: The first wafer to be tested U2: The second wafer under test VBAT: Power pin Vnoise: AC peak voltage Vout: AC peak voltage

[FIG. 1A] is a flowchart of an efficient method for measuring the noise rejection ratio of audio power amplifier chip power supply in an embodiment of the present invention; [ Fig. 1B ] is a schematic structural diagram of a measurement circuit for implementing an efficient measurement method in an embodiment of the present invention; [FIG. 2] is the actual signal change diagram of the power terminal of the tested chip in step (S4) of the present invention; [FIG. 3] is a spectrogram of an input signal in an embodiment of the present invention; [FIG. 4] is an output spectrum diagram of the first wafer under test in an embodiment of the present invention; and 5 is an output spectrum diagram of the second wafer under test in an embodiment of the present invention.

100: Efficient Measurement Methods

S1~S6: Steps

Claims (6)

An efficient method for measuring the noise rejection ratio of an audio power amplifier chip power supply, comprising the following steps: (S1) Select N measured frequency points, and use software to assign a random initial phase to each frequency component corresponding to the N measured frequency points, where N is a positive integer greater than or equal to 1; (S2) Make a program-controlled voltage source of a chip tester provide a DC working voltage, so that the analog signal generator integrates multiple frequency signals to be investigated, and then superimposes the DC working voltage by means of AC coupling ; (S3) Determine whether a voltage at the power supply terminal of a tested chip meets the working conditions of a tested chip, if so, go to step (S4), if not, return to step (S2); (S4) Detecting an actual signal loaded into the power terminal of the chip under test after being superimposed by the analog signal generator, and drawing a spectrum diagram of the input signal; (S5) causing the analog signal collector to capture a signal at the output end of a chip under test to obtain a value of the frequency component after attenuation of each of the N under test frequency points in a spectrum after Fourier transformation; (S6) Draw an output signal spectrogram, and judge whether the amplitude of each of the N measured frequency points meets the requirements. An efficient method for measuring the noise rejection ratio of an audio power amplifier chip as claimed in claim 1, further comprising: a measuring circuit for performing the steps (S1) to (S6) includes a chip to be tested, In the analog signal generator, the analog signal collector, and the digital signal processor, a positive input pin of the tested chip is connected to one end of a first capacitor, and the other end of the first capacitor is connected to a system common ground, A negative input pin of the chip under test is connected to one end of a second capacitor, the other end of the second capacitor is connected to the common ground of the system, a ground pin of the chip under test is connected to the common ground of the system, and the test chip is connected to the common ground of the system. A negative output pin of the chip is connected to a negative electrode of the analog signal collector, a positive output pin of the tested chip is connected to a positive electrode of the analog signal collector, the negative electrode of the analog signal collector and the other end of the positive electrode are both connected. Connected to the digital signal processor, a power pin of the tested chip is respectively connected to one end of a third capacitor, one end of a fourth capacitor and one end of a program control voltage source, and the other end of the third capacitor is connected to the analog signal generator, and the other end of the fourth capacitor is connected to the common ground terminal of the system. An efficient method for measuring the noise rejection ratio of an audio power amplifier chip as claimed in claim 1, further comprising: the judging method in the step (S3) is as follows: a coupling voltage after the coupling in the step (S2)

,in

, then each frequency component has VP=0.0625V, Vpp=0.125V, and the maximum superposition of the amplitudes of N frequency components in the time domain is VACmax=N×0.125, and the size of VACmax and 0.5Vpp is judged to determine the Test whether the voltage at the power supply terminal of the chip meets the working conditions of the tested chip. An efficient method for measuring the power noise rejection ratio of an audio power amplifier chip as claimed in claim 1 or 3, further comprising: in the step (S3), the working condition of the tested chip is a difference of the working voltage of the tested chip. The fluctuation range does not exceed 0.5Vpp. An efficient method for measuring the noise rejection ratio of an audio power amplifier chip power supply as claimed in claim 3, further comprising: the VDC is the DC working voltage provided by the program-controlled voltage source, VAC is an AC voltage component, VP is an AC voltage peak value, Vpp is an AC voltage peak value, rp is the random initial phase in step (S1), PI is a pi coefficient, and fk is a frequency of the measured frequency points. An efficient method for measuring the noise rejection ratio of an audio power amplifier chip as claimed in claim 1, further comprising: in the step (S6), by judging whether the amplitudes of the measured frequency points are all low At -84dBV to judge whether the amplitude meets the requirements.

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