TW202226821A - Encoder and decoder circuits for the transmission of video media using spread spectrum direct sequence modulation - Google Patents

Abstract

The present invention relates generally to video or other media transmission, and more particularly, to encoding and decoding of video media that has been transmitted between a video source and a video sink using spread spectrum direct sequence (SSDS) modulation.

Description

Encoder and Decoder Circuits for Transmission of Video Media Using Spread Spectrum Direct Sequence Modulation

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Application No. 63/118,320, filed on November 25, 2020, both entitled "Encoder and Decoder Circuits for the Transmission of Video Media Using Spread Spectrum Direct Sequence Modulation (for use with Spread Spectrum Direct Sequence Modulation Encoder and Decoder Circuits for Transmission of Video Media)", and both are incorporated herein in their entirety for all purposes.

The present invention relates generally to the transmission of video and/or other media, and more particularly, to use of code division multiple access (CDMA) and spread spectrum direct sequence (SSDS) modulation between video sources and video sinks Encoding and decoding of transmitted video media.

High-resolution video is often produced in a number of different formats, including "720p," "1080i," "1080p," and more recently, "4K." For these formats, "i" refers to interlaced scanning and "p" refers to progressive scanning.

The amount of video data transferred using any of the formats listed above is enormous. For "720p", the transfer rate is 1280 horizontal lines by 720 vertical lines or approximately 921,600 pixels per frame, with a typical refresh rate of 50 or 60 frames per second. A 1080i transmission requires the transmission of 1920 horizontal lines by 540 vertical lines, or 1,036,800 pixels per field, consisting of two interlaced fields per frame, with refresh rates ranging from 12.5 to 60 fields per second. A 1080p transfer involves 1920 horizontal lines by 1080 vertical lines, or 2,073,600 pixels per frame, and typically has refresh rates ranging from 30 to 60 frames per second. 4K video transmission involves 3840 horizontal lines by 2160 vertical lines per frame, typically at a refresh rate of 30 or 60 frames per second.

Given the large amount of bandwidth required to transmit video, various types of video compression are commonly used, such as MPEG, AVC, and HEVC. Problems with video compression include limited interoperability, increased implementation costs, increased latency, and reduced image fidelity. As a result, when displaying compressed video, the picture quality is somewhat degraded compared to uncompressed or visually lossless video.

The severity of the above problems will only get worse in the near future. Consumer electronics companies are now bringing 8K cameras and displays to the market. 8K devices have frame sizes of 7,680 horizontal and 4,320 vertical lines, or 33,177,600 pixels per frame, and typically have a refresh rate of 120 or 240 frames per second. Therefore, the transmission of 8K video will make a series of challenges that already exist worse.

Therefore, there is a need for a video transmitter capable of transmitting uncompressed high-quality, high-resolution video.

The present invention is directed to an encoding and decoding circuit for sharing video media transmitted between a video source and a video sink using a Code Division Multiple Access (CDMA) channel based on Spread Spectrum Direct Sequence (SSDS) modulation.

In one non-exclusive embodiment, encoder circuits and methods are described for applying a set of mutually orthogonal SSDS codes to video data, where ("L") is defined as a code used in a CDMA codebook. length parameter. The method and encoder circuit involve (a) constructing a video vector comprising N samples of a first voltage value and a second voltage value, the N samples being derived from sets of samples representing a plurality of pixels, respectively, (b) using each L SSDS chips from their corresponding codes are modulated for each of the first and second voltage values of the N samples in the video vector, each of the modulations involving modulations depending on the L corresponding SSDS codes, respectively The state of the chip is conditionally inverted or not for the first voltage value and the second voltage value of the N samples, (c) generating a sequence of L differential potential quasi-output signals, each from being conditionally inverted; Accumulation of modulated first and second voltage values for N samples with or without being inverted.

In another non-exclusive embodiment, a decoding circuit and method are described for applying the same set of mutually orthogonal SSDS codes to decode L differential potential quasi-signals into N samples. The method and circuit include (a) receiving a series of L differential potential quasi-signals, (b) providing each received differential potential quasi-signal to N decoder circuits, (c) spreading the N number of spread spectrums from the corresponding codes Direct sequence (SSDS) chips are provided to N decoder circuits respectively, each of the N SSDS chips has a first state or a second state, (d) for each of the N decoder circuits, depending on Whether the SSDS chips provided to each of the N decoder circuits have a first state or a second state, respectively, is demodulated by conditionally inverting or not inverting the differential potential quasi-signal, (e) for N each of the decoder circuits accumulating inverted or non-inverted differential potential quasi-signals at the first storage location and the second storage location; (f) after L demodulation steps (d) and (e), providing N reconstructed samples, N samples derived from the inverted or non-inverted differential potential quasi-signals stored at the first storage location and the second storage location of each of the N decoder circuits, respectively .

In yet another non-exclusive embodiment, a decoder circuit and method is described for generating by averaging voltage values stored on (L) storage devices arranged in a first group derived by averaging The average voltage value of , decodes (L) signals of the video media encoded using SSDS encoding to generate sample video signals, wherein the (L) voltage values are the (L) signals and the (L) SSDS respectively. The chip values are multiplied together.

The following description sets forth various aspects and embodiments of the invention disclosed herein. No specific examples are intended to limit the scope of the invention. Rather, the embodiments provide non-limiting examples of various apparatus and methods included within the scope of the claimed invention. This description is to be read from the perspective of one of ordinary skill in the art. Therefore, information that is well known to those of ordinary skill is not necessarily included. Code Division Multiple Access ( CDMA )

Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used in radio communication technologies including cellular. CDMA is an example of multiple access, where several transmitters can transmit information simultaneously via a single communication channel. In telecommunications applications, CDMA allows multiple users to share a given frequency band without interference from other users. CDMA uses Spread Spectrum Direct Sequence (SSDS), which relies on unique orthogonal codes to encode each user's data. By using unique codes, transmissions from multiple users can be combined and sent without interference between users. On the receiving side, each user uses the same unique code or orthogonal code to demodulate the transmission, recovering each user's data separately. Spread Spectrum Direct Sequence ( SSDS ) modulation

SSDS is a modulation technique whereby a signal in a specific bandwidth (eg, a series of electrical or electromagnetic values) is intentionally spread using orthogonal codes, resulting in a signal with a wider bandwidth. Then a wider bandwidth signal is transmitted through the transmission medium. On the receiving side, the same orthogonal code is used to demodulate the wide bandwidth signal as that on the transmitting side. As a result, the original electrical or electromagnetic signal is restored.

The present invention relates to circuits for encoding and decoding video media for transmission between a video source and a video sink using code division multiple access (CDMA) channel sharing based on spread spectrum direct sequence (SSDS) modulation. During operation, a time-ordered stream of video samples containing color values and pixel-related information is received from the video source and reconstructed for the video sink. As described in more detail below, the number and content of input video samples received from a video source depends on the color space operating at the source. Regardless of the color space used, each video sample represents the sensed or measured amount of light in the specified color space. When a stream of input video samples is received, the input video samples are repeated (1) by "distributing" the input video samples into encoder input vectors according to a predetermined arrangement, and (2) by applying CDMA over SSDS Modulation to each of a plurality of encoder input vectors, applying an orthogonal code, is encoded to generate a plurality of composite EM signals with noise-like properties. (3) Then, the EM signal is transmitted through a transmission medium, such as an HDMI cable. On the receiving side, (4) the incoming EM signal is decoded by applying SSDS-based CMDA demodulation, applying the same orthogonal code, reconstructing the samples into the output vector, and then (5) using the inverse of the predetermined arrangement, by Distribute the reconstructed video samples from the output vector to the output stream "collect" the output vector. As a result, a time-ordered stream of raw video samples containing color and pixel-related information is delivered from the video source to the video sink.

Referring to FIG. 1, a system 10 illustrating the use of Spread Spectrum Direct Sequence (SSDS) based CDMA modulation to transmit electromagnetic (EM) video signals from a digital video source to a digital video sink is shown in accordance with a non-exclusive embodiment of the present invention.

In the following discussion, the process of capturing digital video data in general is described. Once captured, digital video data can be transferred to a video display for near-instant consumption. On the other hand, the captured video data can be stored for later consumption in a time-shifted mode. In either case, this paper proposes to use SSDS-based CDMA modulation to transmit digital video data from a video source (or storage device) to a video sink for display (or storage). video capture

Video source 12 includes an image sensor array 16 , one or more analog digital converters 18 , an image signal processor (ISP 20 ), and a video streamer 21 responsible for generating a stream 22 of video samples. Video source 12 may also optionally be connected to video media storage device 24 . The storage device may be close to the location of the image sensor array 16, or it may be remote.

In various embodiments, video source 12 may be any device capable of capturing imaging information, such as, but not limited to, a video camera, infrared imaging device, ultrasound imaging device, magnetic resonance imaging (MRI) device, computed tomography scan, or virtually any other Types of imaging devices capable of producing video information.

Image sensor 16 is any device capable of generating an electronic signal proportional to the amount of light measured. For example, in a non-exclusive embodiment, the image sensor is a planar array of photodiodes. Each photodiode represents a pixel sample location in the planar array. The number of photodiodes in the planar array can vary widely and depends on the size of the image sensor 16 . For example, a "4K" imaging sensor includes a photodiode array of 3840 horizontal lines by 1080 vertical lines, or a total of 4,147,200 photodiodes. The 8K imaging sensor will have 7,680 horizontal and 4,320 vertical lines, or 3,317,7600 pixels per frame. It should be understood that 4K and 8K are only examples of resolutions and that image sensor 16 may be of any size, including less than 480, 480, 720, 1080, 4K, 8K. The number of photodiodes in the array will of course vary accordingly.

During operation, image sensor 16 continuously repeats the sensing interval at a given refresh rate. During each sensing interval, each photodiode in the array produces a voltage for each pixel location that is inversely proportional to the number of photons produced by the photodiode. As a result, the photodiode array produces a set of voltages that collectively represent the frame. Since the image sensor is continuously refreshed at a given frame playback rate, multiple sets of voltages are continuously generated, and each set of voltages represents a frame.

For each pixel location, a photodiode is placed between the capacitor and ground. Just before the sensing interval, the capacitor is precharged. When sensing, the photodiode generates a current proportional to the amount of light received. When little light is sensed, little capacitor discharges to ground through the photodiode. Conversely, if a lot of light is sensed, most of the voltage on the capacitor will discharge. Therefore, the voltage remaining on the capacitor after the exposure interval is inversely proportional to the amount of light sensed.

For many digital image sensor arrays 16, there is typically a row of analog-to-digital converters ("ADCs") 18, one ADC per column. During a given frame interval, all rows of array 16 are sampled, typically one after the other from top to bottom, sometimes referred to herein as a "row-major" order. For each sample, ADC 18 converts the sensed voltage to a digital value for the pixel location of each column in the array. The frame is complete when all rows of array 16 have been sampled. The above process is repeated in row-major order on a frame-by-frame basis. The end result is a string of bit values, each bit value representing the pixel position in the frame. Likewise, the size and refresh rate of the image sensor are decisive factors in the number of bits per frame. For example, a 4K or 8K digital image sensor will measure 8,294,400 or 33,177,600 digital samples per frame, respectively.

The number of bits used to represent each sample can vary widely. For example, each voltage may be converted by analog-to-digital converter 18 to an 8-bit or 10-bit value. It should be understood that these bit values listed here are merely illustrative, and the number of bits used to represent pixel voltage values may be more or less than 8 or 10.

Image sensor array 16 may be monochrome or color. In the case of a single color, the digital values produced by ADC 18 represent only one color. For color, well-known color techniques such as Bayer filtering are generally applied. Using Bayer filtering, a single photodiode 16 is selectively covered with a filter of a predetermined color (eg, red (R) or blue (B) or green (G)). In alternative embodiments, CYGM (cyan, yellow, green, and magenta) or CMY (cyan, magenta, and yellow) filtering may be used. Regardless of the type of filter used, the amount of filtered light is measured at each sample location.

The ISP 20 is arranged to interpolate the string of digital values received from the ADC 18 . By interpolation, ISP 20 obtains the information contained in the digital values for each pixel measurement and its geometric neighborhood, and defines an estimate of the color of the corresponding pixel. In order to output a full-color image in a specific color space (of which there are many), the ISP 20 interpolates "missing" color values at each location. That is, given a single color measurement for each pixel, the ISP will algorithmically estimate the "missing" color values to create, for example, an RGB or YCbCr representation of the pixel. ISP 20 thus generates a set of samples 22 for a given pixel of a given frame, each set of samples 22 representing a color value (eg, measured and/or interpolated) for a given pixel location within the frame.

The content of a given set of samples 22 can vary because there are many ways to represent color. The information contained in each set of samples 22 may thus vary in different embodiments. In general, RGB is considered full color, while other spaces, such as YCbCr, are approximations of full color, smaller and harder to transmit. RGB provides three color values. For YCbCr, Y is the luminance component, and Cb and Cr are the blue-difference and red-difference chrominance values, respectively. The YCbCr color space is defined by the mathematical coordinate transformation of the associated RGB color space. In another way of representing colors, the "alternate" method can be used. For example, every other pixel is represented by its metric (Y) value, while alternating pixels are represented by a Cb (blue) or Cr (red) value. Thus, in various embodiments, each set of samples 22 includes a number of digital "S" sample values transmitted in parallel. For RGB, the number of samples per set of samples 22 is S = 3, and for YCbCr, S = 2.

In response, the video streamer 21 generates a series of time-ordered sample sets 22. Typically, each sample set 22 outputs light measurements that collectively represent a pixel location on the array 16. The value and/or number of samples are produced by the ISP at each pixel location, depending on the ISP implementation, especially the applied color space.

The output of video streamer 21 is a continuous stream of time-ordered sample sets 22, each sample from left to right, in row-major order, frame by frame representing pixels in a row as long as array 16 is sensing. Then, after transmission, the sample set stream 22 is processed by the video receiver 14 to reconstruct the image sensed by the image array sensor 16 frame by frame.

In another alternative embodiment, the stream of sample sets 22 may be stored in storage device 24 . In this manner, the stream of sample set 22 may be transmitted any time after the video stream is initially captured by image sensor 16 . For example, a stream of sample sets 22 may be captured during a time interval and then transmitted frame by frame to video receiver 14 for display at a later point in time and/or stored in storage unit 24 for transmission to video Receiver 14. In this manner, the video captured by the video source 12 can be time-shifted for display on the video sink 14 .

One advantage of using SSVT in the context of image capture and display is that the image is measured on an inherently error-prone sensor and displayed on an inherently noisy LED array and viewed by the extremely complex and robust human visual system . Therefore, the communication requirements of video are very different from those of traditional digital artifacts such as spreadsheets and e-mail, which require bit-perfect transmission. However, traditional video transmission treats the video signal as another (digital) file. However, with SSVT, the video signal is transmitted in an electrically robust manner. One of the advantages of SSVT is that any uncompensated errors in the receiver's EM signal measurements appear as broad-spectrum temporal and spatial noise in the reconstructed image. This white noise is better for human perception than the blank screens, repetitive images, and blocky compression artifacts produced by traditional bit-sequence transmission. transmission

FIG. 1 further includes a transmit retimer 26 and a spread spectrum video transmission (SSVT) transmitter (TX) 28 on the transmit side. As explained in more detail below, retimer 26 is responsible for decoding or exposing color component information (eg, RGB values) from each sample set 22 in the stream generated by video streamer 21 . The SSVT 28 is then responsible for (a) distributing the sample set 22 to one of the plurality of encoder input vectors using a predetermined arrangement, and (b) applying the SSDS modulation to each of the plurality of encoder input vectors, and (c) ) encode the CDMA code using multiple input vectors based on SSDS to generate the EM potential quasi-signal sequence, and (d) then transmit the EM potential quasi-signal sequence to the video receiver 14 via multiple EM paths or transmission media, such as HDMI cables.

On the receiving side, an SSVT receiver (RX) 30, a retimer 32 and a video receiving end 14 are provided. The functions of the SSVT receiver (RX) 30 and the retimer 32 are the complement of the retimer 26 and the SSVT transmitter 28 on the transmit side. That is, the SSVT receiver RX 30 (a) receives sequences of EM potential quasi-signals from multiple EM paths of the transmission medium, (b) decodes each sequence by applying SSDS-based CDMA demodulation to output vectors on multiple output vectors The reconstructed video samples in (c) collect samples from multiple output vectors into the reconstruction of the original stream of the sample set 22 using the same arrangement used to distribute the input samples into the input vector on the transmitting side. The re-timer 32 then transforms the reconstructed output samples into a format suitable for display by the video receiver 14 or for storage on the receiver side for display in a time-shifted mode. The number of output sample values S in each sample set 22 is determined by the color space applied by the video source. For RGB, S=3, and for YCbCr, S=2. In other cases, the sample values S in each sample set 22 may be less than two (ie, only one (1) or more than three (3).

As described herein, SSDS modulation and demodulation are performed in the analog or electromagnetic ("EM") domain. As explained in more detail below, the stream of input sample set 22 is distributed at a first clock rate (pix-clk) to create encoder input vectors according to a predetermined arrangement. SSDS-based CDMA modulation is then applied to each encoder input vector, resulting in an encoded "EM" signal for each encoder input vector. Then, the EM signal is transmitted by parallel transmission at the second clock rate (SSVT_clk). Applying expansion (SSDS) to each sample in the encoder input vector provides electrical resiliency at the expense of per-sample bandwidth. However, some or all of the lost bandwidth can be recovered by modulating a set of mutually orthogonal codes and transmitting all the resulting EM signals simultaneously (CDMA).

FIG. 2A is a logical block diagram of SSVT transmitter 28 and SSVT receiver 30 connected by transmission medium 34 . The SSVT transmitter 28 includes a distributor 40 and a plurality of encoders 42 . The SSVT receiver 30 includes a plurality of decoders 44 and collectors 46 .

On the transmit side, the distributor 40 of the SSVT receiver 30 is arranged to receive the colour information (eg R, G and B values) exposed in the input set of samples 22 . In response, the allocator 40 takes the exposed color information of a set of input samples 22 and constructs a plurality of encoder input vectors according to a predefined arrangement. In the non-exclusive embodiment shown in FIG. 2A , there are four encoder input vectors (V ₀ , V ₁ , V ₂ , and V ₃ ), one for each of the four EM paths on transmission medium 34 . One. In various embodiments, transmission medium 34 may be a cable such as HDMI, fiber optic, or wireless. One of the plurality of encoders 42 is assigned to one of the four vectors V ₀ , V ₁ , V ₂ and V ₃ , respectively. Each encoder 42 is responsible for encoding the sample values contained in the corresponding encoder input vector and producing an EM signal that is sent over one of the parallel paths on the transmission medium 34 .

In the particular embodiment shown, there are four EM paths, and four encoders 42 each generate EM signals for each of the four paths. However, it should be understood that the present invention should by no means be limited to the four approaches. Rather, the number of paths on the transmission medium 34 may be broadly from one to any number greater than one, including greater than four. permutation example

Referring to Figure 2B, a diagram is shown of _one possible arrangement implemented by allocator 40 for constructing _four vectors _V0 , V1, V2 and _V3 . Each vector contains N samples of color information.

In this non-exclusive embodiment, the exposed color information of the sample sets 22 is "RGB", respectively. In this example, the exposed RGB samples of sample set 22 are assigned to vectors V ₀ , V ₁ , V ₂ and V ₃ from left to right. In other words, the "R", "G" and "B" values of the leftmost sample and the "R" signal of the next sample set 22 are assigned to the vector V ₀ , and the next (left to right) of the next sample 22 The "G", "B", "R" and "G" values are assigned to the vector V ₁ and the next (left to right) "B", "R", "G" and "B" values are assigned to the vector V2, the next ₍ left to right) "R", "G", "R" and "R" values are assigned to vector _V3 . Once the fourth vector _V3 has been assigned its signal, the above process is repeated until each _of the _four vectors _V0 , V1, V2 and _V3 has N samples. In various embodiments, the number of N samples can vary widely.

As an example, consider the non-exclusive embodiment N=60. In this case, the total number of N samples included in the four vectors V ₀ , V ₁ , V ₂ and V ₃ is 240 (60 x 4 = 240). The four encoder input vectors V ₀ , V ₁ , V ₂ and V ₃ , when fully established, include samples of 80 different sample sets 22 (240/3=80) (where S=3). In other words: • Vector V ₀ includes samples P ₀ , N ₀ to P ₀ , N _N-1 ; • Vector V ₁ includes samples P ₁ , N ₀ to P ₁ , N _N-1 ; • Vector V ₂ includes samples P ₂ , N ₀ to P ₂ , N _N-1 ; and • Vector V ₃ includes samples P ₃ , N ₀ to P ₃ , N _N-1 .

It should be understood that the above examples are merely illustrative and should not be construed as limiting in any respect. The number N of samples can be more or less than 60. Furthermore, it should be understood that (a) the exposed color information of each sample set 22 may be any color information (eg, Y, C, Cr, Cb, etc.) and is not limited to RGB.

The number of EM paths on the transmission medium 34 can also vary widely. Accordingly, the number of vectors V and the number of encoders 42 may also vary widely from just one or any number greater than one.

It should also be understood that the arrangement used to construct the vectors, regardless of the number, is arbitrary. Any permutation scheme can be used, limited only to any permutation scheme used on the transmitting side is also used for any permutation scheme on the receiving side.

Referring to Figure 3, a logical block diagram of the SSVT transmitter 28 is shown. The splitter-encoder 40 includes an assembly group 50, a grading group 52, a presentation group 54, and a frame controller 56. The encoder block 60 includes an analog-to-digital converter (DAC) 62 and a set of four encoders 42, one for each EM path on the transmission medium 34.

The distributor 40 is arranged to receive the exposed colour information (eg RGB) of the stream of set samples 22 one after the other. In response, assembly group 50 constructs four vectors V ₀ , V ₁ , V ₂ and V ₃ from the exposed color information (eg, RGB) of the input stream of sample set 22 . As the sample sets 22 are received, they are stored in the assembly group 50 according to a predetermined arrangement. Likewise, allocator 40 may use any number of different permutations when constructing vectors each containing N samples.

Hierarchical group 52 facilitates N samples of each of the four vectors V ₀ , V ₁ , V ₂ and V ₃ from the first clock frequency or domain used by retimer 26 to the second clock frequency or domain used for encoding. The resulting EM potential quasi-signal is crossed and transmitted over the transmission medium 34 . As N=60 and S=3 discussed earlier in the above example, samples representing exactly 80 sets _of RGB samples are contained in the _four encoder input vectors _V0 , V1, V2 and _V3 .

In various embodiments, the first clock frequency may be faster, slower or the same as the second clock frequency. The first clock frequency f_pix is determined by the video format selected by the video source 12 . The second clock frequency f_ssvt is f_pix, the number P of EM paths in the transmission medium 34, the number of samples S in each input/output sample set, and the SSVT transformation parameters N (number of input/output vector positions) and L (each SSDS code length), where f_ssvt = (f_pix * S * L) / (P * N). With this arrangement, the input clock (pix_clk) oscillates at one rate and the SSVT clock (ssvt_clk) oscillates at a different rate. They can be the same or different. Diffusion occurs because N input samples (a single color component) are assigned to the input vector; the encoder then performs a forward transform (SSD-based CDMA) while preparing the next input vector.

Rendering group 54 provides encoder block 60 with N samples (N ₀ to N ₋₁ ) of each of the four encoder input vectors V ₀ , V ₁ , V ₂ , and V ₃ .

Controller 56 controls the operation and timing of assembly group 50 , grading group 52 and presentation group 54 . In particular, the controller is responsible for defining the permutations and number N _of samples used when constructing the _four encoder input vectors _V0 , V1, V2 and _V3 . The controller 56 is also responsible for coordinating the clock domain crossing from the first clock frequency to the second clock frequency, as performed by the hierarchical group 52 . Controller 56 is further responsible for coordinating when presentation group 54 provides encoder block 60 with N (N ₀ to N ₋₁ ) samples of each of the four encoder input vectors V ₀ , V ₁ , V ₂ , and V ₃ .

Within the encoder block 60, a plurality of analog-to-digital converters (DACs) 62 are provided, each digital-to-analog converter being arranged to receive _a common assignment to _four encoder input vectors _V0 , V1, V2 and _V3 One of the P*N samples (P0, N ₀ to P ₃ , N _N-1 ). Each DAC 62 converts the samples it receives from the digital domain into differential pairs of voltage signals in amounts proportional to the digital value of its input. In a non-exclusive embodiment, the output of DAC 62 ranges from a maximum voltage to a minimum voltage.

Four encoders 42 are provided for the four encoder input vectors V ₀ , V ₁ , V ₂ and V ₃ , respectively. Each encoder 42 receives a differential signal pair for each of the N samples (N ₀ to N _-1 ) of its encoder input vector, modulating each of the N differential voltage signal pairs using quadrature SSVT "chips" One, the accumulated modulation value then produces a differential EM potential quasi-output signal. Since there are four encoders 42 in this example, there are EM potential quasi-signals (Level ₀ to Level ₁ ) that are transmitted simultaneously via the transmission medium 34 .

Sequencer circuit 65 coordinates the timing of operations of DAC 62 and encoder 42 . Sequencer circuit 65 is responsible for controlling the clocking of DAC 62 and encoder 42 . Sequencer circuit 65 is also responsible for generating two clock phase signals "clk 1" and "clk 2", which are responsible for controlling the operation of encoder 42, as described in detail below.

Referring to Figure 4, a circuit diagram of an encoder 42 for one of the input vectors V is shown. The encoder circuit 42 includes a plurality of multiplier stages 70 and an accumulator stage 72 including a differential amplifier 74 .

Each multiplier stage 70 is arranged to receive a differential sample signal pair (+Sample _N-1 /-Sample _N-1 to +Sample ₀ ) from one of the DACs 66 at the first (+) and second (-) terminals, respectively /-Sample ₀ ). Each multiplier stage 70 also includes a terminal for receiving a Spread Spectrum Direct Sequence (SSDS) "chip", an inverter 72, switch banks S1-S1, S2-S2 and S3-S3, driven by clk 1 and clk , a first storage device C1 on the first voltage rail, and a second storage device C2 on the second voltage rail.

During operation, each multiplier stage 70 modulates its received differential pair of analog signals by conditionally multiplying by (+1) or (-1) depending on the value of the received SSDS chip. If the SSDS chip is (+1), when clk 1 has a valid state, switch pair S1-S1 and S3-S3 are closed, while switch pair S2-S2 remains open. As a result, differential pairs of +/- samples are all stored on storage devices C1 and C2, respectively, without any inversion (ie, multiplied by +1). On the other hand, if the SSDS chip is (-1), the above complement occurs. In other words, switch pair S1-S1 is open, while switch pair S2-S2 and S3-S3 are closed when clk 1 has an active state. As a result, the differential sample pairs are inverted (multiplied by -1) and stored on C1 and C2, respectively.

The accumulator stage 72 operates to accumulate charges on all of the multiplier stage 70 locations C1 and C2. When clk 1 transitions to inactive state and clk 2 transitions to active state, all clk 1 control switches (S4-S4) are closed and clk 2 control switches (S5-S5, S6-S6) are open. As a result, all charges on the first storage device C1 of all multiplier stages 70 are amplified by amplifier 78 and accumulated on the first input of differential amplifier 74, while all charges on the second storage device C2 of all multiplier stages 70 are amplified by Amplifier 78 amplifies and accumulates on the second input of differential amplifier 74 . In response, differential amplifier 74 generates a pair of differential electromagnetic (EM) potential quasi-signals.

The above process is performed for all four vectors V ₀ , V ₁ , V ₂ and V ₃ . Furthermore, the above process is repeated as long as the SSVT transmitter 28 receives the stream of the sample set 22 . In response, four differential EM output potential quasi-signal streams are sent to SSVT receiver 30 via transmission medium 34 . receiver

On the receiving side, SSVT RX 30 is responsible for decoding the four differential EM potential quasi-output signal streams received via transmission medium 34 back into a format suitable for display. Once in an appropriate format, the video content (eg, signal S) contained in sample 22 can be presented frame by frame on a video display. As a result, the video capture of video source 12 can be recreated by video sink 14 . Alternatively, the decoded video information can be stored for later display in time-shifted mode.

SSVT RX 30 performs the inverse operation of SSVT TX 28 on the transmit side. The SSVT RX 30 uses four decoders 80 and collectors 46 . The decoder 80 reconstructs the four differential EM potential quasi output signals into four decoder output vectors. Collector 46 then assigns the samples of the decoder output vector to the original streams of sample set 22, each comprising S reconstructed samples corresponding to the original S samples at that position in the stream.

Referring to FIG. 5A, a detailed block diagram of the SSVT RX 30, the retimer 32, and the video display 85 of the video receiver 14 is shown. The P-decoders 80 (labeled 0 to P-1 ) are arranged to receive differential EM potential quasi-signals Level ₀ to Level _P-1 , respectively. In response, each decoder 80 produces N differential pair reconstruction samples (Sample ₀ to Sample _N-1 ). With four decoders 80 (P=4), four vectors V ₀ , V ₁ , V ₂ and V ₃ are constructed respectively.

Reconstruction group 82 samples each of the four decoder output vectors V ₀ , V ₁ , V ₂ , and V ₃ and holds N reconstructed samples (Sample ₀ to Sample _N-1 ) at the end of each decoding interval, respectively. of each of the differential pairs. An analog-to-digital converter (ADC) 84 is provided for each of the N samples (Sample ₀ to Sample _N-1 ) of each of the four vectors V ₀ , V ₁ , V ₂ and V ₃ , respectively. Each ADC converts the pair of differential voltage signals it receives into corresponding digital values, thereby generating digital samples for each of the four vectors V ₀ , V ₁ , V ₂ and V ₃ (Sample _N-1 to Sample N-1, respectively). ₀ ). The ADC operates at clock rate = f_ssvt /L.

Collector 46 includes grading group 86 and splitting group 88 . Hierarchical group 86 receives all reconstructed samples (Nn _{-1 to N0} ) for each of the _four decoder output vectors _V0 , V1, V2, and _V3 . Split group 88(a) outputs samples of each of the four decoder output vectors V ₀ , V ₁ , V ₂ and V ₃ (Sample _N-1 to Sample ₀ ) using the same permutation scheme as used on the transmit side. ) split the exposed color information (eg, the S signal) into a stream of sample sets 22 (eg, "for RGB pixels S=3" in this example), and (b) reconstruct the samples from the second clock The domains cross back to the first clock domain. The stream of reconstructed sample set 22 is then provided to retimer 32, which reformats the video signal. The output of the retimer 32 is thus a recreation of the sequence of the time-ordered sample set 22 . The video receiver 14 includes a DAC 103 group and a video display 85 . The group of DACs 103 is responsible for converting the samples 22 in the digital domain back to the analog domain. In one embodiment, DAC 103 is provided for each row in display 85 . Once the samples 22 are converted to the analog domain, they are displayed on a video display 85 in a well-known manner.

The SSVT RX 30 also includes a channel aligner 87 and a collector controller 89 that receive framing information and aperture information from each decoder 80 . In response, collector controller 89 coordinates the timing of grading group 86 and/or splitting group 88 to ensure that all samples provided to the splitting group are from a common time interval during which the SSVT TX 28 transmits the potential quasi-signal. As a result, (a) the splitting of the groups 88 may be delayed until all samples are received and (b) the individual channels of the transmission medium 34 need not all be of the same length, since the splitting of the groups 88 compensates for any timing differences.

FIG. 6 is a logic diagram of one of the four encoders 80 . The encoder 80 includes a differential amplifier 92 and a sample and hold circuit 94 arranged to receive, sample and hold one of the four differential EM potential quasi-signals received via the transmission medium 34 . The EM potential quasi-signals of the samples are then provided to each of the N decoder track circuits 96 (Nn _-1 to _N0 ). The sequencer controller 98 provides the same SSDS chips to each of the N decoder track circuits 96 respectively applied to the transmit side. As a result, the sample outputs (N _n-1 to N ₀ ) are provided to the reconstruction group 82 . Likewise, the same SSDS chips used on the transmit side are used by each decoder track circuit 96 . As a result, the demodulated samples N _n-1 to N ₀ are the same as before modulation on the transmission side.

Collector controller 89 is responsible for keeping track of any permutations and ensuring that split group 88 applies the same permutations that were used when constructing vectors V ₀ , V ₁ , V ₂ and V ₃ on the transmit side.

The collector controller 89 of each decoder 80 also generates a number of control signals, including a strobe signal, an end-of-group (eob) signal, an aperture signal, and a framing signal. A strobe signal is provided to ADC 84 and indicates the timing of when the analog-to-digital conversion process for a given reconstructed bank content can begin. The eob signal is provided to the reconstruction group 82 and represents the moment when the grading group 86 is completely filled with samples. When this happens, the eob signal is asserted, and the next set of reconstructed samples (Nn _-1 to _N0 ) is expected, clearing the decoder track 96 and the hierarchical group 86. The aperture control signal is provided to sample and hold circuit 94 and the framing signal is provided to channel aligner 87 and collector controller 89 . Alternative Embodiment

In the above embodiment, the ADC 84 converts the decoded samples into the digital domain, and the ADC 103 in the video receiver 14 converts the ordered set of samples 22 back to the analog domain prior to display.

As shown in Figure 5B, an alternative embodiment is shown in which the sample output from the reconstruction group 82 remains in the analog domain, thus eliminating the need for the ADC 103 and other components. With this embodiment, ADC 84, split group 88 and retimer 32 are optionally eliminated. Instead, the analog sample output is provided to a staging bank 86, which performs the same permutation on the samples used in constructing vectors V ₀ to V ₃ on the transmit side. The sample output of the binning group 86 is then used to directly drive the display 85 on the video receiver side by means of an optional voltage level converter (not shown). Since different types of displays require different voltages to drive their display panels, voltage level converters can be used to scale the voltages output by hierarchical groups of video samples as needed. As known in the art, any suitable level-to-level converter may be used, such as a latch type or an inverter type.

For this embodiment, collector controller 89 performs several functions. Collector controller 98 is responsible for keeping track of and providing staging group 86 with the correct permutation selection to use. Collector controller 89 may also provide gain and gamma values to display 85 . Gain determines how much amplification is applied and the gamma curve correlates luminous flux to perceived brightness, which linearizes the human optical perception of luminous flux. The framing signal indicates when the video frame is constructed on the display 85 . The inversion signal can optionally be used to control the level converter to invert or not invert the video sample output, which may be required for certain types of display panels, such as OLEDs. If a potential quasi-converter is used, the output of the potential quasi-converter is usually latched. In such an embodiment, a latch signal may be used to control the timing of latching and releasing the level of any shifted meta-video sample output signal. Finally, gate driver control signals are used for gate driver circuits that are typically used to drive the horizontal rows of many displays.

Referring to FIG. 7, a schematic diagram of a representative decoder track circuit 96 is shown. The decoder track circuit 96 includes a multiplier portion 100 and an accumulator portion 102 . The multiplier section 100 includes a first pair of switches S1-S1, a second pair of switches S2-S2, a third pair of switches S3-S3, and a pair of capacitors C1 on first (positive) and second (negative) power rails, respectively -C1. The accumulator section 102 includes additional transistor pairs S4-S4, S5-S5, S6-S6 and S7-S7, an operational amplifier 104, and a pair of capacitors on the first (positive) and second (negative) power rails, respectively _CF and _CF.

For each demodulation cycle, a differential EM potential quasi-signal pair is received at a first potential quasi-input (potential quasi-+) terminal and a second potential quasi-input (potential quasi-) terminal. Depending on the value of the received SSDS chip, the differential EM potential quasi-signal pair is demodulated in the multiplier section 100 by being conditionally inverted by multiplying by (1) or negative (-1).

If the SSDS chip has a value of (+1), when clk 1 is activated, the transistor pairs S1-S1 and S3-S3 are closed, while S2-S2 remains open. As a result, the voltage values of the first potential quasi-input (potential quasi-+) terminal and the second potential quasi-input (potential quasi-) are transferred to and stored by the two capacitors C1 and C1 on the positive and negative rails, respectively. In other words, the input value is multiplied by (+1) and no inversion occurs.

If the value of the SSDS chip is -1, then when clk 1 is activated, the S1-S1 switches are all closed, and the switches S2-S2 and S3-S3 are both open. As a result, the voltage values received at the positive or first (+) terminal and the negative or second (-) terminal are swapped. In other words, the input voltage value provided on the first or positive terminal is directed and stored on capacitor C1 on the lower negative rail, while the voltage value provided on the second or (-) terminal is switched to and stored on the positive on capacitor C1 on the rail. The voltage value received at the input is thus inverted or multiplied by (-1).

When clk 1 transitions to inactive, the accumulated charge on C1 and C1 remains the same. When clk 2 transitions to start, then transistor pair S4-S4 is open and transistor pair S5-S5 and S6-S6 are closed. The accumulated charge on capacitor C1 on the upper or positive rail and C1 on the lower or negative rail is then provided to the differential input of operational amplifier 104 . The output of the operational amplifier 104 is the raw +/- sample pair before encoding on the transmit side.

When Clk 2 starts up, the accumulated charge on the two capacitors C1 and C1 is also transferred to the capacitors CF and CF on the upper or positive rail and the lower or negative rail. During each demodulation cycle, the charge on capacitors C1 and C1 on the upper and lower rails accumulates on the two capacitors CF and CF on the upper and lower rails, respectively. When both the clk 1 and eob signals are active, the transistor pairs S7-S7 are both closed, shorting the plates of each of capacitors CF and CF. As a result, the accumulated charge is removed and the two capacitors CF and CF are reset and ready for the next demodulation cycle.

Since each decoder 80 has N decoder track circuits 96, N decoded or original +/- sample pairs are recreated each demodulation cycle. These N+/- sample pairs are then provided to reconstruction group 82, ADC 84, then collector 46, including binning group 86 and splitting group 88, and finally retimer 32. As a result, the original sample set 22 is recreated with its original color content information (eg, S=3 for RGB) and is ready to be displayed on the display 85 of the video receiver 14 .

The decoder track 96 reconstructs the input potential level samples over L consecutive cycles, demodulating each consecutive input potential level with consecutive SSDS chips of the track code. The result of each L demodulation is accumulated on the feedback capacitor CF. When eob is in effect during clk1 corresponding to the first demodulation cycle of the decode cycle, CF is cleared after eob so that it can accumulate again starting from zero volts or some other reset voltage. In various non-exclusive embodiments, the value of L is a predetermined parameter. Generally, the higher the parameter L, the greater the SSDS process gain and the better the electroelasticity of the SSVT signal being transmitted over the transmission medium 34. On the other hand, the higher the parameter L, the higher the frequency required for the application of SSVT modulation, which may impair the signal quality due to the insertion loss caused by the transmission medium 34.

The demodulation loop described above is repeated iteratively with each of the four decoders 80 . The end result is to recover the original string of time-ordered sample sets 22, each with their original color content information (ie, sample set S ). The sample set 22 is then processed and displayed on the display 85 of the video receiver 14 as is known in the art. Alternatively, the recovered sample set 22 may be stored on the receiving side for display in a time-shifted mode. Passive Multiply Accumulator Decoder

In an alternate embodiment, a passive multiply-accumulator decoder may optionally be used in decoder block 80, as described with respect to FIG. 5A. As described in detail below, the passive multiply-accumulator processes (L) differential pairs of video media samples received via transmission medium 34, where (L) is the length of the SSDS code used to encode the media prior to transmission. This decoder is passive because no active components, such as amplifiers, are used in the decoding process. This decoder also features a multiply-accumulator because during the decoding process, the product of (L) differential sample pairs and their corresponding SSDS chip values are accumulated or stored on multiple storage devices (eg, capacitors).

Referring to Figure 8, a passive multiply accumulator encoder 120 is shown. According to one embodiment, the passive multiply-accumulator encoder 120 includes a chip multiplier stage 122, a first storage bank A, including (+) bank (L) capacitors and (-) bank (L) capacitors, and a first pair of Capacitor 129.

In an alternative embodiment, a differential amplifier 124 having a positive (+) input and a negative (-) input is also provided. In this embodiment, the negative (-) input is selectively coupled to the (+) bank of capacitors (L) by a first capacitor 129 and the positive (+) input is selectively coupled by a second capacitor 129 Coupled to (-) bank (L) capacitors.

A pair of reset elements 128 are also provided on the feedback paths coupled between the (+/-) output and the (-/+) input of the differential amplifier 124, respectively. The gain of the differential amplifier 124 can be set by providing negative feedback between the (+/-) output and the (-/+) input. In a non-exclusive embodiment, each reset element 128 includes a capacitor and a switch (not shown).

Chip multiplier stage 122 is configured to sequentially receive, via transmission medium 34, differential pairs of video media samples that have been encoded by encoder 28 using spread spectrum direct sequence (SSDS) encoding as previously described. Chip multiplier stage 122 is also configured to receive SSDS chip values specified by mutually orthogonal SSDS codes used to encode differential pairs of samples, respectively, by encoder 28 . In a non-exclusive embodiment, the channel aligner 87 is responsible for applying the correct SSDS chip value to each received differential pair sample, respectively.

During operation, one differential pair sample is received with each clock cycle of the sample clock Fssvt. In response to each received differential pair sample, chip multiplier stage 122 performs the following operations: (1) Apply the same SSDS chip value as the mutually orthogonal SSDS code used in encoding to the received differential pair samples; (2) Multiply the differential pair samples with the applied chip value. Depending on the state of the applied chip value for a given differential pair sample, the multiplier is (+1) or (-1). If the chip value is the first state (eg, "1"), the multiplier is (+1). If the chip value is the second state (eg, "0"), the multiplier is (-1); and (3) A voltage charge commensurate with the result of multiplying the capacitors by (+) and (-) is stored in the storage block A, respectively. When the chip value is (+1), the charge is stored without any inversion. If the chip value is (-1), the charge is first inverted before being stored.

The above process is repeated for each sample as (L) differential signal pairs of the video medium are received sequentially. As a result, the (L) capacitors in the (+) and (-) groups are sequentially written and store charges commensurate with the product of the (L) differential samples received, respectively.

Once (L) differential samples have been received and all (L) capacitors of the (+) and (-) capacitor banks of storage bank A have stored the product results, the passive multiply accumulator encoder 120 operates to generate decoded Differential video media sample output (ie Sample _P-1 , _N-1 +, Sample _P-1 , _N-1 -). This is accomplished by asserting an "average" control signal, which results in: (1) interrupting the storage of the product charge in capacitor bank A; (2) storing the charge on all (L) (+) capacitors in bank A shorted together, causing the accumulated charge to be "dumped" onto the first capacitor 129 coupled to the negative (-) input of the differential amplifier 124 . An "average" voltage is achieved on the first capacitor 129 by dumping the accumulated charge on all (+) capacitors; and (3) the charge on all (L) (-) capacitors in storage group A are shorted together, resulting in The accumulated charge is "dumped" onto a second capacitor 129 coupled to the positive (+) terminal of the differential amplifier 124 . An "average" voltage is achieved on the second capacitor 129 by dumping the accumulated charge on all (-) capacitors.

By simply shorting together all (+) capacitors and all (-) capacitors in storage group A, the average value of the accumulated charge of the (L) input differential samples, respectively, is provided on capacitor pair 129 . Therefore, averaging is performed essentially "for free", meaning that the associated process is done passively without any active components (eg, without amplifiers).

The decoded differential video media samples are thus represented by the difference between the average voltages accumulated on the first capacitor 129 and the second capacitor 129 coupled to the positive and negative terminals of the differential amplifier 124, respectively. The differential amplifier 124 is used to amplify the voltage difference between the positive and negative terminals while suppressing any common voltage between the two. With the additional current gain, the decoded differential video media samples are more suitable for driving the reconstruction group 82, as shown in FIG. 5A or FIG. 5B.

The frequency of the differential amplifier 124 need not operate at the same frequency Fssvt used to sample the (L) differential samples of the input. Since the averaging operation is performed for every (L) input sample, the frequency of the differential amplifier 124 only needs to be Fssvt/L. By reducing the speed/settling time requirements of the differential amplifier 124, the power required to perform this function is reduced.

A reset circuit 128 for the differential amplifier 124 is provided to initialize or reset the voltage on the capacitor 129 at the (+/-) input of the differential amplifier to zero volts or some other reset voltage value every Fssvt/L cycle. Without a reset before each averaging operation, the differential amplifier 124 will act as an integrator and accumulate the differential voltage inputs it receives over time, rather than simply amplifying the differential inputs it receives for a single averaging operation.

For the above-described embodiment, bank A cannot be used to store the product charge for input differential samples during averaging operations. Therefore, processing delays may occur.

In an alternate embodiment, the passive multiply-accumulator encoder 120 may also optionally include a second bank B comprising (L) banks of (+) and (-) capacitors, a second differential amplifier 126, a second bank of A capacitor 129, a pair of reset circuits 128 and a multiplexer 130. The second bank B, the differential amplifier 126, the second bank of capacitors 129, and the reset circuit 128 all operate substantially the same as their counterparts as described above. Therefore, for the sake of brevity, a detailed description of these elements is not provided here.

During operation, the two storage groups A and B are used alternately. One is the sample, the other is the average, and vice versa. By using one group for sampling while the other group is averaging, processing latency is reduced in at least two ways. First, multiple input (L) differential signal pairs can be received, multiplied and stored without interruption. Second, any speed/settling time requirements of the differential amplifier after the averaging operation are effectively negated because one group is always sampling while the other is averaging, and vice versa.

To implement the embodiment of the passive multiply-accumulator encoder 120 with two banks A and B, several control signals are required. These control signals include: (1) Provides the sample/average control signal to bank A and the complementary average/sample signal to bank B at the same time. Since the two control signals are complementary, one bank will always sample the current set of incoming (L) differential signals while the differential amplifier associated with the other bank is averaging, and vice versa; and (2) The group selection control signal is provided to the multiplexer 130 . Thus, when one bank is sampling and storing, the multiplexer 130 selects the differential amplifier output (124 or 126) of the other bank that is being averaged. By causing the bank select control signal transition to coincide with the transition of the sample/average control signal, the output of the multiplexer 130 is always selected to select the capacitor bank being averaged. As a result, decoded differential video media samples are continuously generated as long as the chip multiplier stage 122 is receiving the incoming differential input signal.

Referring to FIG. 9, a timing diagram illustrating the alternating nature of the operation of the two sets of embodiments of the passive multiply accumulator encoder 120 is shown.

As shown, the two capacitor banks A and B alternate between sample and average. From left to right, capacitor bank A is initially sampled, then averaged and output to capacitor 129 of differential amplifier 124, and then sampled again. At the same time, capacitor bank B performs complementation, which means it initially averages and outputs the results to the differential amplifier 126, then samples, then averages and outputs the results to the differential amplifier 126. This alternating pattern is continuously repeated by transitioning the state of the average/control signal every (L) clock cycle of Fssvt. As a result, multiple output, decoded, differential, video media samples are generated in succession.

Referring to Figure 10, an exemplary storage group 140 (eg, A or B) and control logic are shown. Using the above example of L=128, the bank 140 would include 128 stages, labeled in Figures 1 to (L). Each stage includes a first pair of switches (S1-S1), a second pair of switches (S2-S2), and complementary capacitors C(+) and C(-).

Each stage is also configured to receive an output from the control logic unit 148, which is used to control the opening/closing of the first pair of switches S1-S1. In a non-exclusive embodiment, the control logic unit 148 includes a wraparound shift register of length (L) bits that wraps a single "1" bit around the (L) stage, respectively. The position of the "1" bit at any point in time selects one of the (L) stages to sample the product of a given differential pair input. By looping the "1" bit to substantially coincide with (L) Fssvt clock cycles, (L) samples are collected on (L) stages, respectively. In various alternative embodiments, the pulse width of a single "1" bit may be the same or slightly smaller than the pulse width of the Fssvt clock. By using a smaller pulse width, any overlap between the sample capacitors of partially conducting adjacent stages (L) can be avoided or mitigated.

Each stage also has an input terminal configured to receive either the sample/average control signal of capacitor bank A, or the complementary average/sample control signal of capacitor bank B. For both groups, this control signal is used to control the opening/closing of switches S2-S2 of the second group.

During the sampling period, the sample/average of capacitor bank A (or the average/sample of capacitor bank B) signal remains in the sampled state. As a result, switches S2-S2 remain open.

During a sample, the control logic unit 148 sequentially loops the single "1" bits for stages (L) through (1), respectively. As a result, only one stage is selected per Fssvt clock cycle. For the selected stage, switches S1-S1 are closed, allowing a charge value commensurate with the product of the currently received differential pair samples to be received and stored on the C(+) and C(-) capacitors of the selected stage, respectively .

By looping through all (L) stages, a charge commensurate with the product of the received (L) input differential signal pair samples is stored on (L) stages over (L) Fssvt clock cycles, respectively. Once all (L) stages have accumulated their charges, they are ready to perform averaging.

To initiate the averaging operation, the sample/average signal of bank A (or the average/sample signal of bank B) transitions to the averaging state and the control logic unit 148 stops the looping of the "1" bit. As a result, switches S1-S1 of all (L) stages are opened and switches S2-S2 of all (L) stages are closed. Therefore, the charges on the complementary capacitors C(+) and C(-) of all (L) stages are "dumped" (ie averaged) onto the capacitors 129 at the (-) and (+) terminals of the corresponding differential amplifier, respectively .

Note that during the "dump"/average process, another capacitor (previously initialized with no charge) can be connected to the set of L capacitors to deliver a fraction of the result (the ratio depends on the size of the extra capacitors combined with the sum of the L capacitors) to the extra capacitor. This technique provides a means to pass the result to the corresponding differential amplifier input, 124 for Bank A or 126 for Bank B.

Although storage groups A and B as described above are symmetric and both include (L) stages, it should be understood that this is by no means required. Conversely, the A and B storage groups do not need to be full copies. There just needs to be enough repetition to be able to handle a continuous stream of differential input samples. For example, one or two storage groups may have fewer than (L) stages. In an alternative embodiment, only a small number of stages in multiple storage groups need to be replicated. The number of potential replica stages need only be sufficient to ensure that averaging is done on the input capacitor 129 of the output amplifier. Even though they share memory elements, the output of the results of one bank (by the amplifiers) can be done during the samples of the next bank because the output amplifiers are "independent" after the evaluation is complete.

Furthermore, each bank does not necessarily require a corresponding differential amplifier. In alternative embodiments, the inputs to a given differential amplifier from multiple banks of storage may be multiplexed, thereby reducing the number of differential amplifiers required.

The various above-described embodiments of passive multiply-accumulator decoder 120 are essentially "drop-in" replacements for the N decoders in decoder block 80 as shown in Figures 5A and 5B. As before, each decoder block 80 is provided with N decoder circuits (N ₀ to N ₋₁ ). Each of the N decoder circuits is configured to sequentially receive differential potential quasi-samples (+/- potential quasi-signals). When a differential potential level signal is received, each of the N passive multiply-accumulator decoder circuits 120 applies a mutually orthogonal quadrature for encoding the potential level position (P) and sample position (N) of the transmitter Unique SSDS code with the same SSDS code. As a result, each passive multiply accumulator decoder circuit 120 produces a differential pair of samples for its given P and N positions. In other words, for all N decoder circuits of each of the (P) decoders 80, the generation from (sample 0 ⁺ , sample 0 ⁻ to sample _P−1 , _N−1 + , sample _P−1 , _{N− 1-} ) of the complete set of differential samples and provided to the reconstruction group 82, as shown in Figures 5A and 5B. In the non-exclusive embodiment described with respect to Figures 5A and 5B and herein with respect to Figure 8, N is 64 channels and the length of the SSDS code is L=128.

The above discussion of various encoders and decoders has been described with respect to differential signaling. However, it should be noted that this is by no means a requirement. In various alternative embodiments, the encoder and decoder may also be configured to operate and process non-differential signals (ie, a single signal). in conclusion

The present examples are to be regarded as illustrative rather than restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

12: Video source 14: Video sink 16: Image sensor array 18: Analog-to-digital converter ("ADC") 20: Image signal processor (ISP) 21: Video streamer 22: Video sample stream, sample Episode 24: Storage Devices, Storage Units 26, 32: Re-Timers 28: Spread Spectrum Video Transmission (SSVT) Transmitter (TX) 30: SSVT Receiver (RX) 34: Transmission Medium 40: Distributor, Distributor-Encoding Encoder 42: Encoder 44: Decoder 46: Collector 50: Assembly Group 52, 86: Hierarchical Group 54: Rendering Group 56: Frame Controller 60: Encoder Block 62, 103: Analog-to-Digital Converter (DAC) 65 : sequencer circuit 70: multiplier stage 72: accumulator stage, inverter 74, 92, 124, 126: differential amplifier 78: amplifier 80: decoder block 82: reconstruction group 84: analog-to-digital converter (ADC) 85: Display 87: Channel Aligner 88: Split Group 89: Collector Controller 94: Sample and Hold Circuit 96: Decoder Track Circuit 98: Controller 100: Multiplier Section 102: Accumulator Section 104: Operational Amplifier 120: passive multiplying accumulator decoder 122: chip multiplier stage 128: reset element 130: multiplexer 148: control logic unit C1: storage device C1-C1, CF: capacitors _clk 1, clk 2: clock phase Signals S1-S1, S2-S2, S3-S3, S4-S4, S5-S5, S6-S6, S7-S7: Switch Group SSDS: Spread Spectrum Direct Sequence

The present invention and its advantages can be best understood by reference to the following description taken in conjunction with the accompanying drawings, wherein: 1 is a diagram illustrating the transmission of electromagnetic (EM) video signals from a digital video source to a digital video signal using Spread Spectrum Direct Sequence (SSDS) based CDMA modulation (Spread Spectrum Video Transmission (SSVT)) in accordance with a non-exclusive embodiment of the present invention System diagram of the receiver. 2A is a logical block diagram of a Spread Spectrum Video Transmission (SSVT) transmitter and SSVT receiver wired via a transmission cable, according to a non-exclusive embodiment of the present invention. 2B is a possible schematic diagram of the arrangement of video signals into vectors, which are modulated prior to transmission, according to a non-exclusive embodiment of the present invention. 3 is a logical block diagram of an encoder-distributor used in an SSVT transmitter according to a non-exclusive embodiment of the present invention. 4 is a circuit diagram of an SSVT encoder according to a non-exclusive embodiment of the present invention. 5A is a logical block diagram illustrating a receiver element for demodulating P received differential pairs of EM potential quasi-signals back to an HDMI signal in accordance with a non-exclusive embodiment of the present invention. 5B is a logical block diagram illustrating another receiver element for demodulating the differential pairs of P received EM potential quasi-signals back to HDMI signals in accordance with another non-exclusive embodiment of the present invention. 6 is a logic diagram of N decoder tracks of a differential pair for demodulating an EM potential quasi-signal in accordance with a non-exclusive embodiment of the present invention. 7 is a circuit diagram of an exemplary decoder track circuit in accordance with a non-exclusive embodiment of the present invention. 8 is a circuit diagram of another decoder circuit for decoding SSDS encoded media signals according to another non-exclusive embodiment of the present invention. 9 is a timing diagram illustrating the operation of the decoder circuit of FIG. 8 according to a non-exclusive embodiment of the present invention. FIG. 10 illustrates storage banks and control logic used in the decoder circuit of FIG. 8 according to a non-exclusive embodiment of the present invention. In the drawings, the same reference numerals are sometimes used to refer to the same structural elements. It should also be understood that the descriptions in the figures are diagrammatic and not to scale.

28: Spread Video Transmission (SSVT) Transmitter (TX)

40: Distributor, distributor-encoder

42: Encoder

50: Assembly group

52: Grading Group

54: Presentation Group

56: Frame Controller

60: Encoder block

62: Analog-to-Digital Converter (DAC)

65: Sequencer circuit

Claims (72)

A method for demodulating a differential potential quasi-signal into a plurality of samples, the method comprising: (a) receiving the differential potential quasi-signal; (b) providing the differential potential quasi-signal to a plurality of decoder circuits; (c) respectively providing a plurality of spread spectrum direct sequence (SSDS) chips to the plurality of decoder circuits, each of the plurality of SSDS chips having a first state or a second state; (d) for each of the plurality of decoder circuits, conditionally depending on whether the SSDS chip provided to each of the plurality of decoder circuits has the first state or the second state, respectively Invert or not invert the differential potential quasi-signal; (e) for each of the plurality of decoder circuits, storing the inversion or non-inversion of the differential potential quasi-signal at a first storage location and a second storage location; and (f) generating a video vector comprising the plurality of samples respectively inverted from the first storage location and the second storage location stored in each of the plurality of decoder circuits Or derived from the differential potential quasi-signal without inversion. The method of claim 1, wherein conditionally inverting or not inverting is performed by a selected decoder circuit of the plurality of decoder circuits, and Further comprising multiplying the differential potential quasi-signal by (+1) if the SSDS chip provided to the select decoder circuit has the first state, or if the SSDS chip has the second state, The differential potential quasi-signal is multiplied by (-1). The method of claim 1 or claim 2, wherein it depends on whether each of the plurality of SSDS chips provided to each of the plurality of decoder circuits respectively has the first A state or having the second state in which each of the plurality of decoder circuits conditionally inverts or does not invert the differential potential quasi-signal by multiplying by (+1) or (-1) . The method of any one of claim 1 to claim 3, further comprising, for each of the plurality of decoder circuits, operating a switching network during the active state of the first clock signal, the switching network is responsible for switching the differential potential level signal to the first storage position and the second storage position, wherein the switching network depends on whether the SSDS chips provided to each of the plurality of decoder circuits respectively are Having the first state or the second state and selectively inverting or not inverting the differential potential quasi-signal to the first storage position and the second storage position. The method of claim 4, further comprising providing the plurality of samples during an active state of the second clock signal. The method of any one of claim 1 to claim 5, further comprising sampling and holding the received differential potential quasi-signals before providing to the plurality of decoder circuits. The method of any one of claims 1 to 6, further comprising converting the plurality of samples in the analog domain to the digital domain. The method of any one of claim 1 to claim 7, wherein the plurality of samples of the video vector each include color information for one or more sets of samples for one or more pixels. The method of claim 8, further comprising splitting the video vector into the one or more samples. The method of claim 9, further comprising splitting the video vector using the same arrangement that was used to create the video vector. A decoder for decoding a differential potential quasi-signal that has been encoded using Spread Spectrum Direct Sequence (SSDS) encoding, the decoder comprising: a plurality of decoder track circuits for generating a plurality of differential sample outputs, each of the decoder track circuits comprising: (a) a first terminal and a second terminal configured to receive a first value and a second value of the differential potential quasi-signal, and a third terminal configured to receive a first state or a an SSDS chip in the second state; (b) a multiplier circuit configured to demodulate the first value of the differential potential level signal by conditionally inverting or not inverting the first value and the second value depending on the state of the SSDS chip; a value and the second value; and (c) a first storage device and a second storage device configured to store a demodulated first value and a second value; (d) an output for providing the demodulated first and second values stored on the first storage means and the second storage means, wherein the plurality of differential sample outputs are derived from the demodulated first and second values provided at outputs of the plurality of encoder track circuits, respectively. The decoder of claim 11, wherein the multiplier circuit is configured to multiply by (+1) or (-1) if the SSDS chip is in the first state or the second state, respectively demodulating the first value and the second value of the differential potential quasi-signal. The decoder of claim 11 or claim 12, wherein the multiplier circuit includes a first set of switches and a second set of switches, wherein the first set of switches and the second set of switches are complementary such that at The first set of switches is closed when the second set of switches is open, and vice versa. The decoder of claim 13, wherein the first set of switches and the second set of switches are coupled between the first and second terminals and the first and second storage devices. The decoder of claim 13 or claim 14, wherein when the SSDS chip has the first state and the multiplier circuit is multiplied by (+1), the first set of switches is open when the second set of switches is open The switches are closed, and when the SSDS chip has the second state and the multiplier circuit is multiplied by (-1), the second set of switches is closed while the first set of switches is open. The decoder of any one of claim 11 to claim 15, wherein the first storage means and the second storage means are first and second storage devices located on first and second power supply rails, respectively, of the multiplier circuit. a capacitor and a second capacitor. The decoder of any one of claim 11 to claim 16, wherein each of the decoder track circuits includes the first and second storage devices selectively coupled between the output terminal and the first and second storage devices between operational amplifiers. A decoder as claimed in any one of claim 11 to claim 17, wherein the multiplier is arranged to perform the demodulation during a first active state of the first clock signal, and the output terminal is arranged to The demodulated first value and the second value are provided during the second active state of the two clock signals. The decoder of any one of claim 11 to claim 18, further comprising a sample and hold circuit configured to sample and hold the differential potential quasi-signal. The decoder of any one of claims 11 to 19, wherein the plurality of differential signal outputs are converted from the analog domain to the digital domain. The decoder of any one of claims 11 to 20, wherein the plurality of differential signal outputs represent a video vector including color information for one or more samples. The decoder of any one of claim 11 to claim 21, further comprising a split group for splitting the video vector into the one or more samples, the split group using and having been used for Create the same permutation of the video vector. A method that includes: (a) receiving differential signal pairs of video media encoded using Spread Spectrum Direct Sequence (SSDS) coding over a transmission medium (L); (b) applying the (L) chip values to the received (L) differential signal pairs, respectively; (c) phase the (L) differential signal pairs with (+1) or (-1) depending on the state of the L chip values respectively applied to each of the (L) differential signal pairs; take; (d) storing the multiplied (L) differential signal pairs in a first capacitor bank, the first capacitor bank having a first (L) capacitor and a second (L) capacitor, each one each for storing a charge commensurate with the product resulting from the multiplication of the (L) differential signal pairs; and (e) generating a decoded differential video media sample by: (i) generating an average value of the charge accumulated on the first set of capacitors and the second set of capacitors, respectively; and (ii) generating the decoded differential video media samples from a differential amplifier associated with the first capacitor bank and arranged to receive the accumulated capacitors of the first and second set of capacitors, respectively the average value of the charge. The method of claim 23, further comprising, by repeating (a) through (e), including (i) and (ii), for a plurality of (L) differentials of video media sequentially received via the transmission medium, respectively The signal pair produces a sequence of decoded differential video media samples. The method of claim 23 or claim 24, further comprising alternately storing the product resulting from the multiplication of the first set (L) of differential signal pairs and the second set (L) of differential signal pairs, respectively in in the first capacitor bank and the second capacitor bank. The method of any one of claim 23 to claim 25, further comprising sequentially performing (e) to determine the average value of the accumulated charges held by the first capacitor bank and the second capacitor bank Alternate between to generate a sequence of decoded differential video media samples. The method of any one of claims 23 to 26, further comprising by time multiplexing outputs of a second amplifier associated with the first capacitor bank and associated with the second capacitor bank A sequence of decoded differential video media samples is generated. The method according to any one of claim 23 to claim 27, wherein when the (L) differential signal pairs of the video media are respectively received sequentially via the transmission medium, (b) and (c) are sequentially performed ), (d) and (e). The method of any one of claim 23 to claim 28, wherein (d) further comprises sequentially storing each of the multiplied (L) differential signal pairs in a buffer of the first capacitor bank Of the (L) stages, each of the (L) stages includes one of the first set of capacitors and one of the second set of capacitors, respectively. The method of any one of claim 23 to claim 29, wherein generating the average of the charges accumulated on the first set of capacitors and the second set of capacitors of the first capacitor bank further comprises: receiving an average control signal at the first capacitor bank; and In response to the average control signal, the first charge stored on the first set of capacitors and the second charge stored on the second set of capacitors are dumped to the first capacitor and the second capacitor coupled to the differential input of the amplifier. on the second capacitor. The method of claim 30, further comprising initializing the first capacitor and the second capacitor prior to dumping the first charge and the second charge. The method of any one of claim 23 to claim 25, further comprising providing one or more control signals to the first capacitor bank, the one or more control signals causing the first capacitor bank to perform (d ) and (e)(i). A decoder for decoding video media that has been encoded using Spread Spectrum Direct Sequence (SSDS) encoding, the decoder comprising: a chip multiplier configured to multiply the (L) SSDS encoded video media signals by the (L) SSDS chip values, respectively; A storage bank having (L) memory elements, each memory element configured to store one of the (L) SSDS encoded video media signals and one of the (L) SSDS chip values, respectively. A multiplication produces a signal commensurate with a product; an averaging element configured to average the signals stored on the (L) memory elements; and An output configured to provide a decoded video media signal output derived from an average of the signals stored on the (L) memory elements. The decoder of claim 33, further configured to, when the (L) SSDs encoded video media signals are sequentially received by the chip multiplier, sequentially store on the (L) memory elements and store them by the (L) memory elements sequentially. The signal commensurate with the product resulting from multiplying the (L) SSDS encoded video media signals and the (L) SSDS chip values. The decoder of claim 33 or claim 34, further comprising a control logic configured to control: (a) When the (L) SSDs-encoded video media signals are sequentially received, sequentially store in the (L) memory elements and the (L) SSDs-encoded video media signals and the (L) ) of the SSDS chip values resulting in a signal commensurate with the product; and (b) after all of the (L) memory elements have stored signals commensurate with the product of multiplying the (L) SSDS-encoded video media signals by the (L) SSDS chip values, respectively, activate the averaging element to average the signal stored on the (L) memory elements. The decoder of claim 35, wherein the control logic is further configured to repeat (a) and ( b) multiple times. The decoder of any one of claim 33 to claim 36, further comprising a second storage bank having (L) memory elements. The decoder of claim 37, further wherein the control logic is further configured to alternately store the product of the multiplication between the first storage bank and the second storage bank. The decoder of any one of claim 33 to claim 38, further comprising a control logic further configured to alternate: (a) the storage of the product of the multiplication between the first storage group and the second storage group for the (L) SSDS encoded video media signals, respectively, for a plurality of groups; and (b) the average of the signals stored on the (L) memory elements of the first storage group when the second storage group, Wherein the averaging is performed for one of the two storage groups while the other of the two storage groups is performing storage, and vice versa. The decoder of any one of claim 33 to claim 39, further comprising an amplifier coupled to the output for providing the decoded video media signal output. The decoder of any one of claim 33 to claim 40, wherein the (L) SSDS encoded video media signals are differential signals, and The multiplier is configured to multiply the differential (L) SSDS encoded video media signals; The storage group is configured to store signals commensurate with the product of the multiplication of the differential (L) SSDS encoded video media signals on a first group of memory elements and a second group of memory elements, respectively; The averaging element is configured to average the signals stored on the first set of memory elements and the second set of memory elements, respectively; and The outputs are differential outputs, and the decoded video media signal output is a differential decoded video media signal output. The decoder of claim 41, further comprising a differential amplifier configured to receive the averaged signals stored on the first set of memory elements and the second set of memory elements and provide at differential outputs The differential decoded video media signal is output. A method for generating an average signal value obtained by averaging signal values stored on (L) storage devices arranged in a first group, by encoding using Spread Spectrum Direct Sequence (SSDS) encoding A device for decoding (L) encoded video media signals to generate a sample video signal, the (L) signal values obtained from multiplying the (L) signals by the (L) SSDS chip values, respectively derived. The apparatus of claim 43, further comprising a multiplier for sequentially receiving the encoded (L) encoded video media signals and sequentially applying the (L) encoded video media signals, respectively The video media signal and the (L) SSDS chip values having a first state or a second state and multiplying them. The apparatus of claim 44, wherein the multiplier is further configured to depend on whether the (L) SSDS chip values applied to each of the (L) signals respectively have the first state or The second state multiplies each of the (L) encoded video media signals by a (+1) value or a (-1) value. The apparatus of any one of claim 43 to claim 45, further comprising a storage group comprising the (L) storage devices, the storage group configured to receive the (L) via When the encoded video media signals are multiplied, the (L) multiplied video media signals are sequentially stored on the (L) storage devices. The apparatus of any one of claim 43 to claim 46, further comprising an amplifier for amplifying an average signal value and outputting the sample video signal. The apparatus of any one of claim 43 to claim 47, wherein: The received (L) video media signals are (L) differential video media signals; the average signal values stored on the (L) storage devices are the differential average signal values stored on the (L) differential storage devices, respectively, and The generated sample video signal is a differential sample video signal. The apparatus of any one of claim 44 to claim 48, wherein the multiplier is a differential multiplier capable of multiplying (L) differential encoded video media signals. The apparatus of any one of claim 47 to claim 49, wherein the amplifier is a differential amplifier capable of outputting differential sample video signals. The apparatus of any one of claim 43 to claim 50, further comprising a second set (L) of storage apparatuses, and the apparatus is further configured to alternate: (a) the reception, multiplication and storage of the (L) encoded media signals in one of the two storage groups; and (b) the generation of the sample video signal by averaging the values stored in the other of the two storage groups, wherein the apparatus is further configured to repeatedly alternate (a) and (b) between the two storage groups over time such that the one storage group is performing (a) while the second storage group is performing as (b) ) and vice versa. The apparatus of any one of claim 43 to claim 51, further comprising a multiplexer configured to pair the first amplifier associated with the first set of storage devices with the second set of storage devices The output of the second amplifier associated with the storage device is multiplexed. A method for applying Spread Spectrum Direct Sequence (SSDS) encoding to video material, the method comprising: (a) constructing a video vector comprising N samples of a first voltage value and a second voltage value, the N samples being respectively derived from sets of samples representing a plurality of pixels; (b) modulating each of the first voltage value and the second voltage value for the N samples of the video vector using N SSDS chips, respectively, each of the modulation involving depending on the N The state of the SSDS chip to conditionally invert or not invert the first voltage value and the second voltage value of the N samples; and (c) generating a differential potential quasi output signal from the accumulation of the modulated first and second voltage values of the N samples that are conditionally inverted or not. The method of claim 53, further comprising iterating over (a) through (c), each iterating using another set of N samples representing the first and second voltage values of another video vector. The method of claim 53 or claim 54, wherein each of the plurality of sets of samples respectively includes a color information for the plurality of pixels. The method of any one of claim 53 to claim 55, wherein the color information includes one or more of the following: (a) red (R) value; (b) blue (B) value; (c) green (G) value; (d) luminance value (Y); (e) chromaticity (C) value; (f) blue-difference chromaticity (Cb) value; (g) red-difference chromaticity (C _r ) value; or (h) any combination of (a) to (g). The method of any one of claim 53 to claim 56, wherein modulating further comprises, if the corresponding SSDS chip for each of the N samples has a first state or a second state, respectively, The first voltage value and the second voltage value for the N samples are then multiplied by (+1) or (-1). The method of claim 57, further comprising, for each of the N samples, storing the multiplied first voltage value and the second voltage value of the N samples in the first N storage means and the second voltage value, respectively. on the second N storage devices. The method of any one of claim 53 to claim 58, further comprising from the modulated first N samples of the N samples stored on the first N storage devices and the second N storage devices, respectively The accumulation of a voltage value and a second voltage value generates the differential potential quasi output signal. The method of any one of claim 53 to claim 59, wherein the differential potential quasi output signal is an electromagnetic signal. The method of any one of claim 53 to claim 60, further comprising transmitting the differential potential quasi output signal to a video receiver via an HDMI transmission medium. An encoder for applying Spread Spectrum Direct Sequence (SSDS) encoding to video material, the encoder comprising: a plurality of multiplier circuits, at least one of the multiplier circuits including and configured to: (a) receiving a sample including a first differential voltage value and a second differential voltage value; (b) the first and second differential voltage values for the sample by conditionally inverting or not inverting the first and second differential voltage values depending on the state of the SSDS chip value is modulated; and (c) storing the modulated first and second differential voltage values of the sample on the first and second storage means; and an accumulator configured to generate a pair of differential potential quasi output signals from the accumulation of a plurality of voltage values respectively stored on a plurality of first storage devices and a second storage device of the plurality of multiplier circuits, The plurality of voltage values are derived from modulation of the plurality of samples received by the plurality of multiplier circuits, respectively. The encoder of claim 62, wherein the at least one multiplier circuit further comprises a first input terminal and a second input terminal, the first input terminal and the second input terminal being configured to receive the sample of the sample, respectively A first differential voltage value and a second differential voltage value. The encoder of claim 53 or claim 63, wherein the at least one multiplier circuit further comprises a switch network configured to conditionally store the first differential voltage value of the sample and The second differential voltage value: (a) if the SSDS chip has a first state, storing the first differential voltage value and the second differential voltage value of the sample on the first storage device and the second storage device, respectively; or (b) If the SSDS chip has a second state, store the first differential voltage value and the second differential voltage value of the sample on the second storage device and the first storage device, respectively. The encoder of claim 64, wherein the switch network comprises: a first set of switches selectively connecting a first input terminal and a second input terminal to the first storage device and a second storage device, respectively; and A second set of switches selectively connects the first input terminal and the second input terminal to the second storage device and the first storage device, respectively. The encoder of claim 65, wherein the first set of switches and the second set of switches are complementary to each other such that when the first set of switches is closed, the second set of switches is open and vice versa. The encoder of claim 66, wherein the state of the SSDS chip determines when the first set of switches and the second set of switches are opened or closed, respectively. The encoder of any one of claim 62 to claim 67, wherein the first storage means and the second storage means are on a first power supply rail and a second power supply rail, respectively, of the at least one multiplier circuit the first capacitor and the second capacitor. The encoder of any one of claim 62 to claim 68, wherein the accumulator includes one or more operational amplifiers configured to receive stored in multiplication with the plurality of operational amplifiers, respectively voltage values on a plurality of first storage devices and second storage devices associated with the circuit. The encoder of any one of claim 62 to claim 69, further configured such that each of the plurality of multiplier circuits performs the modulation during a first active state of the first clock signal, and the The accumulator performs the accumulation during the second active state of the second clock signal. The encoder of any one of claim 62 to claim 70, wherein the plurality of samples define a video vector that includes color information for one or more samples. The encoder of claim 71, wherein the color information for the one or more samples includes one of: (a) red (R) value; (b) blue (B) value; (c) green (G) value; (d) luminance value (Y); (e) chromaticity (C) value; (f) blue-difference chromaticity (Cb) value; (g) red-difference chromaticity (C _r ) value; or

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