TW202226821A - Encoder and decoder circuits for the transmission of video media using spread spectrum direct sequence modulation - Google Patents

Encoder and decoder circuits for the transmission of video media using spread spectrum direct sequence modulation Download PDF

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TW202226821A
TW202226821A TW110143382A TW110143382A TW202226821A TW 202226821 A TW202226821 A TW 202226821A TW 110143382 A TW110143382 A TW 110143382A TW 110143382 A TW110143382 A TW 110143382A TW 202226821 A TW202226821 A TW 202226821A
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differential
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ssds
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TWI810720B (en
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羅伯特 史蒂芬 哈尼鮑爾
羅伯特 J 克拉克
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美商Hyphy 美國公司
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/238Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
    • H04N21/2383Channel coding or modulation of digital bit-stream, e.g. QPSK modulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363Adapting the video stream to a specific local network, e.g. a Bluetooth® network
    • H04N21/43637Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wireless protocol, e.g. Bluetooth, RF or wireless LAN [IEEE 802.11]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
    • H04N21/4382Demodulation or channel decoding, e.g. QPSK demodulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/61Network physical structure; Signal processing
    • H04N21/615Signal processing at physical level

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Television Systems (AREA)
  • Color Television Systems (AREA)

Abstract

The present invention relates generally to video or other media transmission, and more particularly, to encoding and decoding of video media that has been transmitted between a video source and a video sink using spread spectrum direct sequence (SSDS) modulation.

Description

用於使用展頻直接序列調製傳輸視訊媒體的編碼器和解碼器電路Encoder and Decoder Circuits for Transmission of Video Media Using Spread Spectrum Direct Sequence Modulation

相關申請案的交叉引用CROSS-REFERENCE TO RELATED APPLICATIONS

本申請要求於2020年11月25日提交的美國臨時申請 No. 63/118,320 的優先權,兩者名稱均為“Encoder and Decoder Circuits for the Transmission of Video Media Using Spread Spectrum Direct Sequence Modulation(用於使用展頻直接序列調製傳輸視訊媒體的編碼器和解碼器電路)”,並且兩者出於所有目的整體併入本文。 This application claims priority to U.S. Provisional Application No. 63/118,320, filed on November 25, 2020, both entitled "Encoder and Decoder Circuits for the Transmission of Video Media Using Spread Spectrum Direct Sequence Modulation (for use with Spread Spectrum Direct Sequence Modulation Encoder and Decoder Circuits for Transmission of Video Media)", and both are incorporated herein in their entirety for all purposes.

本發明一般涉及視訊和/或其他媒體傳送,更特別地,涉及用於使用分碼多重存取(CDMA)和展頻直接序列(SSDS)調製在視訊源和視訊接收端(video sink)之間的傳輸的視訊媒體的編碼和解碼。The present invention relates generally to the transmission of video and/or other media, and more particularly, to use of code division multiple access (CDMA) and spread spectrum direct sequence (SSDS) modulation between video sources and video sinks Encoding and decoding of transmitted video media.

高解析度視訊通常以多種不同格式產生,包括“720p”、“1080i”、“1080p”和最近的“4K”。對於這些格式,“i”指的是隔行掃描,“p”指的是逐行掃描。High-resolution video is often produced in a number of different formats, including "720p," "1080i," "1080p," and more recently, "4K." For these formats, "i" refers to interlaced scanning and "p" refers to progressive scanning.

使用上面列出的任何格式傳輸的視訊資料量是巨大的。對於“720p”,傳輸速率為 1280 水平線乘 720 垂直線或每訊框大約 921,600 個像素,典型刷新速率為每秒 50 或 60 訊框。1080i 的傳輸需要傳輸 1920 水平線乘 540 垂直線,或每場 1,036,800 個像素,每訊框由兩個隔行掃描場組成,刷新速率範圍為每秒 12.5 到 60 場。1080p 的傳輸涉及 1920 水平線乘 1080 垂直線,或每訊框 2,073,600 個像素,並且通常刷新速率範圍為每秒 30 到 60 訊框。4K 視訊傳輸涉及每訊框 3840 水平線乘 2160 垂直線,通常刷新速率為每秒 30 或 60 訊框。The amount of video data transferred using any of the formats listed above is enormous. For "720p", the transfer rate is 1280 horizontal lines by 720 vertical lines or approximately 921,600 pixels per frame, with a typical refresh rate of 50 or 60 frames per second. A 1080i transmission requires the transmission of 1920 horizontal lines by 540 vertical lines, or 1,036,800 pixels per field, consisting of two interlaced fields per frame, with refresh rates ranging from 12.5 to 60 fields per second. A 1080p transfer involves 1920 horizontal lines by 1080 vertical lines, or 2,073,600 pixels per frame, and typically has refresh rates ranging from 30 to 60 frames per second. 4K video transmission involves 3840 horizontal lines by 2160 vertical lines per frame, typically at a refresh rate of 30 or 60 frames per second.

鑒於傳輸視訊所需的大量頻寬,通常使用各種類型的視訊壓縮,諸如MPEG、AVC和HEVC。視訊壓縮的問題包括有限的互通性、增加的實施成本、增加的時延和降低的影像保真度。因此,與未壓縮或視覺無損視訊相比,在顯示壓縮視訊時,圖片品質一定程度會下降。Given the large amount of bandwidth required to transmit video, various types of video compression are commonly used, such as MPEG, AVC, and HEVC. Problems with video compression include limited interoperability, increased implementation costs, increased latency, and reduced image fidelity. As a result, when displaying compressed video, the picture quality is somewhat degraded compared to uncompressed or visually lossless video.

上述問題的嚴重性在不久的將來只會變得更加嚴重。消費者電子公司現在正在向市場推出8K相機和顯示器。8K設備的訊框大小為 7,680 條水平線和 4,320 條垂直線,或每訊框 33,177,600 像素,並且刷新速率通常為每秒 120 或 240 訊框。因此,8K 視訊的傳輸將使已經存在的一系列挑戰變得更加糟糕。The severity of the above problems will only get worse in the near future. Consumer electronics companies are now bringing 8K cameras and displays to the market. 8K devices have frame sizes of 7,680 horizontal and 4,320 vertical lines, or 33,177,600 pixels per frame, and typically have a refresh rate of 120 or 240 frames per second. Therefore, the transmission of 8K video will make a series of challenges that already exist worse.

因此需要一種能夠傳輸未經壓縮的高品質、高解析度視訊的視訊傳輸器。Therefore, there is a need for a video transmitter capable of transmitting uncompressed high-quality, high-resolution video.

本發明針對使用基於展頻直接序列(SSDS)調製的分碼多重存取(CDMA)通道共用在視訊源和視訊接收端之間傳輸的視訊媒體的編碼和解碼電路。The present invention is directed to an encoding and decoding circuit for sharing video media transmitted between a video source and a video sink using a Code Division Multiple Access (CDMA) channel based on Spread Spectrum Direct Sequence (SSDS) modulation.

在一個非排他性實施例中,描述了用於將一組相互正交的SSDS碼應用於視訊資料的編碼器電路和方法,其中 (“L”) 是限定為在 CDMA 碼本中使用的碼的長度的參數。該方法和編碼器電路涉及(a)建構包括第一電壓值和第二電壓值的N個樣本的視訊向量,N個樣本分別從表示多個像素的多組樣本得出,(b)使用每個來自其對應代碼的L 個SSDS碼片調製用於視訊向量中的N 個樣本的第一電壓值和第二電壓值中的每一個,調製中的每一個涉及分別取決於L個對應SSDS碼片的狀態而條件性地反轉或不反轉N個樣本的第一電壓值和第二電壓值,(c)產生L個差分電位準輸出訊號的序列,每個來自於條件性地被反轉或不被反轉的N個樣本的經調製的第一電壓值和第二電壓值的累加。In one non-exclusive embodiment, encoder circuits and methods are described for applying a set of mutually orthogonal SSDS codes to video data, where ("L") is defined as a code used in a CDMA codebook. length parameter. The method and encoder circuit involve (a) constructing a video vector comprising N samples of a first voltage value and a second voltage value, the N samples being derived from sets of samples representing a plurality of pixels, respectively, (b) using each L SSDS chips from their corresponding codes are modulated for each of the first and second voltage values of the N samples in the video vector, each of the modulations involving modulations depending on the L corresponding SSDS codes, respectively The state of the chip is conditionally inverted or not for the first voltage value and the second voltage value of the N samples, (c) generating a sequence of L differential potential quasi-output signals, each from being conditionally inverted; Accumulation of modulated first and second voltage values for N samples with or without being inverted.

在另一個非排他性實施例中,描述了用於應用同一組相互正交的SSDS碼來將L個差分電位準訊號解碼為N個樣本的解碼電路和方法。該方法和電路包括(a)接收一系列L個差分電位準訊號,(b)將每個接收到的差分電位準訊號提供至N個解碼器電路,(c)將來自對應代碼的N個展頻直接序列(SSDS)碼片分別提供至N個解碼器電路,N個SSDS碼片中的每一個具有第一狀態或第二狀態,(d)對於N個解碼器電路中的每一個,取決於提供至N個解碼器電路的每一個的SSDS碼片分別是否具有第一狀態或第二狀態,藉由條件性地反轉或不反轉差分電位準訊號來解調,(e)對於N個解碼器電路中的每一個,在第一儲存位置和第二儲存位置處累積反轉或不反轉差分電位準訊號;(f)在L個解調步驟(d)和(e)之後,提供N個重建樣本,分別從儲存在N個解碼器電路中的每一個的第一儲存位置和第二儲存位置處的經反轉或未經反轉的差分電位準訊號中得出的N個樣本。In another non-exclusive embodiment, a decoding circuit and method are described for applying the same set of mutually orthogonal SSDS codes to decode L differential potential quasi-signals into N samples. The method and circuit include (a) receiving a series of L differential potential quasi-signals, (b) providing each received differential potential quasi-signal to N decoder circuits, (c) spreading the N number of spread spectrums from the corresponding codes Direct sequence (SSDS) chips are provided to N decoder circuits respectively, each of the N SSDS chips has a first state or a second state, (d) for each of the N decoder circuits, depending on Whether the SSDS chips provided to each of the N decoder circuits have a first state or a second state, respectively, is demodulated by conditionally inverting or not inverting the differential potential quasi-signal, (e) for N each of the decoder circuits accumulating inverted or non-inverted differential potential quasi-signals at the first storage location and the second storage location; (f) after L demodulation steps (d) and (e), providing N reconstructed samples, N samples derived from the inverted or non-inverted differential potential quasi-signals stored at the first storage location and the second storage location of each of the N decoder circuits, respectively .

在又一非排他性實施例中,描述了一種解碼器電路和方法,用於藉由產生藉由對儲存在佈置於第一組中的(L)個存放裝置上的平均電壓值進行平均得出的平均電壓值,對使用SSDS編碼進行編碼的視訊媒體的(L)個訊號進行解碼以產生樣本視訊訊號,其中該(L)個電壓值是該(L)個訊號分別與(L)個SSDS碼片值進行相乘而得出的。In yet another non-exclusive embodiment, a decoder circuit and method is described for generating by averaging voltage values stored on (L) storage devices arranged in a first group derived by averaging The average voltage value of , decodes (L) signals of the video media encoded using SSDS encoding to generate sample video signals, wherein the (L) voltage values are the (L) signals and the (L) SSDS respectively. The chip values are multiplied together.

以下描述列舉了本文揭露的本發明的各個方面和實施例。沒有特定實施例旨在限定本發明的範圍。相反,實施例提供了包括在要求保護的發明範圍內的各種裝置和方法的非限制性示例。該描述將從本領域普通技術人員的角度來閱讀。因此,不一定包括普通技術人員熟知的資訊。 分碼多重存取( CDMA The following description sets forth various aspects and embodiments of the invention disclosed herein. No specific examples are intended to limit the scope of the invention. Rather, the embodiments provide non-limiting examples of various apparatus and methods included within the scope of the claimed invention. This description is to be read from the perspective of one of ordinary skill in the art. Therefore, information that is well known to those of ordinary skill is not necessarily included. Code Division Multiple Access ( CDMA )

分碼多重存取(CDMA)是眾所周知的通道存取協定,通常用於包括蜂巢在內的無線電通訊技術。CDMA是多址存取的示例,其中幾個發射器可以經由單個通訊通道同時發送資訊。在電信應用中,CDMA 允許多個使用者共用給定的頻帶,而不受其他使用者的干擾。 CDMA 採用展頻直接序列 (SSDS),這種編碼依賴於唯一的正交碼來編碼每個使用者的資料。藉由使用唯一代碼,可以將多個使用者的傳輸合併發送,而不會在使用者之間產生干擾。在接收側,每個使用者使用相同的唯一碼或正交碼來解調傳輸,分別恢復每個使用者的資料。 展頻直接序列( SSDS )調製 Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used in radio communication technologies including cellular. CDMA is an example of multiple access, where several transmitters can transmit information simultaneously via a single communication channel. In telecommunications applications, CDMA allows multiple users to share a given frequency band without interference from other users. CDMA uses Spread Spectrum Direct Sequence (SSDS), which relies on unique orthogonal codes to encode each user's data. By using unique codes, transmissions from multiple users can be combined and sent without interference between users. On the receiving side, each user uses the same unique code or orthogonal code to demodulate the transmission, recovering each user's data separately. Spread Spectrum Direct Sequence ( SSDS ) modulation

SSDS是一種調製技術,藉由該技術,特定頻寬中的訊號(例如,一系列電或電磁值)使用正交碼被有意地擴展,從而產生具有更寬頻寬的訊號。然後經由傳輸介質傳輸更寬頻寬的訊號。在接收側,使用與發送側調製相同的正交碼來解調寬頻寬訊號。結果,恢復了原始的電或電磁訊號。SSDS is a modulation technique whereby a signal in a specific bandwidth (eg, a series of electrical or electromagnetic values) is intentionally spread using orthogonal codes, resulting in a signal with a wider bandwidth. Then a wider bandwidth signal is transmitted through the transmission medium. On the receiving side, the same orthogonal code is used to demodulate the wide bandwidth signal as that on the transmitting side. As a result, the original electrical or electromagnetic signal is restored.

本發明涉及用於使用基於展頻直接序列(SSDS)調製的分碼多重存取(CDMA)通道共用來編碼和解碼在視訊源和視訊接收端之間傳輸的視訊媒體的電路。在操作期間,從視訊源接收包含顏色值和像素相關資訊的按時間排序的視訊樣本串流,並為視訊接收端重建。如下文更詳細描述的,從視訊源接收的輸入視訊樣本的數量和內容取決於在源處操作的顏色空間。無論使用哪種顏色空間,每個視訊樣本都表示指定顏色空間中的感測或測量的光量。當接收到輸入視訊樣本串流時,輸入視訊樣本被重複(1)藉由根據預定排列將輸入視訊樣本分配到編碼器輸入向量中來“分佈”,以及(2)藉由應用基於SSDS的 CDMA 調製到多個編碼器輸入向量中的每一個,應用正交碼,進行編碼,以產生具有類雜訊特性的多個複合EM訊號。(3)然後,EM 訊號經由傳輸介質傳輸,諸如 HDMI 電纜。在接收側,(4)傳入的 EM 訊號藉由應用基於SSDS的 CMDA 解調進行解碼,應用相同的正交碼,將樣本重建為輸出向量,然後(5)使用預定排列的逆,藉由將重建的視訊樣本從輸出向量分配到輸出串流“收集”輸出向量。結果,包含顏色和像素相關資訊的按時間排序的原始視訊樣本串流從視訊源傳遞到視訊接收端。The present invention relates to circuits for encoding and decoding video media for transmission between a video source and a video sink using code division multiple access (CDMA) channel sharing based on spread spectrum direct sequence (SSDS) modulation. During operation, a time-ordered stream of video samples containing color values and pixel-related information is received from the video source and reconstructed for the video sink. As described in more detail below, the number and content of input video samples received from a video source depends on the color space operating at the source. Regardless of the color space used, each video sample represents the sensed or measured amount of light in the specified color space. When a stream of input video samples is received, the input video samples are repeated (1) by "distributing" the input video samples into encoder input vectors according to a predetermined arrangement, and (2) by applying CDMA over SSDS Modulation to each of a plurality of encoder input vectors, applying an orthogonal code, is encoded to generate a plurality of composite EM signals with noise-like properties. (3) Then, the EM signal is transmitted through a transmission medium, such as an HDMI cable. On the receiving side, (4) the incoming EM signal is decoded by applying SSDS-based CMDA demodulation, applying the same orthogonal code, reconstructing the samples into the output vector, and then (5) using the inverse of the predetermined arrangement, by Distribute the reconstructed video samples from the output vector to the output stream "collect" the output vector. As a result, a time-ordered stream of raw video samples containing color and pixel-related information is delivered from the video source to the video sink.

參考圖1,示出了根據本發明的非排他性實施例的示出使用基於展頻直接序列(SSDS)的 CDMA 調製將電磁(EM)視訊訊號從數位視訊源傳輸到數位視訊接收端的系統 10。Referring to FIG. 1, a system 10 illustrating the use of Spread Spectrum Direct Sequence (SSDS) based CDMA modulation to transmit electromagnetic (EM) video signals from a digital video source to a digital video sink is shown in accordance with a non-exclusive embodiment of the present invention.

在下面的討論中,描述了通常如何捕獲數位視訊資料的過程。捕獲後,數位視訊資料可以傳輸到視訊顯示器以進行近乎即時的消耗。另一方面,可以將捕獲的視訊資料儲存起來以供以後以時移模式消耗。在任一情況下,本文建議使用基於SSDS的CDMA調製將數位視訊資料從視訊源(或存放裝置)傳輸到視訊接收端以供顯示(或儲存)。 視訊捕獲 In the following discussion, the process of capturing digital video data in general is described. Once captured, digital video data can be transferred to a video display for near-instant consumption. On the other hand, the captured video data can be stored for later consumption in a time-shifted mode. In either case, this paper proposes to use SSDS-based CDMA modulation to transmit digital video data from a video source (or storage device) to a video sink for display (or storage). video capture

視訊源12包括影像感測器陣列16、一或更多類比數位轉換器18、影像訊號處理器(ISP 20)和負責產生視訊樣本串流22的視訊流化器21。視訊源12也可以可選地連接到視訊媒體存放裝置24。存放裝置可以接近影像感測器陣列16的位置,也可以是遠端的。Video source 12 includes an image sensor array 16 , one or more analog digital converters 18 , an image signal processor (ISP 20 ), and a video streamer 21 responsible for generating a stream 22 of video samples. Video source 12 may also optionally be connected to video media storage device 24 . The storage device may be close to the location of the image sensor array 16, or it may be remote.

在各種實施例中,視訊源12可以是能夠捕獲成像資訊的任何設備,諸如但不限於攝影機、紅外線成像設備、超音波成像設備、核磁共振影像(MRI)設備、電腦斷層掃描,或幾乎任何其他類型的能夠產生視訊資訊的成像設備。In various embodiments, video source 12 may be any device capable of capturing imaging information, such as, but not limited to, a video camera, infrared imaging device, ultrasound imaging device, magnetic resonance imaging (MRI) device, computed tomography scan, or virtually any other Types of imaging devices capable of producing video information.

影像感測器16是能夠產生與測量的光量成比例的電子訊號的任何設備。例如,在非排他性實施例中,影像感測器是光電二極體的平面陣列。每個光電二極體表示平面陣列中的像素樣本位置。平面陣列中的光電二極體的數量可以有很大的變化,並且取決於影像感測器 16 的尺寸。例如,“4K”成像感測器包括 3840 條水平線乘以 1080 條垂直線的光電二極體陣列,或者總共4,147,200 個光電二極體。8K成像感測器將有 7,680 條水平線和 4,320 條垂直線,或每訊框 3,317,7600 個像素。應當理解,4K和8K僅僅是解析度的示例,並且影像感測器16可以是任何尺寸,包括小於480、480、720、1080、4K、8K。陣列中光電二極體的數量當然會相應變化。Image sensor 16 is any device capable of generating an electronic signal proportional to the amount of light measured. For example, in a non-exclusive embodiment, the image sensor is a planar array of photodiodes. Each photodiode represents a pixel sample location in the planar array. The number of photodiodes in the planar array can vary widely and depends on the size of the image sensor 16 . For example, a "4K" imaging sensor includes a photodiode array of 3840 horizontal lines by 1080 vertical lines, or a total of 4,147,200 photodiodes. The 8K imaging sensor will have 7,680 horizontal and 4,320 vertical lines, or 3,317,7600 pixels per frame. It should be understood that 4K and 8K are only examples of resolutions and that image sensor 16 may be of any size, including less than 480, 480, 720, 1080, 4K, 8K. The number of photodiodes in the array will of course vary accordingly.

在操作期間,影像感測器16以給定的刷新速率連續地重複感測間隔。在每個感測間隔期間,陣列中的每個光電二極體為每個像素位置產生電壓,該電壓與光電二極體產生的光子數量成反比。結果,光電二極體陣列產生一組電壓,這些電壓共同表示訊框。由於影像感測器以給定的畫面播放速率不斷刷新,因此連續不斷地產生多組電壓,每組電壓表示訊框。During operation, image sensor 16 continuously repeats the sensing interval at a given refresh rate. During each sensing interval, each photodiode in the array produces a voltage for each pixel location that is inversely proportional to the number of photons produced by the photodiode. As a result, the photodiode array produces a set of voltages that collectively represent the frame. Since the image sensor is continuously refreshed at a given frame playback rate, multiple sets of voltages are continuously generated, and each set of voltages represents a frame.

對於每個像素位置,光電二極體設置在電容器和地之間。就在感測間隔之前,電容器被預充電。感測時,光電二極體會產生與接收到的光量成正比的電流。當感測到幾乎沒有光時,幾乎沒有電容器通過光電二極體對地放電。相反,如果感測到大量光,則電容器上的大部分電壓都會放電。因此,曝光間隔後電容器上剩餘的電壓與感測的光的量成反比。For each pixel location, a photodiode is placed between the capacitor and ground. Just before the sensing interval, the capacitor is precharged. When sensing, the photodiode generates a current proportional to the amount of light received. When little light is sensed, little capacitor discharges to ground through the photodiode. Conversely, if a lot of light is sensed, most of the voltage on the capacitor will discharge. Therefore, the voltage remaining on the capacitor after the exposure interval is inversely proportional to the amount of light sensed.

對於許多數位影像感測器陣列16,通常存在一行類比數位轉換器(“ADC”)18,每列具有一個ADC。在給定的訊框間隔期間,對陣列16的所有行進行取樣,通常從上到下一個接一個,在本文中有時稱為“行優先”順序。對於每個樣本,ADC 18將感測到的電壓轉換為陣列中每一列的像素位置的數位值。當陣列16的所有行都已被取樣時,訊框就完成了。上述過程在逐訊框的基礎上以行優先順序重複。最終結果是一串數位值,每個數位值表示訊框中的像素位置。同樣,影像感測器的尺寸和刷新速率是每訊框數位值數量的決定性因素。例如,4K 或8K數位影像感測器每訊框將分別測量 8,294,400 或 33,177,600 個數位樣本。For many digital image sensor arrays 16, there is typically a row of analog-to-digital converters ("ADCs") 18, one ADC per column. During a given frame interval, all rows of array 16 are sampled, typically one after the other from top to bottom, sometimes referred to herein as a "row-major" order. For each sample, ADC 18 converts the sensed voltage to a digital value for the pixel location of each column in the array. The frame is complete when all rows of array 16 have been sampled. The above process is repeated in row-major order on a frame-by-frame basis. The end result is a string of bit values, each bit value representing the pixel position in the frame. Likewise, the size and refresh rate of the image sensor are decisive factors in the number of bits per frame. For example, a 4K or 8K digital image sensor will measure 8,294,400 or 33,177,600 digital samples per frame, respectively.

用於表示每個樣本的位數可以廣泛地變化。例如,每個電壓可以由類比數位轉換器18轉換成8位或10位的值。應當理解,此處列出的這些位值僅是說明性的,用於表示像素電壓值的位元的數量可以多於或少於8或10。The number of bits used to represent each sample can vary widely. For example, each voltage may be converted by analog-to-digital converter 18 to an 8-bit or 10-bit value. It should be understood that these bit values listed here are merely illustrative, and the number of bits used to represent pixel voltage values may be more or less than 8 or 10.

影像感測器陣列16可以是單色的或彩色的。在單色的情況下,由ADC 18產生的數位值僅表示一種顏色。對於彩色的,通常應用眾所周知的顏色技術,諸如拜耳濾波。利用拜耳濾波,單個光電二極體16選擇性地覆蓋有預定顏色(例如,紅色(R)或藍色(B)或綠色(G))的濾波器。在替代實施例中,可以使用CYGM(青色、黃色、綠色和品紅色)或CMY(青色、品紅色和黃色)濾波。無論使用哪種類型的濾波器,都會在每個樣本位置測量濾波的光的量。Image sensor array 16 may be monochrome or color. In the case of a single color, the digital values produced by ADC 18 represent only one color. For color, well-known color techniques such as Bayer filtering are generally applied. Using Bayer filtering, a single photodiode 16 is selectively covered with a filter of a predetermined color (eg, red (R) or blue (B) or green (G)). In alternative embodiments, CYGM (cyan, yellow, green, and magenta) or CMY (cyan, magenta, and yellow) filtering may be used. Regardless of the type of filter used, the amount of filtered light is measured at each sample location.

ISP 20被佈置為對從ADC 18接收的數位值串進行內插。藉由內插,ISP 20獲取包含在用於每個像素測量及其幾何鄰域的數位值中的資訊,並定義對應的像素的顏色的估計。為了在特定顏色空間(有很多)中輸出全彩影像,ISP 20 在每個位置會插入“缺失”顏色值。也就是說,給定每個像素的單色測量值,ISP 會藉由演算法估計“缺失”的顏色值,以創建例如像素的 RGB 或 YCbCr 表示。ISP 20因此為給定訊框的給定像素產生一組樣本22,每組樣本22表示訊框內給定像素位置的顏色值(如測量的和/或內插的)。The ISP 20 is arranged to interpolate the string of digital values received from the ADC 18 . By interpolation, ISP 20 obtains the information contained in the digital values for each pixel measurement and its geometric neighborhood, and defines an estimate of the color of the corresponding pixel. In order to output a full-color image in a specific color space (of which there are many), the ISP 20 interpolates "missing" color values at each location. That is, given a single color measurement for each pixel, the ISP will algorithmically estimate the "missing" color values to create, for example, an RGB or YCbCr representation of the pixel. ISP 20 thus generates a set of samples 22 for a given pixel of a given frame, each set of samples 22 representing a color value (eg, measured and/or interpolated) for a given pixel location within the frame.

給定的一組樣本22的內容可以變化,因為有許多方式來表示顏色。在不同的實施例中,包含在每組樣本22中的資訊因此可以變化。通常,RGB 被認為是全彩色,而其他空間,諸如 YCbCr是全彩色的近似值,更小而難以傳輸。RGB 提供三種顏色值。對於 YCbCr,Y 是亮度分量,Cb 和 Cr 分別是藍差和紅差色度值。YCbCr 顏色空間由關聯的 RGB 顏色空間的數學座標變換定義。在另一種表示顏色的方式中,可以使用“交替”方法。例如,每隔一個像素由其量度(Y)值表示,而交替像素由 Cb(藍色)或 Cr(紅色)值表示。因此,在各種實施例中,每組樣本22包括平行傳輸的一些數位“S”個樣本值。對於 RGB,每組樣本 22 的樣本數為 S = 3,而對於 YCbCr,S = 2。The content of a given set of samples 22 can vary because there are many ways to represent color. The information contained in each set of samples 22 may thus vary in different embodiments. In general, RGB is considered full color, while other spaces, such as YCbCr, are approximations of full color, smaller and harder to transmit. RGB provides three color values. For YCbCr, Y is the luminance component, and Cb and Cr are the blue-difference and red-difference chrominance values, respectively. The YCbCr color space is defined by the mathematical coordinate transformation of the associated RGB color space. In another way of representing colors, the "alternate" method can be used. For example, every other pixel is represented by its metric (Y) value, while alternating pixels are represented by a Cb (blue) or Cr (red) value. Thus, in various embodiments, each set of samples 22 includes a number of digital "S" sample values transmitted in parallel. For RGB, the number of samples per set of samples 22 is S = 3, and for YCbCr, S = 2.

作為回應,視訊流化器 21 產生一系列按時間排序的樣本集22。通常,每個樣本集 22 輸出整體表示陣列 16 上的一個像素位置的光測量值。樣本的值和/或數量由每個像素位置的ISP 產生,這取決於 ISP 的實現,尤其是應用的顏色空間。In response, the video streamer 21 generates a series of time-ordered sample sets 22. Typically, each sample set 22 outputs light measurements that collectively represent a pixel location on the array 16. The value and/or number of samples are produced by the ISP at each pixel location, depending on the ISP implementation, especially the applied color space.

視訊流化器21的輸出是按時間排序的樣本集22的連續串流,每個樣本從左到右,以行優先順序,訊框接訊框表示行中的像素,只要陣列16正在感應。然後,在傳輸之後,由視訊接收端14處理樣本集串流22,以重建由影像陣列感測器16逐訊框感測的影像。The output of video streamer 21 is a continuous stream of time-ordered sample sets 22, each sample from left to right, in row-major order, frame by frame representing pixels in a row as long as array 16 is sensing. Then, after transmission, the sample set stream 22 is processed by the video receiver 14 to reconstruct the image sensed by the image array sensor 16 frame by frame.

在另一個可選實施例中,樣本集22的串流可以儲存在存放裝置24中。以這種方式,樣本集22的串流可以在視訊串流最初被影像感測器16捕獲之後的任何時間被傳輸。例如,可以在一個時間間隔期間捕獲樣本集22的串流,然後逐訊框傳輸到視訊接收端14以供在稍後的某個時間點顯示和/或儲存在儲存單元24中以傳輸到視訊接收端14。按照這種方式,視訊源12捕獲的視訊可在視訊接收端14上進行時移顯示。In another alternative embodiment, the stream of sample sets 22 may be stored in storage device 24 . In this manner, the stream of sample set 22 may be transmitted any time after the video stream is initially captured by image sensor 16 . For example, a stream of sample sets 22 may be captured during a time interval and then transmitted frame by frame to video receiver 14 for display at a later point in time and/or stored in storage unit 24 for transmission to video Receiver 14. In this manner, the video captured by the video source 12 can be time-shifted for display on the video sink 14 .

在影像捕獲和顯示的上下文中使用 SSVT 的一個優勢在於,影像在本質上容易出錯的感測器上測量,並顯示在本質上嘈雜的 LED 陣列上,並由極其複雜和穩健的人類視覺系統查看。因此,視訊的通訊要求與諸如試算表和電子郵件等傳統數位工件的通訊要求有很大不同,後者需要位元完美的傳輸。然而,傳統的視訊傳輸將視訊訊號視為另一種(數位)文檔。然而,使用 SSVT,視訊訊號以電氣穩健的方式傳輸。 SSVT 的優點之一是在接收器的 EM 訊號測量中出現的任何未補償誤差在重建影像中表現為廣譜時間和空間雜訊。這種白色雜訊比傳統位元序列傳輸產生的空白螢幕、重複影像和塊狀壓縮偽影更適合人類認知。 傳輸 One advantage of using SSVT in the context of image capture and display is that the image is measured on an inherently error-prone sensor and displayed on an inherently noisy LED array and viewed by the extremely complex and robust human visual system . Therefore, the communication requirements of video are very different from those of traditional digital artifacts such as spreadsheets and e-mail, which require bit-perfect transmission. However, traditional video transmission treats the video signal as another (digital) file. However, with SSVT, the video signal is transmitted in an electrically robust manner. One of the advantages of SSVT is that any uncompensated errors in the receiver's EM signal measurements appear as broad-spectrum temporal and spatial noise in the reconstructed image. This white noise is better for human perception than the blank screens, repetitive images, and blocky compression artifacts produced by traditional bit-sequence transmission. transmission

圖1進一步包括發送側的發送重計時器26和展頻視訊傳輸(SSVT)發射器(TX)28。如以下更詳細解釋的,重計時器26負責解碼或暴露來自由視訊流化器21產生的串流中的每個樣本集22的顏色分量資訊(例如,RGB值)。SSVT 28然後負責用於(a)使用預定排列將樣本集 22 分佈到多個編碼器輸入向量中的一個,以及(b)對多個編碼器輸入向量中的每一個應用SSDS調製,以及(c)使用基於SSDS的多個輸入向量編碼CDMA編碼以產生EM電位準訊號序列,以及(d)然後藉由多個EM路徑或傳輸介質,諸如HDMI電纜向視訊接收端14傳輸EM電位準訊號序列。FIG. 1 further includes a transmit retimer 26 and a spread spectrum video transmission (SSVT) transmitter (TX) 28 on the transmit side. As explained in more detail below, retimer 26 is responsible for decoding or exposing color component information (eg, RGB values) from each sample set 22 in the stream generated by video streamer 21 . The SSVT 28 is then responsible for (a) distributing the sample set 22 to one of the plurality of encoder input vectors using a predetermined arrangement, and (b) applying the SSDS modulation to each of the plurality of encoder input vectors, and (c) ) encode the CDMA code using multiple input vectors based on SSDS to generate the EM potential quasi-signal sequence, and (d) then transmit the EM potential quasi-signal sequence to the video receiver 14 via multiple EM paths or transmission media, such as HDMI cables.

在接收側,提供SSVT接收器(RX) 30、重計時器32和視訊接收端14。 SSVT接收器(RX)30和重計時器32的功能是重計時器26和SSVT發射器28在發送側的互補。也就是說,SSVT接收器RX 30 (a)從傳輸介質的多個EM路徑接收EM電位準訊號序列,(b)藉由應用基於SSDS的CDMA解調來解碼每個序列以在多個輸出向量中重建視訊樣本(c)使用用於將輸入樣本分佈到發送側的輸入向量中的相同排列,將來自多個輸出向量的樣本收集到樣本集22的原始串流的重建中。重計時器32然後將重建的輸出樣本變換成適合由視訊接收端14顯示或儲存在接收側以在時移模式下顯示的格式。每個樣本集22中的輸出樣本值S的數量由視訊源應用的顏色空間確定。對於 RGB,S=3,並且對於 YCbCr,S=2。在其他情況下,每個樣本集 22 中的樣本值 S 可以小於二(即,僅一(1)或多於三(3)。On the receiving side, an SSVT receiver (RX) 30, a retimer 32 and a video receiving end 14 are provided. The functions of the SSVT receiver (RX) 30 and the retimer 32 are the complement of the retimer 26 and the SSVT transmitter 28 on the transmit side. That is, the SSVT receiver RX 30 (a) receives sequences of EM potential quasi-signals from multiple EM paths of the transmission medium, (b) decodes each sequence by applying SSDS-based CDMA demodulation to output vectors on multiple output vectors The reconstructed video samples in (c) collect samples from multiple output vectors into the reconstruction of the original stream of the sample set 22 using the same arrangement used to distribute the input samples into the input vector on the transmitting side. The re-timer 32 then transforms the reconstructed output samples into a format suitable for display by the video receiver 14 or for storage on the receiver side for display in a time-shifted mode. The number of output sample values S in each sample set 22 is determined by the color space applied by the video source. For RGB, S=3, and for YCbCr, S=2. In other cases, the sample values S in each sample set 22 may be less than two (ie, only one (1) or more than three (3).

如本文所述,SSDS調製和解調在類比或電磁(“EM”)域中執行。如以下更詳細解釋的,輸入樣本集22的串流以第一時脈速率(pix-clk)分佈以根據預定排列創建編碼器輸入向量。然後將基於SSDS的 CDMA 調製應用於每個編碼器輸入向量,從而為每個編碼器輸入向量產生編碼的“EM”訊號。然後,EM 訊號藉由以第二時脈速率(SSVT_clk) 平行傳輸進行傳輸。對編碼器輸入向量中的每個樣本應用擴展(SSDS)可提供電氣彈性,但會犧牲每個樣本的頻寬。然而,藉由調製一組相互正交的代碼並同時傳輸所有得到的 EM 訊號 (CDMA),可以恢復部分或全部丟失的頻寬。As described herein, SSDS modulation and demodulation are performed in the analog or electromagnetic ("EM") domain. As explained in more detail below, the stream of input sample set 22 is distributed at a first clock rate (pix-clk) to create encoder input vectors according to a predetermined arrangement. SSDS-based CDMA modulation is then applied to each encoder input vector, resulting in an encoded "EM" signal for each encoder input vector. Then, the EM signal is transmitted by parallel transmission at the second clock rate (SSVT_clk). Applying expansion (SSDS) to each sample in the encoder input vector provides electrical resiliency at the expense of per-sample bandwidth. However, some or all of the lost bandwidth can be recovered by modulating a set of mutually orthogonal codes and transmitting all the resulting EM signals simultaneously (CDMA).

圖2A是藉由傳輸介質34連接的SSVT發射器28和SSVT接收器30的邏輯框圖。SSVT發射器28包括分配器40和多個編碼器42。SSVT接收器30包括多個解碼器44和收集器46。FIG. 2A is a logical block diagram of SSVT transmitter 28 and SSVT receiver 30 connected by transmission medium 34 . The SSVT transmitter 28 includes a distributor 40 and a plurality of encoders 42 . The SSVT receiver 30 includes a plurality of decoders 44 and collectors 46 .

在發送側,SSVT接收器30的分配器40被佈置為接收在樣本22的輸入集合中暴露的顏色資訊(例如,R、G和B值)。作為回應,分配器40獲取一組輸入樣本22的暴露的顏色資訊,並根據預定義的排列建構多個編碼器輸入向量。在圖2A中所示的非排他性實施例中,有四個編碼器輸入向量(V 0、V 1、V 2和V 3),一個分別用於傳輸介質34上的四個EM路徑中的每一個。在多個實施例中,傳輸介質34可以是諸如HDMI、光纖或無線的電纜。多個編碼器42之一被分別分配給四個向量V 0、V 1、V 2和V 3之一。每個編碼器42負責對包含在相應編碼器輸入向量中的樣本值進行編碼,並產生經由傳輸介質34上的並行路徑之一發送的EM訊號。 On the transmit side, the distributor 40 of the SSVT receiver 30 is arranged to receive the colour information (eg R, G and B values) exposed in the input set of samples 22 . In response, the allocator 40 takes the exposed color information of a set of input samples 22 and constructs a plurality of encoder input vectors according to a predefined arrangement. In the non-exclusive embodiment shown in FIG. 2A , there are four encoder input vectors (V 0 , V 1 , V 2 , and V 3 ), one for each of the four EM paths on transmission medium 34 . One. In various embodiments, transmission medium 34 may be a cable such as HDMI, fiber optic, or wireless. One of the plurality of encoders 42 is assigned to one of the four vectors V 0 , V 1 , V 2 and V 3 , respectively. Each encoder 42 is responsible for encoding the sample values contained in the corresponding encoder input vector and producing an EM signal that is sent over one of the parallel paths on the transmission medium 34 .

在所示的此特定實施例中,有四個EM路徑,並且四個編碼器42每個分別為四個路徑中的每一個產生EM訊號。然而,應當理解,本發明決不應當限於四種途徑。相反,傳輸介質34上的路徑的數量可以廣泛地從一到多於一的任何數量,包括多於四。 排列示例 In the particular embodiment shown, there are four EM paths, and four encoders 42 each generate EM signals for each of the four paths. However, it should be understood that the present invention should by no means be limited to the four approaches. Rather, the number of paths on the transmission medium 34 may be broadly from one to any number greater than one, including greater than four. permutation example

參考圖2B,示出了由分配器40實施的用於建構四個向量V 0、V 1、V 2和V 3的一種可能排列的圖。每個向量包括N個顏色資訊樣本。 Referring to Figure 2B, a diagram is shown of one possible arrangement implemented by allocator 40 for constructing four vectors V0 , V1, V2 and V3 . Each vector contains N samples of color information.

在此非排他性實施例中,樣本集22的暴露顏色資訊分別是“RGB”。在此示例中,樣本集22的暴露的RGB樣本從左到右被分配給向量V 0、V 1、V 2和V 3。換言之,最左邊樣本的“R”、“G”和“B”值以及下一個樣本集22的“R”訊號被分配給向量V 0,而下一個樣本 22 的下一個(從左到右)“G”、“B”、“R”和“G”值被分配給向量 V 1,下一個(從左到右)“B”、“R”、“G”和“B”值分配給向量 V 2,下一個(從左到右)“R”、“G”、“R”和“R”值分配給向量 V 3。一旦第四向量V 3被分配了它的訊號,就重複上述過程,直到四個向量V 0、V 1、V 2和V 3中的每一個都具有N個樣本。在多個實施例中,N個樣本的數量可以廣泛地變化。 In this non-exclusive embodiment, the exposed color information of the sample sets 22 is "RGB", respectively. In this example, the exposed RGB samples of sample set 22 are assigned to vectors V 0 , V 1 , V 2 and V 3 from left to right. In other words, the "R", "G" and "B" values of the leftmost sample and the "R" signal of the next sample set 22 are assigned to the vector V 0 , and the next (left to right) of the next sample 22 The "G", "B", "R" and "G" values are assigned to the vector V 1 and the next (left to right) "B", "R", "G" and "B" values are assigned to the vector V2, the next ( left to right) "R", "G", "R" and "R" values are assigned to vector V3 . Once the fourth vector V3 has been assigned its signal, the above process is repeated until each of the four vectors V0 , V1, V2 and V3 has N samples. In various embodiments, the number of N samples can vary widely.

作為示例,考慮非排他性實施例N= 60。在這種情況下,四個向量 V 0、V 1、V 2和 V 3中包括的N個樣本的總數為 240 (60 x 4 = 240)。四個編碼器輸入向量 V 0、V 1、V 2和 V 3在完全建立時包括 80 個不同樣本集 22 (240/3 = 80) 的樣本(其中 S = 3)。換句話說: ● 向量 V 0包括樣本 P 0、N 0到 P 0、N N-1; ● 向量 V 1包括樣本 P 1、N 0到 P 1、N N-1; ● 向量 V 2包括樣本 P 2、N 0到 P 2、N N-1;以及 ● 向量 V 3包括樣本 P 3、N 0到 P 3、N N-1As an example, consider the non-exclusive embodiment N=60. In this case, the total number of N samples included in the four vectors V 0 , V 1 , V 2 and V 3 is 240 (60 x 4 = 240). The four encoder input vectors V 0 , V 1 , V 2 and V 3 , when fully established, include samples of 80 different sample sets 22 (240/3=80) (where S=3). In other words: • Vector V 0 includes samples P 0 , N 0 to P 0 , N N-1 ; • Vector V 1 includes samples P 1 , N 0 to P 1 , N N-1 ; • Vector V 2 includes samples P 2 , N 0 to P 2 , N N-1 ; and • Vector V 3 includes samples P 3 , N 0 to P 3 , N N-1 .

應當理解,以上示例僅僅是說明性的並且在任何方面都不應被解釋為限制性的。樣本的數量N可以多於或少於60個。此外,應當理解,(a)每個樣本集22的暴露的顏色資訊可以是任何顏色資訊(例如,Y、C、Cr、Cb等)並且不限於 RGB。It should be understood that the above examples are merely illustrative and should not be construed as limiting in any respect. The number N of samples can be more or less than 60. Furthermore, it should be understood that (a) the exposed color information of each sample set 22 may be any color information (eg, Y, C, Cr, Cb, etc.) and is not limited to RGB.

傳輸介質34上的EM路徑的數量也可以廣泛地變化。因此,向量V的數量和編碼器42的數量也可以從僅一個或大於一的任何數量廣泛變化。The number of EM paths on the transmission medium 34 can also vary widely. Accordingly, the number of vectors V and the number of encoders 42 may also vary widely from just one or any number greater than one.

還應該理解,用於建構向量的排列方案,無論數量如何,都是任意的。可以使用任何排列方案,僅限於在發送側使用的任何排列方案也用於接收側的任何排列方案。It should also be understood that the arrangement used to construct the vectors, regardless of the number, is arbitrary. Any permutation scheme can be used, limited only to any permutation scheme used on the transmitting side is also used for any permutation scheme on the receiving side.

參考圖3,示出了SSVT發射器28的邏輯框圖。分配器-編碼器 40 包括組裝組 50、分級組 52、呈現組 54 和訊框控制器 56。編碼器塊 60 包括類比數位轉換器(DAC) 62和四個編碼器 42的組,一個對於傳輸介質 34 上的每個 EM 路徑。Referring to Figure 3, a logical block diagram of the SSVT transmitter 28 is shown. The splitter-encoder 40 includes an assembly group 50, a grading group 52, a presentation group 54, and a frame controller 56. The encoder block 60 includes an analog-to-digital converter (DAC) 62 and a set of four encoders 42, one for each EM path on the transmission medium 34.

分配器40被佈置成一個接一個地接收集合樣本22的串流的暴露的顏色資訊(例如,RGB)。作為回應,組裝組50根據樣本集22的輸入串流的暴露的顏色資訊(例如RGB)建構四個向量V 0、V 1、V 2和V 3。當接收到樣本集22時,根據預定排列它們被儲存在組裝組50。同樣,當建構每個包含N個樣本的向量時,分配器40可以使用任何數量的不同排列。 The distributor 40 is arranged to receive the exposed colour information (eg RGB) of the stream of set samples 22 one after the other. In response, assembly group 50 constructs four vectors V 0 , V 1 , V 2 and V 3 from the exposed color information (eg, RGB) of the input stream of sample set 22 . As the sample sets 22 are received, they are stored in the assembly group 50 according to a predetermined arrangement. Likewise, allocator 40 may use any number of different permutations when constructing vectors each containing N samples.

分級組52促進四個向量V 0、V 1、V 2和V 3中的每一個的N個樣本從重計時器26使用的第一時鐘頻率或域到用於編碼的第二時鐘頻率或域的交叉以及在傳輸介質34上傳輸所產生的EM電位準訊號。如先前在上面的示例中討論的N=60和S=3,恰好表示80組RGB樣本的樣本包含在四個編碼器輸入向量V 0、V 1、V 2和 V 3中。 Hierarchical group 52 facilitates N samples of each of the four vectors V 0 , V 1 , V 2 and V 3 from the first clock frequency or domain used by retimer 26 to the second clock frequency or domain used for encoding. The resulting EM potential quasi-signal is crossed and transmitted over the transmission medium 34 . As N=60 and S=3 discussed earlier in the above example, samples representing exactly 80 sets of RGB samples are contained in the four encoder input vectors V0 , V1, V2 and V3 .

在多個實施例中,第一時鐘頻率可以更快、更慢或與第二時鐘頻率相同。第一時鐘頻率 f_pix 由視訊源 12 選擇的視訊格式確定。第二時鐘頻率 f_ssvt 是 f_pix、傳輸介質 34 中 EM 路徑的數量 P、每個輸入/輸出樣本集中的樣本數量 S以及 SSVT 變換參數 N(輸入/輸出向量位置的數量)和 L(每個SSDS代碼的長度)的函數,其中f_ssvt = (f_pix * S * L) / (P * N)。藉由這種安排,輸入時鐘 (pix_clk) 以一種速率振盪,SSVT 時鐘 (ssvt_clk) 以不同的速率振盪。它們可以相同或不同。擴散的出現是因為N個輸入樣本(單個顏色分量)被分配給輸入向量;然後編碼器在準備下一個輸入向量的同時執行前向變換(基於SSDS的 CDMA)。In various embodiments, the first clock frequency may be faster, slower or the same as the second clock frequency. The first clock frequency f_pix is determined by the video format selected by the video source 12 . The second clock frequency f_ssvt is f_pix, the number P of EM paths in the transmission medium 34, the number of samples S in each input/output sample set, and the SSVT transformation parameters N (number of input/output vector positions) and L (each SSDS code length), where f_ssvt = (f_pix * S * L) / (P * N). With this arrangement, the input clock (pix_clk) oscillates at one rate and the SSVT clock (ssvt_clk) oscillates at a different rate. They can be the same or different. Diffusion occurs because N input samples (a single color component) are assigned to the input vector; the encoder then performs a forward transform (SSD-based CDMA) while preparing the next input vector.

呈現組54將四個編碼器輸入向量V 0、V 1、V 2和V 3中的每一個的N個樣本(N 0到N -1)提供給編碼器塊60。 Rendering group 54 provides encoder block 60 with N samples (N 0 to N −1 ) of each of the four encoder input vectors V 0 , V 1 , V 2 , and V 3 .

控制器56控制組裝組50、分級組52和呈現組54的操作和定時。具體地,控制器負責在建構四個編碼器輸入向量 V 0、V 1、V 2和 V 3時定義所使用的排列和樣本的數量N。控制器56還負責協調從第一時鐘頻率到第二時鐘頻率的時鐘域交叉,如分級組52所執行的那樣。控制器56進一步負責協調呈現組54向編碼器塊60提供四個編碼器輸入向量V 0、V 1、V 2和V 3的每一個的N(N 0到N -1)個樣本的時機。 Controller 56 controls the operation and timing of assembly group 50 , grading group 52 and presentation group 54 . In particular, the controller is responsible for defining the permutations and number N of samples used when constructing the four encoder input vectors V0 , V1, V2 and V3 . The controller 56 is also responsible for coordinating the clock domain crossing from the first clock frequency to the second clock frequency, as performed by the hierarchical group 52 . Controller 56 is further responsible for coordinating when presentation group 54 provides encoder block 60 with N (N 0 to N −1 ) samples of each of the four encoder input vectors V 0 , V 1 , V 2 , and V 3 .

在編碼器塊 60 內,提供了多個類比數位轉換器(DAC) 62,每個數模轉換器被佈置為接收共同分配給四個編碼器輸入向量 V 0、V 1、V 2和 V 3的P*N樣本(P0, N 0到P 3, N N-1)之一。每個 DAC 62 從數位域轉換其接收到的樣本成電壓訊號的差分對,其量與其輸入的數位值成正比。在非排他性實施例中,DAC 62的輸出範圍從最大電壓到最小電壓。 Within the encoder block 60, a plurality of analog-to-digital converters (DACs) 62 are provided, each digital-to-analog converter being arranged to receive a common assignment to four encoder input vectors V0 , V1, V2 and V3 One of the P*N samples (P0, N 0 to P 3 , N N-1 ). Each DAC 62 converts the samples it receives from the digital domain into differential pairs of voltage signals in amounts proportional to the digital value of its input. In a non-exclusive embodiment, the output of DAC 62 ranges from a maximum voltage to a minimum voltage.

分別為四個編碼器輸入向量V 0、V 1、V 2和V 3提供四個編碼器42。每個編碼器42接收其編碼器輸入向量的N個樣本(N 0到N -1)中的每一個的差分訊號對,使用正交SSVT“碼片”調製N個差分電壓訊號對中的每一個,累積調製值然後產生差分EM電位準輸出訊號。由於在此示例中存在四個編碼器42,因此存在經由傳輸介質34同時傳輸的EM電位準訊號(Level 0到Level 1)。 Four encoders 42 are provided for the four encoder input vectors V 0 , V 1 , V 2 and V 3 , respectively. Each encoder 42 receives a differential signal pair for each of the N samples (N 0 to N -1 ) of its encoder input vector, modulating each of the N differential voltage signal pairs using quadrature SSVT "chips" One, the accumulated modulation value then produces a differential EM potential quasi-output signal. Since there are four encoders 42 in this example, there are EM potential quasi-signals (Level 0 to Level 1 ) that are transmitted simultaneously via the transmission medium 34 .

定序器電路65協調DAC 62和編碼器42的操作時機。定序器電路65負責控制DAC 62和編碼器42的時鐘。如下文詳細描述的,定序器電路65還負責產生兩個時鐘相位訊號“clk 1”和“clk 2”,它們負責控制編碼器42的操作。Sequencer circuit 65 coordinates the timing of operations of DAC 62 and encoder 42 . Sequencer circuit 65 is responsible for controlling the clocking of DAC 62 and encoder 42 . Sequencer circuit 65 is also responsible for generating two clock phase signals "clk 1" and "clk 2", which are responsible for controlling the operation of encoder 42, as described in detail below.

參考圖4,示出了用於輸入向量V之一的編碼器42的電路圖。編碼器電路42包括多個乘法器級70和包括差分放大器74的累加器級72。Referring to Figure 4, a circuit diagram of an encoder 42 for one of the input vectors V is shown. The encoder circuit 42 includes a plurality of multiplier stages 70 and an accumulator stage 72 including a differential amplifier 74 .

每個乘法器級70被佈置為在第一(+)和第二(-)終端處分別接收來自DAC66之一的差分樣本訊號對(+Sample N-1/-Sample N-1到+Sample 0/-Sample 0)。每個乘法器級70還包括用於接收展頻直接序列(SSDS)“碼片”的終端、逆變器72、開關組S1-S1、S2-S2和S3-S3、由clk 1和clk驅動的開關組、第一電壓軌上的第一存放裝置C1和第二電壓軌上的第二存放裝置C2。 Each multiplier stage 70 is arranged to receive a differential sample signal pair (+Sample N-1 /-Sample N-1 to +Sample 0 ) from one of the DACs 66 at the first (+) and second (-) terminals, respectively /-Sample 0 ). Each multiplier stage 70 also includes a terminal for receiving a Spread Spectrum Direct Sequence (SSDS) "chip", an inverter 72, switch banks S1-S1, S2-S2 and S3-S3, driven by clk 1 and clk , a first storage device C1 on the first voltage rail, and a second storage device C2 on the second voltage rail.

在操作期間,每個乘法器級70根據接收的SSDS碼片的值,藉由條件性地乘以(+1)或(-1)來調製其接收的類比訊號差分對。如果SSDS碼片為 (+1),則當 clk 1 具有有效狀態時,開關對 S1-S1 和 S3-S3 閉合,而開關對 S2-S2 保持打開狀態。結果,+/-樣本的差分對都被分別儲存在存放裝置C1和C2上而沒有任何反轉(即,乘以+1)。另一方面,如果SSDS碼片為(-1),則發生上述的補數。換言之,開關對 S1-S1 打開,而開關對 S2-S2 和 S3-S3 在 clk 1 具有有效狀態時閉合。結果,差分樣本對被反轉(乘以 -1)並分別儲存在 C1 和 C2 上。During operation, each multiplier stage 70 modulates its received differential pair of analog signals by conditionally multiplying by (+1) or (-1) depending on the value of the received SSDS chip. If the SSDS chip is (+1), when clk 1 has a valid state, switch pair S1-S1 and S3-S3 are closed, while switch pair S2-S2 remains open. As a result, differential pairs of +/- samples are all stored on storage devices C1 and C2, respectively, without any inversion (ie, multiplied by +1). On the other hand, if the SSDS chip is (-1), the above complement occurs. In other words, switch pair S1-S1 is open, while switch pair S2-S2 and S3-S3 are closed when clk 1 has an active state. As a result, the differential sample pairs are inverted (multiplied by -1) and stored on C1 and C2, respectively.

累加器級 72 操作以在所有乘法器級 70 的存放裝置 C1 和 C2 上累加電荷。當 clk 1 過渡為非有效狀態且 clk 2 過渡為有效狀態時,所有 clk 1 控制開關(S4-S4)閉合並且 clk 2 控制開關 (S5-S5, S6-S6) 打開。結果,所有乘法器級70的第一存放裝置C1上的所有電荷被放大器78放大並累積在差分放大器74的第一輸入上,而所有乘法器級70的第二存放裝置C2上的所有電荷由放大器78放大並累積在差分放大器74的第二輸入上。作為回應,差分放大器74產生一對差分電磁(EM)電位準訊號。The accumulator stage 72 operates to accumulate charges on all of the multiplier stage 70 locations C1 and C2. When clk 1 transitions to inactive state and clk 2 transitions to active state, all clk 1 control switches (S4-S4) are closed and clk 2 control switches (S5-S5, S6-S6) are open. As a result, all charges on the first storage device C1 of all multiplier stages 70 are amplified by amplifier 78 and accumulated on the first input of differential amplifier 74, while all charges on the second storage device C2 of all multiplier stages 70 are amplified by Amplifier 78 amplifies and accumulates on the second input of differential amplifier 74 . In response, differential amplifier 74 generates a pair of differential electromagnetic (EM) potential quasi-signals.

對所有四個向量V 0、V 1、V 2和V 3執行上述過程。此外,只要 SSVT 發射器 28 接收到樣本集 22 的串流,就不斷重複上述過程。作為回應,四個差分 EM 輸出電位準訊號串流經由傳輸介質34被發送到 SSVT 接收器 30。 接收器 The above process is performed for all four vectors V 0 , V 1 , V 2 and V 3 . Furthermore, the above process is repeated as long as the SSVT transmitter 28 receives the stream of the sample set 22 . In response, four differential EM output potential quasi-signal streams are sent to SSVT receiver 30 via transmission medium 34 . receiver

在接收側,SSVT RX 30負責將經由傳輸介質34接收的四個差分EM電位準輸出訊號串流解碼回適合顯示的格式。一旦採用合適的格式,包含在樣本22中的視訊內容(例如,訊號S)可以逐訊框呈現在視訊顯示器上。結果,視訊源12的視訊捕獲可以由視訊接收端14重新創建。可替代地,可以儲存解碼的視訊資訊以供稍後以時移模式顯示。On the receiving side, SSVT RX 30 is responsible for decoding the four differential EM potential quasi-output signal streams received via transmission medium 34 back into a format suitable for display. Once in an appropriate format, the video content (eg, signal S) contained in sample 22 can be presented frame by frame on a video display. As a result, the video capture of video source 12 can be recreated by video sink 14 . Alternatively, the decoded video information can be stored for later display in time-shifted mode.

SSVT RX 30在發送側執行SSVT TX 28的逆操作。 SSVT RX 30使用四個解碼器80和收集器46。解碼器80將四個差分EM電位準輸出訊號重建為四個解碼器輸出向量。然後,收集器 46 將解碼器輸出向量的樣本分配給樣本集22的原始串流,每個包括與串流中該位置處的原始S個樣本相對應的S個重建樣本。SSVT RX 30 performs the inverse operation of SSVT TX 28 on the transmit side. The SSVT RX 30 uses four decoders 80 and collectors 46 . The decoder 80 reconstructs the four differential EM potential quasi output signals into four decoder output vectors. Collector 46 then assigns the samples of the decoder output vector to the original streams of sample set 22, each comprising S reconstructed samples corresponding to the original S samples at that position in the stream.

參考圖5A,示出了視訊接收端14的SSVT RX 30、重計時器32和視訊顯示器85的詳細框圖。 P解碼器80(標記為0到P-1)被佈置為分別接收差分EM電位準訊號Level 0到Level P-1。作為回應,每個解碼器80產生N個差分對重建樣本(Sample 0到Sample N-1)。在有四個解碼器80(P=4)的情況下,分別建構四個向量V 0、V 1、V 2和V 3Referring to FIG. 5A, a detailed block diagram of the SSVT RX 30, the retimer 32, and the video display 85 of the video receiver 14 is shown. The P-decoders 80 (labeled 0 to P-1 ) are arranged to receive differential EM potential quasi-signals Level 0 to Level P-1 , respectively. In response, each decoder 80 produces N differential pair reconstruction samples (Sample 0 to Sample N-1 ). With four decoders 80 (P=4), four vectors V 0 , V 1 , V 2 and V 3 are constructed respectively.

重建組82分別在每個解碼間隔結束時對四個解碼器輸出向量V 0、V 1、V 2和V 3中的每一個進行取樣並保持N個重建樣本(Sample 0到Sample N-1)的差分對中的每一個。分別為四個向量V 0、V 1、V 2和V 3中的每一個的N個樣本(Sample 0到Sample N-1)中的每一個提供類比數位轉換器(ADC)84。每個 ADC 將其接收到的差分電壓訊號對轉換為相應的數位值,從而分別為四個向量 V 0、V 1、V 2和 V 3中的每一個產生數位樣本(Sample N-1到 Sample 0)。 ADC 以時脈速率 = f_ssvt /L運行。 Reconstruction group 82 samples each of the four decoder output vectors V 0 , V 1 , V 2 , and V 3 and holds N reconstructed samples (Sample 0 to Sample N-1 ) at the end of each decoding interval, respectively. of each of the differential pairs. An analog-to-digital converter (ADC) 84 is provided for each of the N samples (Sample 0 to Sample N-1 ) of each of the four vectors V 0 , V 1 , V 2 and V 3 , respectively. Each ADC converts the pair of differential voltage signals it receives into corresponding digital values, thereby generating digital samples for each of the four vectors V 0 , V 1 , V 2 and V 3 (Sample N-1 to Sample N-1, respectively). 0 ). The ADC operates at clock rate = f_ssvt /L.

收集器46包括分級組86和拆分組88。分級組86接收四個解碼器輸出向量V 0、V 1、V 2和V 3中的每一個的所有重建樣本(N n-1到N 0)。拆分組88(a)使用與在發送側使用的相同排列方案,將四個解碼器輸出向量V 0、V 1、V 2和V 3中的每一個的樣本(Sample N-1到Sample 0)拆分為樣本集22的串流(例如,在此示例中,“對於RGB像素S=3”)的暴露的顏色資訊(例如,S訊號),並且(b)將重建樣本從第二時鐘域交叉回到第一時鐘域。然後將重建樣本集22的串流提供至重計時器32,重計時器32重新格式化視訊訊號。重計時器32的輸出因此是按時間排序的樣本集22的序列的再創造。視訊接收端14包括DAC 103組和視訊顯示器85。DAC 103組負責將在數位域中的樣本22轉換回到類比域。在一個實施例中,為顯示器85中的每一行提供DAC 103。一旦樣本22被轉換為模擬域,它們就以眾所周知的方式顯示在視訊顯示器85上。 Collector 46 includes grading group 86 and splitting group 88 . Hierarchical group 86 receives all reconstructed samples (Nn -1 to N0 ) for each of the four decoder output vectors V0 , V1, V2, and V3 . Split group 88(a) outputs samples of each of the four decoder output vectors V 0 , V 1 , V 2 and V 3 (Sample N-1 to Sample 0 ) using the same permutation scheme as used on the transmit side. ) split the exposed color information (eg, the S signal) into a stream of sample sets 22 (eg, "for RGB pixels S=3" in this example), and (b) reconstruct the samples from the second clock The domains cross back to the first clock domain. The stream of reconstructed sample set 22 is then provided to retimer 32, which reformats the video signal. The output of the retimer 32 is thus a recreation of the sequence of the time-ordered sample set 22 . The video receiver 14 includes a DAC 103 group and a video display 85 . The group of DACs 103 is responsible for converting the samples 22 in the digital domain back to the analog domain. In one embodiment, DAC 103 is provided for each row in display 85 . Once the samples 22 are converted to the analog domain, they are displayed on a video display 85 in a well-known manner.

SSVT RX 30還包括通道對準器87和收集器控制器89,其從每個解碼器80接收定框資訊和孔徑資訊。作為回應,收集器控制器89協調分級組86和/或拆分組 88 的時機以確保提供至拆分組的所有樣本都來自 SSVT TX 28 發送電位準訊號的公共時間間隔。結果,(a) 組 88 的拆分可能延遲到所有樣本被接收並且(b)傳輸介質34的單個通道不必都具有相同的長度,因為拆分組88補償了任何時機差。The SSVT RX 30 also includes a channel aligner 87 and a collector controller 89 that receive framing information and aperture information from each decoder 80 . In response, collector controller 89 coordinates the timing of grading group 86 and/or splitting group 88 to ensure that all samples provided to the splitting group are from a common time interval during which the SSVT TX 28 transmits the potential quasi-signal. As a result, (a) the splitting of the groups 88 may be delayed until all samples are received and (b) the individual channels of the transmission medium 34 need not all be of the same length, since the splitting of the groups 88 compensates for any timing differences.

圖6是四個編碼器80之一的邏輯圖。編碼器80包括差分放大器92和取樣及保持電路94,其被佈置為接收、取樣及保持經由傳輸介質34接收的四個差分EM電位準訊號之一。然後將樣本的EM電位準訊號提供至N個解碼器軌道電路96(N n-1到N 0)中的每一個。定序器控制器98向分別應用於發送側的N個解碼器軌道電路96中的每一個提供相同的SSDS碼片。結果,樣本輸出(N n-1到N 0)被提供至重建組82。同樣,在發送側使用的相同SSDS碼片被每個解碼器軌道電路96使用。結果,解調的樣本N n-1到 N 0與發送側調製之前相同。 FIG. 6 is a logic diagram of one of the four encoders 80 . The encoder 80 includes a differential amplifier 92 and a sample and hold circuit 94 arranged to receive, sample and hold one of the four differential EM potential quasi-signals received via the transmission medium 34 . The EM potential quasi-signals of the samples are then provided to each of the N decoder track circuits 96 (Nn -1 to N0 ). The sequencer controller 98 provides the same SSDS chips to each of the N decoder track circuits 96 respectively applied to the transmit side. As a result, the sample outputs (N n-1 to N 0 ) are provided to the reconstruction group 82 . Likewise, the same SSDS chips used on the transmit side are used by each decoder track circuit 96 . As a result, the demodulated samples N n-1 to N 0 are the same as before modulation on the transmission side.

收集器控制器89負責跟蹤任何排列並確保拆分組88應用與在發送側建構向量V 0、V 1、V 2和V 3時使用的相同排列。 Collector controller 89 is responsible for keeping track of any permutations and ensuring that split group 88 applies the same permutations that were used when constructing vectors V 0 , V 1 , V 2 and V 3 on the transmit side.

每個解碼器80的收集器控制器89還產生多個控制訊號,包括選通訊訊號、組的末端(eob)訊號、孔徑訊號和定框訊號。選通訊訊號被提供至ADC 84並且指示給定重建組內容的模數轉換過程何時可以開始的時機。eob訊號被提供至重建組82並且表示分級組86完全充滿樣本的時機。當這種情況發生時,eob 訊號起效,預期下一組重建樣本(N n-1到N 0),清除解碼器軌道96和分級組86。孔徑控制訊號被提供至取樣及保持電路94,定框訊號被提供至通道對準器87和收集器控制器89。 替代實施例 The collector controller 89 of each decoder 80 also generates a number of control signals, including a strobe signal, an end-of-group (eob) signal, an aperture signal, and a framing signal. A strobe signal is provided to ADC 84 and indicates the timing of when the analog-to-digital conversion process for a given reconstructed bank content can begin. The eob signal is provided to the reconstruction group 82 and represents the moment when the grading group 86 is completely filled with samples. When this happens, the eob signal is asserted, and the next set of reconstructed samples (Nn -1 to N0 ) is expected, clearing the decoder track 96 and the hierarchical group 86. The aperture control signal is provided to sample and hold circuit 94 and the framing signal is provided to channel aligner 87 and collector controller 89 . Alternative Embodiment

在上述實施例中,ADC 84將解碼的樣本轉換至數位域中,並且視訊接收端14中的ADC 103將有序的樣本集22在顯示之前轉換回類比域。In the above embodiment, the ADC 84 converts the decoded samples into the digital domain, and the ADC 103 in the video receiver 14 converts the ordered set of samples 22 back to the analog domain prior to display.

如圖5B中所示,示出了替代實施例,其中來自重建組82的樣本輸出保持在模擬域中,因此消除了對ADC 103和其他元件的需要。藉由此實施例,可選地消除ADC 84、拆分組88和重計時器32。相反,類比樣本輸出被提供至分級儲存組86,分級儲存組86對在發送側建構向量V 0到V 3時使用的樣本執行相同的排列。分級組86的樣本輸出然後用於藉由可選的電位準轉換器(未示出)直接驅動視訊接收端的顯示器85。由於不同類型的顯示器需要不同的電壓來驅動它們的顯示面板,因此可以根據需要使用電位準轉換器來縮放分級組的視訊樣本輸出的電壓。如本領域已知的,可以使用任何合適的電位準轉換器,諸如鎖存器類型或逆變器類型。 As shown in Figure 5B, an alternative embodiment is shown in which the sample output from the reconstruction group 82 remains in the analog domain, thus eliminating the need for the ADC 103 and other components. With this embodiment, ADC 84, split group 88 and retimer 32 are optionally eliminated. Instead, the analog sample output is provided to a staging bank 86, which performs the same permutation on the samples used in constructing vectors V 0 to V 3 on the transmit side. The sample output of the binning group 86 is then used to directly drive the display 85 on the video receiver side by means of an optional voltage level converter (not shown). Since different types of displays require different voltages to drive their display panels, voltage level converters can be used to scale the voltages output by hierarchical groups of video samples as needed. As known in the art, any suitable level-to-level converter may be used, such as a latch type or an inverter type.

對於此實施例,收集器控制器89執行若干功能。收集器控制器98負責保持續跟蹤並向分級組86提供要使用的正確排列選擇。收集器控制器89還可以向顯示器85提供增益和伽馬值。增益確定應用了多少放大並且伽馬曲線將光通量與感知亮度相關聯,這使人類對光通量的光學感知線性化。定框訊號表示在顯示器85上建構視訊訊框的時機。反轉訊號可以可選地用於控制電位準轉換器以反轉或不反轉視訊樣本輸出,這可能是某些類型的顯示面板,諸如OLED所需要的。如果使用電位準轉換器,則電位準轉換器的輸出通常被鎖存。在這樣的實施例中,可以使用鎖存訊號來控制任何移位元視訊樣本輸出訊號的電位準的鎖存和釋放的時機。最後,閘極驅動器控制訊號用於通常用於驅動許多顯示器的水平行的閘極驅動器電路。For this embodiment, collector controller 89 performs several functions. Collector controller 98 is responsible for keeping track of and providing staging group 86 with the correct permutation selection to use. Collector controller 89 may also provide gain and gamma values to display 85 . Gain determines how much amplification is applied and the gamma curve correlates luminous flux to perceived brightness, which linearizes the human optical perception of luminous flux. The framing signal indicates when the video frame is constructed on the display 85 . The inversion signal can optionally be used to control the level converter to invert or not invert the video sample output, which may be required for certain types of display panels, such as OLEDs. If a potential quasi-converter is used, the output of the potential quasi-converter is usually latched. In such an embodiment, a latch signal may be used to control the timing of latching and releasing the level of any shifted meta-video sample output signal. Finally, gate driver control signals are used for gate driver circuits that are typically used to drive the horizontal rows of many displays.

參考圖7,示出了表示性解碼器軌道電路96的示意圖。解碼器軌道電路96包括乘法器部分100和累加器部分102。乘法器部分100包括第一對開關S1-S1、第二對開關S2-S2、第三對開關S3-S3和分別位於第一(正)和第二(負)電源軌線上的一對電容器 C1-C1。累加器部分102包括附加的電晶體對S4-S4、S5-S5、S6-S6和S7-S7、運算放大器104以及分別在第一(正)和第二(負)電源軌線上的一對電容器C F和C FReferring to FIG. 7, a schematic diagram of a representative decoder track circuit 96 is shown. The decoder track circuit 96 includes a multiplier portion 100 and an accumulator portion 102 . The multiplier section 100 includes a first pair of switches S1-S1, a second pair of switches S2-S2, a third pair of switches S3-S3, and a pair of capacitors C1 on first (positive) and second (negative) power rails, respectively -C1. The accumulator section 102 includes additional transistor pairs S4-S4, S5-S5, S6-S6 and S7-S7, an operational amplifier 104, and a pair of capacitors on the first (positive) and second (negative) power rails, respectively CF and CF.

對於每個解調週期,在第一電位準輸入(電位準+)端和第二電位準輸入(電位準-)端處接收差分EM電位準訊號對。根據接收到的SSDS碼片的值,差分EM電位準訊號對在乘法器部分100中藉由乘以(1)或負(-1)條件性地反轉來解調。For each demodulation cycle, a differential EM potential quasi-signal pair is received at a first potential quasi-input (potential quasi-+) terminal and a second potential quasi-input (potential quasi-) terminal. Depending on the value of the received SSDS chip, the differential EM potential quasi-signal pair is demodulated in the multiplier section 100 by being conditionally inverted by multiplying by (1) or negative (-1).

如果SSDS碼片具有(+1)的值,則當 clk 1 啟動時,電晶體對 S1-S1 和 S3-S3 閉合,而 S2-S2 保持打開。結果,第一電位準輸入(電位準+)端和第二電位準輸入(電位準-)的電壓值分別傳遞到正負軌上的兩個電容器C1和C1上並由其儲存。換句話說,輸入值乘以(+1)並且不會發生反轉。If the SSDS chip has a value of (+1), when clk 1 is activated, the transistor pairs S1-S1 and S3-S3 are closed, while S2-S2 remains open. As a result, the voltage values of the first potential quasi-input (potential quasi-+) terminal and the second potential quasi-input (potential quasi-) are transferred to and stored by the two capacitors C1 and C1 on the positive and negative rails, respectively. In other words, the input value is multiplied by (+1) and no inversion occurs.

如果SSDS碼片的值為-1,則當clk 1啟動時,S1-S1開關都關閉,而開關S2-S2和S3-S3都打開。結果,在正或第一(+)端和負或第二(-)端處接收的電壓值被交換。換句話說,在第一或正端提供的輸入電壓值被引導並儲存在下負軌上的電容器 C1 上,而在第二或(-)端上提供的電壓值被切換至並儲存在正上軌上的電容器 C1 上。在輸入端接收到的電壓值由此被反轉或乘以(-1)。If the value of the SSDS chip is -1, then when clk 1 is activated, the S1-S1 switches are all closed, and the switches S2-S2 and S3-S3 are both open. As a result, the voltage values received at the positive or first (+) terminal and the negative or second (-) terminal are swapped. In other words, the input voltage value provided on the first or positive terminal is directed and stored on capacitor C1 on the lower negative rail, while the voltage value provided on the second or (-) terminal is switched to and stored on the positive on capacitor C1 on the rail. The voltage value received at the input is thus inverted or multiplied by (-1).

當 clk 1 過渡為不啟動時,C1 和 C1 上的累積電荷保持不變。當 clk 2 過渡為啟動,然後電晶體對 S4-S4 打開,而電晶體對 S5-S5 和 S6-S6 閉合。然後將上軌或正軌上的電容器C1和下軌或負軌上的C1上的累積電荷提供至運算放大器104的差分輸入。運算放大器104的輸出是在發送側進行編碼之前的原始+/-樣本對。When clk 1 transitions to inactive, the accumulated charge on C1 and C1 remains the same. When clk 2 transitions to start, then transistor pair S4-S4 is open and transistor pair S5-S5 and S6-S6 are closed. The accumulated charge on capacitor C1 on the upper or positive rail and C1 on the lower or negative rail is then provided to the differential input of operational amplifier 104 . The output of the operational amplifier 104 is the raw +/- sample pair before encoding on the transmit side.

當 Clk 2 啟動時,兩個電容器 C1 和 C1 上的累積電荷也被傳遞到上軌或正軌和下軌或負軌上的電容器 CF 和 CF。在每個解調週期中,上軌和下軌上的電容器 C1 和 C1 上的電荷分別累積到上軌和下軌上的兩個電容器 CF 和 CF 上。當 clk 1 和 eob 訊號都有效時,電晶體對 S7-S7 都閉合,使電容器 CF 和 CF 中的每一個的極板短路。結果,積累的電荷被去除,兩個電容器CF和CF被復位並為下一個解調週期做好準備。When Clk 2 starts up, the accumulated charge on the two capacitors C1 and C1 is also transferred to the capacitors CF and CF on the upper or positive rail and the lower or negative rail. During each demodulation cycle, the charge on capacitors C1 and C1 on the upper and lower rails accumulates on the two capacitors CF and CF on the upper and lower rails, respectively. When both the clk 1 and eob signals are active, the transistor pairs S7-S7 are both closed, shorting the plates of each of capacitors CF and CF. As a result, the accumulated charge is removed and the two capacitors CF and CF are reset and ready for the next demodulation cycle.

由於每個解碼器80具有N個解碼器軌道電路96,N個解碼或原始+/-樣本對在每個解調週期被重新創建。然後將這些N+/- 樣本對提供至重建組 82、ADC 84,然後是收集器 46,包括分級組 86 和拆分組 88,最後是重計時器 32。結果,原始樣本集22用其原始顏色內容資訊(例如,對於RGB,S=3)重新創建,並準備好在視訊接收端14的顯示器85上顯示。Since each decoder 80 has N decoder track circuits 96, N decoded or original +/- sample pairs are recreated each demodulation cycle. These N+/- sample pairs are then provided to reconstruction group 82, ADC 84, then collector 46, including binning group 86 and splitting group 88, and finally retimer 32. As a result, the original sample set 22 is recreated with its original color content information (eg, S=3 for RGB) and is ready to be displayed on the display 85 of the video receiver 14 .

解碼器軌道96在連續L個週期上重建輸入電位準樣本,用該軌道代碼的連續SSDS碼片解調每個連續輸入電位準。每個L次解調的結果在回饋電容器 CF 上累加。當 eob 在 clk1 對應於解碼週期的第一個解調週期期間生效時,CF 在 eob 之後被清除,以便它可以從零伏或其他一些復位電壓開始再次累積。在多個非排他性實施例中,L的值是預定參數。通常,參數L越高,SSDS過程增益越大,並且SSVT訊號在傳輸介質34上傳輸的電彈性越好。另一方面,參數L越高,SSVT調製的應用所需的頻率就越高,由於傳輸介質34引起的插入損耗,這可能會損害訊號品質。The decoder track 96 reconstructs the input potential level samples over L consecutive cycles, demodulating each consecutive input potential level with consecutive SSDS chips of the track code. The result of each L demodulation is accumulated on the feedback capacitor CF. When eob is in effect during clk1 corresponding to the first demodulation cycle of the decode cycle, CF is cleared after eob so that it can accumulate again starting from zero volts or some other reset voltage. In various non-exclusive embodiments, the value of L is a predetermined parameter. Generally, the higher the parameter L, the greater the SSDS process gain and the better the electroelasticity of the SSVT signal being transmitted over the transmission medium 34. On the other hand, the higher the parameter L, the higher the frequency required for the application of SSVT modulation, which may impair the signal quality due to the insertion loss caused by the transmission medium 34.

用四個解碼器80中的每一個反復重複上述解調迴圈。最終結果是恢復按時間排序的樣本集22的原始串,每個樣本具有它們的原始顏色內容資訊(即,樣本集 S )。如本領域已知的,樣本集22隨後被處理並顯示在視訊接收端14的顯示器85上。可替代地,可以將恢復的樣本集22儲存在接收側,以便以時移模式顯示。 無源乘法累加器解碼器 The demodulation loop described above is repeated iteratively with each of the four decoders 80 . The end result is to recover the original string of time-ordered sample sets 22, each with their original color content information (ie, sample set S ). The sample set 22 is then processed and displayed on the display 85 of the video receiver 14 as is known in the art. Alternatively, the recovered sample set 22 may be stored on the receiving side for display in a time-shifted mode. Passive Multiply Accumulator Decoder

在替代實施例中,無源乘法累加器解碼器可以可選地用於解碼器塊80中,如關於圖5A所描述的。如下文詳細描述的,無源乘法累加器處理經由傳輸介質34接收的視訊媒體樣本的(L)差分對組,其中(L)是用於對傳輸前的媒體進行編碼的SSDS碼的長度。此解碼器是無源的,因為在解碼過程中不使用有源元件,諸如放大器。此解碼器還具有乘法累加器的特徵,因為在解碼過程中,(L)個差分樣本對的乘積結果及其對應的 SSDS碼片值被累加或儲存在多個存放裝置(例如電容器)上。In an alternate embodiment, a passive multiply-accumulator decoder may optionally be used in decoder block 80, as described with respect to FIG. 5A. As described in detail below, the passive multiply-accumulator processes (L) differential pairs of video media samples received via transmission medium 34, where (L) is the length of the SSDS code used to encode the media prior to transmission. This decoder is passive because no active components, such as amplifiers, are used in the decoding process. This decoder also features a multiply-accumulator because during the decoding process, the product of (L) differential sample pairs and their corresponding SSDS chip values are accumulated or stored on multiple storage devices (eg, capacitors).

參考圖8,示出了無源乘法累加器編碼器120。根據一個實施例,無源乘法累加器編碼器120包括碼片乘法器級122、第一儲存組A,包括(+)組(L)電容器和(-)組(L)電容器,以及第一對電容器129。Referring to Figure 8, a passive multiply accumulator encoder 120 is shown. According to one embodiment, the passive multiply-accumulator encoder 120 includes a chip multiplier stage 122, a first storage bank A, including (+) bank (L) capacitors and (-) bank (L) capacitors, and a first pair of Capacitor 129.

在可選實施例中,還提供了具有正(+)輸入端和負輸入端(-)的差分放大器124。在此實施例中,負(-)輸入端藉由第一電容器129選擇性地耦接到(+)組電容器(L),而正(+)輸入端藉由第二個電容器129選擇性地耦接到(-)組(L)電容器。In an alternative embodiment, a differential amplifier 124 having a positive (+) input and a negative (-) input is also provided. In this embodiment, the negative (-) input is selectively coupled to the (+) bank of capacitors (L) by a first capacitor 129 and the positive (+) input is selectively coupled by a second capacitor 129 Coupled to (-) bank (L) capacitors.

還分別提供了位於耦接在差分放大器124的(+/-)輸出和(-/+)輸入之間的回饋路徑上的一對復位元件128。藉由在 (+/-) 輸出和 (-/+)輸入之間提供負反饋,可以設置差分放大器124的增益。在非排他性實施例中,每個復位元件128包括電容器和開關(未示出)。A pair of reset elements 128 are also provided on the feedback paths coupled between the (+/-) output and the (-/+) input of the differential amplifier 124, respectively. The gain of the differential amplifier 124 can be set by providing negative feedback between the (+/-) output and the (-/+) input. In a non-exclusive embodiment, each reset element 128 includes a capacitor and a switch (not shown).

碼片乘法器級122被配置為經由傳輸介質34順序地接收已經由編碼器28使用如前所述的展頻直接序列(SSDS)編碼編碼的視訊媒體樣本的差分對。碼片乘法器級122還被配置為接收由用於分別由編碼器28對樣本的差分對進行編碼的相互正交的SSDS碼指定的SSDS碼片值。在非排他性實施例中,通道對準器87負責將正確的SSDS碼片值分別應用於每個接收到的差分對樣本。Chip multiplier stage 122 is configured to sequentially receive, via transmission medium 34, differential pairs of video media samples that have been encoded by encoder 28 using spread spectrum direct sequence (SSDS) encoding as previously described. Chip multiplier stage 122 is also configured to receive SSDS chip values specified by mutually orthogonal SSDS codes used to encode differential pairs of samples, respectively, by encoder 28 . In a non-exclusive embodiment, the channel aligner 87 is responsible for applying the correct SSDS chip value to each received differential pair sample, respectively.

在操作期間,利用樣本時鐘Fssvt的每個時鐘週期接收一個差分對樣本。回應於每個接收到的差分對樣本,碼片乘法器級 122 執行以下操作: (1)將與編碼時使用的相互正交的SSDS碼相同的SSDS碼片值應用於接收到的差分對樣本; (2)將差分對樣本與應用的碼片值相乘。根據給定差分對樣本的應用碼片值的狀態,乘數為(+1)或(-1)。如果碼片值是第一狀態(例如,“1”),則乘數是(+1)。如果碼片值為第二狀態(例如,“0”),則乘數為(-1);以及 (3)在儲存塊A中分別儲存與(+)和(-)對電容器相乘的乘積結果相稱的電壓電荷。當碼片值為(+1)時,則儲存電荷而不進行任何反轉。如果碼片值為(-1),則電荷在儲存前首先反轉。 During operation, one differential pair sample is received with each clock cycle of the sample clock Fssvt. In response to each received differential pair sample, chip multiplier stage 122 performs the following operations: (1) Apply the same SSDS chip value as the mutually orthogonal SSDS code used in encoding to the received differential pair samples; (2) Multiply the differential pair samples with the applied chip value. Depending on the state of the applied chip value for a given differential pair sample, the multiplier is (+1) or (-1). If the chip value is the first state (eg, "1"), the multiplier is (+1). If the chip value is the second state (eg, "0"), the multiplier is (-1); and (3) A voltage charge commensurate with the result of multiplying the capacitors by (+) and (-) is stored in the storage block A, respectively. When the chip value is (+1), the charge is stored without any inversion. If the chip value is (-1), the charge is first inverted before being stored.

隨著視訊媒體的(L)個差分訊號對被順序接收,對每個樣本重複上述過程。結果,(+)和(-)組中的(L)電容器被順序寫入並儲存分別與接收到的(L)差分樣本的乘積相稱的電荷。The above process is repeated for each sample as (L) differential signal pairs of the video medium are received sequentially. As a result, the (L) capacitors in the (+) and (-) groups are sequentially written and store charges commensurate with the product of the (L) differential samples received, respectively.

一旦已經接收到(L)個差分樣本並且儲存組A的(+)和(-)電容器組的所有(L)個電容器已經儲存了乘積結果,無源乘法累加器編碼器120操作以產生解碼的差分視訊媒體樣本輸出(即Sample P-1, N-1+, Sample P-1, N-1-)。這是藉由生效“平均”控制訊號來實現的,這會導致: (1)中斷電容器組 A 中乘積電荷的儲存; (2)儲存組A中的所有(L)個(+)電容器上的電荷一起短路,導致累積的電荷被“轉儲”到耦接到差分放大器124的負(-)輸入端的第一電容器129上。藉由轉儲所有(+)電容器上的累積電荷,在第一電容器129上實現“平均”電壓;以及 (3) 儲存組 A 中所有(L)個 (-) 電容器上的電荷一起短路,導致累積的電荷“轉儲”到耦接到差分放大器124的正 (+) 端的第二電容器 129 上。藉由轉儲所有(-)電容器上的累積電荷,在第二電容器129上實現“平均”電壓。 Once (L) differential samples have been received and all (L) capacitors of the (+) and (-) capacitor banks of storage bank A have stored the product results, the passive multiply accumulator encoder 120 operates to generate decoded Differential video media sample output (ie Sample P-1 , N-1 +, Sample P-1 , N-1 -). This is accomplished by asserting an "average" control signal, which results in: (1) interrupting the storage of the product charge in capacitor bank A; (2) storing the charge on all (L) (+) capacitors in bank A shorted together, causing the accumulated charge to be "dumped" onto the first capacitor 129 coupled to the negative (-) input of the differential amplifier 124 . An "average" voltage is achieved on the first capacitor 129 by dumping the accumulated charge on all (+) capacitors; and (3) the charge on all (L) (-) capacitors in storage group A are shorted together, resulting in The accumulated charge is "dumped" onto a second capacitor 129 coupled to the positive (+) terminal of the differential amplifier 124 . An "average" voltage is achieved on the second capacitor 129 by dumping the accumulated charge on all (-) capacitors.

藉由簡單地將儲存組A中的所有(+)電容器和所有(-)電容器短路在一起,在電容器對129上分別提供了(L)個輸入差分樣本的累積電荷的平均值。因此,平均基本上是“免費”執行的,這意味著相關過程是在沒有任何有源元件(例如,沒有放大器)的情況下被動完成的。By simply shorting together all (+) capacitors and all (-) capacitors in storage group A, the average value of the accumulated charge of the (L) input differential samples, respectively, is provided on capacitor pair 129 . Therefore, averaging is performed essentially "for free", meaning that the associated process is done passively without any active components (eg, without amplifiers).

解碼的差分視訊媒體樣本因此由分別耦接到差分放大器124的正端和負端的第一電容器129和第二電容器129上累積的平均電壓之間的差來表示。差分放大器124用於放大正負端之間的電壓差,同時抑制兩者之間的任何公共電壓。如圖5A或圖5B所示,利用附加電流增益,解碼的差分視訊媒體樣本更適合驅動重建組82。The decoded differential video media samples are thus represented by the difference between the average voltages accumulated on the first capacitor 129 and the second capacitor 129 coupled to the positive and negative terminals of the differential amplifier 124, respectively. The differential amplifier 124 is used to amplify the voltage difference between the positive and negative terminals while suppressing any common voltage between the two. With the additional current gain, the decoded differential video media samples are more suitable for driving the reconstruction group 82, as shown in FIG. 5A or FIG. 5B.

差分放大器124的頻率不需要以用於對輸入的(L)個差分樣本進行取樣的相同頻率Fssvt操作。由於對每(L)個輸入樣本執行平均操作,差分放大器124的頻率只需Fssvt/L。藉由降低差分放大器124的速度/穩定時間要求,降低了執行該功能所需的功率。The frequency of the differential amplifier 124 need not operate at the same frequency Fssvt used to sample the (L) differential samples of the input. Since the averaging operation is performed for every (L) input sample, the frequency of the differential amplifier 124 only needs to be Fssvt/L. By reducing the speed/settling time requirements of the differential amplifier 124, the power required to perform this function is reduced.

提供用於差分放大器124的復位電路128以在每個Fssvt/L週期將差分放大器的(+/-)輸入處的電容器129上的電壓初始化或復位為零伏或某個其他復位電壓值。在每次平均操作之前沒有復位的情況下,差分放大器124將充當積分器並且隨著時間累積它接收到的差分電壓輸入,而不是簡單地放大它接收到的用於單個平均操作的差分輸入。A reset circuit 128 for the differential amplifier 124 is provided to initialize or reset the voltage on the capacitor 129 at the (+/-) input of the differential amplifier to zero volts or some other reset voltage value every Fssvt/L cycle. Without a reset before each averaging operation, the differential amplifier 124 will act as an integrator and accumulate the differential voltage inputs it receives over time, rather than simply amplifying the differential inputs it receives for a single averaging operation.

對於上述實施例,儲存組A不能用於在平均操作期間儲存用於輸入差分樣本的乘積電荷。因此,可能會導致處理延遲。For the above-described embodiment, bank A cannot be used to store the product charge for input differential samples during averaging operations. Therefore, processing delays may occur.

在替代實施例中,無源乘法累加器編碼器120還可以可選地包括第二儲存組B,其包括(L)組(+)和(-)電容器、第二差分放大器126、第二組電容器129,一對復位電路128和多工器130。第二儲存組B、差分放大器126、第二組電容器129和復位電路128都與如上所述的它們的對應物基本上相同地操作。因此,為簡潔起見,此處不提供這些元件的詳細說明。In an alternate embodiment, the passive multiply-accumulator encoder 120 may also optionally include a second bank B comprising (L) banks of (+) and (-) capacitors, a second differential amplifier 126, a second bank of A capacitor 129, a pair of reset circuits 128 and a multiplexer 130. The second bank B, the differential amplifier 126, the second bank of capacitors 129, and the reset circuit 128 all operate substantially the same as their counterparts as described above. Therefore, for the sake of brevity, a detailed description of these elements is not provided here.

在操作期間,交替使用兩個儲存組A和B。一個是樣本,另一個是平均,反之亦然。藉由在另一組進行平均時使用一個組進行取樣,處理延遲至少以兩種方式減少。首先,可以不間斷地接收、相乘和儲存多組輸入(L)差分訊號對。其次,平均操作之後差分放大器的任何速度/穩定時間要求都被有效地否定了,因為一個組總是在樣本,而另一組在平均,反之亦然。During operation, the two storage groups A and B are used alternately. One is the sample, the other is the average, and vice versa. By using one group for sampling while the other group is averaging, processing latency is reduced in at least two ways. First, multiple input (L) differential signal pairs can be received, multiplied and stored without interruption. Second, any speed/settling time requirements of the differential amplifier after the averaging operation are effectively negated because one group is always sampling while the other is averaging, and vice versa.

為了實現具有兩個儲存組A和B的無源乘法累加器編碼器120的實施例,需要幾個控制訊號。這些控制訊號包括: (1) 提供至儲存組 A 的樣本/平均控制訊號,同時提供至儲存組 B 的互補平均/樣本訊號。由於這兩個控制訊號是互補的,所以一個儲存組將總是對當前輸入的(L)差分訊號集合進行取樣,而與另一個儲存組相關的差分放大器正在平均,反之亦然;以及 (2)將組選擇控制訊號提供至多工器130。因此,當一個儲存組正在樣本和儲存時,多工器130選擇正在平均的另一儲存組的差分放大器輸出(124或126)。藉由使組選擇控制訊號過渡為與樣本/平均控制訊號的過渡一致,多工器130的輸出總是被選擇以挑選正在平均的電容器組。結果,只要碼片乘法器級122正在接收輸入的差分輸入訊號,就連續產生解碼的差分視訊媒體樣本。 To implement the embodiment of the passive multiply-accumulator encoder 120 with two banks A and B, several control signals are required. These control signals include: (1) Provides the sample/average control signal to bank A and the complementary average/sample signal to bank B at the same time. Since the two control signals are complementary, one bank will always sample the current set of incoming (L) differential signals while the differential amplifier associated with the other bank is averaging, and vice versa; and (2) The group selection control signal is provided to the multiplexer 130 . Thus, when one bank is sampling and storing, the multiplexer 130 selects the differential amplifier output (124 or 126) of the other bank that is being averaged. By causing the bank select control signal transition to coincide with the transition of the sample/average control signal, the output of the multiplexer 130 is always selected to select the capacitor bank being averaged. As a result, decoded differential video media samples are continuously generated as long as the chip multiplier stage 122 is receiving the incoming differential input signal.

參考圖9,示出了說明無源乘法累加器編碼器120的兩組實施例的操作的交替性質的時機圖。Referring to FIG. 9, a timing diagram illustrating the alternating nature of the operation of the two sets of embodiments of the passive multiply accumulator encoder 120 is shown.

如圖所示,兩個電容器組A和B在樣本和平均之間交替。從左到右,電容器組A最初取樣,然後平均並將結果輸出到差分放大器124的電容器129,然後再次取樣。同時,電容器組 B 執行補充,這意味著它最初對結果進行平均並將結果輸出到差分放大器 126,然後進行取樣,然後對結果進行平均並將結果輸出到差分放大器 126。藉由過渡Fssvt 的每(L)個時鐘週期的平均/控制訊號的狀態來不斷重複這種交替模式。結果,連續產生多個輸出、解碼、差分、視訊媒體樣本。As shown, the two capacitor banks A and B alternate between sample and average. From left to right, capacitor bank A is initially sampled, then averaged and output to capacitor 129 of differential amplifier 124, and then sampled again. At the same time, capacitor bank B performs complementation, which means it initially averages and outputs the results to the differential amplifier 126, then samples, then averages and outputs the results to the differential amplifier 126. This alternating pattern is continuously repeated by transitioning the state of the average/control signal every (L) clock cycle of Fssvt. As a result, multiple output, decoded, differential, video media samples are generated in succession.

參考圖10,示出了示例性儲存組140(例如,A或B)和控制邏輯。使用L=128的上述示例,儲存組140將包括128個級,在圖1至(L)中標記。每個級包括第一對開關(S1-S1)、第二對開關(S2-S2)以及互補電容器C(+)和C(-)。Referring to Figure 10, an exemplary storage group 140 (eg, A or B) and control logic are shown. Using the above example of L=128, the bank 140 would include 128 stages, labeled in Figures 1 to (L). Each stage includes a first pair of switches (S1-S1), a second pair of switches (S2-S2), and complementary capacitors C(+) and C(-).

每個級還被配置為接收來自控制邏輯單元148的輸出,其用於控制第一對開關S1-S1的打開/閉合。在非排他性實施例中,控制邏輯單元148包括長度為(L)位的迴圈移位暫存器,其將單個“1”位分別迴圈到(L)級周圍。“1”位在任何時間點的位置選擇(L)級中的一個用於對給定的差分對輸入的乘積進行取樣。藉由迴圈“1”位以與(L)個Fssvt時鐘週期基本一致,(L)個樣本分別在(L)個級上收集。在多個替代實施例中,單個“1”位的脈衝寬度可以與Fssvt時鐘的脈衝寬度相同或稍小。藉由使用較小的脈衝寬度,可以避免或減輕部分導通的相鄰級(L)的樣本電容器之間的任何重疊。Each stage is also configured to receive an output from the control logic unit 148, which is used to control the opening/closing of the first pair of switches S1-S1. In a non-exclusive embodiment, the control logic unit 148 includes a wraparound shift register of length (L) bits that wraps a single "1" bit around the (L) stage, respectively. The position of the "1" bit at any point in time selects one of the (L) stages to sample the product of a given differential pair input. By looping the "1" bit to substantially coincide with (L) Fssvt clock cycles, (L) samples are collected on (L) stages, respectively. In various alternative embodiments, the pulse width of a single "1" bit may be the same or slightly smaller than the pulse width of the Fssvt clock. By using a smaller pulse width, any overlap between the sample capacitors of partially conducting adjacent stages (L) can be avoided or mitigated.

每個級還具有輸入端,該輸入端子被配置為接收電容器組 A 的樣本/平均控制訊號,或電容器組 B 的互補平均/樣本控制訊號。對於兩個組,此控制訊號用於控制第二組開關S2-S2的打開/閉合。Each stage also has an input terminal configured to receive either the sample/average control signal of capacitor bank A, or the complementary average/sample control signal of capacitor bank B. For both groups, this control signal is used to control the opening/closing of switches S2-S2 of the second group.

在樣本期間,電容器組A的樣本/平均值(或電容器組B的平均值/樣本)訊號保持在樣本狀態。結果,開關S2-S2保持打開。During the sampling period, the sample/average of capacitor bank A (or the average/sample of capacitor bank B) signal remains in the sampled state. As a result, switches S2-S2 remain open.

在樣本期間,控制邏輯單元148順序地迴圈分別用於級(L)至(1)的單個“1”位。結果,每個 Fssvt 時鐘週期只選擇一個級。對於選定的級,開關 S1-S1 閉合,允許接收與當前接收到的差分對樣本的乘積結果相稱的電荷值,並將其分別儲存在選定的級的 C(+) 和 C(-) 電容器上。During a sample, the control logic unit 148 sequentially loops the single "1" bits for stages (L) through (1), respectively. As a result, only one stage is selected per Fssvt clock cycle. For the selected stage, switches S1-S1 are closed, allowing a charge value commensurate with the product of the currently received differential pair samples to be received and stored on the C(+) and C(-) capacitors of the selected stage, respectively .

藉由迴圈藉由所有(L)級,與接收的(L)個輸入差分訊號對樣本的乘積相稱的電荷分別在(L)個Fssvt時鐘週期上儲存在(L)級上。一旦所有(L)級都累積了它們的電荷,就可以準備好執行平均操作了。By looping through all (L) stages, a charge commensurate with the product of the received (L) input differential signal pair samples is stored on (L) stages over (L) Fssvt clock cycles, respectively. Once all (L) stages have accumulated their charges, they are ready to perform averaging.

為了啟動平均操作,儲存組A的樣本/平均訊號(或儲存組B的平均/樣本訊號)過渡到平均狀態並且控制邏輯單元148停止“1”位的迴圈。結果,所有(L)級的開關S1-S1打開,所有(L)級的開關S2-S2閉合。因此,所有(L)級的互補電容器C(+)和C(-)上的電荷分別被“轉儲”(即平均)到對應差分放大器的(-)和(+)端處的電容器129上。To initiate the averaging operation, the sample/average signal of bank A (or the average/sample signal of bank B) transitions to the averaging state and the control logic unit 148 stops the looping of the "1" bit. As a result, switches S1-S1 of all (L) stages are opened and switches S2-S2 of all (L) stages are closed. Therefore, the charges on the complementary capacitors C(+) and C(-) of all (L) stages are "dumped" (ie averaged) onto the capacitors 129 at the (-) and (+) terminals of the corresponding differential amplifier, respectively .

注意,在“轉儲”/平均過程中,可以將另一個電容器(之前初始化為沒有電荷)連接到L個電容器的集合以傳送一部分結果(該比例取決於額外電容器的大小與L電容器的總和)到額外電容器。這種技術提供了將結果傳遞到相應差分放大器輸入的手段,124 用於組A或 126 用於組B。Note that during the "dump"/average process, another capacitor (previously initialized with no charge) can be connected to the set of L capacitors to deliver a fraction of the result (the ratio depends on the size of the extra capacitors combined with the sum of the L capacitors) to the extra capacitor. This technique provides a means to pass the result to the corresponding differential amplifier input, 124 for Bank A or 126 for Bank B.

儘管如上所述的儲存組A和B是對稱的並且都包括(L)級,但是應該理解這絕不是必需的。相反,A 和 B 儲存組不需要是完整的副本。只需要有足夠的重複來滿足可以處理連續的差分輸入樣本串流的要求。例如,一個或兩個儲存組的級數可以少於(L)個。在替代實施例中,僅需要複製多個儲存組中的少量級。潛在複製級的數量只需要足以確保完成對輸出放大器的輸入電容器129的平均操作。即使它們共用記憶元件,一個儲存組的結果(由放大器)的輸出也可以在下一個儲存組的樣本期間完成,因為輸出放大器在評估完成後“獨立”。Although storage groups A and B as described above are symmetric and both include (L) stages, it should be understood that this is by no means required. Conversely, the A and B storage groups do not need to be full copies. There just needs to be enough repetition to be able to handle a continuous stream of differential input samples. For example, one or two storage groups may have fewer than (L) stages. In an alternative embodiment, only a small number of stages in multiple storage groups need to be replicated. The number of potential replica stages need only be sufficient to ensure that averaging is done on the input capacitor 129 of the output amplifier. Even though they share memory elements, the output of the results of one bank (by the amplifiers) can be done during the samples of the next bank because the output amplifiers are "independent" after the evaluation is complete.

此外,每個儲存組不一定需要相應的差分放大器。在替代實施例中,可以多工從多個儲存組到給定差分放大器的輸入,從而減少所需的差分放大器的數量。Furthermore, each bank does not necessarily require a corresponding differential amplifier. In alternative embodiments, the inputs to a given differential amplifier from multiple banks of storage may be multiplexed, thereby reducing the number of differential amplifiers required.

無源乘法累加器解碼器120的各種上述實施例本質上是用於如圖5A和圖5B所示的解碼器塊80中的N個解碼器的“插入式”替代。如前所述,每個解碼器塊80提供有N個解碼器電路(N 0到N -1)。N個解碼器電路中的每一個被配置為順序地接收差分電位準樣本(+/-電位準訊號)。當接收到差分電位準訊號時,N個無源乘法累加器解碼器電路120中的每一個應用與用於對發送端的電位準位置(P)和樣本位置(N)進行編碼的相互正交的SSDS碼相同的唯一SSDS碼。結果,每個無源乘法累加器解碼器電路120為其給定的 P 和N位置產生樣本的差分對。換言之,對於(P)個解碼器80中的每一個的所有N個解碼器電路,產生從(樣本0 +,樣本0 -到樣本 P-1, N-1+,樣本 P-1, N-1-)的差分樣本的完整集合並提供至重建組82,如圖5A和圖5B所示。在關於圖5A和圖5B以及本文關於圖8描述的非排他性實施例中,N是64個通道並且SSDS碼的長度是L=128。 The various above-described embodiments of passive multiply-accumulator decoder 120 are essentially "drop-in" replacements for the N decoders in decoder block 80 as shown in Figures 5A and 5B. As before, each decoder block 80 is provided with N decoder circuits (N 0 to N −1 ). Each of the N decoder circuits is configured to sequentially receive differential potential quasi-samples (+/- potential quasi-signals). When a differential potential level signal is received, each of the N passive multiply-accumulator decoder circuits 120 applies a mutually orthogonal quadrature for encoding the potential level position (P) and sample position (N) of the transmitter Unique SSDS code with the same SSDS code. As a result, each passive multiply accumulator decoder circuit 120 produces a differential pair of samples for its given P and N positions. In other words, for all N decoder circuits of each of the (P) decoders 80, the generation from (sample 0 + , sample 0 to sample P−1 , N−1 + , sample P−1 , N− 1- ) of the complete set of differential samples and provided to the reconstruction group 82, as shown in Figures 5A and 5B. In the non-exclusive embodiment described with respect to Figures 5A and 5B and herein with respect to Figure 8, N is 64 channels and the length of the SSDS code is L=128.

多種編碼器和解碼器的上述討論是關於差分訊號來描述的。然而,應該注意的是,這絕不是要求。在多種替代實施例中,編碼器和解碼器也可以被配置為操作和處理非差分訊號(即,單個訊號)。 結論 The above discussion of various encoders and decoders has been described with respect to differential signaling. However, it should be noted that this is by no means a requirement. In various alternative embodiments, the encoder and decoder may also be configured to operate and process non-differential signals (ie, a single signal). in conclusion

本實施例應該被認為是說明性的而不是限制性的,並且本發明不限於本文給出的細節,而是可以在所附申請專利範圍的範圍和等同物內進行修正。The present examples are to be regarded as illustrative rather than restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

12:視訊源 14:視訊接收端 16:影像感測器陣列 18:類比數位轉換器(“ADC”) 20:影像訊號處理器(ISP) 21:視訊流化器 22:視訊樣本串流、樣本集 24:存放裝置、儲存單元 26、32:重計時器 28:展頻視訊傳輸(SSVT)發射器(TX) 30:SSVT接收器(RX) 34:傳輸介質 40:分配器、分配器-編碼器 42:編碼器 44:解碼器 46:收集器 50:組裝組 52、86:分級組 54:呈現組 56:訊框控制器 60:編碼器塊 62、103:類比數位轉換器(DAC) 65:定序器電路 70:乘法器級 72:累加器級、逆變器 74、92、124、126:差分放大器 78:放大器 80:解碼器塊 82:重建組 84:類比數位轉換器(ADC) 85:顯示器 87:通道對準器 88:拆分組 89:收集器控制器 94:取樣及保持電路 96:解碼器軌道電路 98:控制器 100:乘法器部分 102:累加器部分 104:運算放大器 120:無源乘法累加器解碼器 122:碼片乘法器級 128:復位元件 130:多工器 148:控制邏輯單元 C1:存放裝置 C1-C1、C F:電容器 clk 1、clk 2:時鐘相位訊號 S1-S1、S2-S2、S3-S3、S4-S4、S5-S5、S6-S6、S7-S7:開關組 SSDS:展頻直接序列 12: Video source 14: Video sink 16: Image sensor array 18: Analog-to-digital converter ("ADC") 20: Image signal processor (ISP) 21: Video streamer 22: Video sample stream, sample Episode 24: Storage Devices, Storage Units 26, 32: Re-Timers 28: Spread Spectrum Video Transmission (SSVT) Transmitter (TX) 30: SSVT Receiver (RX) 34: Transmission Medium 40: Distributor, Distributor-Encoding Encoder 42: Encoder 44: Decoder 46: Collector 50: Assembly Group 52, 86: Hierarchical Group 54: Rendering Group 56: Frame Controller 60: Encoder Block 62, 103: Analog-to-Digital Converter (DAC) 65 : sequencer circuit 70: multiplier stage 72: accumulator stage, inverter 74, 92, 124, 126: differential amplifier 78: amplifier 80: decoder block 82: reconstruction group 84: analog-to-digital converter (ADC) 85: Display 87: Channel Aligner 88: Split Group 89: Collector Controller 94: Sample and Hold Circuit 96: Decoder Track Circuit 98: Controller 100: Multiplier Section 102: Accumulator Section 104: Operational Amplifier 120: passive multiplying accumulator decoder 122: chip multiplier stage 128: reset element 130: multiplexer 148: control logic unit C1: storage device C1-C1, CF: capacitors clk 1, clk 2: clock phase Signals S1-S1, S2-S2, S3-S3, S4-S4, S5-S5, S6-S6, S7-S7: Switch Group SSDS: Spread Spectrum Direct Sequence

本發明及其優點可以藉由參考以下結合附圖進行的描述得到最好的理解,其中: 圖1是示出根據本發明的非排他性實施例的使用基於展頻直接序列(SSDS)的CDMA調製(展頻視訊傳輸(SSVT))將電磁(EM)視訊訊號從數位視訊源傳輸到數位視訊接收端的系統圖。 圖2A是根據本發明的非排他性實施例的經由傳輸電纜連線的展頻視訊傳輸(SSVT)發射器和SSVT接收器的邏輯框圖。 圖2B是根據本發明的非排他性實施例的視訊訊號排列成向量的一種可能的示意圖,這些向量在傳輸前進行調製。 圖3是根據本發明的非排他性實施例的SSVT發射器中使用的編碼器-分配器的邏輯框圖。 圖4是根據本發明非排他性實施例的SSVT編碼器的電路圖。 圖5A是說明根據本發明的非排他性實施例的用於將P個接收到的EM電位準訊號的差分對解調回HDMI訊號的接收器元件的邏輯框圖。 圖5B是說明根據本發明的另一個非排他性實施例的用於將P個接收到的EM電位準訊號的差分對解調回HDMI訊號的另一個接收器元件的邏輯框圖。 圖6是根據本發明的非排他性實施例的用於解調EM電位準訊號的一對差分對的N個解碼器軌道的邏輯圖。 圖7是根據本發明的非排他性實施例的表示性解碼器軌道電路的電路圖。 圖8是根據本發明的另一個非排他性實施例的用於解碼SSDS編碼的媒體訊號的另一個解碼器電路的電路圖。 圖9是根據本發明的非排他性實施例的示出圖8的解碼器電路的操作的時機圖。 圖10示出了根據本發明的非排他性實施例的在圖8的解碼器電路中使用的儲存組和控制邏輯。 在附圖中,有時使用相同的附圖標記來表示相同的結構元件。 還應該理解,圖中的描述是圖解的而不是按比例的。 The present invention and its advantages can be best understood by reference to the following description taken in conjunction with the accompanying drawings, wherein: 1 is a diagram illustrating the transmission of electromagnetic (EM) video signals from a digital video source to a digital video signal using Spread Spectrum Direct Sequence (SSDS) based CDMA modulation (Spread Spectrum Video Transmission (SSVT)) in accordance with a non-exclusive embodiment of the present invention System diagram of the receiver. 2A is a logical block diagram of a Spread Spectrum Video Transmission (SSVT) transmitter and SSVT receiver wired via a transmission cable, according to a non-exclusive embodiment of the present invention. 2B is a possible schematic diagram of the arrangement of video signals into vectors, which are modulated prior to transmission, according to a non-exclusive embodiment of the present invention. 3 is a logical block diagram of an encoder-distributor used in an SSVT transmitter according to a non-exclusive embodiment of the present invention. 4 is a circuit diagram of an SSVT encoder according to a non-exclusive embodiment of the present invention. 5A is a logical block diagram illustrating a receiver element for demodulating P received differential pairs of EM potential quasi-signals back to an HDMI signal in accordance with a non-exclusive embodiment of the present invention. 5B is a logical block diagram illustrating another receiver element for demodulating the differential pairs of P received EM potential quasi-signals back to HDMI signals in accordance with another non-exclusive embodiment of the present invention. 6 is a logic diagram of N decoder tracks of a differential pair for demodulating an EM potential quasi-signal in accordance with a non-exclusive embodiment of the present invention. 7 is a circuit diagram of an exemplary decoder track circuit in accordance with a non-exclusive embodiment of the present invention. 8 is a circuit diagram of another decoder circuit for decoding SSDS encoded media signals according to another non-exclusive embodiment of the present invention. 9 is a timing diagram illustrating the operation of the decoder circuit of FIG. 8 according to a non-exclusive embodiment of the present invention. FIG. 10 illustrates storage banks and control logic used in the decoder circuit of FIG. 8 according to a non-exclusive embodiment of the present invention. In the drawings, the same reference numerals are sometimes used to refer to the same structural elements. It should also be understood that the descriptions in the figures are diagrammatic and not to scale.

28:展頻視訊傳輸(SSVT)發射器(TX) 28: Spread Video Transmission (SSVT) Transmitter (TX)

40:分配器、分配器-編碼器 40: Distributor, distributor-encoder

42:編碼器 42: Encoder

50:組裝組 50: Assembly group

52:分級組 52: Grading Group

54:呈現組 54: Presentation Group

56:訊框控制器 56: Frame Controller

60:編碼器塊 60: Encoder block

62:類比數位轉換器(DAC) 62: Analog-to-Digital Converter (DAC)

65:定序器電路 65: Sequencer circuit

Claims (72)

一種用於將一差分電位準訊號解調為多個樣本的方法,該方法包括: (a)接收該差分電位準訊號; (b)將該差分電位準訊號提供至多個解碼器電路; (c)分別向該多個解碼器電路提供多個展頻直接序列(SSDS)碼片,該多個SSDS碼片中的每一個具有一第一狀態或一第二狀態; (d)對於該多個解碼器電路中的每一個,取決於提供至該多個解碼器電路中的每一個的該SSDS碼片分別是否具有該第一狀態或者該第二狀態,條件性地反轉或不反轉該差分電位準訊號; (e)對於該多個解碼器電路中的每一個,在一第一儲存位置和一第二儲存位置處儲存該反轉或不反轉該差分電位準訊號;以及 (f)產生包括該多個樣本的一視訊向量,該多個樣本分別是從儲存在該多個解碼器電路中的每一個的該第一儲存位置和該第二儲存位置處的經反轉或未經反轉的差分電位準訊號得出的。 A method for demodulating a differential potential quasi-signal into a plurality of samples, the method comprising: (a) receiving the differential potential quasi-signal; (b) providing the differential potential quasi-signal to a plurality of decoder circuits; (c) respectively providing a plurality of spread spectrum direct sequence (SSDS) chips to the plurality of decoder circuits, each of the plurality of SSDS chips having a first state or a second state; (d) for each of the plurality of decoder circuits, conditionally depending on whether the SSDS chip provided to each of the plurality of decoder circuits has the first state or the second state, respectively Invert or not invert the differential potential quasi-signal; (e) for each of the plurality of decoder circuits, storing the inversion or non-inversion of the differential potential quasi-signal at a first storage location and a second storage location; and (f) generating a video vector comprising the plurality of samples respectively inverted from the first storage location and the second storage location stored in each of the plurality of decoder circuits Or derived from the differential potential quasi-signal without inversion. 如請求項1所述的方法,其中,條件性地反轉或不反轉是由該多個解碼器電路中的一選擇解碼器電路執行的,並且 進一步包括如果提供至該選擇解碼器電路的該SSDS碼片具有該第一狀態,則將該差分電位準訊號乘以(+1),或者如果該SSDS碼片具有該第二狀態,則將該差分電位準訊號乘以(-1)。 The method of claim 1, wherein conditionally inverting or not inverting is performed by a selected decoder circuit of the plurality of decoder circuits, and Further comprising multiplying the differential potential quasi-signal by (+1) if the SSDS chip provided to the select decoder circuit has the first state, or if the SSDS chip has the second state, The differential potential quasi-signal is multiplied by (-1). 如請求項1或請求項2所述的方法,其中取決於提供至該多個解碼器電路中的每一個解碼器電路的該多個SSDS碼片中的每一個SSDS碼片分別是否具有該第一狀態或具有該第二狀態,該多個解碼器電路中的每一個解碼器電路藉由乘以(+1)或(-1)而條件性地反轉或不反轉該差分電位準訊號。The method of claim 1 or claim 2, wherein it depends on whether each of the plurality of SSDS chips provided to each of the plurality of decoder circuits respectively has the first A state or having the second state in which each of the plurality of decoder circuits conditionally inverts or does not invert the differential potential quasi-signal by multiplying by (+1) or (-1) . 如請求項1至請求項3中任一項所述的方法,進一步包括對於該多個解碼器電路中的每一個,在第一時鐘訊號的有效狀態期間操作一切換網路,該切換網路負責將該差分電位準訊號切換至該第一儲存位置和該第二儲存位置,其中該切換網路取決於提供至該多個解碼器電路中的每一個解碼器電路的該SSDS碼片分別是否具有第一狀態或該第二狀態而選擇性地反轉或不反轉該差分電位準訊號至該第一儲存位置和第二儲存位置。The method of any one of claim 1 to claim 3, further comprising, for each of the plurality of decoder circuits, operating a switching network during the active state of the first clock signal, the switching network is responsible for switching the differential potential level signal to the first storage position and the second storage position, wherein the switching network depends on whether the SSDS chips provided to each of the plurality of decoder circuits respectively are Having the first state or the second state and selectively inverting or not inverting the differential potential quasi-signal to the first storage position and the second storage position. 如請求項4所述的方法,進一步包括在第二時鐘訊號的有效狀態期間提供該多個樣本。The method of claim 4, further comprising providing the plurality of samples during an active state of the second clock signal. 如請求項1至請求項5中任一項所述的方法,進一步包括在提供至該多個解碼器電路之前對所接收的差分電位準訊號進行取樣及保持。The method of any one of claim 1 to claim 5, further comprising sampling and holding the received differential potential quasi-signals before providing to the plurality of decoder circuits. 如請求項1至請求項6中任一項所述的方法,進一步包括將模擬域中的該多個樣本轉換至數位域中。The method of any one of claims 1 to 6, further comprising converting the plurality of samples in the analog domain to the digital domain. 如請求項1至請求項7中任一項所述的方法,其中該視訊向量的該多個樣本分別包含用於一或更多像素的一組或多組樣本的顏色資訊。The method of any one of claim 1 to claim 7, wherein the plurality of samples of the video vector each include color information for one or more sets of samples for one or more pixels. 如請求項8所述的方法,進一步包括將該視訊向量拆分為該一或更多樣本。The method of claim 8, further comprising splitting the video vector into the one or more samples. 如請求項9所述的方法,進一步包括使用曾用於創建該視訊向量的相同排列來拆分該視訊向量。The method of claim 9, further comprising splitting the video vector using the same arrangement that was used to create the video vector. 一種用於對已經使用展頻直接序列(SSDS)編碼進行編碼的一差分電位準訊號進行解碼的一解碼器,該解碼器包括: 多個解碼器軌道電路,用於產生多個差分樣本輸出,該解碼器軌道電路中的每一個包括: (a)一第一終端和一第二終端,被配置為接收該差分電位準訊號的一第一值和一第二值,以及一第三終端,被配置為接收具有一第一狀態或一第二狀態的一SSDS碼片; (b)一乘法器電路,被配置為藉由取決於SSDS碼片的狀態而條件性地反轉或不反轉該第一值和該第二值來解調該差分電位準訊號的該第一值和該第二值;以及 (c)一第一存放裝置和一第二存放裝置,被配置為儲存經一解調的第一值和第二值; (d)輸出端,用於提供儲存在該第一存放裝置和該第二存放裝置上的該經解調的第一值和第二值, 其中,該多個差分樣本輸出是分別從在多個編碼器軌道電路的輸出端處提供的該經解調的第一值和第二值匯出的。 A decoder for decoding a differential potential quasi-signal that has been encoded using Spread Spectrum Direct Sequence (SSDS) encoding, the decoder comprising: a plurality of decoder track circuits for generating a plurality of differential sample outputs, each of the decoder track circuits comprising: (a) a first terminal and a second terminal configured to receive a first value and a second value of the differential potential quasi-signal, and a third terminal configured to receive a first state or a an SSDS chip in the second state; (b) a multiplier circuit configured to demodulate the first value of the differential potential level signal by conditionally inverting or not inverting the first value and the second value depending on the state of the SSDS chip; a value and the second value; and (c) a first storage device and a second storage device configured to store a demodulated first value and a second value; (d) an output for providing the demodulated first and second values stored on the first storage means and the second storage means, wherein the plurality of differential sample outputs are derived from the demodulated first and second values provided at outputs of the plurality of encoder track circuits, respectively. 如請求項11所述的解碼器,其中,該乘法器電路被配置為如果該SSDS碼片分別是該第一狀態或該第二狀態,則藉由乘以(+1)或(-1)對該差分電位準訊號的該第一值和該第二值進行解調。The decoder of claim 11, wherein the multiplier circuit is configured to multiply by (+1) or (-1) if the SSDS chip is in the first state or the second state, respectively demodulating the first value and the second value of the differential potential quasi-signal. 如請求項11或請求項12所述的解碼器,其中該乘法器電路包括一第一組開關和一第二組開關,其中該第一組開關和該第二組開關是互補的,使得在該第二組開關打開時該第一組開關閉合,反之亦然。The decoder of claim 11 or claim 12, wherein the multiplier circuit includes a first set of switches and a second set of switches, wherein the first set of switches and the second set of switches are complementary such that at The first set of switches is closed when the second set of switches is open, and vice versa. 如請求項13所述的解碼器,其中該第一組開關和該第二組開關耦接在該第一終端和第二終端與該第一存放裝置和該第二存放裝置之間。The decoder of claim 13, wherein the first set of switches and the second set of switches are coupled between the first and second terminals and the first and second storage devices. 如請求項13或請求項14所述的解碼器,其中當該SSDS碼片具有該第一狀態並且該乘法器電路乘以(+1)時,在該第二組開關打開時該第一組開關閉合,以及當SSDS碼片具有該第二狀態並且該乘法器電路乘以(-1)時,在該第一組開關打開時該第二組開關閉合。The decoder of claim 13 or claim 14, wherein when the SSDS chip has the first state and the multiplier circuit is multiplied by (+1), the first set of switches is open when the second set of switches is open The switches are closed, and when the SSDS chip has the second state and the multiplier circuit is multiplied by (-1), the second set of switches is closed while the first set of switches is open. 如請求項11至請求項15中任一項所述的解碼器,其中該第一存放裝置和第二存放裝置是分別位於該乘法器電路的第一電源軌線和第二電源軌線上的第一電容器和第二電容器。The decoder of any one of claim 11 to claim 15, wherein the first storage means and the second storage means are first and second storage devices located on first and second power supply rails, respectively, of the multiplier circuit. a capacitor and a second capacitor. 如請求項11至請求項16中任一項所述的解碼器,其中,該解碼器軌道電路中的每一個包括選擇性地耦接在該輸出端子與該第一存放裝置和第二存放裝置之間的運算放大器。The decoder of any one of claim 11 to claim 16, wherein each of the decoder track circuits includes the first and second storage devices selectively coupled between the output terminal and the first and second storage devices between operational amplifiers. 如請求項11至請求項17中任一項所述的解碼器,其中該乘法器被佈置為在第一時鐘訊號的第一有效狀態期間執行該解調,並且該輸出端子被佈置為在第二時鐘訊號的第二有效狀態期間提供經解調的該第一值和該第二值。A decoder as claimed in any one of claim 11 to claim 17, wherein the multiplier is arranged to perform the demodulation during a first active state of the first clock signal, and the output terminal is arranged to The demodulated first value and the second value are provided during the second active state of the two clock signals. 如請求項11至請求項18中任一項所述的解碼器,進一步包括取樣及保持電路,被配置為對該差分電位準訊號進行取樣及保持。The decoder of any one of claim 11 to claim 18, further comprising a sample and hold circuit configured to sample and hold the differential potential quasi-signal. 如請求項11至請求項19中任一項所述的解碼器,其中,該多個差分訊號輸出被從類比域轉換至數位域中。The decoder of any one of claims 11 to 19, wherein the plurality of differential signal outputs are converted from the analog domain to the digital domain. 如請求項11至請求項20中任一項所述的解碼器,其中該多個差分訊號輸出表示包含用於一或更多樣本的顏色資訊的一視訊向量。The decoder of any one of claims 11 to 20, wherein the plurality of differential signal outputs represent a video vector including color information for one or more samples. 如請求項11至請求項21中任一項所述的解碼器,進一步包括用於將該視訊向量拆分為該一或更多樣本的一拆分組,該拆分組使用與曾用於創建該視訊向量相同的排列。The decoder of any one of claim 11 to claim 21, further comprising a split group for splitting the video vector into the one or more samples, the split group using and having been used for Create the same permutation of the video vector. 一種方法,包括: (a)經由一傳輸媒體(L)接收已使用展頻直接序列(SSDS)編碼進行編碼的視訊媒體的差分訊號對; (b)將(L)個碼片值分別應用於所接收的(L)個差分訊號對; (c)取決於分別應用於該(L)個差分訊號對中的每一個的該L個碼片值的狀態,將該(L)個差分訊號對與(+1)或(-1)相乘; (d)將相乘後的該(L)個差分訊號對儲存在一第一電容器組中,該第一電容器組具有第一組(L)個電容器和第二組(L)個電容器,每一個分別用於儲存與由該(L)個差分訊號對的該相乘產生的乘積相稱的一電荷;以及 (e)藉由以下方式產生一經解碼的差分視訊媒體樣本: (i)分別產生在該第一組電容器和該第二組電容器上累積的該電荷的一平均值;以及 (ii)從一差分放大器產生該經解碼的差分視訊媒體樣本,該差分放大器與該第一電容器組相關聯並且被佈置為接收分別在該第一組電容器和該第二組電容器上累積的該電荷的該平均值。 A method that includes: (a) receiving differential signal pairs of video media encoded using Spread Spectrum Direct Sequence (SSDS) coding over a transmission medium (L); (b) applying the (L) chip values to the received (L) differential signal pairs, respectively; (c) phase the (L) differential signal pairs with (+1) or (-1) depending on the state of the L chip values respectively applied to each of the (L) differential signal pairs; take; (d) storing the multiplied (L) differential signal pairs in a first capacitor bank, the first capacitor bank having a first (L) capacitor and a second (L) capacitor, each one each for storing a charge commensurate with the product resulting from the multiplication of the (L) differential signal pairs; and (e) generating a decoded differential video media sample by: (i) generating an average value of the charge accumulated on the first set of capacitors and the second set of capacitors, respectively; and (ii) generating the decoded differential video media samples from a differential amplifier associated with the first capacitor bank and arranged to receive the accumulated capacitors of the first and second set of capacitors, respectively the average value of the charge. 如請求項23所述的方法,進一步包括藉由重複(a)到(e),包括(i)和(ii),為分別經由該傳輸媒體順序接收的視訊媒體的多組(L)個差分訊號對產生經解碼的差分視訊媒體樣本的序列。The method of claim 23, further comprising, by repeating (a) through (e), including (i) and (ii), for a plurality of (L) differentials of video media sequentially received via the transmission medium, respectively The signal pair produces a sequence of decoded differential video media samples. 如請求項23或請求項24所述的方法,進一步包括交替地將由第一組(L)個差分訊號對和第二組(L)個差分訊號對的該相乘產生的該乘積分別儲存在該第一電容器組和第二電容器組中。The method of claim 23 or claim 24, further comprising alternately storing the product resulting from the multiplication of the first set (L) of differential signal pairs and the second set (L) of differential signal pairs, respectively in in the first capacitor bank and the second capacitor bank. 如請求項23至請求項25中任一項所述的方法,進一步包括順序地執行(e)以藉由在由該第一電容器組和第二電容器組保持的該累積的電荷的該平均值之間進行交替來產生經解碼的差分視訊媒體樣本的序列。The method of any one of claim 23 to claim 25, further comprising sequentially performing (e) to determine the average value of the accumulated charges held by the first capacitor bank and the second capacitor bank Alternate between to generate a sequence of decoded differential video media samples. 如請求項23至請求項26中任一項所述的方法,進一步包括藉由對與該第一電容器組相關聯的和與第二電容器組相關聯的第二放大器的輸出進行時間複用來產生經解碼的差分視訊媒體樣本的序列。The method of any one of claims 23 to 26, further comprising by time multiplexing outputs of a second amplifier associated with the first capacitor bank and associated with the second capacitor bank A sequence of decoded differential video media samples is generated. 如請求項23至請求項27中任一項所述的方法,其中,當視訊媒體的該(L)個差分訊號對分別經由該傳輸媒體被順序接收時,順序地執行(b)、(c)、(d)和(e)。The method according to any one of claim 23 to claim 27, wherein when the (L) differential signal pairs of the video media are respectively received sequentially via the transmission medium, (b) and (c) are sequentially performed ), (d) and (e). 如請求項23至請求項28中任一項所述的方法,其中(d)進一步包括將該相乘後的(L)個差分訊號對中的每一個順序地儲存在該第一電容器組的(L)個級中,該(L)個級中的每一個分別包括該第一組電容器中的一個和該第二組電容器中的一個。The method of any one of claim 23 to claim 28, wherein (d) further comprises sequentially storing each of the multiplied (L) differential signal pairs in a buffer of the first capacitor bank Of the (L) stages, each of the (L) stages includes one of the first set of capacitors and one of the second set of capacitors, respectively. 如請求項23至請求項29中任一項所述的方法,其中產生在該第一電容器組的該第一組電容器和該第二組電容器上累積的該電荷的該平均值進一步包括: 在該第一電容器組處接收一平均控制訊號;以及 回應於該平均控制訊號,將儲存在該第一組電容器上的第一電荷和儲存在該第二組電容器上的第二電荷轉儲到與該放大器的差分輸入耦接的第一電容器和第二電容器上。 The method of any one of claim 23 to claim 29, wherein generating the average of the charges accumulated on the first set of capacitors and the second set of capacitors of the first capacitor bank further comprises: receiving an average control signal at the first capacitor bank; and In response to the average control signal, the first charge stored on the first set of capacitors and the second charge stored on the second set of capacitors are dumped to the first capacitor and the second capacitor coupled to the differential input of the amplifier. on the second capacitor. 如請求項30所述的方法,進一步包括在轉儲該第一電荷和該第二電荷之前初始化該第一電容器和該第二電容器。The method of claim 30, further comprising initializing the first capacitor and the second capacitor prior to dumping the first charge and the second charge. 如請求項23至請求項25中任一項所述的方法,進一步包括向該第一電容器組提供一或更多控制訊號,該一或更多控制訊號致使該第一電容器組在執行(d)和(e)(i)之間進行交替。The method of any one of claim 23 to claim 25, further comprising providing one or more control signals to the first capacitor bank, the one or more control signals causing the first capacitor bank to perform (d ) and (e)(i). 一種解碼器,用於對已經使用展頻直接序列(SSDS)編碼進行編碼的視訊媒體進行解碼,該解碼器包括: 一碼片乘法器,被配置為將(L)個經SSDS編碼的視訊媒體訊號分別與(L)個SSDS碼片值相乘; 具有(L)個記憶元件的一儲存組,每個記憶元件被配置為儲存與由該(L)個經SSDS編碼的視訊媒體訊號中的一個分別與該(L)個SSDS碼片值中的一個相乘產生的一乘積相稱的訊號; 一平均元件,被配置為對儲存在該(L)個記憶元件上的訊號進行平均;以及 一輸出端,被配置為提供一經解碼的視訊媒體訊號輸出,該經解碼的視訊媒體訊號輸出是從儲存在該(L)個記憶元件上的該訊號的平均值得出的。 A decoder for decoding video media that has been encoded using Spread Spectrum Direct Sequence (SSDS) encoding, the decoder comprising: a chip multiplier configured to multiply the (L) SSDS encoded video media signals by the (L) SSDS chip values, respectively; A storage bank having (L) memory elements, each memory element configured to store one of the (L) SSDS encoded video media signals and one of the (L) SSDS chip values, respectively. A multiplication produces a signal commensurate with a product; an averaging element configured to average the signals stored on the (L) memory elements; and An output configured to provide a decoded video media signal output derived from an average of the signals stored on the (L) memory elements. 如請求項33所述的解碼器,進一步被配置為當該(L)個經SSDS編碼的視訊媒體訊號被該碼片乘法器順序接收時,在該(L)個記憶元件上順序儲存與由該(L)個經SSDS編碼的視訊媒體訊號和該(L)個SSDS碼片值相乘產生的該乘積相稱的該訊號。The decoder of claim 33, further configured to, when the (L) SSDs encoded video media signals are sequentially received by the chip multiplier, sequentially store on the (L) memory elements and store them by the (L) memory elements sequentially. The signal commensurate with the product resulting from multiplying the (L) SSDS encoded video media signals and the (L) SSDS chip values. 如請求項33或請求項34所述的解碼器,進一步包括一控制邏輯,被配置為控制: (a)當該(L)個經SSDS編碼的視訊媒體訊號被順序接收時,在該(L)個記憶元件中順序儲存與由該(L)個經SSDS編碼的視訊媒體訊號與該(L)個SSDS碼片值相乘產生的乘積相稱的訊號;以及 (b)在所有的該(L)個記憶元件已儲存與由(L)個經SSDS編碼的視訊媒體訊號分別與該(L)SSDS碼片值相乘產生的乘積相稱的訊號之後,啟動該平均元件以對儲存在該(L)個記憶元件上的該訊號進行平均。 The decoder of claim 33 or claim 34, further comprising a control logic configured to control: (a) When the (L) SSDs-encoded video media signals are sequentially received, sequentially store in the (L) memory elements and the (L) SSDs-encoded video media signals and the (L) ) of the SSDS chip values resulting in a signal commensurate with the product; and (b) after all of the (L) memory elements have stored signals commensurate with the product of multiplying the (L) SSDS-encoded video media signals by the (L) SSDS chip values, respectively, activate the averaging element to average the signal stored on the (L) memory elements. 如請求項35所述的解碼器,其中,該控制邏輯進一步被配置為針對分別由該碼片乘法器順序接收的多組該(L)個經SSDS編碼的視訊媒體訊號重複(a)和(b)多次。The decoder of claim 35, wherein the control logic is further configured to repeat (a) and ( b) multiple times. 如請求項33至請求項36中任一項所述的解碼器,進一步包括具有(L)個記憶元件的一第二儲存組。The decoder of any one of claim 33 to claim 36, further comprising a second storage bank having (L) memory elements. 如請求項37所述的解碼器,進一步其中,該控制邏輯進一步被配置為在該第一儲存組和該第二儲存組之間交替儲存該乘法的該乘積。The decoder of claim 37, further wherein the control logic is further configured to alternately store the product of the multiplication between the first storage bank and the second storage bank. 如請求項33至請求項38中任一項所述的解碼器,進一步包括一控制邏輯,該控制邏輯進一步被配置為交替: (a)分別針對多組該(L)個經SSDS編碼的視訊媒體訊號在該第一儲存組和該第二儲存組之間的該乘法的該乘積的儲存;以及 (b)當第二儲存組時,儲存在該第一儲存組的該(L)個記憶元件上的該訊號的該平均, 其中針對該兩個儲存組中的一個進行該平均,同時該兩個儲存組中的另一個進行儲存,反之亦然。 The decoder of any one of claim 33 to claim 38, further comprising a control logic further configured to alternate: (a) the storage of the product of the multiplication between the first storage group and the second storage group for the (L) SSDS encoded video media signals, respectively, for a plurality of groups; and (b) the average of the signals stored on the (L) memory elements of the first storage group when the second storage group, Wherein the averaging is performed for one of the two storage groups while the other of the two storage groups is performing storage, and vice versa. 如請求項33至請求項39中任一項所述的解碼器,進一步包括耦接到該輸出端的一放大器,用於提供該經解碼的視訊媒體訊號輸出。The decoder of any one of claim 33 to claim 39, further comprising an amplifier coupled to the output for providing the decoded video media signal output. 如請求項33至請求項40中任一項所述的解碼器,其中,該(L)個經SSDS編碼的視訊媒體訊號是差分訊號,以及 該乘法器被配置為對該差分的(L)個經SSDS編碼的視訊媒體訊號進行相乘; 該儲存組被配置為將與該差分的(L)個經SSDS編碼的視訊媒體訊號相乘的該乘積相稱的訊號分別儲存在一第一組記憶元件和一第二組記憶元件上; 該平均元件被配置為對分別儲存在該第一組記憶元件和該第二組記憶元件上的訊號進行平均;以及 該輸出端是差分輸出端,並且該經解碼的視訊媒體訊號輸出是差分的經解碼的視訊媒體訊號輸出。 The decoder of any one of claim 33 to claim 40, wherein the (L) SSDS encoded video media signals are differential signals, and The multiplier is configured to multiply the differential (L) SSDS encoded video media signals; The storage group is configured to store signals commensurate with the product of the multiplication of the differential (L) SSDS encoded video media signals on a first group of memory elements and a second group of memory elements, respectively; The averaging element is configured to average the signals stored on the first set of memory elements and the second set of memory elements, respectively; and The outputs are differential outputs, and the decoded video media signal output is a differential decoded video media signal output. 如請求項41所述的解碼器,進一步包括一差分放大器,該差分放大器被配置為接收儲存在該第一組記憶元件和該第二組記憶元件上的平均訊號,並在差分輸出端處提供該差分的經解碼的視訊媒體訊號輸出。The decoder of claim 41, further comprising a differential amplifier configured to receive the averaged signals stored on the first set of memory elements and the second set of memory elements and provide at differential outputs The differential decoded video media signal is output. 一種用於藉由產生對儲存在佈置於第一組中的(L)個存放裝置上的訊號值進行平均而得出的平均訊號值,藉由對使用展頻直接序列(SSDS)編碼進行編碼的(L)個經編碼的視訊媒體訊號進行解碼來產生一樣本視訊訊號的裝置,該(L)個訊號值是從分別將該(L)個訊號與(L)個SSDS碼片值相乘而得出的。A method for generating an average signal value obtained by averaging signal values stored on (L) storage devices arranged in a first group, by encoding using Spread Spectrum Direct Sequence (SSDS) encoding A device for decoding (L) encoded video media signals to generate a sample video signal, the (L) signal values obtained from multiplying the (L) signals by the (L) SSDS chip values, respectively derived. 如請求項43所述的裝置,進一步包括一乘法器,該乘法器用於順序地接收該經編碼的(L)個經編碼的視訊媒體訊號,並順序地分別應用該(L)個經編碼的視訊媒體訊號和具有一第一狀態或一第二狀態的該(L)個SSDS碼片值並將它們相乘。The apparatus of claim 43, further comprising a multiplier for sequentially receiving the encoded (L) encoded video media signals and sequentially applying the (L) encoded video media signals, respectively The video media signal and the (L) SSDS chip values having a first state or a second state and multiplying them. 如請求項44所述的裝置,其中該乘法器進一步被配置為取決於應用於該(L)個訊號中的每一訊號的該(L)個SSDS碼片值分別是否具有該第一狀態或該第二狀態,將該(L)個經編碼的視訊媒體訊號中的每一個與(+1)值或(-1)值相乘。The apparatus of claim 44, wherein the multiplier is further configured to depend on whether the (L) SSDS chip values applied to each of the (L) signals respectively have the first state or The second state multiplies each of the (L) encoded video media signals by a (+1) value or a (-1) value. 如請求項43至請求項45中任一項所述的裝置,進一步包括一儲存組,該儲存組包括該(L)個存放裝置,該儲存組被配置為在分別接收該(L)個經編碼的視訊媒體訊號並將它們相乘時,將相乘後的該(L)個視訊媒體訊號順序地儲存在該(L)個存放裝置上。The apparatus of any one of claim 43 to claim 45, further comprising a storage group comprising the (L) storage devices, the storage group configured to receive the (L) via When the encoded video media signals are multiplied, the (L) multiplied video media signals are sequentially stored on the (L) storage devices. 如請求項43至請求項46中任一項所述的裝置,進一步包括一放大器,該放大器用於放大一平均訊號值並輸出該樣本視訊訊號。The apparatus of any one of claim 43 to claim 46, further comprising an amplifier for amplifying an average signal value and outputting the sample video signal. 如請求項43至請求項47中任一項所述的裝置,其中: 所接收到(L)個視訊媒體訊號是(L)個差分視訊媒體訊號; 儲存在該(L)個存放裝置上的該平均訊號值分別是儲存在(L)個差分存放裝置上的差分平均訊號值,以及 所產生的樣本視訊訊號是差分樣本視訊訊號。 The apparatus of any one of claim 43 to claim 47, wherein: The received (L) video media signals are (L) differential video media signals; the average signal values stored on the (L) storage devices are the differential average signal values stored on the (L) differential storage devices, respectively, and The generated sample video signal is a differential sample video signal. 如請求項44至請求項48中任一項所述的裝置,其中,該乘法器是能夠將(L)個差分的經編碼的視訊媒體訊號進行相乘的差分乘法器。The apparatus of any one of claim 44 to claim 48, wherein the multiplier is a differential multiplier capable of multiplying (L) differential encoded video media signals. 如請求項47至請求項49中任一項所述的裝置,其中,該放大器是能夠輸出差分樣本視訊訊號的差分放大器。The apparatus of any one of claim 47 to claim 49, wherein the amplifier is a differential amplifier capable of outputting differential sample video signals. 如請求項43至請求項50中任一項所述的裝置,進一步包括第二組(L)個存放裝置,並且該裝置進一步被配置為交替: (a)在該兩個儲存組中的一個中對該(L)個經編碼的媒體訊號的接收、相乘和儲存;以及 (b)藉由對儲存在該兩個儲存組中的另一個中的值進行平均而進行的該樣本視訊訊號的產生, 其中,該裝置進一步被配置為隨著時間在該兩個儲存組之間重複交替(a)和(b),使得該一個儲存組在執行(a),同時該第二儲存組在如(b)中所述的進行平均,反之亦然。 The apparatus of any one of claim 43 to claim 50, further comprising a second set (L) of storage apparatuses, and the apparatus is further configured to alternate: (a) the reception, multiplication and storage of the (L) encoded media signals in one of the two storage groups; and (b) the generation of the sample video signal by averaging the values stored in the other of the two storage groups, wherein the apparatus is further configured to repeatedly alternate (a) and (b) between the two storage groups over time such that the one storage group is performing (a) while the second storage group is performing as (b) ) and vice versa. 如請求項43至請求項51中任一項所述的裝置,進一步包括一多工器,該多工器被配置為對與該第一組存放裝置相關聯的第一放大器和與第二組存放裝置相關聯的第二放大器的輸出進行多工。The apparatus of any one of claim 43 to claim 51, further comprising a multiplexer configured to pair the first amplifier associated with the first set of storage devices with the second set of storage devices The output of the second amplifier associated with the storage device is multiplexed. 一種用於將展頻直接序列(SSDS)編碼應用於視訊資料的方法,該方法包括: (a)建構包括一第一電壓值和一第二電壓值的N個樣本的一視訊向量,該N個樣本是分別從表示多個像素的多組樣本得出的; (b)分別使用N個SSDS碼片調製用於該視訊向量的該N個樣本的該第一電壓值和第二電壓值中的每一個,該調製中的每一個涉及分別取決於該N個SSDS碼片的狀態而條件性地反轉或不反轉該N個樣本的該第一電壓值和第二電壓值;以及 (c)從條件性地被反轉或不被反轉的該N個樣本的該經調製的第一電壓值和第二電壓值的累加,產生一差分電位準輸出訊號。 A method for applying Spread Spectrum Direct Sequence (SSDS) encoding to video material, the method comprising: (a) constructing a video vector comprising N samples of a first voltage value and a second voltage value, the N samples being respectively derived from sets of samples representing a plurality of pixels; (b) modulating each of the first voltage value and the second voltage value for the N samples of the video vector using N SSDS chips, respectively, each of the modulation involving depending on the N The state of the SSDS chip to conditionally invert or not invert the first voltage value and the second voltage value of the N samples; and (c) generating a differential potential quasi output signal from the accumulation of the modulated first and second voltage values of the N samples that are conditionally inverted or not. 如請求項53所述的方法,進一步包括反覆運算(a)到(c),每個反覆運算使用表示另一個視訊向量的第一電壓值和第二電壓值的另一組N個樣本。The method of claim 53, further comprising iterating over (a) through (c), each iterating using another set of N samples representing the first and second voltage values of another video vector. 如請求項53或請求項54所述的方法,其中,該多組樣本中的每一個分別包括用於該多個像素的一顏色資訊。The method of claim 53 or claim 54, wherein each of the plurality of sets of samples respectively includes a color information for the plurality of pixels. 如請求項53至請求項55中任一項所述的方法,其中,該顏色資訊包括以下中的一或更多: (a)紅色(R)值; (b)藍色(B)值; (c)綠色(G)值; (d)亮度值(Y); (e)色度(C)值; (f)藍差色度(Cb)值; (g)紅差色度(C r)值;或者 (h)(a)至(g)的任何組合。 The method of any one of claim 53 to claim 55, wherein the color information includes one or more of the following: (a) red (R) value; (b) blue (B) value; (c) green (G) value; (d) luminance value (Y); (e) chromaticity (C) value; (f) blue-difference chromaticity (Cb) value; (g) red-difference chromaticity (C r ) value; or (h) any combination of (a) to (g). 如請求項53至請求項56中任一項所述的方法,其中調製進一步包括,如果用於該該N個樣本中的每一樣本的相應SSDS碼片分別具有第一狀態或第二狀態,則將用於該N個樣本的該第一電壓值和該第二電壓值與(+1)或(-1)相乘。The method of any one of claim 53 to claim 56, wherein modulating further comprises, if the corresponding SSDS chip for each of the N samples has a first state or a second state, respectively, The first voltage value and the second voltage value for the N samples are then multiplied by (+1) or (-1). 如請求項57所述的方法,進一步包括對於該N個樣本中的每一個,將該N個樣本的相乘後的第一電壓值和第二電壓值分別儲存在第一N個存放裝置和第二N個存放裝置上。The method of claim 57, further comprising, for each of the N samples, storing the multiplied first voltage value and the second voltage value of the N samples in the first N storage means and the second voltage value, respectively. on the second N storage devices. 如請求項53至請求項58中任一項所述的方法,進一步包括從分別儲存在該第一N個存放裝置和該第二N個存放裝置上的該N個樣本的該經調製的第一電壓值和第二電壓值的累加,產生該差分電位準輸出訊號。The method of any one of claim 53 to claim 58, further comprising from the modulated first N samples of the N samples stored on the first N storage devices and the second N storage devices, respectively The accumulation of a voltage value and a second voltage value generates the differential potential quasi output signal. 如請求項53至請求項59中任一項所述的方法,其中,該差分電位準輸出訊號是電磁訊號。The method of any one of claim 53 to claim 59, wherein the differential potential quasi output signal is an electromagnetic signal. 如請求項53至請求項60中任一項所述的方法,進一步包括經由一HDMI傳輸介質將該差分電位準輸出訊號傳輸到一視訊接收端。The method of any one of claim 53 to claim 60, further comprising transmitting the differential potential quasi output signal to a video receiver via an HDMI transmission medium. 一種用於將展頻直接序列(SSDS)編碼應用於視訊資料的編碼器,該編碼器包括: 多個乘法器電路,該乘法器電路中的至少一個包括並且被配置為: (a)接收包一括第一差分電壓值和一第二差分電壓值的一樣本; (b)藉由取決於SSDS碼片的狀態而條件性地反轉或不反轉該第一差分電壓值和第二差分電壓值,對該樣本的該第一差分電壓值和第二差分電壓值進行調製;以及 (c)將該樣本的經調製的第一差分電壓值和第二差分電壓值儲存在第一存放裝置和第二存放裝置上;以及 一累加器,被配置為從分別儲存在該多個乘法器電路的多個第一存放裝置和第二存放裝置上的多個電壓值的累加,產生一對差分電位準輸出訊號, 該多個電壓值是分別由該多個乘法器電路接收的多個樣本的調製得出的。 An encoder for applying Spread Spectrum Direct Sequence (SSDS) encoding to video material, the encoder comprising: a plurality of multiplier circuits, at least one of the multiplier circuits including and configured to: (a) receiving a sample including a first differential voltage value and a second differential voltage value; (b) the first and second differential voltage values for the sample by conditionally inverting or not inverting the first and second differential voltage values depending on the state of the SSDS chip value is modulated; and (c) storing the modulated first and second differential voltage values of the sample on the first and second storage means; and an accumulator configured to generate a pair of differential potential quasi output signals from the accumulation of a plurality of voltage values respectively stored on a plurality of first storage devices and a second storage device of the plurality of multiplier circuits, The plurality of voltage values are derived from modulation of the plurality of samples received by the plurality of multiplier circuits, respectively. 如請求項62所述的編碼器,其中該至少一個乘法器電路進一步包括一第一輸入端子和一第二輸入端子,該第一輸入端子和第二輸入端子被配置為分別接收該樣本的該第一差分電壓值和第二差分電壓值。The encoder of claim 62, wherein the at least one multiplier circuit further comprises a first input terminal and a second input terminal, the first input terminal and the second input terminal being configured to receive the sample of the sample, respectively A first differential voltage value and a second differential voltage value. 如請求項53或請求項63所述的編碼器,其中該至少一個乘法器電路進一步包括一開關網路,該開關網路被配置為如下條件性地儲存該樣本的該第一差分電壓值和該第二差分電壓值: (a)如果該SSDS碼片具有一第一狀態,將該樣本的該第一差分電壓值和該第二差分電壓值分別儲存在該第一存放裝置和第二存放裝置上;或者 (b)如果該SSDS碼片具有一第二狀態,將該樣本的該第一差分電壓值和該第二差分電壓值分別儲存在該第二存放裝置和第一存放裝置上。 The encoder of claim 53 or claim 63, wherein the at least one multiplier circuit further comprises a switch network configured to conditionally store the first differential voltage value of the sample and The second differential voltage value: (a) if the SSDS chip has a first state, storing the first differential voltage value and the second differential voltage value of the sample on the first storage device and the second storage device, respectively; or (b) If the SSDS chip has a second state, store the first differential voltage value and the second differential voltage value of the sample on the second storage device and the first storage device, respectively. 如請求項64所述的編碼器,其中,該開關網路包括: 一第一組開關,其選擇性地將一第一輸入端子和一第二輸入端子分別連接到該第一存放裝置和一第二存放裝置;以及 一第二組開關,其選擇性地將該第一輸入端子和該第二輸入端子分別連接到該第二存放裝置和該第一存放裝置。 The encoder of claim 64, wherein the switch network comprises: a first set of switches selectively connecting a first input terminal and a second input terminal to the first storage device and a second storage device, respectively; and A second set of switches selectively connects the first input terminal and the second input terminal to the second storage device and the first storage device, respectively. 如請求項65所述的編碼器,其中,該第一組開關和該第二組開關彼此互補,使得當該第一組開關閉合時,該第二組開關打開,反之亦然。The encoder of claim 65, wherein the first set of switches and the second set of switches are complementary to each other such that when the first set of switches is closed, the second set of switches is open and vice versa. 如請求項66所述的編碼器,其中,該SSDS碼片的狀態確定該第一組開關和該第二組開關分別何時打開或閉合。The encoder of claim 66, wherein the state of the SSDS chip determines when the first set of switches and the second set of switches are opened or closed, respectively. 如請求項62至請求項67中任一項所述的編碼器,其中該第一存放裝置和第二存放裝置分別是在該至少一個乘法器電路的第一電源軌線和第二電源軌線上的第一電容器和第二電容器。The encoder of any one of claim 62 to claim 67, wherein the first storage means and the second storage means are on a first power supply rail and a second power supply rail, respectively, of the at least one multiplier circuit the first capacitor and the second capacitor. 如請求項62至請求項68中任一項所述的編碼器,其中,該累加器包括一或更多運算放大器,該一或更多運算放大器被配置為分別接收儲存在與該多個乘法器電路相關聯的多個第一存放裝置和第二存放裝置上的電壓值。The encoder of any one of claim 62 to claim 68, wherein the accumulator includes one or more operational amplifiers configured to receive stored in multiplication with the plurality of operational amplifiers, respectively voltage values on a plurality of first storage devices and second storage devices associated with the circuit. 如請求項62至請求項69中任一項所述的編碼器,進一步被配置為使得該多個乘法器電路中的每一個在第一時鐘訊號的第一有效狀態期間執行該調製,並且該累加器在第二時鐘訊號的第二有效狀態期間執行該累加。The encoder of any one of claim 62 to claim 69, further configured such that each of the plurality of multiplier circuits performs the modulation during a first active state of the first clock signal, and the The accumulator performs the accumulation during the second active state of the second clock signal. 如請求項62至請求項70中任一項所述的編碼器,其中該多個樣本限定包含用於一或更多樣本的顏色資訊的視訊向量。The encoder of any one of claim 62 to claim 70, wherein the plurality of samples define a video vector that includes color information for one or more samples. 如請求項71所述的編碼器,其中用於該一或更多樣本的顏色資訊包括以下之一: (a)紅色(R)值; (b)藍色(B)值; (c)綠色(G)值; (d)亮度值(Y); (e)色度(C)值; (f)藍差色度(Cb)值; (g)紅差色度(C r)值;或者 The encoder of claim 71, wherein the color information for the one or more samples includes one of: (a) red (R) value; (b) blue (B) value; (c) green (G) value; (d) luminance value (Y); (e) chromaticity (C) value; (f) blue-difference chromaticity (Cb) value; (g) red-difference chromaticity (C r ) value; or
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