TW202226609A - Beam-shaping secondary optical components for micro light emitting diodes - Google Patents

Abstract

The invention is directed towards employing semiconductor-based waveguides as secondary optical components that reduce the beam divergence of light generated by LEDs. A lighting source includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes an LED. The second semiconductor die is bonded to the first semiconductor device and includes a crystalline waveguide having a first waveguide surface, a second waveguide surface, and a waveguide body. The first waveguide surface receives light from the LED. The waveguide body is comprised of a crystalline material that transmits the received light from the first waveguide surface to the second waveguide surface. The second waveguide surface emits the received portion of the light with a second beam divergence that is significantly less than the first beam divergence.

Description

Beam-Shaping Secondary Optical Assemblies for Micro-Light Emitting Diodes

The present invention relates to beam shaping secondary optical assemblies for micro light emitting diodes. <Cross-reference to related applications>

This application claims US Provisional Application No. 63, filed on December 21, 2020, and entitled "BEAM-SHAPING SECONDARY OPTICAL COMPONENTS FOR MICRO LIGHT EMITTING DIODES" /128,582 and the benefit of US Non-Provisional Application No. 17/154,762, filed January 21, 2021, the entire contents of which are incorporated herein by reference.

Light emitting diodes (LEDs) convert electrical energy into light energy and offer many benefits over other light sources, such as reduced size, improved durability, and increased efficiency. LEDs can be used as light sources in many display systems, such as televisions, computer monitors, laptops, tablets, smartphones, projection systems, and wearable electronic devices. Development of micro-LEDs (micro-LEDs; "μLEDs") based on III-nitride semiconductors (such as alloys of AlN, GaN, InN, AlGaInP, other quaternary phosphorous compositions, and the like) has begun for various displays applications, due to its small size (eg, having linear dimensions of less than 100 μm, less than 50 μm, less than 10 μm, or less than 5 μm), high packing density (and thus higher resolution), and high brightness. For example, micro-LEDs that emit light of different colors (eg, red, green, and blue) can be used to form sub-pixels in display systems such as televisions or near-eye display systems.

The present invention generally relates to micro light emitting diodes (micro LEDs). More specifically, the present invention relates to the fabrication and use of crystalline waveguides as secondary optics for microLEDs to collimate and/or reduce the beam divergence of the light emitted by the LEDs. Waveguides and LEDs can be used in combination for the light source. According to some embodiments, the light source may include a first semiconductor die and a second semiconductor die. The first semiconductor die may include a first light emitting device (LED). The first LED may include a first light emitting surface (LES) that emits light (generated within the first LED) out of the first LED with a first beam divergence. The second semiconductor die can be bonded to the first semiconductor device and can include the first crystalline waveguide. The first waveguide may include a first waveguide surface, a second waveguide surface, and a waveguide body. The first waveguide surface can be configured to receive at least a portion of the light generated within the first LED from the first LES of the first LED. The second waveguide surface can be configured as a second LES. The waveguide body may comprise a transparent crystalline material that transmits light received by the first waveguide surface to the second waveguide surface. The first waveguide surface, the second waveguide surface, and the waveguide body can be configured such that the second waveguide surface emits the received portion of the light generated within the first LED out of the first waveguide with a second beam divergence. The second beam divergence may be significantly smaller than the first beam divergence.

In some embodiments, the light source is included in a wearable device that generates a virtual reality environment for a user wearing it. In other embodiments, the light source is included in a wearable device that generates an augmented reality environment for a user wearing it. The first LED can be a micro light emitting diode. The spatial dimension of the first LES of the first LED may be less than 10 microns. In some embodiments, the spatial dimension of each of the first waveguide surface and the second waveguide surface may be less than 5 microns. The first waveguide surface may be smaller than the second waveguide surface.

The transparent crystalline material may be gallium nitride (GaN) grown on a semiconductor substrate. Each spatial dimension of each defect in the optical resurfacing of the first waveguide may be less than 5 nanometers (nm). The first semiconductor die may include an LED array that includes the first LED. The second semiconductor die may include an array of waveguides that includes the first waveguide. There may be a one-to-one correspondence between each LED in the LED array and each waveguide in the waveguide array. The first LED may uniquely correspond to the first waveguide.

In some embodiments, the waveguide array can be formed on a continuous layer of transparent crystalline material. The waveguide body of each waveguide in the waveguide array may protrude from a continuous layer of transparent crystalline material. The proximal surface of each waveguide in the waveguide array may comprise a portion of a continuous layer of transparent crystalline material. The distal surface of each waveguide in the waveguide array can be displaced from a continuous layer of transparent crystalline material.

In other embodiments, the waveguide array can be formed on discrete layers of transparent crystalline material. The discontinuous layer of transparent crystalline material may comprise an array of separate dielectric layer portions formed through an etching process. There may be a one-to-one correspondence between each dielectric layer portion in the array of respective dielectric layer portions and each waveguide in the waveguide array.

The waveguide body may have a tapered shape characterized as a taper angle associated with the growth process of the transparent crystalline material on the semiconductor substrate. Due to the crystal growth process and/or the tapered shape, the first surface area of the first waveguide surface may be smaller than the second surface area of the second waveguide surface. The waveguide body may have a mesa shape formed at least in part by removing a portion of the transparent crystalline material from the second semiconductor die through an etching process.

The first waveguide may further include a reflective layer encapsulating a portion of the waveguide body. The waveguide body can be configured to reduce transmission losses associated with the waveguide body and to reduce the beam divergence of the received portion of the light generated within the first LED. The second semiconductor die may further include a first dielectric layer encapsulating at least a portion of the waveguide body. The first dielectric layer may cover the first waveguide surface. The second semiconductor die may further include a second dielectric layer and a transparent crystalline material layer. The second dielectric layer may cover the second waveguide surface. A layer of transparent crystalline material may be interposed between the first dielectric layer and the second dielectric layer.

The second semiconductor die may further include an opaque spacer structure. The spacer structure can be positioned around at least a portion of the perimeter of the second waveguide surface and extend beyond the plane of the second semiconductor die. The positioning of the spacer structure can define a columnar volume that extends beyond the plane of the second semiconductor die. The spacer structure can be configured to confine the transmission of light emitted by the second waveguide surface and exiting the second semiconductor die within a columnar volume extending beyond the plane of the second semiconductor die.

In some embodiments, the second waveguide surface can have a curved shape formed at least in part by removing a portion of the transparent crystalline material from the second semiconductor die through an etching process, such that the curved shape of the second waveguide surface is configured In order to reduce the beam divergence of the light emitted from the second waveguide surface and leaving the second semiconductor die.

In at least one embodiment, the shape of the second waveguide surface is a flat surface. The second semiconductor die may include a convex dielectric lens, eg, a convex lens including and/or fabricated from a dielectric material. In some embodiments, the dielectric material may include silicon dioxide or any other dielectric material that includes sufficient photorefractive properties. The second waveguide surface may be covered by a convex dielectric lens that receives a portion of the light generated within the first LED and emitted by the second waveguide surface with the second beam divergence. The convex dielectric lens may emit a received portion of light with a third beam divergence that is smaller than the second beam divergence. The light source may further include a transparent glass substrate bonded to the second semiconductor die and covering the second waveguide surface. The second semiconductor die may be inserted between the first semiconductor die and the glass substrate.

In some embodiments, a method of fabricating a light source can include growing an array of crystalline waveguides on a layer of crystalline material positioned on a first semiconductor wafer. A metallization layer can be deposited and/or formed over at least a portion of the crystalline material. The metallization layer can provide optical isolation of each waveguide in the array of crystalline waveguides from each of the other waveguides in the array of waveguides. The crystalline waveguide array is physically removable from the first semiconductor wafer. The waveguide array can be bonded to an array of light emitting devices (LEDs). There may be a one-to-one correspondence between each waveguide in the crystalline waveguide array and each LED in the LED array. Each waveguide in the array of crystalline waveguides can be configured to reduce the beam divergence of light emitted from the corresponding LED.

Another method for fabricating a light source includes growing an array of three-dimensional (3D) crystalline structures on a layer of crystalline material. A layer of crystalline material can be positioned on the first semiconductor wafer. Arrays of 3D crystalline structures can be used to make imprinting and/or embossing tools. The imprinting tool may have a shape complementary to the shape of the array of 3D crystalline structures. In some embodiments, the embossing tool is a soft embossing and/or embossing tool. In other embodiments, the embossing tool is a hard embossing and/or embossing tool. Imprinting tools can be used to form waveguide arrays. An array of waveguides can be bonded to an array of light emitting devices (LEDs) to form a light source. The waveguide array can be configured to reduce the beam divergence of light emitted from the LED array.

This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used alone to determine the scope of the claimed subject matter. This subject matter should be understood with reference to appropriate portions of the entire specification, any or all drawings, and each solution of the invention. The foregoing, along with other features and examples, are described in greater detail below in the following specification, scope of claims, and accompanying drawings.

The present invention generally relates to light emitting diodes (LEDs). More specifically and without limitation, disclosed herein are techniques for fabricating and using semiconductor-based optical waveguides as secondary optical components for light emitting diodes (LEDs) and/or micro LEDs (μLEDs).

成比例，其中θ為如自正交於LED之發光表面（LES）之向量量測的角度。由此等類朗伯LED發射之光束的角分佈（或光束發散度）可特徵界定為大約120°之半高全寬（full width at half maximum；FWHM），（亦即，

）。對於類朗伯光束發散度之實例，參見圖11A之角分佈1108。 Given its small size and mass, and its low power requirements, μLEDs are good candidates for light sources in various devices such as, but not limited to, mobile devices with pixel-based displays and those with head-mounted and/or near-eye Wearable device for display. However, the light generated by μLEDs may not be directly used as a light source for some applications and/or devices. At least because the angular distribution of the light produced by the μLEDs is relatively broad and/or dispersed, the light produced by the μLEDs may be too diffuse for direct use in devices that require light with a relatively small and/or well-defined beam spot and/or applied light source. That is, the light beams generated and emitted by the μLEDs may be relatively divergent and/or misaligned, making the divergent light beams unusable as light sources for displays in devices and/or applications. For example, a typical μLED can radiate a beam with a beam profile that approximates Lambert's cosine law. The angular distribution of the intensity of a Lambertian-like beam can be roughly equal to

is proportional, where θ is the angle as measured from a vector normal to the light emitting surface (LES) of the LED. The angular distribution (or beam divergence) of the beam emitted by such Lambertian-like LEDs can be characterized as a full width at half maximum (FWHM) of approximately 120°, (ie,

). For an example of Lambertian-like beam divergence, see angular distribution 1108 of Figure 11A.

The Lambertian distribution of light can be too diffuse for many applications, such as those using μLEDs as the light source for one or more pixels in a display. For example, some applications may require a substantial portion of the optical output of an LED (eg, 80% of beam intensity or power) to be within an emission cone with a relatively small opening and/or emission angle (eg, 20°). Accordingly, skilled artisans have considered using conventional beam shaping techniques to collimate the beam profile of the μLED (or reduce its beam divergence).

Such conventional beam shaping (eg, beam collimation) techniques for light produced by μLEDs include the use of lenses (eg, microlenses) as secondary optical components to reduce the divergence of the beam. However, conventional microlenses may not sufficiently reduce beam divergence. Thus, even after passing through conventional microlenses, a substantial portion of the light beam of the μLED can be distributed outside the desired emission cone relative to various applications using the μLED as a light source. Conventionally, microlenses are fabricated via imprinting and/or embossing processes (eg, nanoimprint lithography processes) performed on amorphous (or non-crystalline) materials (eg, fused silica). Conventional nanoimprint lithography may require the use of expensive "hard" embossing tools. In addition to the high cost of the tool, the surface finish of conventionally manufactured hard embossing tools may not be of sufficient quality to emboss microlenses of the size required to reduce the beam divergence of the μLED. Due to the small surface area of the light emitting surface of the μLED, the surface area of the microlenses required to collimate the beam can be on the order of a few square microns. It is difficult and expensive to reliably manufacture hard imprint tools with features on the order of a few microns in size. Adequately collimating the beam and/or reducing the beam divergence of this microlens may require any imperfections in the surface finish of the lens to be less than about 5 nm. Conventional methods of making hard tools may not be able to reliably produce such small feature sizes and/or sufficiently smooth surface finishes. If the feature size of the microlens is not small enough or if relatively large (eg, >5 nm) defects are present in the surface modification of the embossing tool, the microlens may not adequately reduce beam divergence. For many applications, microlenses fabricated via hard embossing tools or other conventional methods may not adequately reduce the beam divergence of the light emitted by the μLEDs.

Thus, and compared to conventional microlens-based approaches, various embodiments herein relate to the fabrication and use of semiconductor-based waveguides as secondary optical components to reduce the beam divergence of light produced by LEDs and μLEDs. For example, beam shaping secondary optics (eg, any of the waveguides discussed herein) can be used to shape the beam profile (eg, reduce beam divergence) of light produced by the μLED. Thus, beam shaping optics can be used to use μLEDs in applications that require well-collimated light and/or less diffuse optical intensity and/or power distribution.

More specifically, in various embodiments, non-known and novel semiconductor-based waveguide structures (eg, enhanced waveguides fabricated from crystalline semiconductor materials) are used as secondary optical components for μLEDs. Semiconductor-based waveguides are used to collimate and/or reduce the beam divergence of light generated by LEDs and/or μLEDs. Reducing the beam divergence can substantially increase the optical power density of the LED's beam to require highly collimated light and/or tightly controlled beam profiles (eg, beams with relatively small divergence and/or well-defined beam spots) LEDs are used in various applications. Various inventive embodiments are described herein pertaining to the fabrication and utilization of semiconductor-based waveguides as secondary optical components for LEDs. Various specific examples include devices, systems, methods, materials, embossing/embossing tools, and the like.

。 In some embodiments, the μLED can emit a beam characterized by a first beam divergence (see, eg, FIG. 11A , which shows a Lambertian-like beam with a FWHM of about 120°). When using an enhanced waveguide as a secondary optical component for an LED, the beam (after passing through the waveguide) can be characterized as a second beam divergence that is significantly smaller than the first beam divergence. For example, the second beam divergence may be such that about 80% of the beam power or intensity is confined within an emission cone of about 20°. Without the use of enhanced waveguides, only about 11% of the first beam divergence would be within this emission cone. For an example of reducing beam divergence via a waveguide as a secondary optical component, see angular profile 1160 of Figure 11C. The significant reduction in beam divergence is indicated by a visual comparison between the first beam divergence (eg, angular profile 1108 of FIG. 11A ) and the second beam divergence (eg, angular profile 1160 of FIG. 11C ). With an optical coupling efficiency (between the μLED and the waveguide) of about 70%, the use of a waveguide can result in a transmission gain that is at least 5 times greater than the transmission gain using a μLED without a waveguide. For example, as mentioned above, without the waveguide, about 11% of the light is confined within the 20° emission cone, while with the waveguide, the overall efficiency (at the desired emission cone within) is approximately

.

In various embodiments, the waveguide structures may be fabricated from semiconductor materials such as, but not limited to, gallium nitride (GaN). To fabricate the waveguide, layers of semiconductor material may be deposited on a semiconductor substrate (eg, a semiconductor wafer) formed from the respective semiconductor materials. The semiconductor material of the waveguide structure may be the material from which the crystalline structure is grown. Through crystal growth, a crystalline structure can grow on the deposited layer of semiconductor material. In crystalline form, the semiconductor material can be relatively transparent to the frequencies of light emitted by the μLED. Due to the optical properties of the crystalline material (eg, its index of refraction relative to the index of refraction outside the crystalline material), the crystalline structure can sufficiently confine and transmit the waveguide that is received and serves as the frequency characteristic of the μLED.

That is, due to the optical properties and shape of the waveguide, the sidewall surfaces of the waveguide (eg, those surfaces of the waveguide body that are generally aligned with the beam transmission direction) can provide significant internal reflection of light within the waveguide. Furthermore, due to the nature of growing crystalline structures on semiconductor substrates, the waveguide structures may include tapered shapes. At least due to the tapered shape (created due to the process of growing the crystalline structure), the waveguide structure can be used to reduce the beam divergence of the received light and increase the internal reflection of the waveguide sidewalls. Thus, the waveguide structure can act as a focusing and/or collimating waveguide that shapes the received beam. In addition, at least the exit surface of the waveguide (eg, the surface of the waveguide that emits light after passing through the body of the waveguide) can be shaped (eg, via an etching process) to include lenses that further increase the focusing and/or collimating power of the waveguide (or beam shaping) effect. For example, the exit surface of the waveguide can be etched and/or polished to a surface shaped like a spherical and/or convex lens.

In some embodiments, one or more μLEDs (eg, a 1D or 2D array of μLEDs) or an array of another such light emitting device can be fabricated on and/or bonded to the first semiconductor die. One or more waveguides (corresponding 1D or 2D arrays of waveguides) can be fabricated on the second semiconductor die. The first semiconductor die and the second semiconductor die may be bonded such that each μLED is aligned with a corresponding waveguide (eg, there is a one-to-one correspondence between the μLED and the waveguide of the respective semiconductor die). The LEDs in the LED array may include light emitting surfaces (LES) that emit at least a portion of the light generated within the active area of the LEDs. The light emitted by the LES of the LED may have a first beam divergence as measured by the angular distribution of the beam. For example, the first beam divergence may be Lambertian-like and characterized as having a FWHM of about 120°.

When bonding the first semiconductor die and the second semiconductor die, the dies can be aligned such that each LED in the LED array is aligned with its corresponding waveguide in the waveguide array. The waveguide may include a first waveguide surface, a second waveguide surface, and a waveguide body, and sidewalls of the body. The first waveguide surface can be closely aligned with the LES of the LED such that the first waveguide surface receives light emitted by the LES of the LED, eg, the light of the LED is incident on the first waveguide surface and into the volume of space defined by the waveguide body. In some embodiments, the first waveguide surface is generally a flat surface. The direction of light beam transmission may generally be normal to the plane of the first waveguide surface. Thus, the first waveguide surface can be configured as a light receiving surface that acts as an entrance (into the volume of space defined by the waveguide body) for the light of the LED or other light incident on the first waveguide surface. The volume of space defined by the waveguide body may be filled with crystalline material. The crystalline material (and thus the waveguide body) can transmit at least a substantial portion of the received light from the first waveguide surface to the second waveguide surface due to the significant internal reflection of the waveguide, eg there is little light absorption or light leakage from the waveguide body.

The second waveguide surface can be configured to emit light (eg, light transmitted from the first waveguide surface to the second waveguide surface through the waveguide body) out of the waveguide body and into the surrounding environment of the waveguide. That is, the second waveguide surface can be configured as the light exit surface and/or the light emitting surface of the waveguide. The shape of the waveguide body and/or the shape of the second waveguide surface can be used to significantly collimate the beam and/or significantly reduce the beam divergence. Furthermore, due to the optical transmission efficiency of the waveguide (eg, the optical transparency of the waveguide) and its significant optical internal reflection properties, the light beam experiences less optical power loss as the angular divergence of the light beam is reduced through it passing through the waveguide.

As mentioned above, the light beam can enter the waveguide with a first beam divergence via the first waveguide surface. The light beam can exit the waveguide via the second waveguide surface with a second beam divergence that is significantly smaller than the first beam divergence. For example, the first beam divergence may be characterized as a FWHM of about 120°. The second beam divergence may be characterized such that approximately 80% of the beam is contained within the emission cone having an opening angle of approximately 20°. Thus, the waveguide can act as a secondary optical component that collimates or at least significantly reduces the beam divergence of the light from the LED.

Some embodiments may be "high fill factor" embodiments, where the aspect ratio of the waveguide body is increased. The increased aspect ratio can improve the collimation and/or divergence reduction capabilities of the waveguide. Various embodiments may include "spacer" structures that optically isolate adjacent waveguides and still provide greater collimation and/or divergence reduction capabilities of the waveguides. Additionally and/or alternatively, yet other specific examples include dielectric "lens" structures that act as a secondary optical component of a waveguide (or a tertiary optical component of an LED). Such dielectric lens structures can provide even greater collimation and/or divergence reduction capabilities of the waveguide. Some specific examples include the use of crystalline waveguide growth processes to fabricate "soft" or "hard" imprinting or embossing tools in the form of waveguide arrays. Such imprinting tools can be used to fabricate similarly shaped waveguide structures in other materials. Accordingly, the waveguides discussed herein can be fabricated via other methods (eg, embossing or embossing) and/or other waveguide materials.

Using a waveguide as a secondary optical component to reduce the beam divergence of the light emitted by the LED has several advantages over the use of conventional microlenses for focusing the light from the LED. For many applications where conventional microlenses may not adequately reduce beam divergence, enhancing the beam shaping properties of the waveguide can significantly reduce beam divergence and enable use in the application. Thus, when used as secondary optical components for μLEDs, the waveguides discussed herein may enable the use of μLEDs in applications where microlenses may be deficient as beam collimators. That is, the divergence of the beam of the μLED after passing through the waveguide can be sufficiently small to be used in various applications where conventional methods based on microlenses cannot sufficiently reduce the beam divergence. Thus, the combination of μLEDs and enhanced waveguides can be used as a light source in many applications where a beam of relatively low beam divergence is required.

As mentioned above, manufacturing conventional microlenses may require the use of relatively expensive "hard" imprinting or embossing tools. In contrast to embossing-based fabrication, the waveguides discussed herein are formed through a semiconductor fabrication process. Such processes include, but are not limited to, growing the crystalline structure of the waveguide on the wafer; depositing oxide and/or metallization layers on portions of the wafer (eg, via a lithography process); and etching the wafer and/or the waveguides. surface (eg, via an etch process). Such semiconductor processes do not require expensive imprinting tools. As mentioned above, the surfaces of conventional imprinting tools may not be smooth enough to accurately and uniformly imprint microlenses with feature sizes on the order of a few microns. For example, defects on the imprint surface of the imprint tool may be larger than 5 nm, and for some applications, the resulting microlenses may not adequately collimate light. That is, surface defects in conventional imprinting tools can cause the microlenses to provide significant scattering and/or dispersion of the light beam to be collimated. Thus, the various waveguide embodiments discussed herein can provide significantly more collimation and/or beam divergence reduction than using microlenses.

Instead of using imprinting tools that are expensive and/or not sufficiently "smooth" (eg, free of surface defects greater than a feature size threshold), fabricating the waveguides discussed herein involves growing a crystalline structure comprising a crystalline host of the waveguide. The crystal growth process can result in crystal structures grown on a wafer (eg, a semiconductor substrate) that are extremely uniform (in shape and crystal structure) across the wafer. As mentioned above, the waveguide body may include a tapered shape (eg, a truncated pyramid and/or a mesa structure), where the tapered shape of the waveguide is extremely uniform across the wafer due to the crystal growth process. The precise shape and uniformity of the waveguides can result in precise and uniform optical properties, resulting in a significant and uniform reduction in beam divergence across wafer-fabricated waveguides. The use of a waveguide as an example of a secondary optical component can provide significantly more reduction in beam divergence, and can be significantly cheaper to manufacture, than using conventional microlenses to collimate the LED's beam.

The microLEDs and waveguides described herein can be used in conjunction with various technologies such as artificial reality systems. Artificial reality systems, such as head mounted display (HMD) or heads-up display (HUD) systems, typically include displays configured to present artificial images depicting objects in a virtual environment. Displays can present virtual objects or combine images of real objects with virtual objects, such as in virtual reality (VR), augmented reality (AR), or mixed reality (MR) applications . In AR systems, for example, a user can see through, for example, see-through transparent display glasses or lenses (often called optical see-through) or by viewing a displayed image of the surrounding environment captured by a camera (often called video see-through). View both the displayed image of the virtual object (eg, computer-generated image (CGI)) and the displayed image of the surrounding environment. In some AR systems, an LED-based display subsystem may be used to present artificial images to the user.

As used herein, the term "light emitting diode (LED)" refers to at least an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting region (ie, an active region) between the n-type semiconductor layer and the p-type semiconductor layer. ) of the light source. The light emitting region may include one or more semiconductor layers forming one or more heterostructures such as quantum wells. In some embodiments, the light emitting region may include multiple semiconductor layers forming one or more multiple-quantum-wells (MQWs), each of the one or more multiple-quantum wells including multiple (eg, about 2 to 6) quantum wells.

As used herein, the term "micro LED" or "μLED" refers to an LED having a chip with a linear dimension of less than about 200 μm, such as less than 100 μm, less than 50 μm, less than 20 μm, less than 10 μm or smaller. For example, the linear dimensions of microLEDs can be as small as 6 μm, 5 μm, 4 μm, 2 μm or less. Some microLEDs may have linear dimensions (eg, length or diameter) comparable to the minority carrier diffusion length. However, the disclosures herein are not limited to micro LEDs, and can also be applied to small and large LEDs.

As used herein, the term "bonding" may refer to various methods used to physically and/or electrically connect two or more devices and/or wafers, such as bonding, metal-to-metal bonding, metal-oxide bonding , wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding, soldering, under bump metallization, and the like. For example, bonding may use a curable adhesive (eg, epoxy) to physically bond two or more devices and/or wafers through adhesion. Metal-to-metal bonding may include, for example, wire bonding or flip-chip bonding between metals using solder interfaces (eg, pads or balls), conductive adhesives, or welded joints. Metal oxide bonding can form metal and oxide patterns on each surface, bond the oxide segments together, and then bond the metal segments together to create conductive paths. Wafer-to-wafer bonding can bond two wafers (eg, silicon wafers or other semiconductor wafers) without any intermediate layers and is based on chemical bonds between the surfaces of the two wafers. Wafer-to-wafer bonding can include wafer cleaning and other pretreatments, alignment and pre-bonding at room temperature, and annealing at elevated temperatures, such as about 250° C. or higher. Die-to-wafer bonding can use bumps on a wafer to align the features of the preformed chip with the drivers of the wafer. Hybrid bonding may include, for example, wafer cleaning, high precision alignment of contacts on one wafer to contacts on another wafer, dielectric bonding of dielectric materials within a wafer at room temperature, and Metal bonding of contacts by annealing at 250°C to 300°C or higher. As used herein, the term "bump" may generally refer to metal interconnects used or formed during bonding.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the examples of the present invention. It will be apparent, however, that various examples may be practiced without these specific details. For example, devices, systems, structures, assemblies, methods, and other components may be shown as components in block diagram form so as not to obscure the examples in unnecessary detail. In other instances, well-known devices, processes, systems, structures and techniques may be shown without necessary detail in order not to obscure the examples. The figures and descriptions are not intended to be limiting. The terms and expressions that have been used in this disclosure are used as terms of description and are not limiting and are not intended to exclude any equivalents of the features shown and described, or parts thereof, when such terms and expressions are used. The word "instance" is used herein to mean "serving as an instance, instance, or illustration." Any particular example or design described herein as an "example" is not necessarily to be construed as preferred or advantageous over other particular examples or designs. Micro LED used as light source

1 is a simplified block diagram of an example of an artificial reality system environment 100 including a near-eye display 120, according to some specific examples. The artificial reality system environment 100 shown in FIG. 1 may include a near-eye display 120 , an optional external imaging device 150 , and an optional input/output interface 140 , each of which may be coupled to an optional console 110 . Although FIG. 1 shows an example of an artificial reality system environment 100 including a near-eye display 120, an external imaging device 150, and an input/output interface 140, any number of these components may be included in the artificial reality system environment 100, Or any of these components may be omitted. For example, there may be multiple near-eye displays 120 monitored by one or more external imaging devices 150 in communication with the console 110 . In some configurations, the augmented reality system environment 100 may not include the external imaging device 150 , the optional input/output interface 140 , and the optional console 110 . In alternate configurations, different components or additional components may be included in the artificial reality system environment 100 .

The near-eye display 120 may be a head-mounted display that presents content to a user. Examples of content presented by near-eye display 120 include one or more of images, video, audio, or any combination thereof. In some embodiments, the audio may be presented via an external device (eg, speakers and/or headphones) that receives audio information from the near-eye display 120, the console 110, or both, and presents the audio based on the audio information material. The near-eye display 120 may include one or more rigid bodies, which may be rigidly or non-rigidly coupled to each other. Rigid coupling between rigid bodies allows the coupled rigid bodies to act as a single rigid body. A non-rigid coupling between rigid bodies allows the rigid bodies to move relative to each other. In various embodiments, the near-eye display 120 may be implemented in any suitable form factor, including a pair of glasses. Some specific examples of near-eye displays 120 are further described below with respect to FIGS. 2 and 3 . Additionally, in various embodiments, the functionality described herein may be used in a headset that combines images of the environment external to near-eye display 120 with artificial reality content (eg, computer-generated imagery). Accordingly, the near-eye display 120 can utilize the generated content (eg, images, video, sound, etc.) to augment the image of the physical real-world environment outside the near-eye display 120 to present the augmented reality to the user.

In various specific examples, near-eye display 120 may include one or more of display electronics 122 , display optics 124 , and eye tracking unit 130 . In some embodiments, the near-eye display 120 may also include one or more localizers 126 , one or more position sensors 128 , and an inertial measurement unit (IMU) 132 . In various specific examples, near-eye display 120 may omit any of eye tracking unit 130, locator 126, position sensor 128, and IMU 132, or include additional elements. Additionally, in some embodiments, near-eye display 120 may include elements that combine the functionality of the various elements described in connection with FIG. 1 .

Display electronics 122 may display or facilitate display of images to a user based on data received from, for example, console 110 . In various specific examples, display electronics 122 may include one or more display panels, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an inorganic light emitting diode (inorganic light emitting diode; ILED) display, micro light emitting diode (μLED) display, active-matrix OLED display (AMOLED), transparent OLED display (transparent OLED display; TOLED) or some other display. For example, in one implementation of near-eye display 120, display electronics 122 may include a front TOLED panel, a rear display panel, and optical components (eg, attenuators, polarizers, etc.) between the front and rear display panels filter, or diffractive or spectral coatings). Display electronics 122 may include pixels to emit light in a primary color such as red, green, blue, white, or yellow. In some implementations, the display electronics 122 may display three-dimensional (3D) images through stereoscopic effects, which are produced by a two-dimensional panel, to generate a subjective perception of image depth. For example, the display electronics 122 may include left and right displays positioned in front of the user's left and right eyes, respectively. The left and right displays may present copies of the image that are horizontally shifted relative to each other to create a stereoscopic effect (ie, the perception of depth of the image by a user viewing the image).

In some embodiments, display optics 124 may optically display image content (eg, using optical waveguides and couplers), or amplify image light received from display electronics 122 to correct for optical errors associated with the image light , and the corrected image light is presented to the user of the near-eye display 120 . In various specific examples, display optics 124 may include one or more optical elements, such as substrates, optical waveguides, apertures, Fresnel lenses, convex lenses, concave lenses, filters, input/output couplers, or may affect self- Any other suitable optical element for the image light emitted by display electronics 122 . Display optics 124 may include a combination of different optical elements, as well as mechanical couplings to maintain relative spacing and orientation of the optical elements in the combination. One or more of the optical elements in display optics 124 may have an optical coating, such as an anti-reflective coating, a reflective coating, a filter coating, or a combination of different optical coatings.

The magnification of the image light by the display optics 124 may allow the display electronics 122 to be physically smaller, lighter in weight and consume less power than larger displays. Additionally, zooming in increases the field of view of the displayed content. The amount of magnification of the image light by display optics 124 can be changed by adjusting, adding optical elements, or removing optical elements from display optics 124 . In some embodiments, display optics 124 may project the displayed image to one or more image planes that may be further away from the user's eye than near-eye display 120 .

Display optics 124 may also be designed to correct for one or more types of optical errors, such as two-dimensional optical errors, three-dimensional optical errors, or any combination thereof. Two-dimensional errors may include optical aberrations that occur in two dimensions. Example types of two-dimensional errors may include barrel distortion, pincushion distortion, longitudinal chromatic aberration, and lateral chromatic aberration. Three-dimensional errors may include optical errors that occur in three dimensions. Example types of three-dimensional errors may include spherical aberration, coma, curvature of field, and astigmatism.

The locators 126 may be objects located in particular locations on the near-eye display 120 relative to each other and relative to a reference point on the near-eye display 120 . In some implementations, the console 110 can identify the localizer 126 in the image captured by the external imaging device 150 to determine the position, orientation, or both of the artificial reality headset. The positioner 126 may be an LED, a corner cube reflector, a reflective marker, a type of light source that contrasts with the environment in which the near-eye display 120 operates, or any combination thereof. In the specific example where the locator 126 is an active component (eg, an LED or other type of light emitting device), the locator 126 may emit in the visible light band (eg, about 380 nm to 750 nm), in the infrared (IR) band ( For example, about 750 nm to 1 mm), in the ultraviolet band (eg, about 10 nm to about 380 nm), in another portion of the electromagnetic spectrum, or in any combination of portions of the electromagnetic spectrum.

External imaging device 150 may include one or more cameras, one or more video cameras, any other device capable of capturing images including one or more of locators 126, or any combination thereof. Additionally, external imaging device 150 may include one or more filters (eg, to increase signal-to-noise ratio). External imaging device 150 may be configured to detect light emitted or reflected from locator 126 in the field of view of external imaging device 150 . In specific examples where the positioners 126 include passive elements (eg, retro-reflectors), the external imaging device 150 may include light sources that illuminate some or all of the positioners 126, which may reflect light back to the external imaging device Light source in 150. Slow calibration data may be communicated from external imaging device 150 to console 110, and external imaging device 150 may receive one or more calibration parameters from console 110 to adjust one or more imaging parameters (eg, focal length, focus, Frame rate, sensor temperature, shutter speed, aperture, etc.).

The position sensor 128 may generate one or more measurement signals in response to movement of the near-eye display 120 . Examples of position sensors 128 may include accelerometers, gyroscopes, magnetometers, other motion detection or error correction sensors, or any combination thereof. For example, in some embodiments, the position sensor 128 may include a plurality of accelerometers to measure translational motion (eg, forward/backward, up/down, or left/right) and to Multiple gyroscopes that measure rotational motion (eg, pitch, yaw, or roll). In some specific examples, the various position sensors may be oriented orthogonal to each other.

The IMU 132 may be an electronic device that generates fast calibration data based on measurement signals received from one or more of the position sensors 128 . Position sensor 128 may be located external to IMU 132, internal to IMU 132, or any combination of external and internal. Based on one or more measurement signals from one or more position sensors 128 , IMU 132 may generate fast calibration data indicating the estimated position of near-eye display 120 relative to the initial position of near-eye display 120 . For example, IMU 132 may integrate measurement signals received from an accelerometer over time to estimate a velocity vector, and integrate the velocity vector over time to determine an estimated location of a reference point on near-eye display 120. Alternatively, the IMU 132 may provide the sampled measurement signals to the console 110, which may determine the quick calibration data. While a reference point may generally be defined as a point in space, in various embodiments, a reference point may also be defined as a point within near-eye display 120 (eg, the center of IMU 132).

Eye tracking unit 130 may include one or more eye tracking systems. Eye tracking may refer to determining the position of the eye relative to the near-eye display 120, including the orientation and orientation of the eye. The eye tracking system can include an imaging system to image one or more eyes, and optionally a light emitter that can generate light directed toward the eye so that light reflected by the eye can be captured by the imaging system. For example, eye tracking unit 130 may include incoherent or coherent light sources (eg, laser diodes) that emit light in the visible or infrared spectrum, and cameras that capture light reflected by the user's eyes. As another example, eye tracking unit 130 may capture reflected radio waves emitted by miniature radar units. Eye tracking unit 130 may use low power light transmitters that emit light at frequencies and intensities that will not damage the eyes or cause physical discomfort. Eye-tracking unit 130 may be configured to increase the contrast in the eye image captured by eye-tracking unit 130 while reducing the overall power consumed by eye-tracking unit 130 (eg, reducing light emission by the eye-tracking unit 130 ) the power consumed by the device and the imaging system). For example, in some implementations, eye tracking unit 130 may consume less than 100 milliwatts of power.

The near-eye display 120 may use the orientation of the eyes to, for example, determine the user's inter-pupillary distance (IPD), determine the gaze direction, introduce depth cues (eg, blurry images outside the user's primary line of sight), collect information about Heuristics of user interaction in VR media (eg, time spent on any particular individual, object, or frame, which varies according to the stimuli exposed), is oriented in part based on at least one of the user's eyes some other features, or any combination thereof. Because the orientation of the user's two eyes can be determined, the eye tracking unit 130 may be able to determine where the user is looking. For example, determining the user's gaze direction may include determining a convergence point based on the determined orientation of the user's left and right eyes. The point of convergence may be the point where the two orbital axes of the user's eyes meet. The user's gaze direction may be the direction of a line passing through the point of convergence and the midpoint between the pupils of the user's eyes.

The input/output interface 140 may be a device that allows the user to send action requests to the console 110 . An action request may be a request to perform a specific action. For example, an action request can be to start or end an application or to perform a specific action within the application. The input/output interface 140 may include one or more input devices. Example input devices may include keyboards, mice, game controllers, gloves, buttons, touch screens, or any other suitable device for receiving motion requests and communicating the received motion requests to console 110 . Action requests received by input/output interface 140 may be communicated to console 110, which may perform actions corresponding to the requested actions. In some embodiments, input/output interface 140 may provide haptic feedback to the user according to instructions received from console 110 . For example, input/output interface 140 may provide haptic feedback when an action request is received or when console 110 has performed the requested action and communicated instructions to input/output interface 140 . In some embodiments, the external imaging device 150 may be used to track the input/output interface 140, such as tracking a controller (which may include, for example, an IR light source) or the orientation or position of the user's hand to determine the user's movement. In some embodiments, the near-eye display 120 may include one or more imaging devices to track the input/output interface 140, such as tracking the position or position of a controller or a user's hand to determine the user's movement.

Console 110 may provide content to near-eye display 120 for presentation to a user based on information received from one or more of external imaging device 150 , near-eye display 120 , and input/output interface 140 . In the example shown in FIG. 1 , the console 110 may include an application store 112 , a headset tracking module 114 , an artificial reality engine 116 , and an eye tracking module 118 . Some specific examples of console 110 may include different modules or additional modules than those described in connection with FIG. 1 . The functionality described further below may be distributed among the components of the console 110 in a manner different from that described here.

In some embodiments, console 110 may include a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor. The processor may include multiple processing units that execute instructions in parallel. A non-transitory computer-readable storage medium can be any memory, such as a hard disk drive, removable memory, or solid state disk drive (eg, flash memory or dynamic random access memory (DRAM) ). In various embodiments, the modules of console 110 described in connection with FIG. 1 may be encoded as instructions in a non-transitory computer-readable storage medium that, when executed by a processor, cause the processor to perform the operations described further below. Describe the function.

The application store 112 may store one or more applications for execution by the console 110 . An application may include a set of instructions that, when executed by a processor, generate content for presentation to a user. The content generated by the application may be in response to input received from the user through the movement of the user's eyes, or input received from the input/output interface 140 . Examples of applications may include gaming applications, conferencing applications, video playback applications, or other suitable applications.

The headset tracking module 114 can use the slow calibration information from the external imaging device 150 to track the movement of the near-eye display 120 . For example, the headset tracking module 114 may use the locator observed from the slow calibration information and the model of the near-eye display 120 to determine the location of the reference point of the near-eye display 120. The headset tracking module 114 may also use the position information from the quick calibration information to determine the position of the reference point of the near-eye display 120 . Additionally, in some embodiments, the headset tracking module 114 may use portions of the fast calibration information, the slow calibration information, or any combination thereof, to predict the future orientation of the near-eye display 120 . The headset tracking module 114 may provide the estimated or predicted future position of the near-eye display 120 to the artificial reality engine 116 .

The AR engine 116 can execute applications within the AR system environment 100 and receive the position information of the near-eye display 120 , the acceleration information of the near-eye display 120 , the speed information of the near-eye display 120 , the near-eye display 120 from the headset tracking module 114 . the predicted future position, or any combination thereof. The artificial reality engine 116 may also receive estimated eye position and orientation information from the eye tracking module 118 . Based on the received information, the artificial reality engine 116 can determine the content to be provided to the near-eye display 120 for presentation to the user. For example, if the received information indicates that the user has looked to the left, the artificial reality engine 116 may generate content for the near-eye display 120 that reflects the movement of the user's eye in the virtual environment. Additionally, the artificial reality engine 116 may execute an action within an application executing on the console 110 in response to an action request received from the input/output interface 140 and provide feedback to the user indicating that the action has been executed. The feedback may be visual or auditory feedback provided via the near-eye display 120 , or haptic feedback provided via the input/output interface 140 .

The eye tracking module 118 can receive the eye tracking data from the eye tracking unit 130 and determine the position of the user's eyes based on the eye tracking data. The position of the eye may include the orientation, orientation, or both of the eye relative to the near-eye display 120 or any element thereof. Because the axis of rotation of the eye changes depending on the orientation of the eye in its socket, determining the orientation of the eye in its socket may allow the eye tracking module 118 to more accurately determine the orientation of the eye.

2 is a perspective view of an example of a near-eye display in the form of an HMD device 200 for implementing some examples disclosed herein. The HMD device 200 may be part of, for example, a VR system, an AR system, an MR system, or any combination thereof. The HMD device 200 may include a body 220 and a head strap 230 . 2 shows the bottom side 223, the front side 225, and the left side 227 of the main body 220 in perspective view. The head strap 230 may have an adjustable or extendable length. There may be sufficient space between the body 220 of the HMD device 200 and the head strap 230 to allow the user to mount the HMD device 200 on the user's head. In various specific examples, HMD device 200 may include additional components, fewer components, or different components. For example, in some embodiments, instead of head strap 230, HMD device 200 may include temples and temple tips as shown, for example, in FIG. 3 below.

The HMD device 200 may present media to a user that includes a virtual and/or augmented view of a physical real-world environment with computer-generated elements. Examples of media presented by HMD device 200 may include imagery (eg, two-dimensional (2D) or three-dimensional (3D) imagery), video (eg, 2D or 3D video), audio, or any combination thereof. Such images and video may be presented to each eye of the user by one or more display assemblies (not shown in FIG. 2 ) enclosed in the body 220 of the HMD device 200 . In various embodiments, one or more display assemblies may include a single electronic display panel or multiple electronic display panels (eg, one display panel for each eye of a user). Examples of electronic display panels may include, for example, LCDs, OLED displays, ILED displays, μLED displays, AMOLED, TOLED, some other display, or any combination thereof. HMD device 200 may include two eyebox regions.

In some implementations, HMD device 200 may include various sensors (not shown), such as depth sensors, motion sensors, position sensors, and eye tracking sensors. Some of these sensors may use structured light patterns for sensing. In some implementations, HMD device 200 may include an input/output interface for communicating with a console. In some implementations, HMD device 200 may include a virtual reality engine (not shown) that executes applications within HMD device 200 and receives depth information of HMD device 200 from various sensors , location information, acceleration information, velocity information, predicted future location, or any combination thereof. In some implementations, the information received by the virtual reality engine may be used to generate signals (eg, display commands) for one or more display assemblies. In some implementations, HMD device 200 may include positioners (not shown, such as positioner 126 ) in fixed positions on body 220 relative to each other and relative to a reference point. Each of these locators can emit light that can be detected by an external imaging device.

3 is a perspective view of an example of a near-eye display 300 in the form of a pair of glasses for implementing some of the examples disclosed herein. Near-eye display 300 may be a specific implementation of near-eye display 120 of FIG. 1, and may be configured to operate as a virtual reality display, augmented reality display, and/or mixed reality display. Near-eye display 300 may include frame 305 and display 310 . Display 310 may be configured to present content to a user. In some specific examples, display 310 may include display electronics and/or display optics. For example, as described above with respect to the near-eye display 120 of FIG. 1, the display 310 may include an LCD display panel, an LED display panel, or an optical display panel (eg, a waveguide display assembly).

The near-eye display 300 may further include various sensors 350a, 350b, 350c, 350d, and 350e on or within the frame 305. In some specific examples, sensors 350a-350e may include one or more depth sensors, motion sensors, position sensors, inertial sensors, or ambient light sensors. In some embodiments, sensors 350a-350e may include one or more image sensors configured to generate image data representing different fields of view in different directions. In some embodiments, sensors 350a - 350e may be used as input devices to control or affect the displayed content of near-eye display 300 and/or provide an interactive VR/AR/MR experience to a user of near-eye display 300 . In some embodiments, sensors 350a-350e may also be used for stereoscopic imaging.

In some specific examples, the near-eye display 300 may further include one or more illuminators 330 to project light into the physical environment. The projected light can be associated with different frequency bands (eg, visible light, infrared light, ultraviolet light, etc.) and can be used for various purposes. For example, illuminator 330 may project light in a dark environment (or in an environment with low intensity infrared light, ultraviolet light, etc.) to assist sensors 350a-350e in capturing images of different objects within the dark environment. In some embodiments, illuminator 330 may be used to project certain light patterns onto objects within the environment. In some embodiments, illuminator 330 may be used as a positioner, such as positioner 126 described above with respect to FIG. 1 .

In some embodiments, the near-eye display 300 may also include a high-resolution camera 340 . Camera 340 may capture images of the physical environment in the field of view. The captured image may be processed, for example, by a virtual reality engine (eg, the artificial reality engine 116 of FIG. 1 ) to add virtual objects to the captured image or to modify physical objects in the captured image, and the processed image may be displayed by a display 310 is displayed to the user for AR or MR applications.

4 illustrates an example of an optical see-through augmented reality system 400 including a waveguide display, according to some embodiments. Augmented reality system 400 may include projector 410 and combiner 415 . Projector 410 may include a light source or image source 412 and projector optics 414 . In some embodiments, the light source or image source 412 may comprise one or more of the micro-LED devices described above. In some embodiments, the image source 412 may include a plurality of pixels that display virtual objects, such as an LCD display panel or an LED display panel. In some embodiments, image source 412 may include a light source that produces coherent or partially coherent light. For example, image source 412 may include laser diodes, vertical cavity surface emitting lasers, LEDs, and/or the microLEDs described above. In some embodiments, image source 412 may include a plurality of light sources (eg, the array of microLEDs described above) each emitting monochromatic image light corresponding to a primary color (eg, red, green, or blue). In some embodiments, image source 412 can include three two-dimensional arrays of microLEDs, wherein each two-dimensional array of microLEDs can include a microLED configured to emit light of a primary color (eg, red, green, or blue) LED. In some embodiments, image source 412 may include an optical pattern generator, such as a spatial light modulator. Projector optics 414 may include one or more optical components that may condition the light from image source 412 , such as expanding the light, collimating light, scanning the light, or projecting light from image source 412 to combiner 415 . The one or more optical components may include, for example, one or more lenses, liquid lenses, mirrors, apertures, and/or gratings. For example, in some embodiments, image source 412 may include one or more one-dimensional arrays or elongated two-dimensional arrays of microLEDs, and projector optics 414 may include a one-dimensional array configured to scan microLEDs Or one or more one-dimensional scanners (eg, micromirrors or microscopes) that elongate a two-dimensional array to generate image frames. In some embodiments, projector optics 414 may include a liquid lens (eg, a liquid crystal lens) having a plurality of electrodes that allows scanning of light from image source 412 .

Combiner 415 may include an input coupler 430 for coupling light from projector 410 into substrate 420 of combiner 415 . The combiner 415 can transmit at least 50% of the light in the first wavelength range and reflect at least 25% of the light in the second wavelength range. For example, the first wavelength range may be visible light from about 400 nm to about 650 nm, and the second wavelength range may be in the infrared band, eg, from about 800 nm to about 1000 nm. The input coupler 430 may include a volume holographic grating, a diffractive optical element (DOE) (eg, a surface relief grating), a sloped surface of the substrate 420 , or a refractive coupler (eg, a wedge or horn) . For example, the input coupler 430 may comprise a reflective volume Bragg grating or a transmissive volume Bragg grating. For visible light, the input coupler 430 may have a coupling efficiency greater than 30%, 50%, 75%, 90%, or higher. Light coupled into substrate 420 may propagate within substrate 420 via, for example, total internal reflection (TIR). Substrate 420 may be in the form of the lenses of a pair of eyeglasses. Substrate 420 may have a flat or curved surface, and may include one or more types of dielectric materials, such as glass, quartz, plastic, polymer, poly(methyl methacrylate) (PMMA), crystal, or ceramic. The thickness of the substrate may range, for example, from less than about 1 mm to about 10 mm or greater than 10 mm. The substrate 420 may be transparent to visible light.

The substrate 420 may include or be coupled to a plurality of output couplers 440 each configured to extract from the substrate 420 at least a portion of the light directed by the substrate 420 and propagating within the substrate, and to divert all of the light from the substrate 420. The extracted light 460 is directed to the orbit 495 where the eyes 490 of the user of the augmented reality system 400 may be located when the augmented reality system 400 is in use. The plurality of output couplers 440 can replicate the exit pupil to increase the size of the eye socket 495 so that the displayed image is visible in a larger area. Like the input coupler 430, the output coupler 440 may include a grating coupler (eg, a volume holographic grating or a surface relief grating), other diffractive optical elements (DOE), crystals, and the like. For example, the output coupler 440 may comprise a reflective volume Bragg grating or a transmissive volume Bragg grating. The output coupler 440 may have different coupling (eg, diffraction) efficiencies at different orientations. Substrate 420 may also allow light 450 from the environment in front of combiner 415 to pass through with little or no loss. Output coupler 440 may also allow light 450 to pass through with minimal loss. For example, in some implementations, output coupler 440 may have very low diffraction efficiency for light 450, such that light 450 may be refracted or otherwise pass through output coupler 440 with little loss, and thus may Has an intensity higher than the extracted light 460. In some implementations, output coupler 440 can have high diffraction efficiency for light 450 and can diffract light 450 in certain desired directions (ie, at certain desired diffraction angles) with little loss. As a result, the user may be able to view a combined image of the environment in front of the combiner 415 and the image of the virtual object projected by the projector 410 .

5A illustrates an example of a near-eye display (NED) device 500 including a waveguide display 530, according to some specific examples. NED device 500 may be an example of near-eye display 120, augmented reality system 400, or another type of display device. NED device 500 may include light source 510 , projection optics 520 and waveguide display 530 . Light source 510 may include multiple panels for light emitters of different colors, such as a panel for red light emitters 512 , a panel for green light emitters 514 , and a panel for blue light emitters 516 . Red light emitters 512 are organized into arrays; green light emitters 514 are organized into arrays; and blue light emitters 516 are organized into arrays. The size and spacing of the light emitters in light source 510 can be small. For example, each light emitter can have a diameter of less than 2 μm (eg, about 1.2 μm), and the pitch can be less than 2 μm (eg, about 1.5 μm). Thus, the number of light emitters in each of red light emitter 512, green light emitter 514, and blue light emitter 516 may be equal to or greater than the number of pixels in the display image, such as 960x720, 1280x720, 1440x 1080, 1920×1080, 2160×1080 or 2560×1080 pixels. Therefore, the display image can be simultaneously generated by the light sources 510 . Scanning elements may not be used in NED device 500 .

Before reaching waveguide display 530, the light emitted by light source 510 may be conditioned by projection optics 520, which may include an array of lenses. Projection optics 520 may collimate or focus light emitted by light source 510 to waveguide display 530 , which may include a coupler 532 for coupling light emitted by light source 510 into waveguide display 530 . Light coupled into waveguide display 530 may propagate within waveguide display 530, eg, via total internal reflection as described above with respect to FIG. 4 . The coupler 532 may also couple a portion of the light propagating within the waveguide display 530 out of the waveguide display 530 and towards the eye 590 of the user.

5B shows an example of a near-eye display (NED) device 550 including a waveguide display 580, according to some specific examples. In some embodiments, NED device 550 may use scanning mirror 570 to project light from light source 540 into an image field in which the user's eye 590 may be located. NED device 550 may be an example of near-eye display 120, augmented reality system 400, or another type of display device. Light source 540 may include one or more columns or rows of light emitters of different colors, such as columns of red light emitters 542 , columns of green light emitters 544 , and columns of blue light emitters 546 . For example, red light emitters 542, green light emitters 544, and blue light emitters 546 may each include N columns, each column including, for example, 2560 light emitters (pixels). Red light emitters 542 are organized into arrays; green light emitters 544 are organized into arrays; and blue light emitters 546 are organized into arrays. In some specific examples, light source 540 may include a single row of light emitters for each color. In some specific examples, light source 540 may include multiple rows of light emitters for each of red, green, and blue, where each row may include, for example, 1080 light emitters. In some embodiments, the size and/or spacing of the light emitters in light source 540 may be relatively large (eg, about 3 to 5 μm), and thus light source 540 may not include enough to simultaneously produce a complete display image light transmitter. For example, the number of light emitters for a single color may be less than the number of pixels in the displayed image (eg, 2560x1080 pixels). The light emitted by light source 540 may be a collection of collimated or diverging beams.

The light emitted by the light source 540 may be conditioned by various optical devices such as collimating lenses or free-form optical elements 560 before reaching the scanning mirror 570 . Free-form optical element 560 may include, for example, a faceted facet or another light-folding element that may direct light emitted by light source 540 toward scanning mirror 570, such as to change the direction of propagation of light emitted by light source 540, for example, by about 90° or more . In some specific examples, the free-form optical element 560 can be rotated to scan the light. Scanning mirror 570 and/or free-form optical element 560 can reflect and project light emitted by light source 540 to waveguide display 580 , which can include a coupler 582 for coupling the light emitted by light source 540 into waveguide display 580 . Light coupled into waveguide display 580 may propagate within waveguide display 580, eg, via total internal reflection as described above with respect to FIG. 4 . The coupler 582 may also couple a portion of the light propagating within the waveguide display 580 out of the waveguide display 580 and towards the eye 590 of the user.

Scanning mirror 570 may comprise a microelectromechanical system (MEMS) mirror or any other suitable mirror. Scanning mirror 570 can be rotated to scan in one or two dimensions. As scanning mirror 570 rotates, light emitted by light source 540 may be directed to different areas of waveguide display 580 so that the complete display image may be projected onto waveguide display 580 and directed by waveguide display 580 to the user during each scan cycle Eye 590. For example, in embodiments where light source 540 includes light emitters for all pixels in one or more columns or rows, scanning mirror 570 may be rotated in a row or column direction (eg, x-direction or y-direction) to scan image. In embodiments where light source 540 includes light emitters of some, but not all, pixels in one or more columns or rows, scanning mirror 570 may be in both the column and row directions (eg, both the x-direction and the y-direction) Rotate to project the display image (for example, using a raster-type scan pattern).

The NED device 550 may operate in a predefined display period. A display period (eg, a display cycle) may refer to the duration of scanning or projecting a complete image. For example, the display period may be the inverse of the desired frame rate. In the NED device 550 including the scan mirror 570, the display period may also be referred to as a scan period or scan cycle. The light generation by the light source 540 can be synchronized with the rotation of the scanning mirror 570 . For example, each scan cycle may include multiple scan steps, wherein the light source 540 may generate a different light pattern in each respective scan step.

During each scan cycle, the display image can be projected onto the waveguide display 580 and the user's eye 590 as the scan mirror 570 rotates. The actual color value and light intensity (eg, brightness) for a given pixel orientation of the displayed image may be the average of the three colors (eg, red, green, and blue) beams illuminating that pixel orientation during a scan cycle. After the scanning cycle is completed, the scanning mirror 570 can be returned to the initial position to project the light of the previous columns of the next display image, or can be rotated in the opposite direction or in a scanning pattern to project the light of the next display image, in which a new set of The driving signal may be fed to the light source 540 . The same procedure can be repeated as the scan mirror 570 is rotated in each scan cycle. Thus, different images can be projected to the user's eye 590 in different scan cycles.

6 illustrates an example of an image source assembly 610 in a near-eye display system 600 according to some embodiments. Image source assembly 610 may include, for example, a display panel 640 that may generate a display image to be projected to a user's eye, and may project the display image generated by display panel 640 to a waveguide display as described above with respect to FIGS. 4-5B projector 650. The display panel 640 may include a light source 642 and a driver circuit 644 for the light source 642 . Light source 642 may include light source 510 or 540, for example. Projector 650 may include, for example, free-form optics 560, scanning mirror 570, and/or projection optics 520, as described above. The near-eye display system 600 may also include a controller 620 that synchronously controls the light source 642 and the projector 650 (eg, the scanning mirror 570). Image source assembly 610 may generate and output image light to a waveguide display (not shown in FIG. 6 ), such as waveguide display 530 or 580 . As described above, a waveguide display can receive image light at one or more in-coupling elements and direct the received image light to one or more out-coupling elements. The input and output coupling elements may include, for example, diffraction gratings, holographic gratings, crystals, or any combination thereof. The input coupling elements can be selected such that total internal reflection of the waveguide display occurs. The out-coupling element may couple a portion of the TIR image light out of the waveguide display.

As described above, light source 642 may include a plurality of light emitters configured in an array or matrix. Each light emitter can emit monochromatic light, such as red light, blue light, green light, infrared light, and the like. While RGB colors are often discussed in this disclosure, the specific examples described herein are not limited to the use of red, green, and blue as primary colors. Other colors can also be used as the primary colors of the near-eye display system 600 . In some embodiments, a display panel according to an embodiment may use more than three primary colors. Each pixel in light source 642 may include three sub-pixels including red micro-LEDs, green micro-LEDs, and blue micro-LEDs. Semiconductor LEDs typically include functional light-emitting layers within multiple layers of semiconductor material. The multiple layers of semiconductor material may include different compound materials or the same base material with different dopants and/or different doping densities. For example, the plurality of layers of semiconductor material can include layers of n-type material, active regions that can include heterostructures (eg, one or more quantum wells), and layers of p-type material. Multiple layers of semiconductor material can be grown on the surface of a substrate having a certain orientation. In some embodiments, to improve light extraction efficiency, mesas may be formed that include at least some of the layers of semiconductor material.

The controller 620 may control the image rendering operations of the image source assembly 610 , such as the operation of the light source 642 and/or the projector 650 . For example, controller 620 may determine instructions for image source assembly 610 to present one or more display images. The commands may include display commands and scan commands. In some embodiments, the display instructions may include an image file (eg, a bitmap file). Display instructions may be received from, for example, a console, such as console 110 described above with respect to FIG. 1 . Scan commands may be used by image source assembly 610 to generate image light. The scan instructions may specify, for example, the type of image light source (eg, monochromatic or polychromatic), the scan rate, the orientation of the scanning device, one or more lighting parameters, or any combination thereof. Controller 620 may include a combination of hardware, software and/or firmware not shown here in order not to obscure other aspects of the present invention.

In some embodiments, the controller 620 may be a graphics processing unit (GPU) of the display device. In other embodiments, the controller 620 may be other kinds of processors. Operations performed by controller 620 may include acquiring content for display and dividing the content into discrete segments. Controller 620 may provide scan commands to light source 642, the scan commands including addresses corresponding to individual source elements of light source 642 and/or electrical biases applied to the individual source elements. The controller 620 may instruct the light source 642 to sequentially render discrete segments using light emitters corresponding to one or more columns of pixels in the image ultimately displayed to the user. The controller 620 can also instruct the projector 650 to perform various adjustments to the light. For example, controller 620 may control projector 650 to scan discrete segments to different regions of the coupling elements of a waveguide display (eg, waveguide display 580) as described above with respect to FIG. 5B. Thus, at the exit pupil of the waveguide display, each discrete portion appears in a different respective orientation. Although each discrete segment is presented at different separate times, the presentation and scanning of the discrete segments occurs quickly enough that the user's eye can integrate the different segments into a single image or series of images.

Image processor 630 may be a general-purpose processor and/or one or more application-specific circuits dedicated to performing the features described herein. In one embodiment, a general-purpose processor may be coupled to memory to execute software instructions that cause the processor to perform certain programs described herein. In another embodiment, image processor 630 may be one or more circuits dedicated to performing certain features. Although image processor 630 is shown in FIG. 6 as a separate unit from controller 620 and driver circuit 644, in other embodiments, image processor 630 may be a subunit of controller 620 or driver circuit 644. In other words, controller 620 or driver circuit 644 may perform various image processing functions of image processor 630 in these specific examples. The image processor 630 may also be referred to as an image processing circuit.

In the example shown in FIG. 6 , light source 642 may be driven by driver circuit 644 based on data or commands sent from controller 620 or image processor 630 (eg, display and scan commands). In one specific example, the driver circuit 644 may include a circuit panel that connects to the various light emitters of the light source 642 and mechanically holds the light emitters. Light source 642 may emit light according to one or more illumination parameters set by controller 620 and potentially adjusted by image processor 630 and driver circuit 644 . Lighting parameters may be used by light source 642 to generate light. Illumination parameters can include, for example, source wavelength, pulse rate, pulse amplitude, beam type (continuous or pulsed), other parameters that can affect the light emitted, or any combination thereof. In some embodiments, the source light generated by light source 642 may include a plurality of red, green, and blue light beams, or any combination thereof.

Projector 650 may perform a set of optical functions, such as focusing, combining, conditioning, or scanning the image light produced by light source 642 . In some specific examples, projector 650 may include a combination assembly, a light conditioning assembly, or a scanning mirror assembly. Projector 650 may include one or more optical components that optically adjust and potentially redirect light from light source 642 . An example of light conditioning may include conditioning the light, such as expanding, collimating, correcting one or more optical errors (eg, curvature of field, chromatic aberrations, etc.), some other light conditioning, or any combination thereof. The optical components of projector 650 may include, for example, lenses, mirrors, apertures, gratings, or any combination thereof.

Projector 650 may redirect image light via one or more reflective and/or refractive portions thereof such that the image light is projected toward the waveguide display in certain orientations. The orientation of the image light redirected to the waveguide display may depend on the particular orientation of one or more reflective and/or refractive moieties. In some embodiments, projector 650 includes a single scanning mirror that scans in at least two dimensions. In other embodiments, projector 650 may include a plurality of scanning mirrors that each scan in directions orthogonal to each other. Projector 650 may perform raster scanning (horizontal or vertical), dual resonance scanning, or any combination thereof. In some embodiments, the projector 650 may perform controlled vibration along the horizontal and/or vertical directions at a particular oscillation frequency to scan in two dimensions and produce a two-dimensional projected image of the media presented to the user's eye. In other embodiments, projector 650 may include a lens or lens that may be used for similar or the same function as one or more scanning mirrors. In some embodiments, image source assembly 610 may not include a projector, wherein light emitted by light source 642 may be directly incident on the waveguide display.

In semiconductor LEDs, photons are typically generated via recombination of electrons and holes within the active region (eg, one or more semiconductor layers) with some internal quantum efficiency, where the internal quantum efficiency is the radiated electrons in the active region where the photons are emitted - The ratio of hole reorganization. The resulting light can then be extracted from the LED in a specific direction or within a specific solid angle. The ratio between the number of emitted photons extracted from the LED and the number of electrons passed through the LED is called the external quantum efficiency, which describes the efficiency with which the LED converts injected electrons into photons extracted from the device.

The external quantum efficiency can be proportional to the injection efficiency, the internal quantum efficiency and the extraction efficiency. Injection efficiency refers to the proportion of electrons injected into the active region through the device. Extraction efficiency is the fraction of photons generated in the active region that escape from the device. For LEDs, and in particular for microLEDs with reduced physical size, improving internal and external quantum efficiency and/or controlling the emission spectrum can be challenging. In some embodiments, to improve light extraction efficiency, mesas may be formed that include at least some of the layers of semiconductor material.

FIG. 7A shows an example of an LED 700 having a vertical mesa structure. LED 700 may be a light emitter in light source 510 , 540 or 642 . LED 700 may be a micro-LED made of inorganic material, such as multiple layers of semiconductor material. The layered semiconductor light emitting device may include a plurality of layers of III-V semiconductor materials. Group III-V semiconductor materials may include one or more group III elements, such as aluminum (Al), gallium (Ga), or indium (In), and group V elements, such as nitrogen (N), phosphorus (P), arsenic (As ) or antimony (Sb). When the group V element of the III-V semiconductor material includes nitrogen, the III-V semiconductor material is referred to as a III-nitride material. Layered semiconductor light emitting devices can be fabricated by growing multiple epitaxial layers on a substrate using techniques such as: vapor-phase epitaxy (VPE), liquid-phase epitaxy (liquid-phase) epitaxy; LPE), molecular beam epitaxy (MBE), or metalorganic chemical vapor deposition (MOCVD). For example, layers of semiconductor material may be grown layer by layer in a lattice orientation (eg, polar, non-polar, or semi-polar orientation) on a substrate, such as a GaN, GaAs, or GaP substrate, or including but not limited to the following Substrates: sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinel, or those with a shared β-LiAlO ₂ structure Quaternary tetragonal oxides, where the substrate can be cut in specific directions to expose specific planes as growth surfaces.

In the example shown in FIG. 7A, LED 700 may include a substrate 710, which may include, for example, a sapphire substrate or a GaN substrate. The semiconductor layer 720 may be grown on the substrate 710 . The semiconductor layer 720 may include a III-V material, such as GaN, and may be p-doped (eg, doped with Mg, Ca, Zn, or Be) or n-doped (eg, doped with Si or Ge). One or more active layers 730 may be grown on the semiconductor layer 720 to form active regions. The active layer 730 may comprise III-V materials, such as one or more InGaN layers, one or more AlInGaP layers, and/or one or more GaN layers, which may form one or more heterostructures, such as one or more Multiple quantum wells or MQWs. The semiconductor layer 740 may be grown on the active layer 730 . The semiconductor layer 740 may include a III-V material, such as GaN, and may be p-doped (eg, doped with Mg, Ca, Zn, or Be) or n-doped (eg, doped with Si or Ge). One of the semiconductor layer 720 and the semiconductor layer 740 may be a p-type layer, and the other may be an n-type layer. The semiconductor layer 720 and the semiconductor layer 740 sandwich the active layer 730 to form a light emitting region. For example, LED 700 may include an InGaN layer between a p-type GaN layer doped with magnesium and an n-type GaN layer doped with silicon or oxygen. In some embodiments, LED 700 may include an AlInGaP layer between a p-type AlInGaP layer doped with zinc or magnesium and an n-type AlInGaP layer doped with selenium, silicon, or tellurium.

In some embodiments, an electron-blocking layer (EBL) (not shown in FIG. 7A ) can be grown to form a layer between active layer 730 and at least one of semiconductor layer 720 or semiconductor layer 740 . EBL can reduce electron leakage current and improve the efficiency of LED. In some embodiments, a heavily doped semiconductor layer 750, such as a P ⁺ or P ⁺⁺ semiconductor layer, can be formed on semiconductor layer 740 and serve as a contact layer for forming ohmic contacts and reducing the contact resistance of the device. In some embodiments, conductive layer 760 may be formed on heavily doped semiconductor layer 750 . The conductive layer 760 may include, for example, indium tin oxide (ITO) or an Al/Ni/Au film. In one example, the conductive layer 760 may include a transparent ITO layer.

In order to make contact with the semiconductor layer 720 (eg, n-GaN layer) and to more efficiently extract the light emitted by the active layer 730 from the LED 700, the semiconductor material layers (including the heavily doped semiconductor layer 750, the semiconductor layer 740, the active layer 730 and semiconductor layer 720) may be etched to expose semiconductor layer 720 and form mesa structures including layers 720-760. The mesa structure can confine charge carriers within the device. Etching the mesa structures can result in the formation of mesa sidewalls 732 that can be normal to the growth plane. A passivation layer 770 may be formed on the sidewalls 732 of the mesa structure. Passivation layer 770 may include an oxide layer, such as a SiO ₂ layer, and may act as a reflector to reflect the emitted light out of LED 700 . Contact layer 780 , which can include a metal layer, such as Al, Au, Ni, Ti, or any combination thereof, can be formed on semiconductor layer 720 and can serve as an electrode for LED 700 . Furthermore, another contact layer 790 such as an Al/Ni/Au metal layer can be formed on the conductive layer 760 and can serve as another electrode of the LED 700 .

When a voltage signal is applied to contact layers 780 and 790, electrons and holes can recombine in active layer 730, where the recombination of electrons and holes can cause photon emission. The wavelength and energy of the emitted photons may depend on the energy band gap between the valence and conduction bands in active layer 730 . For example, the InGaN active layer can emit green or blue light, the AlGaN active layer can emit blue to ultraviolet light, and the AlInGaP active layer can emit red, orange, yellow, or green light. The emitted photons may be reflected by passivation layer 770 and may exit LED 700 from the top (eg, conductive layer 760 and contact layer 790 ) or the bottom (eg, substrate 710 ).

In some specific examples, LED 700 may include one or more other components, such as lenses, on a light emitting surface, such as substrate 710, to focus or collimate emitted light or to couple emitted light into a waveguide. In some embodiments, the LED can include a mesa of another shape, such as a planar, conical, semi-parabolic, or parabolic shape, and the base area of the mesa can be circular, rectangular, hexagonal, or triangular. For example, LEDs may include mesas in a curved shape (eg, a parabolic shape) and/or a non-curved shape (eg, a conical shape). The table top can be truncated or untruncated.

7B is a cross-sectional view of an example of an LED 705 having a parabolic mesa structure. Similar to LED 700, LED 705 may include multiple layers of semiconductor material, such as multiple layers of III-V semiconductor material. A layer of semiconductor material may be epitaxially grown on a substrate 715, such as a GaN substrate or a sapphire substrate. For example, semiconductor layer 725 may be grown on substrate 715 . The semiconductor layer 725 may include a III-V material, such as GaN, and may be p-doped (eg, doped with Mg, Ca, Zn, or Be) or n-doped (eg, doped with Si or Ge). One or more active layers 735 may be grown on the semiconductor layer 725 . The active layer 735 may comprise III-V materials, such as one or more InGaN layers, one or more AlInGaP layers, and/or one or more GaN layers, which may form one or more heterostructures, such as one or more Multiple quantum wells. The semiconductor layer 745 may be grown on the active layer 735 . The semiconductor layer 745 may include a III-V material, such as GaN, and may be p-doped (eg, doped with Mg, Ca, Zn, or Be) or n-doped (eg, doped with Si or Ge). One of the semiconductor layer 725 and the semiconductor layer 745 may be a p-type layer, and the other may be an n-type layer.

In order to contact semiconductor layer 725 (eg, an n-type GaN layer) and to more efficiently extract light emitted by active layer 735 from LED 705, the semiconductor layer may be etched to expose semiconductor layer 725 and form mesas comprising layers 725-745 structure. The mesa structure can confine charge carriers within the implanted region of the device. Etching the mesa structures may result in the formation of mesa sidewalls (also referred to herein as facets) that may not be parallel or in some cases orthogonal to the growth planes associated with the crystalline growth of layers 725-745.

As shown in Figure 7B, LED 705 may have a mesa structure including a flat top. A dielectric layer 775 (eg, SiO ₂ or SiNx) may be formed on the facets of the mesa structure. In some specific examples, the dielectric layer 775 may include multiple layers of dielectric material. In some embodiments, metal layer 795 may be formed on dielectric layer 775 . Metal layer 795 may include one or more metals or metal alloy materials, such as aluminum (Al), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), copper (Cu), or any combination thereof. Dielectric layer 775 and metal layer 795 can form a mesa reflector that can reflect light emitted by active layer 735 toward substrate 715 . In some embodiments, the mesa reflector can be parabolically shaped to act as a parabolic reflector that can at least partially collimate the emitted light.

Electrical contacts 765 and 785 may be formed on semiconductor layer 745 and semiconductor layer 725, respectively, to serve as electrodes. Electrical contact 765 and electrical contact 785 may each include a conductive material, such as Al, Au, Pt, Ag, Ni, Ti, Cu, or any combination thereof (eg, Ag/Pt/Au or Al/Ni/Au), and Can act as an electrode for LED 705. In the example shown in FIG. 7B, electrical contact 785 can be an n-contact, and electrical contact 765 can be a p-contact. Electrical contacts 765 and semiconductor layer 745 (eg, a p-type semiconductor layer) may form a back reflector for reflecting light emitted by active layer 735 back toward substrate 715 . In some embodiments, electrical contacts 765 and metal layer 795 comprise the same material and can be formed using the same process. In some embodiments, additional conductive layers (not shown) may be included as intermediate conductive layers between electrical contacts 765 and 785 and the semiconductor layer.

Electrons and holes can recombine in active layer 735 when voltage signals are applied across contacts 765 and 785 . The recombination of electrons and holes can cause photons to be emitted, thus producing light. The wavelength and energy of the emitted photons may depend on the energy band gap between the valence and conduction bands in active layer 735 . For example, the InGaN active layer can emit green or blue light, while the AlInGaP active layer can emit red, orange, yellow, or green light. The emitted photons can travel in many different directions, and can be reflected by the mesa reflector and/or back reflector, and can exit the LED 705, eg, from the bottom side (eg, substrate 715) shown in Figure 7B. One or more other secondary optical components, such as lenses or gratings, may be formed on a light emitting surface, such as substrate 715, to focus or collimate and/or couple the emitted light into a waveguide.

One-dimensional or two-dimensional arrays of the LEDs described above can be fabricated on a wafer to form a light source (eg, light source 642). The driver circuit (eg, driver circuit 644 ) may be fabricated on, for example, a silicon wafer using a CMOS process. The LED and driver circuits on the wafer can be diced and then bonded together, or can be bonded at the wafer level and then diced. Various bonding techniques can be used to bond the LEDs and driver circuits, such as bonding, metal-to-metal bonding, metal oxide bonding, wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding, and the like.

8A shows an example of a die-to-wafer bonding method for an LED array according to some embodiments . In the example shown in FIG. 8A , LED array 801 may include a plurality of LEDs 807 on carrier substrate 805 . Carrier substrate 805 may include various materials such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like. LED 807 can be fabricated by, for example, growing various epitaxial layers, forming mesa structures, and forming electrical contacts or electrodes before performing bonding. The epitaxial layer may include various materials such as GaN, InGaN, (AlGaIn)P, (AlGaIn)AsP, (AlGaIn)AsN, (AlGaIn)Pas, (Eu:InGa)N, (AlGaIn)N, or the like, and An n-type layer, a p-type layer, and an active layer may be included, the active layer including one or more heterostructures, such as one or more quantum wells or MQWs. The electrical contacts may include various conductive materials, such as metals or metal alloys.

Wafer 803 may include base layer 809 on which passive or active integrated circuits (eg, driver circuits 811 ) are fabricated. The base layer 809 may include, for example, a silicon wafer. The driver circuit 811 may be used to control the operation of the LED 807 . For example, the driver circuit for each LED 807 may include a 2T1C pixel structure with two transistors and one capacitor. Wafer 803 may also include bonding layer 813 . The bonding layer 813 may include various materials such as metals, oxides, dielectrics, CuSn, AuTi, and the like. In some embodiments, a patterned layer 815 can be formed on the surface of the bonding layer 813, where the patterned layer 815 can include a metal gate made of a conductive material such as Cu, Ag, Au, Al, or the like grid.

LED array 801 can be bonded to wafer 803 via bonding layer 813 or patterned layer 815 . For example, patterned layer 815 can include metal pads or bumps made of various materials such as CuSn, AuSn, or nanoporous Au, which can be used to connect LEDs 807 in LED array 801 Aligned with corresponding driver circuits 811 on wafer 803 . In one example, LED array 801 can be directed toward wafer 803 until LEDs 807 are in contact with respective metal pads or bumps corresponding to driver circuits 811 . Some or all of the LEDs 807 can be aligned with the driver circuit 811 and can then be bonded to the wafer 803 through the patterned layer 815 by various bonding techniques such as metal-to-metal bonding. After the LEDs 807 have been bonded to the wafer 803 , the carrier substrate 805 can be removed from the LEDs 807 .

8B illustrates an example of an inter-wafer bonding method for an LED array according to some embodiments. As shown in FIG. 8B , the first wafer 802 may include a substrate 804 , a first semiconductor layer 806 , an active layer 808 , and a second semiconductor layer 810 . Substrate 804 may include various materials such as GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like. The first semiconductor layer 806, the active layer 808, and the second semiconductor layer 810 may include various semiconductor materials, such as GaN, InGaN, (AlGaIn)P, (AlGaIn)AsP, (AlGaIn)AsN, (AlGaIn)Pas, (Eu:InGa) )N, (AlGaIn)N or the like. In some embodiments, the first semiconductor layer 806 can be an n-type layer, and the second semiconductor layer 810 can be a p-type layer. For example, the first semiconductor layer 806 may be an n-doped GaN layer (eg, doped with Si or Ge), and the second semiconductor layer 810 may be a p-doped GaN layer (eg, doped with Mg, Ca, Zn or Be). The active layer 808 may include, for example, one or more layers of GaN, one or more layers of InGaN, one or more layers of AlInGaP, and the like, which layers may form one or more heterostructures, such as one or more quantum wells or MQW.

In some embodiments, the first wafer 802 may also include a bonding layer. Bonding layer 812 may include various materials such as metals, oxides, dielectrics, CuSn, AuTi, or the like. In one example, the bonding layer 812 may include p-contacts and/or n-contacts (not shown). In some embodiments, other layers may also be included on the first wafer 802 , such as a buffer layer between the substrate 804 and the first semiconductor layer 806 . The buffer layer may include various materials such as polycrystalline GaN or AlN. In some specific examples, the contact layer may be between the second semiconductor layer 810 and the bonding layer 812 . The contact layer may include any suitable material for providing electrical contacts to the second semiconductor layer 810 and/or the first semiconductor layer 806 .

The first wafer 802 may be bonded to the wafer 803 including the driver circuit 811 and the bonding layer 813 as described above via the bonding layer 813 and/or the bonding layer 812 . The bonding layer 812 and the bonding layer 813 may be made of the same material or different materials. Bonding layer 813 and bonding layer 812 may be substantially flat. The first wafer 802 can be bonded to the wafer 803 by various methods, such as intermetallic bonding, eutectic bonding, metal oxide bonding, anodic bonding, thermocompression bonding, ultraviolet (UV) bonding, and/or melting engage.

As shown in FIG. 8B , first wafer 802 may be bonded to wafer 803 with the p-side of first wafer 802 (eg, second semiconductor layer 810 ) facing down (ie, toward wafer 803 ). . After bonding, the substrate 804 can be removed from the first wafer 802, and the first wafer 802 can then be processed from the n-side. Processing may include, for example, forming certain mesa shapes for individual LEDs, and forming optical components corresponding to individual LEDs.

9A - 9D illustrate an example of a method for hybrid bonding of LED arrays according to certain embodiments. Hybrid bonding may typically include wafer cleaning and activation, high precision alignment of contacts on one wafer to contacts on another wafer, dielectric bonding of dielectric materials at the surface of the wafer at room temperature, and Metal bonding of contacts by annealing at high temperature. Figure 9A shows a substrate 910 on which passive or active circuits 920 are fabricated. As described above with respect to FIGS. 8A-8B, the substrate 910 may include, for example, a silicon wafer. Circuit 920 may include driver circuitry for the LED array. The bonding layer may include dielectric regions 940 and contact pads 930 connected to circuit 920 via electrical interconnects 922 . The contact pads 930 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, or the like. The dielectric material in the dielectric region 940 may include SiCN, SiO ₂ , SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ or the like. The bonding layer can be planarized and polished using, for example, chemical mechanical polishing, where the planarization or polishing can cause a depression (bowl-like profile) in the contact pad. The surface of the bonding layer can be cleaned and activated by, for example, an ion (eg, plasma) or fast atom (eg, Ar) beam 905 . The activated surface can be atomically clean and reactive when the wafers are contacted, eg, at room temperature, for forming a direct bond between the wafers.

Figure 9B shows a wafer 950 that includes an array of microLEDs 970 fabricated thereon, as described above with respect to, eg, Figures 7A-8B. Wafer 950 may be a carrier wafer, and may include, for example, GaAs, InP, GaN, AlN, sapphire, SiC, Si, or the like. Micro LED 970 may include an n-type layer, an active region, and a p-type layer epitaxially grown on wafer 950 . The epitaxial layer may include the various III-V semiconductor materials described above, and may be processed from the p-type layer side to etch mesa structures in the epitaxial layer, such as substantially vertical structures, parabolic structures, conical structures, or its similar. A passivation layer and/or a reflective layer may be formed on the sidewalls of the mesa structure. A p-contact 980 and an n-contact 982 can be formed in the dielectric material layer 960 deposited on the mesa structure and can be in electrical contact with the p-type and n-type layers, respectively. The dielectric material in the dielectric material layer 960 may include, for example, SiCN, SiO ₂ , SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , or the like. The p-contact 980 and the n-contact 982 may include, for example, Cu, Ag, Au, Al, W, Mo, Ni, Ti, Pt, Pd, or the like. The top surfaces of p-contact 980, n-contact 982 and dielectric material layer 960 may form a bonding layer. The bonding layer can be planarized and polished using, for example, chemical mechanical polishing, where polishing can cause recesses in p-contact 980 and n-contact 982 . The bonding layer can then be cleaned and activated by, for example, an ion (eg, plasma) or fast atom (eg, Ar) beam 915 . Activated surfaces can be atomically clean and reactive when the wafers are contacted, eg, at room temperature, for forming direct bonds between wafers.

Figure 9C shows a room temperature bonding process for bonding the dielectric materials in the bonding layers. For example, after surface activation of the bonding layer including dielectric regions 940 and contact pads 930 and the bonding layer including p-contact 980, n-contact 982 and dielectric material layer 960, wafer 950 and micro LEDs may be inverted 970 and make contact with the substrate 910 and the circuits formed thereon. In some embodiments, compressive pressure 925 may be applied to substrate 910 and wafer 950 such that the bonding layers are pressed against each other. Due to surface activation and recesses in the contacts, the dielectric region 940 and the layer of dielectric material 960 can be in direct contact due to surface attractive forces and can react and form chemical bonds therebetween because the surface atoms can have dangling bonds And can be in an unstable energy state after activation. Thus, the dielectric regions 940 and the dielectric material in the dielectric material layer 960 can be bonded together with or without thermal treatment or pressure.

9D illustrates an annealing process for bonding the contacts in the bonding layers after bonding the dielectric material in the bonding layers. For example, contact pads 930 and p-contacts 980 or n-contacts 982 may be joined together by annealing, eg, at a temperature of about 200°C to 400°C or higher. During the annealing process, the heat 935 can cause the contacts to expand more than the dielectric material (due to the different coefficients of thermal expansion), and thus can close the recessed gap between the contacts such that the contact pad 930 and p-contact 980 or n Contacts 982 can make contact and can form a direct metal bond at the activated surface.

In some embodiments where the two bonded wafers include materials with different coefficients of thermal expansion (CTE), the dielectric material bonded at room temperature can help reduce or prevent contact pads from different thermal expansion. misaligned. In some embodiments, to further reduce or avoid misalignment of contact pads at high temperatures during annealing, between microLEDs, between groups of microLEDs, through portions in the substrate, or Grooves are formed all or the like.

After the microLEDs are bonded to the driver circuit, the substrate on which the microLEDs are fabricated can be thinned or removed, and various secondary optical components can be fabricated on the light-emitting surface of the microLEDs, such as to extract, collimate, and redirect from The light emitted by the active area of the micro LED. In one example, microlenses can be formed on the microLEDs, where each microlens can correspond to a respective microLED, and can help improve light extraction efficiency and collimate light emitted by the microLEDs. In some embodiments, the secondary optical components can be fabricated in the substrate or in the n-type layer of the microLED. In some embodiments, the secondary optical components can be fabricated in a dielectric layer deposited on the n-type side of the microLED. Examples of secondary optical components may include lenses, gratings, anti-reflection (AR) coatings, crystals, photonic crystals, or the like.

FIG. 10 shows an example of an LED array 1000 with a secondary optical component fabricated thereon, according to some specific examples. LED array 1000 may be fabricated by bonding an LED chip or wafer to a silicon wafer including circuits fabricated thereon using any suitable bonding technique such as described above with respect to FIGS. 8A-9D. In the example shown in Figure 10, LED array 1000 may be bonded using hybrid bonding techniques between wafers as described above with respect to Figures 9A-9D. The LED array 1000 may include a substrate 1010, which may be, for example, a silicon wafer. Integrated circuits 1020 such as LED driver circuits can be fabricated on substrate 1010 . The integrated circuit 1020 can be connected to the p-contact 1074 and the n-contact 1072 of the microLED 1070 via interconnects 1022 and contact pads 1030, which can form a metal bond with the p-contact 1074 and the n-contact 1072. The dielectric layer 1040 on the substrate 1010 may be bonded to the dielectric layer 1060 via fusion bonding.

The substrate of the LED chip or wafer (not shown) can be thinned or removed to expose the n-type layer 1050 of the microLED 1070 . Various secondary optical components such as spherical microlenses 1082, gratings 1084, microlenses 1086, antireflection layers 1088, and the like can be formed in or on top of n-type layer 1050. For example, a grayscale mask and a photoresist that responds linearly to exposure light can be used, or an etch mask formed by thermal reflow of a patterned photoresist layer can be used to etch spheres in the semiconductor material of the microLED 1070 Microlens array. Secondary optical components may also be etched in the dielectric layer deposited over n-type layer 1050 using similar photolithography or other techniques. For example, a microlens array can be formed in the polymer layer via thermal reflow of the polymer layer patterned using a binary mask. The microlens array in the polymer layer can be used as a secondary optical component or can be used as an etch mask for transferring the profile of the microlens array into a dielectric or semiconductor layer. The dielectric layer may include, for example, SiCN, SiO ₂ , SiN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , or the like. In some embodiments, the micro-LED 1070 may have a plurality of corresponding secondary optical components, such as micro-lenses and anti-reflection coatings, micro-lenses etched in semiconductor material and micro-lenses etched in dielectric material layers, micro-lenses and gratings, spherical and aspherical lenses, and the like. Three different secondary optical components are shown in FIG. 10 to show some examples of secondary optical components that can be formed on microLED 1070, which does not necessarily imply the simultaneous use of different secondary optical components for each LED array. Crystalline waveguide for reducing the beam divergence of light produced by an LED

In addition to and/or in place of the secondary optical components discussed in connection with Figure 10, in some embodiments, semiconductor-based waveguides may also be used as secondary optical components. As mentioned above, the light beams emitted by LEDs can be too divergent and/or diffuse to be useful in many applications (eg, as light sources in head mounted displays, near eye displays, head up displays, and the like). For example, it may not be possible to directly use an LED emitting a beam with a Lambertian-like distribution without having some secondary optical components to collimate the beam and/or reduce the beam divergence. The waveguides discussed herein can be used as secondary optical components to shape the beam of an LED (eg, to collimate the beam and/or reduce beam divergence). When using waveguides as secondary optical components, these Lambertian-like LEDs can be used in applications that require relatively collimated light sources and/or beams with narrow beam profiles (eg, beams with small beam divergence).

，其中I為光束強度且θ為自正交於LES 1126之向量量測的角度。在類朗伯角分佈1108之曲線中，y軸表示光束強度（ I）且x軸表示角分佈（θ）之角度。因為大量的光1106之強度及/或功率在窄角度範圍（例如，

）之外，所以角分佈1108可能過於漫射及/或分散而無法在許多應用中直接使用LED 1102作為光源1102。 11A shows an example angular distribution 1108 of light 1106 emitted by a Lambertian-like light emitting device 1102, according to some specific examples . Lighting device 1102 may be an LED, such as any LED discussed herein, including but not limited to LED 700 of FIG. 7A , LED 705 of FIG. 7B , and/or LED 1070 of FIG. 10 . The LEDs 1102 may be micro light emitting diodes (μLEDs). Thus, the LED 1102 can include a light emitting surface (LES) 1126 that emits light (as indicated by arrow 1106 ) at a first beam divergence. The linear dimensions of the LES 1126 may be less than 10 microns. The first beam divergence can be characterized as a Lambertian-like distribution 1108, eg,

, where I is the beam intensity and θ is the angle measured from a vector normal to the LES 1126 . In the plot of the Lambertian-like distribution 1108, the y-axis represents the beam intensity ( I ) and the x-axis represents the angle of the angular distribution (θ). Because a large amount of light 1106 has an intensity and/or power over a narrow angular range (eg,

), so the angular distribution 1108 may be too diffuse and/or diffuse to directly use the LED 1102 as the light source 1102 in many applications.

11B shows a cross-sectional view of a light source 1110 that includes an array of waveguides 1114 as a beam collimating secondary optical component for an array of light emitting devices 1112, according to some embodiments. The light source 1100 of FIG. 11B can be used in a variety of applications where a relatively collimated beam with reduced beam divergence is desired compared to the light-emitting-only device 1102 shown in FIG. 11A that does not use any secondary optical components. The waveguide array 1114 may include a first waveguide 1140 . The array of light emitting devices may include a first light emitting device (eg, light emitting device 1102 of FIG. 11A ). As shown by the Lambertian angle distribution 1108 of FIG. 11A, the light emitting surface (LES) 1126 of the light emitting device 1102 can emit a light beam at a first beam divergence. Each of the other light emitting devices in light emitting device array 1112 may be another instance of light emitting device 1102 . Thus, each light emitting device in the array 1112 can emit a relatively uncollimated light beam having a Lambertian-like distribution 1008 (eg, a first beam divergence). See the bottom of FIG. 12A for a projected view of an illustrative (but non-limiting) embodiment of the three-dimensional (3D) structure of the waveguide array 1114. In Figure 12A, the waveguide array 1114 is a two-dimensional (2D) waveguide array. In other specific examples, the waveguide array 1114 may be a one-dimensional (1D) waveguide array.

Light emitting device array 1112 may be similar to at least one of LED array 801 of FIG. 8A , LED array 970 of FIGS. 9B-9D , and/or LED array 1000 of FIG. 10 . Thus, although not shown in FIG. 11B , the LED array 1114 may be included in a semiconductor wafer (or a portion of a semiconductor wafer, eg, a semiconductor die), such as, but not limited to, the first wafer 802 of FIG. 8B or the first wafer 802 of FIGS. 9B to 9B Wafer 950 of Figure 9D. In some embodiments, the LED array 1114 may include or be embedded within a first semiconductor die (eg, a portion of the wafer that has been removed or separated from other portions of the wafer) not shown in FIG. 11B .

Similarly, the waveguide array 1114 may be included in the second semiconductor die 1120 . The second semiconductor die 1120 may be bonded to the first semiconductor die including the LED array 1112 . The first semiconductor die (not shown in FIG. 11B ) and the second semiconductor die 1120 may be aligned such that there is a one-to-one correspondence between each LED in the LED array 1112 and each waveguide in the waveguide array 1114 . For example, the first LED 1102 in the LED array 1112 uniquely corresponds to the first waveguide 1140 in the waveguide array 1114 .

Each of the waveguides in the waveguide array 1114 that includes the first waveguide 1140 may include a semiconductor material. In some embodiments, the semiconductor material may comprise a crystalline structure, that is, the semiconductor material may be a crystalline material. In some non-limiting embodiments, the semiconductor material of the waveguide may be gallium nitride (GaN). The semiconductor material of the waveguide can be an optically transparent material (eg, optically transparent for at least a majority of the frequencies of light generated by the LEDs in the LED array 1112). The optically transparent crystalline semiconductor material is illustrated in FIG. 11B by the cross-hatched pattern shown in the first waveguide 1140 and each of the other waveguides in the waveguide array 1114 .

The first waveguide 1140 may include a first waveguide surface 1142 , a second waveguide surface 1144 and a waveguide body 1146 . As indicated by the cross-hatched pattern shown in the waveguides in the waveguide array 1114, including but not limited to the first waveguide 1140, the volume of space defined by the waveguide body 1146 may be filled with crystalline semiconductor material. As discussed further in connection with at least FIG. 12, the waveguides may be fabricated through one or more semiconductor processes. Semiconductor processing can enable fine surface finishing on waveguides. For example, the spatial dimensions of any defects in the first waveguide surface 1142 and/or the second waveguide surface 1144 may be less than 5 nanometers (nm).

The first semiconductor die (not shown in FIG. 11B ) and the second semiconductor die 1120 may be aligned such that the first LED 1102 corresponds to the first waveguide 1140 . Accordingly, the first waveguide surface 1142 may be configured and/or configured to receive at least a portion of the light generated within the first LED 1102 from the LES 1126 of the first LED 1102. According to some embodiments, the received light may have a first beam divergence (eg, characterized as an angular distribution 1108 ) of the light 1106 emitted by the Lambertian-like light source 1102 . After the light beam enters the first waveguide 1140 , the waveguide body 1146 may transmit the light beam to the second waveguide surface 1144 . The second waveguide surface 1144 can be configured to emit light (eg, light transmitted from the first waveguide surface 1142 to the second waveguide surface 1144 via the waveguide body 1146 ) out of the waveguide body 1146 and into the surrounding environment of the first waveguide . That is, the second waveguide surface 1144 can be configured as the light exit surface and/or the light emitting surface of the waveguide. The light exiting the second waveguide surface 1144 may have a second beam divergence that is substantially less than the first beam divergence of the light beam entering the first waveguide surface 1142 (eg, the second beam divergence is less than the first beam divergence) Divergence).

The shape of the waveguide body 1146 and the shape of the first waveguide surface 1142 and/or the second waveguide surface 1144 can be used to significantly collimate and/or significantly reduce beam divergence when the beam is transmitted through the first waveguide 1140 . Furthermore, due to the optical transmission efficiency of the first waveguide 1140 (eg, the optical transparency of crystalline semiconductor materials) and its significant optical internal reflection properties, the light beam experiences negligible as the angular divergence of the light beam is reduced through it traverses the waveguide optical power loss.

As shown in FIG. 11B , the shape of the waveguide body 1146 may be tapered in which the surface area of the end including the first waveguide surface 1142 is less than the surface area of the end including the second waveguide surface 1144 . The tapered shape may be characterized as a taper angle (eg, the angle formed by the intersection of the first waveguide surface 1142 and the sidewall of the waveguide body 1146). The taper angle can be a characteristic of the crystal growth process used for waveguides on semiconductor substrates. The tapered shape of the waveguide body 1146 can be used to increase the internal reflection of the first waveguide 1140 (eg, reduce transmission losses associated with the waveguide body 1146) and enhance the beam divergence from the first beam divergence to the second beam divergence decrease.

To further increase the internal reflection associated with the waveguide and to further enhance the reduction of beam divergence from the first beam divergence to the second beam divergence, an optically reflective layer 1152 may be included in the second semiconductor die 1120 . The reflective layer 1152 can encapsulate at least a portion of the waveguide body 1146 (eg, sidewalls of the waveguide body 1146 ). The reflective layer 1152 may be a metallization layer (eg, aluminum and/or gold layer) that prevents light leakage from the sidewalls of the waveguide body 1146 .

The shape of the second waveguide surface 1144 can be formed to further reduce the beam divergence of the light emitted by the first waveguide 1140 . As shown in FIG. 11B, the shape of the second waveguide surface may resemble a spherical and/or convex lens. That is, the shape of the second waveguide surface may be a curved shape. This curved shape can further collimate and/or focus the beam.

11C shows an example angular distribution 1160 of light emitted by a Lambertian-like light emitting device 1102 that uses a waveguide 1140 as a secondary optical component, according to some embodiments . As discussed above, the light emitted by the waveguide 1140 may have a second beam divergence that is significantly less than the first beam divergence of the light emitted by the LEDs 1102 . The second beam divergence can be characterized as the angular distribution 1160 of FIG. 11C , where I is the beam intensity and θ is the angle measured from the vector normal to the LES 1126 of the first LED 1102. In the graph of the angular distribution 1108 of light emitted by the first waveguide 1140, the y-axis represents the beam intensity ( I ) and the x-axis represents the angle of the angular distribution (θ). A comparison of the angular distribution 1160 with the angular distribution 1108 of FIG. 11A clearly indicates that the second beam divergence is significantly less than the first beam divergence. The second beam divergence may allow about 80% of the beam power or intensity to be confined within an emission cone of about 20°. Thus, when used as a secondary optical component of the first LED 1102, the first waveguide 1140 can act as a beam collimating waveguide that significantly reduces the beam divergence of the beam emitted by the first LED 1102. Each waveguide in the waveguide array 1114 may be similar to the first waveguide 1140 . Thus, each waveguide in the waveguide array 1114 can act as a beam collimating waveguide that significantly reduces the beam divergence of the beams of its corresponding LEDs in the LED array 1112.

Returning to FIG. 11B, the longitudinal dimension or direction of the waveguide (eg, first waveguide 1140) may refer to the direction of light beam propagation or transmission within the waveguide. Thus, the longitudinal direction of the first waveguide 1140 can be substantially aligned with the direction of the vector normal to the first waveguide surface 1142 (eg, the vertical direction of FIG. 11B ). The length of the first waveguide 1140 (or the waveguide body 1146 ) may refer to the spatial distance between the first waveguide surface 1142 and the second waveguide surface 1144 . The lateral direction and/or dimension of the waveguide may refer to a direction and/or dimension that is substantially orthogonal to the longitudinal direction and/or dimension. In some embodiments, the curvature "apex" corresponding to the first waveguide length may be measured from the first waveguide surface 1142 (which is a flat surface in the embodiment shown in FIG. 11B ) to the second waveguide surface 1144 The apex is, for example, the point on the curvature of the second waveguide surface 1144 that is farthest from the plane of the first waveguide surface 1142 . The transverse (or lateral) dimension or direction of the waveguide (eg, first waveguide 1140) may refer to a direction orthogonal to the longitudinal dimension of the waveguide. Thus, the lateral (or lateral) dimension of the first waveguide 1140 can be aligned with a vector that is substantially within the "plane" of the first waveguide surface 1142 (eg, the horizontal direction of FIG. 11B ). The width of the first waveguide 1140 (or the waveguide body 1146 ) may refer to the spatial distance between opposing points on the sidewalls of the waveguide body 1146 . Due to the tapered shape of the waveguide body 1146, the width varies along the longitudinal dimension. Thus, the width of the first waveguide 1140 may refer to the "average" width of the waveguide body 1146 (eg, as determined via integration along the longitudinal direction of the waveguide body 1146). The aspect ratio of a waveguide may refer to the ratio of the length of the waveguide to the width (or average width) of the waveguide.

The second semiconductor die 1120 may include a first dielectric layer 1122 and a second dielectric layer 1124 that encapsulate the waveguide array 1114 . At least one of the dielectric layers 1122/1124 may include an oxide material, such as, but not limited to, silicon dioxide ( _SiO2 ). Accordingly, at least one of the dielectric layers may be an oxide layer (eg, a silicon dioxide layer). In other embodiments, at least one of the dielectric layers 1122/1124 may include a nitride material, such as, but not limited to, silicon nitride. Accordingly, at least one of the dielectric layers may be a nitride layer (eg, a silicon nitride layer). The first dielectric layer 1122 can encapsulate at least a portion of the waveguide body 1146 . The first dielectric layer 1122 may cover at least a portion of the first waveguide surface 1142 . The second dielectric layer 1124 may cover at least a portion of the second waveguide surface 1144 . The second semiconductor die 1120 may additionally include a layer of crystalline material 1150 interposed between the first semiconductor die and the second semiconductor die 1120 . The first dielectric layer 1122 and/or the second dielectric layer 1124 may serve as a passivation layer for the semiconductor layer 1150 and each of the waveguides (eg, the first waveguide 1140).

As discussed further in connection with at least FIG. 12 , the waveguide array 1114 may be grown and/or formed on a continuous layer of crystalline material 1150 . The waveguide body of each waveguide can protrude vertically from and/or beyond the continuous layer of crystalline material 1150. The proximal (or proximate) surface of each waveguide in the waveguide array relative to the corresponding LED (eg, the first waveguide surface 1142 of the first waveguide 1140 ) may include a portion of the continuous layer 1150 of transparent crystalline material. The distal surface of each waveguide in the waveguide array relative to the corresponding LED (eg, the second waveguide surface 1144 of the first waveguide 1140 ) can be displaced vertically from the continuous layer of transparent crystalline material 1150 . The curved shape of the second waveguide surface 1144 can be formed by an etching process on the layer 1150 of crystalline material. As used herein, the terms distal and proximal can refer to substantially opposite directions or portions of a waveguide. The proximal (or proximate) portion of the waveguide may refer to the portion of the waveguide that is closer to the LED that will illuminate the waveguide, such as the portion of the waveguide 1140 that includes the first waveguide surface 1142. The distal portion or end of the waveguide 1140 is the portion that includes the second waveguide surface 1144 .

The light source 1110 may optionally include a transparent substrate layer 1130 . The transparent substrate layer 1130 may be a transparent glass layer bonded to the second semiconductor die 1120 such that the second semiconductor die 1120 is interposed between the first semiconductor die and the transparent substrate layer 1130 . In some embodiments, the transparent substrate layer 1130 can be bonded to the second dielectric layer 1124 to cover the exit surface of the waveguide (eg, the second waveguide surface 1144). The second dielectric layer 1124 (and/or the first dielectric layer 1122 ) may include SiO ₂ . Thus, the second dielectric layer 1124 may serve as a light emitting surface of the waveguide (eg, the second waveguide surface 1144 ) and/or a passivation layer for the layer of semiconductor material 1150 . Light emitted by the second waveguide surface 1144 (and the light emitting surface of any of the other waveguides) can be transmitted through the passivated second dielectric layer 1124 and/or the transparent substrate layer 1130 without significant power attenuation/absorption and / or scattered.

Due to the reduced beam divergence (eg, characterized by angular distribution 1160 of FIG. 11C ), light source 1110 (or any of the other light sources discussed herein) can be used and/or included as a wearable The light source in the installation. For example, the light source 1100 may be included in a wearable device that generates a virtual reality environment for a user wearing it (eg, the head mounted display device 200 of FIG. 2 ). As another example, the light source 1100 may be included in a wearable device that creates an augmented reality environment for a user wearing it (eg, the near-eye display 300 of FIG. 3 ).

12A illustrates a semiconductor process 1200 for fabricating the waveguide array 1114 of FIG. 11B, according to some embodiments. Portions of the discussion regarding semiconductor process 1200 will refer to light source 1100 of FIG. 11B. The semiconductor process 1200 may begin at step 1202 in which a layer 1150 of crystalline material is formed on the semiconductor substrate 1104 . In some embodiments, the semiconductor substrate 1104 may be a crystalline growth substrate wafer including a growth material such as, but not limited to, Si/AlO ₃ . The crystalline material of the crystalline material layer 1150 may include, but is not limited to, GaN. The array of crystal structures is grown on the crystal growth substrate 1104 . The array of crystalline structures includes at least a first crystalline structure (which corresponds to the first waveguide 1140, and thus the first waveguide 1140 and the first crystalline structure 1140 may be referred to interchangeably throughout).

Through the steps of process 1200, each crystalline structure in the array is formed as a waveguide in waveguide array 1114 (or FIG. 11B). The array of crystalline structures corresponds to the array of waveguides 1114 , and the first crystalline structure 1140 (or the first waveguide 1140 ) in the array of crystalline structures corresponds to the first waveguide 1140 in the array of waveguides 1114 . Thus, the terms crystalline structure and waveguide are used interchangeably herein. Once grown, each crystalline structure (or waveguide) in the crystalline (or waveguide) array comprising the first waveguide 1140 extends beyond the layer 1150 of crystalline material. Due to the crystal growth process, the shape and structure of the crystal structures are remarkably uniform throughout the array of crystal structures. Accordingly, the following discussion of the first crystalline structure (or waveguide) 1140 applies to each of the crystalline structures (or waveguides).

The first crystalline structure 1140 extends beyond and/or protrudes from the crystalline material layer 1150. The first crystalline structure 1140 includes a waveguide body 1146 , sidewalls 1148 of the body 1146 and a first surface 1142 . The first surface 1142 is the distal surface relative to the layer 1150 of crystalline material. Due to the crystal growth process, the sidewall 1148 forms a taper angle with the normal vector to the surface of the crystalline material layer 1150 . The taper angle is inward such that the sidewalls 1148 are closer together near the first surface 1142 than they are near the surface of the crystalline material layer 1150 . Accordingly, the orientation, taper angle, and first surface 1142 of the sidewalls 1148 define the features of the tapered shape of the waveguide body 1146 . Although not shown in the cross-sectional view of the steps of the process 1200 in Figure 12A, the first crystalline structure 1140 (or the first waveguide 1140) is a symmetrical three-dimensional (3D) structure. Due to its tapered shape, the 3D waveguide body 1146 may be a pyramid-shaped crystalline body 1146 . The first surface 1142 may form a truncated pyramid-shaped waveguide body 1146 . In some embodiments, the crystal growth process results in the tapered waveguide body 1146 having a hexagonal pyramid shape truncated through the first surface 1142 .

The bottom of FIG. 12A shows a perspective view of an illustrative (but non-limiting) embodiment of a three-dimensional (3D) structure of waveguide array 1114 (which is formed from an array of crystalline structures through the steps of process 1200). As shown in the bottom of Figure 12A, the waveguide array 1114 is a two-dimensional (2D) waveguide array. In other specific examples, the waveguide array 1114 may be a one-dimensional (1D) waveguide array. Note the truncated hexagonal pyramid shape of the waveguides included in the waveguide array 1114. Light receiving surfaces (eg, first waveguide surface 1142 of first waveguide 1140 ) are shown facing up in perspective view of waveguide array 1114 , while light emitting surfaces (eg, second waveguide surface 1144 of first waveguide 1140 ) are viewed from this perspective Invisible. It should be noted that the vertical orientation (relative to the plane of the page) of the waveguide array 1114 shown in Figure 12A is reversed from the vertical orientation of the waveguide array shown in Figure 11B. For example, the "lower" plane shown in such a projected view may represent the second dielectric layer 1124 or the transparent substrate layer 1130 . It should be noted that the vertical orientation (relative to the plane of the page) of the waveguide array 1114 shown in Figure 12A is reversed from the vertical orientation of the waveguide array shown in Figure 11B. Likewise, the vertical orientation of the illustration of steps 1202-1208 of process 1200 shown in FIG. 12A is reversed from the vertical orientation of waveguide array 1114 shown in FIG. 11B. The vertical illustration of steps 1210-1218 of process 1200 shown in FIG. 12A is the same as the vertical orientation of waveguide 1114 shown in FIG. 11B.

Process 1200 may then proceed to step 1204, where an optically reflective layer 1152 may be formed on the array of crystalline structures. The reflective layer 1152 may be formed on the "upper" surface of the crystalline material layer 1150 . As shown in step 1204, the reflective layer 1152 may cover the sidewalls 1148 of the first crystalline structure 1140, but not the first surface 1142. As also shown in step 1204, the reflective layer 1152 can cover at least a portion of the upper surface of the layer of crystalline material 1150, wherein the covered portion is between adjacent crystalline structures in the array of crystalline structures. The reflective layer 1152 can encapsulate at least a portion of the waveguide body 1146 . The reflective layer 1152 may be a metallization layer (eg, an aluminum layer) that prevents light leakage from the sidewalls 1148 of the waveguide body 1146 .

Also at step 1204, a first dielectric layer 1122 may be formed over the array of crystalline structures such that each of the crystalline structures (including the first crystalline structure 1140) is interposed between the first dielectric layer 1122 and the crystal growth substrate 1104. between. The first dielectric layer 1122 may be a dioxide layer including silicon dioxide (SiO ₂ ) or another optically transparent dioxide. In other embodiments, the first dielectric layer 1122 may be a nitride layer, such as a silicon nitride layer. The first dielectric layer 1122 can encapsulate at least a portion of the waveguide body 1146 . The first dielectric layer 1122 may cover at least a portion of the first surface 1142 . As shown in step 1204, a reflective layer 1152 may be interposed between the crystalline material layer 1150 and the first dielectric layer 1122.

At step 1206, transfer wafer 1154 may be bonded to first dielectric layer 1122 such that each of crystalline material layer 1150, reflective layer 1152, and first dielectric layer 1122 is interposed between crystal growth substrate 1104 and the transfer wafer Between circles 1154. Process 1200 may proceed to step 1208 where crystal growth substrate 1104 may be removed from layer 1150 of crystalline material. It should also be noted that, at least for purposes of illustration, the bonded transfer wafer 1154, first dielectric layer 1122, and crystalline material layer 1150 have been rotated 180 ^° (in the plane of the page) such that each of their vertical orientations have been rotated flip.

At step 1210, a semiconductor etch process may be used to remove a portion of the layer 1150 of crystalline material. An etching process can be used to form a second surface on each of the crystalline structures. Step 1210 shows that in addition to the first waveguide surface 1142 , the first waveguide structure 1140 also includes a second waveguide surface 1144 . The semiconductor etching process may include forming a spherical, convex, or any other lens-like shape for the second waveguide surface 1144 . In step 1212 , a second dielectric layer 1124 may be formed on the waveguide array 1114 . The second dielectric layer 1124 may cover the second waveguide surface of the waveguide, including but not limited to the second waveguide surface 1144 of the first waveguide 1140 . Therefore, the waveguide can be inserted between the first dielectric layer 1122 and the second dielectric layer 1124 . The structure including the waveguide array 1114 interposed between the first dielectric layer 1122 and the second dielectric layer 1124 may be a semiconductor die (or the entire wafer), such as the second semiconductor die 1120 .

Process 1200 may proceed to step 1214 where transparent substrate layer 1130 may be bonded to second dielectric layer 1124 such that second dielectric layer 1124 is interposed between waveguide array 1114 and transparent substrate layer 1130 . At step 1216 , the transfer wafer 1154 may be removed from the second semiconductor die 1120 . At step 1218 , the second semiconductor die 1120 may be bonded to the first semiconductor die including the light emitting device array 1112 . The first semiconductor die may be bonded to the first dielectric layer 1122 of the second semiconductor die 1120 . The light source 1110 of FIG. 11B is formed by bonding the second semiconductor die 1120 including the waveguide array 1114 to the first semiconductor die including the LED array 1112 .

FIG. 12B illustrates a method 1220 for fabricating the light source 1110 of FIG. 11B according to some embodiments. The method 1220 can include at least part of one or more steps of the semiconductor process 1200 of FIG. 12A. Method 1220 begins at block 1222 in which an array of crystalline structures is grown on a layer of crystalline material deposited on a semiconductor substrate. For example, as in step 1202 of process 1200, the crystalline structure forming the waveguide array 1114 may be a layer of crystalline material 1150 grown. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (eg, crystal growth substrate 1104). At block 1224 , a reflective layer (eg, metallization layer 1252 ) may be formed and/or deposited over portions of an array of crystalline structures (eg, waveguide array 1114 ), as shown in the diagram of step 1204 of process 1200 . Similar to step 1204 of process 1200, a first dielectric layer (eg, first dielectric layer 1122) may be formed and/or deposited over portions of the reflective layer and/or the waveguide array.

At block 1226, the transfer wafer may be bonded to the first dielectric layer (eg, see step 1206 of process 1200). At block 1228, the semiconductor substrate (eg, crystal growth substrate 1104) may be physically separated from the array of crystalline structures and/or the layer of crystalline material (see step 1208 of process 1200). At block 1230, portions of the crystalline material are later removed (eg, via an etching process) to form light emitting surfaces (eg, second waveguide surface 1144) of each of the waveguides (eg, see step 1210 of process 1200 ). ).

At block 1232, a second dielectric layer (eg, second dielectric layer 1124) is formed and/or deposited over the layer of crystalline material (eg, see step 1212 of process 1200). At block 1234, a transparent substrate layer (eg, transparent substrate layer 1130) may be bonded to a second dielectric layer (eg, see step 1214 of process 1200). At block 1236, the transfer wafer may be physically separated from the first dielectric layer (eg, see step 1216 of process 1200). At block 1238, a first semiconductor die comprising an array of light emitting devices is bonded to a second semiconductor die (eg, 1120) comprising an array of waveguides (eg, see step 1218 of process 1200).

In some embodiments of both process 1200 and method 1220, as well as other processes and methods discussed herein, a first semiconductor die (or another die) including an LED array is formed on a first semiconductor wafer. A second semiconductor die (or another die) including the waveguide array can be formed on the second semiconductor die. A first semiconductor wafer (eg, a wafer including an LED array) may be sawn (or diced) to form a first plurality of semiconductor dies including the first semiconductor die. That is, the first semiconductor die may be included in the first portion of the first semiconductor wafer. A first portion of the first semiconductor wafer may be removed (eg, sawed off and/or diced) from the first semiconductor wafer to form a first semiconductor die. Similarly, a second semiconductor wafer (eg, a wafer including a waveguide array) may be sawn (or diced) to form a second plurality of semiconductor dies including the second semiconductor die. That is, the second semiconductor die may be included in the first portion of the second semiconductor wafer. The first portion of the second semiconductor wafer may be removed (eg, sawed off and/or diced) from the second semiconductor wafer to form a second semiconductor die.

In some embodiments, the die comprising the LED array (eg, the first semiconductor die) may be bonded to the die comprising the waveguide array (eg, the second semiconductor die) after the die is formed by sawing or dicing the corresponding wafer semiconductor die). That is, each of the first semiconductor wafer and the second semiconductor wafer may be diced prior to step 1238 . For example, the second semiconductor wafer may be diced between steps 1236 and 1238 to form a second semiconductor die. The first semiconductor wafer may be singulated (to form the first die) after the LED array is fabricated on the first wafer. Thus, at step 1238, the first semiconductor die and the second semiconductor die may be aligned and bonded. Such instances may be referred to as die-level instances, since the individual dies are bonded to each other after the dies are sawn from the respective wafers. In other embodiments, the first and second semiconductor dies may be bonded prior to dicing the wafer. For example, the first and second semiconductor dies may be bonded prior to singulation of the first and second semiconductor dies from the first and second semiconductor wafers while the first and second dies remain their respective dies part of the circle. Throughout, such instances may be referred to as wafer-level instances. High fill factor crystalline waveguide

FIG. 13 shows a specific example of a high fill factor waveguide array 1314. The waveguide embodiment shown in Figure 13 may be referred to as a "high fill factor" embodiment. Specific examples of high fill factor include waveguide array 1314 . The term "fill factor" of a waveguide array (or specific instance) can refer to the surface area (or linear dimension) of the light emitting surface of the waveguide (eg, the second waveguide surface of the waveguide) and the spacing between the waveguides (eg, between adjacent waveguides in the array) the ratio of the spatial or linear distance). Thus, this ratio for high fill factor embodiments may be greater than this ratio for the embodiments discussed in connection with Figures 11A-12B.

As used herein, the term "pitch" may refer to or otherwise indicate the spatial distance between adjacent elements in an array (eg, a waveguide array or an LED array). In various embodiments, each LED/waveguide pair bonded to the LED array of the waveguide array can serve as a light source for a pixel in a display (eg, a pixel in a near-eye display). Thus, the LED/waveguide array spacing may match or at least be similar to the light receiving surface spacing of a pixel array of a display. For such embodiments, waveguides/LEDs may be advantageous for fully and/or uniformly illuminating the light receiving surface of the corresponding pixel. It may also be beneficial to reduce and/or minimize any "dark spots" of illumination between adjacent light-receiving surfaces of pixels. By increasing the fill factor (eg, the ratio of the area of the surface that emits light (eg, the light emitting surface of the waveguide) to the distance between the light emitting surfaces of the waveguide), high fill factor embodiments achieve greater uniformity of pixel illumination and proximity of pixels Reduction and/or attenuation of "dark spots" of illumination between light-receiving surfaces. Various high fill factor embodiments can increase the fill factor ratio by increasing the surface area of the waveguide illumination surface.

In high fill factor embodiments, the light emitting surface of the waveguides (eg, the second waveguide surface of the waveguides included in the waveguide array 1314) may have a larger surface area than the light emitting waveguide surfaces of the waveguides of the embodiments discussed in connection with FIGS. 11A-12B surface area, such as a larger fill factor. The larger surface area of the second waveguide surface of the waveguide can provide more uniform and/or complete illumination of the pixels where the waveguide's corresponding LED acts as a light source. The waveguide can illuminate the pixel uniformly with its larger light emitting surface. Thus, "dark spots" between adjacent pixels (eg, areas that receive little to no illumination from the waveguide) are attenuated, reduced, and/or minimized by the high fill factor embodiments discussed herein. Compared to the waveguide array 1114 shown in and/or discussed in connection with FIGS. 11B-12B , the high fill factor waveguides included in the waveguide array 1314 may additionally provide a reduction in the beam divergence of the light passing through the waveguides. More decrease.

13 shows three views of a high fill factor waveguide array 1314: a perspective view 1302, a top view 1304, and a cross-sectional view 1306. The high fill factor waveguide array 1314 can include a first high fill factor waveguide 1340 . As shown in Figure 13, the waveguide array 1314 is a 2D waveguide array. However, similar to the non-high fill factor waveguide array 1114 of FIG. 11B, the high fill factor waveguide array 1314 can be fabricated as a ID array of high fill factor waveguides. A high fill factor waveguide (eg, first waveguide 1340) may include a light emitting structure (eg, light emitting structure 1358) as part of its waveguide body. The light emitting structure may comprise the same material (eg, GaN) as the waveguide body. The light emitting structure may be positioned on a portion of the tapered waveguide body that is wider than another portion of the waveguide body. That is, the light emitting structure of the waveguide can be located at the distal end of the waveguide instead of the proximal end of the waveguide. The light emitting structure can further "widen" the light emitting surface of the waveguide, which increases the surface area of the light emitting surface. Therefore, the light emitting structure can increase the fill factor of the array. The light emitting surface of the waveguide (eg, second waveguide surface 1344 ) is positioned on the "underside" of the light emitting structure (eg, light emitting structure 1358 ) of perspective 1302 .

During the fabrication of high fill factor embodiments, an etch process may be used to alter and/or enhance the shape of the sidewalls and waveguide body of the waveguide from the "predetermined" shape of the sidewalls and waveguide body (eg, to a preset created by the crystal growth process) shape). This enhanced shape may include forming the light emitting structures mentioned above (eg, light emitting structure 1358). The light emitting structure formed on the distal end of the waveguide body can be formed through this etching process. For a non-limiting example of one such variation of the predetermined shape of the waveguide body, see the high fill factor specific example discussed in connection with Figures 13-14B. Enhanced shapes can increase the fill factor of the waveguide and beam collimation and/or divergence reducing effects. The enhanced shape may include changing the taper (eg, taper angle) of the waveguide body along the longitudinal dimension of the waveguide. In addition to "shaping" the waveguide through an etching process, the aspect ratio of the waveguide can be increased. The increased aspect ratio can further enhance the collimation and/or beam divergence reduction properties of the waveguide.

Similar to the first waveguide 1140 in the waveguide array 1114 , the first waveguide 1340 in the waveguide array 1314 includes a first waveguide surface 1342 , a second waveguide surface 1344 and a waveguide body 1346 . It should be noted that the second waveguide surface 1344 is located on the light emitting structure 1358. The first waveguide surface 1342 receives the light generated by the LED, and the second waveguide surface 1344 transmits the received light out of the waveguide body 1346 . The distal end of the waveguide body 1346 (eg, the portion of the waveguide body 1346 furthest away from the light-receiving waveguide surface (eg, the first waveguide surface 1344 )) includes a light emitting structure 1358 . In perspective view 1302, second waveguide surface 1344 is positioned on the "underside" of light emitting structure 1358. Light emitting structure 1358 is a bulk structure formed of a crystalline material including a waveguide body 1346, such as GaN. The light emitting structure 1358 may be a bulk structure. In some embodiments, the shape of the bulk structure 1358 may be a tapered shape. One or more lateral (or lateral) dimensions of light emitting structures 1358 (eg, a spatial dimension substantially orthogonal to a dimension along the direction in which light travels through waveguide body 1346 ) may be larger than the sides of the remainder of waveguide body 1346 to size.

As shown in side view 1306 and similar to waveguide array 1114 , waveguide array 1314 may be bonded to transparent substrate layer 1330 . Referring back to Figures 11B-12A, the first waveguide 1140 (and each of the other waveguides in the waveguide array 1114) may have a first aspect ratio. Here, the aspect ratio may refer to the ratio of the approximate longitudinal dimension of the waveguide body to the approximate lateral or lateral dimension of the waveguide body. The first high fill factor waveguide 1340 (and each of the other waveguides in the high fill factor waveguide array 1314) has a second aspect ratio. A visual comparison between the cross-sectional view 1306 and the cross-sectional view of the light source 1110 of FIG. 11B shows that the second aspect ratio (of the first waveguide 1340 ) is greater than the first aspect ratio (of the first waveguide 1140 ). The "height" of the light emitting structure 1358 may facilitate an increase in the aspect ratio. It should be noted that the "width" of the light emitting structure 1358 contributes to the increase of the fill factor of the waveguide 1340. Larger aspect ratios and fill factors for high fill factor waveguides can be achieved by etching the waveguide to change the shape of the waveguide body. The larger aspect ratio and fill factor of the high fill factor waveguides in the array 1314 may provide further beam collimation and/or more beam divergence reduction compared to the smaller aspect ratio of the waveguide array 1114. The fabrication of such high fill factor waveguides is discussed in conjunction with Figures 14A-14B. However, as shown in perspective view 1302 and cross-sectional view 1306, the shape of waveguide body 1346 approximates a hexagonal mesa. The etching process can form trenches 1356 between adjacent waveguides. The trenches 1356 can reduce the average width of the waveguide, which increases the aspect ratio of the waveguide.

The shape of the trenches 1356 (formed through the etch process) may form a "progressive" tapered shape of the waveguide body 1346, where the tapered shape enhances beam collimation and/or reduces beam divergence. The etching process can vary the taper angle along the longitudinal dimension of the waveguide body 1346 . The shape of the waveguide body 1346 may be characterized as two (or more than two) taper angles. The cross-sectional view 1306 shows that the taper angle near the second waveguide surface 1344 is smaller than the taper angle nearer the first waveguide surface 1342. That is, the taper angle of the light beam exiting from the first waveguide 1340 (via the second waveguide surface 1344 ) may be smaller than the taper angle of the light beam entering the vicinity of the first waveguide 1340 (via the first waveguide surface 1342 ). A reduction in the cone angle (as the beam is transmitted through the waveguide body 1346) may result in further beam collimation and/or an increase in beam divergence. A larger taper angle near the first waveguide surface 1342 (compared to a smaller taper angle near the second waveguide surface 1342) can result in a larger distance between adjacent light entering the waveguide surface (eg, the first waveguide surface 1342) and/or spacing. In some embodiments, the taper angle may vary continuously along the longitudinal dimension of the waveguide body 1346.

These views also show that light emitting structures (eg, light emitting structure 1358) are formed through discontinuous layers of crystalline material. These discontinuities in the GaN of the light emitting structure may at least partially optically isolate the waveguides in the waveguide array 1314. This optical isolation can result in less "light leakage" between physically adjacent waveguides in the waveguide array 1314. Such discontinuities can cause the array of crystalline material structures to act as light emitting structures that increase the fill factor of the waveguide array. The light emitting structures can be formed and/or fabricated through etching processes of crystalline materials.

14A illustrates a semiconductor process 1400 for fabricating the high fill factor waveguide array 1314 of FIG. 13 according to some embodiments. Portions of the discussion regarding semiconductor process 1400 will refer to the high fill factor waveguide array 1314 of FIG. 13 and the process 1200 of FIG. 12A. The semiconductor process 1400 may begin at step 1402 where a layer 1350 of crystalline material is formed on the semiconductor substrate 1304 . Similar to step 1202, an array of crystalline structures may be grown on the layer of crystalline material 1350 deposited on the semiconductor substrate 1304. Thus, the semiconductor material of substrate 1304 may be a crystal growth substrate. Through the etching of the crystalline material layer in the step of process 1400 , the array of crystalline structures is formed into a high fill factor waveguide array 1314 . The waveguide array 1314 includes a first high fill factor waveguide 1340 . The first waveguide 1340 includes a first waveguide surface 1342 and sidewalls 1348 .

A comparison of the illustration of step 1402 with step 1202 shows that for high fill factor embodiments, the initial thickness of the crystalline material layer (eg, crystalline material layer 1350 ) may be greater than the thickness of the corresponding crystalline material layer (eg, crystalline material layer 1350 ) for non-high fill factor embodiments. , the thickness of the crystalline material layer 1150). The increased thickness of the crystalline material layer 1350 can increase the fill factor of the first waveguide 1340 . For example, as shown in step 1403, etching away portions of the crystalline material layer 1350 (with its increased thickness) enables the first waveguide 1340 to be shaped to provide beam divergence as the beam travels through the first waveguide 1340 The greater the degree of reduction. In some embodiments, the increased thickness increases the aspect ratio of the high fill factor embodiment.

At step 1403, a semiconductor etch process is performed on the crystalline material layer 1350. As shown in the illustration of step 1403 , the etching process can selectively remove portions of the crystalline material layer of increased thickness to increase the fill factor of the first waveguide 1340 . In some embodiments, the etching shapes each of the first waveguide 1340 and the other waveguides to form a hexagonal mesa-shaped waveguide body with a bulk light emitting structure on a distal portion of the waveguide body. Etching alters the shape of the waveguide sidewalls 1348 to form the progressively tapered shape of the waveguide body 1346 . The etching process can create trenches 1356 between adjacent waveguides and light emitting structures 1358 . The shape of the waveguide body 1346, the light emitting structure 1358 and the trench 1356 can be changed by changing the etching process.

In some embodiments, the semiconductor substrate 1304 may be a crystalline growth substrate wafer including a growth material such as, but not limited to, Si/AlO ₃ . The crystalline material of the crystalline material layer 1350 may include, but is not limited to, GaN. The crystal structure array is grown on the crystal growth substrate 1304 . The array of crystalline structures includes at least a first crystalline structure 1340 .

Process 1400 may then proceed to step 1404, where an optically reflective layer 1352 may be formed on the array of crystalline structures. Similar to step 1204, a reflective layer 1352 at step 1404 may be formed on the "upper" surface of the layer 1350 of crystalline material. Also similar to step 1204, at step 1404 a first dielectric layer 1322 may be formed over the array of crystalline structures such that each of the crystalline structures (including the first crystalline structure 1340) is interposed between the first dielectric layer 1322 and the between the crystal growth substrates 1304 .

Similar to step 1206, at step 1406, the transfer wafer 1354 may be bonded to the first dielectric layer 1322 such that each of the crystalline material layer 1350, the reflective layer 1352, and the first dielectric layer 1322 is inserted into the crystal growth Between the substrate 1304 and the transfer wafer 1354 . Process 1400 may proceed to step 1408 . Step 1408 may be similar to step 1208 in that the crystal growth substrate 1304 may be removed from the layer of crystalline material 1350 . Also similar to step 1208, at step 1408 the bonded transfer wafer 1354, first dielectric layer 1322 and crystalline material layer 1350 have been rotated 180 ^° (in the plane of the page) such that each of their vertical orientations have been rotated flip.

Similar to step 1210, at step 1410, a semiconductor etch process may be used to remove a portion of the layer 1350 of crystalline material. An etching process can be used to form a second surface on each of the crystalline structures. It should be noted that the etching process performed at step 1410 is performed on the surface of the crystalline material layer 1350 that is opposite to the surface of the crystalline material layer 1350 on which the etching process of step 1403 is performed. Step 1410 shows that in addition to the first waveguide surface 1342 , the first waveguide structure 1340 also includes a second waveguide surface 1344 . The semiconductor etching process may include forming a spherical, convex, or any other lens-like shape for the second waveguide surface 1344 . Similar to step 1212, at step 1412, a second dielectric layer 1324 may be formed on the waveguide array 1314. The second dielectric layer 1324 may cover the second waveguide surface of the waveguide, including but not limited to the second waveguide surface 1344 of the first waveguide 1340 . Therefore, the waveguide can be inserted between the first dielectric layer 1322 and the second dielectric layer 1324 . The structure including the waveguide array 1314 interposed between the first dielectric layer 1322 and the second dielectric layer 1324 may be a semiconductor die (or the entire wafer), such as the second semiconductor die 1320 .

Process 1400 may proceed to step 1414 where, similar to step 1214, transparent substrate layer 1330 may be bonded to second dielectric layer 1324 such that second dielectric layer 1324 is interposed between waveguide array 1314 and second dielectric layer 1324 . At step 1416 , transfer wafer 1354 may be removed from second semiconductor die 1320 .

14B illustrates a method 1420 for fabricating the high fill factor waveguide array 1314 of FIG. 13, according to some embodiments. The method 1420 can include at least part of one or more steps of the semiconductor process 1400 of Figure 14A. The method 1420 begins at block 1422 in which an array of crystalline structures is grown on a layer of crystalline material deposited on a semiconductor substrate. For example, as in step 1402 of process 1400, the crystalline structure forming the waveguide array 1314 may be a layer 1350 of grown crystalline material. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (eg, crystal growth substrate 1304).

At block 1423, portions of the crystalline material layer are removed from the crystalline structure to shape the waveguide body. Portions of the crystalline material may be removed through a semiconductor etch process, as discussed in connection with step 1403 of process 1400 . At block 1424 , a reflective layer (eg, metallization layer 1352 ) may be formed and/or deposited over portions of an array of crystalline structures (eg, waveguide array 1314 ), as shown in the illustration of step 1404 of process 1400 . Similar to step 1404 of process 1400, a first dielectric layer (eg, first dielectric layer 1322) may be formed and/or deposited over portions of the reflective layer and/or the waveguide array. At block 1426, the transfer wafer may be bonded to the first dielectric layer (eg, see step 1406 of process 1400). At block 1428, the semiconductor substrate (eg, crystal growth substrate 1304) may be physically separated from the array of crystalline structures and/or the layer of crystalline material (see step 1408 of process 1400). At block 1430 , portions of the crystalline material are later removed (eg, via an etching process) to form light emitting surfaces (eg, second waveguide surface 1344 ) of each of the waveguides (eg, see step 1410 of process 1400 ) ). It should be noted that the etching process performed at step 1430 is performed on the surface of the crystalline material layer 1350 opposite to the surface of the crystalline material layer 1350 on which the etching process of step 1423 was performed.

At block 1432, a second dielectric layer (eg, second dielectric layer 1324) is formed and/or deposited over the layer of crystalline material (eg, see step 1412 of process 1400). At block 1434, a transparent substrate layer (eg, transparent substrate layer 1330) may be bonded to a second dielectric layer (eg, see step 1414 of process 1400). At block 1436, the transfer wafer may be physically separated from the first dielectric layer (eg, see step 1416 of process 1400). At block 1238, a first semiconductor die comprising an array of light emitting devices is bonded to a second semiconductor die (eg, 1120) comprising an array of waveguides (eg, see step 1218 of process 1200). With baffled ( baffled ) waveguide

FIG. 15 shows a specific example of an array 1514 of crystalline ribbon spacer waveguides. The waveguide embodiments shown in FIG. 15 may be referred to as "baffled" embodiments because the opaque baffle structure that optically isolates each waveguide from adjacent waveguides provides enhanced collimation and/or enhanced collimation of the light beam passing through the waveguides. Divergence is reduced. The optical isolation of the spacer structure also reduces "light leakage" between adjacent waveguides. The waveguide may additionally and/or alternatively include oxide "lens" structures that act as secondary or tertiary optical components that provide even further collimation and/or divergence reduction of the light beam passing through the waveguide. In various specific examples discussed throughout, at least one or both of the semiconductor spacer structures and/or dielectric lens structures discussed in connection with Figures 15-16B may be adapted and additionally deployed in connection with Figures 11B-11B in any of the specific examples discussed in 14B.

As shown in FIG. 15 , the crystalline waveguide 1514 includes a first waveguide 1540 . Similar to the other waveguides discussed throughout, the first waveguide 1540 includes a first waveguide surface 1542 for the light of the LED to enter the waveguide body 1546 of the first waveguide 1540 . The waveguide body 1546 transmits light from the first waveguide surface 1542 to the second waveguide surface 1544 (which is a flat surface in Figure 15). Similar to the other specific examples discussed throughout, the second waveguide surface 1544 may emit a light beam (with its reduced beam divergence) out of the waveguide body 1546 . As discussed further below, the emitted beam may enter the dielectric lens structure 1560 for further beam shaping (eg, collimation and/or divergence reduction).

The dielectric lens structure 1560 may include a transparent dioxide material such as, but not limited to, SiO ₂ . Therefore, the dielectric lens structure 1560 may be a dioxide lens structure. In other embodiments, the dielectric material used to fabricate the dielectric lens structure 1560 may be silicon nitride. Due to the difference between the refractive index of the semiconductor material of the waveguide body 1546 and the refractive index of the dielectric material of the dielectric lens structure 1560 (eg, silicon dioxide or silicon nitride), light can be refracted through the lens structure 1560 and/or or lensing. As shown in FIG. 15, at least one surface of the dielectric lens structure 1560 (eg, the second lens surface 1564 serving as the light emitting surface of the lens 1560) may have a shape similar to a spherical and/or convex lens. Another surface of the dielectric lens structure 1560 (eg, the first lens surface 1562 serving as the lens light entry surface) can be a flat surface to mate with the light emitting surface of the first waveguide 1540 (eg, the second waveguide surface 1544). Light emitted by the second waveguide surface 1544 may be received by the first lens surface 1562 , pass through the lens structure 1560 and be emitted by the second lens surface 1564 . Accordingly, the lens structure 1560 can further shape the profile of the light beam emitted by the first waveguide 1540, eg, the lens structure 1560 can further collimate and/or reduce the divergence of the light beam of the LED. It should be noted that the dielectric lens structure 1560 can act as a passivation layer for the first waveguide 1540 . One or more spacer structures (eg, first spacer structure 1582 and second spacer structure 1584 ) can be formed from semiconductor material layer 1550 (or a secondary dielectric layer, such as, but not limited to, the second dielectric layer of FIG. 11B ) 1124 and/or the second dielectric layer 1324 of FIG. 14A) extend and/or protrude. As discussed below, the baffle structure can be used to further optically isolate and/or shape the beam profile (eg, increase collimation and/or reduce beam divergence). Although shown in FIG. 15 as two separate spacer structures, the first spacer structure 1582 and the second spacer structure 1584 may be a single 3D spacer structure extending into and out of the page.

The spacer structures (the first spacer structure 1582 and the second spacer structure 1584 ) may include opaque semiconductor materials such as, but not limited to, silicon (Si). The opaque semiconductor material may be an optically absorbing material, at least for the frequencies emitted by the LED. The baffle structure of the waveguides can be used to effectively absorb the portion of the light beam (emitted by the waveguide) that will "interfere" with the light beam emitted by adjacent waveguides. That is, the baffle structure further collimates the beam emitted by the waveguide by removing portions of the beam near the edge of the beam profile that still fall outside the desired emission cone for various applications using LEDs as light sources.

As mentioned above, the waveguide may additionally and/or alternatively include a dielectric lens structure (eg, dielectric lens structure 1560) aligned with the light emitting surface of the waveguide (second waveguide surface 1544 of the first waveguide 1540). The dielectric lens structure may include an optically transparent semiconductor material (eg, a dielectric material) that refracts incident light such that the beam divergence of the incident light beam is reduced as it travels through the lens structure. The dielectric material may be a dioxide such as, but not limited to, silicon dioxide (SiO ₂ ). Thus, the dielectric lens may be an oxide lens. Alignment of the dielectric lens structures with their corresponding waveguides allows the lens structures to receive light beams emitted from the light emitting surfaces of the waveguides. As discussed throughout, the angular divergence of light emitted by the emitting surface of the waveguide has been significantly reduced by its passage through the waveguide body. The light beam emitted by the waveguide is transmitted through (and refracted by) the dielectric lens structure for further collimation and/or divergence reduction. The dielectric lens structures can act as spherical and/or convex lenses to further collimate and/or reduce beam divergence. That is, the dielectric lens structure can act as a collimating secondary optical component for the combination of the LED and semiconductor waveguide (or as a tertiary optical component for the LED).

16A illustrates a semiconductor process 1600 for fabricating the spacer waveguide array 1514 of FIG. 15, according to some embodiments. Portions of the discussion of semiconductor process 1600 will refer to spaced waveguide array 1514 of FIG. 15 and process 1200 of FIG. 12A and/or process 1400 of FIG. 14A. For example, process 1200 and/or process 1400 may be adapted to include semiconductor spacer structures (first spacer structure 1582 and second spacer structure 1584) and/or dielectric lenses for the waveguides in the corresponding waveguide arrays structure (dielectric lens structure 1560).

The semiconductor process 1600 may begin at step 1602 where a layer 1550 of crystalline material is formed on the semiconductor substrate 1504 . Similar to step 1202 of process 1200, an array of crystalline structures may be grown on layer 1550 of crystalline material deposited on semiconductor substrate 1504. Thus, the semiconductor material of substrate 1504 may be a crystal growth substrate. The semiconductor substrate 1504 may be a semiconductor wafer. The semiconductor material of substrate 1504 may be an optically opaque and/or optically absorbing material such as, but not limited to, silicon (Si). The semiconductor substrate 1504 can be a silicon wafer. The array of crystalline structures is formed through the steps of process 1600 into an array of spaced waveguides 1514 . The waveguide array 1514 includes a first baffled waveguide 1540 . The first waveguide 1540 includes a first waveguide surface 1542 , a waveguide body 1546 , and sidewalls 1548 surrounding the waveguide body 1546 .

At step 1604 (and similar to step 1204 of process 1200), an optically reflective layer 1552 may be formed on the array of crystalline structures. The reflective layer 1552 formed at step 1604 may be formed on the "upper" surface of the crystalline material layer 1550. Also similar to step 1204, at step 1604, a first dielectric layer 1522 may be formed over the array of crystalline structures such that the body of each of the crystalline structures (including the waveguide body 1546 of the first crystalline structure 1540) is inserted into the first crystalline structure 1540. Between a dielectric layer 1522 and the semiconductor substrate 1504 . Note that for the first waveguide 1140 in the waveguide array 1114 (see, eg, FIG. 12A ), a thin portion of the first dielectric layer covers the flat first waveguide surface 1142 of the first waveguide 1140 . In contrast, the first dielectric layer 1522 of the baffled waveguide array 1514 (eg, see FIG. 15 ) does not cover the flat first waveguide surface 1542 of the first waveguide 1540 . Specific examples may vary, and in some specific examples (eg, first waveguide 1140, first waveguide 1340, and first waveguide body 1540), an optically transparent first dielectric layer (eg, first dielectric layer 1122, A dielectric layer 1322 and first dielectric layer 1522) can completely cover light entering the first waveguide surfaces (eg, first waveguide surface 1142, first waveguide surface 1342, and first waveguide surface 1542). In other embodiments, the first dielectric layer may only partially cover or not cover the first waveguide surface of the waveguide at all.

Process 1600 proceeds to step 1606 where an etching process is performed on semiconductor substrate 1504 . As shown in the illustration of step 1606, a semiconductor etch process selectively removes portions of the semiconductor substrate 1504 from the layer of semiconductor material 1550. The etching process exposes the light emitting surface of each of the waveguides. For example, for the first waveguide 1540, the second waveguide surface 1544 is exposed. The second waveguide surface 1544 will be the light emitting surface of the first waveguide 1540 . In this particular example, each of the first waveguide surface 1542 and the second waveguide surface 1544 of the first waveguide 1540 is a flat surface. In contrast and as shown in Figure 12A, for the first waveguide 1140 in the waveguide array 1114, only the first waveguide surface 1142 is a flat surface. The second waveguide surface 1144 (eg, the light emitting surface) of the first waveguide 1140 is a curved surface. Any of the specific examples discussed herein may include a flat light emitting surface (eg, the second waveguide surface of the waveguide).

Portions of the opaque (or opaque) semiconductor substrate 1504 that are not removed by the etch process form opaque spacer structures that optically isolate each of the waveguides from its adjacent waveguides. As shown in step 1606, the first spacer structure 1582 and the second spacer structure 1584 optically isolate the first waveguide 1540 from the other waveguides in the waveguide array 1514. Because the first spacer structure 1582 and the second spacer structure 1584 are oriented along the longitudinal dimension of the first waveguide 1540, the spacer structure can be used to further collimate light emitted by the second surface 1544 of the first waveguide 1540 and/or reduce the beam divergence of the light. Although not shown in the 2D plane of FIG. 16A, the baffle structure may be a 3D baffle structure that completely surrounds the light beam emitted for the second waveguide surface 1544 of the first waveguide 1540. In some embodiments, the first spacer structure 1582 and the second spacer structure 1584 can form a 3D continuous spacer structure surrounding the light beam emitted by the first waveguide 1540 .

Similar to step 1212, in step 1608, a second dielectric layer 1524 may be formed on the waveguide array 1514. The second dielectric layer 1524 may cover the second waveguide surface, such as the light emitting surface of the waveguide, including but not limited to the second waveguide surface 1544 of the first waveguide 1540 . As shown in the illustration of step 1608, the second dielectric layer 1524 may substantially encapsulate the spacer structures (eg, the first spacer structure 1582 and the second spacer structure 1584).

Process 1600 may proceed to step 1610 . The vertical (or longitudinal) orientation of waveguide array 1514 has been flipped for illustrating step 1610, at least for clarity. At step 1610, an etching process may be performed on the second dielectric layer 1524. The etching process can be specific to the oxide material (eg, SiO ₂ ) of the second dielectric layer 1524 . That is, the etch process of step 1608 may not significantly etch (or remove) the semiconductor material (eg, Si) or the semiconductor material layer 1550 of the spacer structures (eg, the first spacer structure 1582 and the second spacer structure 1584 ) of semiconductor materials and/or waveguides (eg, GaN). An etch process may be performed to remove portions of the second dielectric layer 1524 such that for each of the waveguides (eg, the first baffled waveguide 1540 ), only the dielectric lens structures (eg, the dielectric lens structures 1560 ) remain ).

16B illustrates a method 1620 for fabricating the baffled waveguide array 1514 of FIG. 15, according to certain embodiments. The method 1620 can include at least part of one or more steps of the semiconductor process 1600 of FIG. 16A. Method 1620 begins at block 1622 with growing an array of crystalline structures on a layer of crystalline material deposited on a semiconductor substrate. Similar to step 1602 of process 1600 of FIG. 16A, the crystalline structure forming waveguide array 1514 may be a layer 1550 of grown crystalline material. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (eg, crystal growth substrate 1504).

At block 1624, a reflective layer (eg, metallization layer 1552) may be formed and/or deposited over portions of an array of crystalline structures (eg, array of waveguides 1514). Similar to step 1204 of process 1200, a first dielectric layer (eg, first dielectric layer 1522) may be formed and/or deposited over portions of the reflective layer and/or the waveguide array. As shown in step 1604 of process 1600, the reflective layer may provide at least partial optical isolation of each waveguide in the array of waveguides from each of the other waveguides.

At block 1626, portions of the semiconductor substrate are removed (eg, via a semiconductor etching process performed on the semiconductor substrate) to form one or more spacer structures for the light emitting surface of each waveguide in the array of waveguides. For example, as shown in the illustration of step 1606 of process 1600, first spacer structure 1582 and second spacer structure 1584 may be formed by etching semiconductor substrate 1504 to block (or constrain) the first spacer structure 1584 through an absorption process Light emitted by the second waveguide surface 1544 of the waveguide 1540. At block 1628 and as shown in the illustration of step 1608 of process 1600, a second dielectric layer may be formed to cover the crystalline material layer (eg, crystalline material layer 1550) and/or the light emitting surface of the waveguide (eg, the first a second waveguide surface 1544 of a waveguide 1540). At block 1630 and as shown in the illustration of step 1610 of process 1600, portions of the second dielectric layer are removed (eg, via an etch process performed on the second dielectric layer) to form use in a waveguide array One or more dielectric lens structures on the light emitting surface of each waveguide. For example, as shown in the illustration of step 1610 of process 1600 , a dielectric lens structure 1560 may be formed by etching the second dielectric layer 1524 for beams emitted through the flat second waveguide surface 1544 of the first waveguide 1540 reshape. Embossing Tools for Fabricating Waveguide Arrays

Various specific examples may include making "soft" or "hard" stamping and/or embossing tools. This embossing tool can be used to fabricate in materials other than the crystalline material (eg, GaN) used to grow the crystalline structure comprising the waveguide body via imprinting and/or embossing processes (eg, nanoimprint lithography processes) waveguide. For example, such tools can be used to imprint and/or emboss waveguides similar to those discussed herein in amorphous materials (eg, silica or another refractive material). Processes 1760 and 1780 of Figures 17A-17B relate to making "soft" stamping and/or embossing tools. Processes 1860 and 1880 of Figures 18A-18B relate to making "hard" stamping and/or embossing tools.

17A illustrates a semiconductor process 1760 for fabricating a soft embossing tool 1700 for embossing waveguide arrays in amorphous materials, according to some embodiments. Portions of the discussion regarding semiconductor process 1760 will refer to waveguide array 1114 of FIG. 11B and process 1200 of FIG. 12A. Semiconductor process 1760 may begin at step 1762 where a layer 1750 of crystalline material is formed on semiconductor substrate 1704 . Similar to step 1202 of process 1200, an array of crystalline structures 1714 may be grown on a layer of crystalline material 1750 deposited on semiconductor substrate 1704. Thus, the semiconductor material of substrate 1704 may be a crystal growth substrate. The shape of the array of crystalline structures 1714 is similar to the array of waveguides 1114 due to the crystal growth process. Therefore, the shape of the crystal structures is substantially uniform throughout the crystal structure array 1714 based on the crystal growth process. Process 1760 includes “transferring” the shape of the array of crystalline structures 1714 (and thus the shape of the waveguide array 1114 of FIG. Accordingly, reference point 1702 is shown in the diagram of the steps of process 1760 to track the transfer of the shape of crystalline structure array 1714 to soft embossing tool 1700 .

At step 1764, a layer 1706 of elastic (or "soft") material may be formed (or deposited) on the array 1714 of crystalline structures. In some non-limiting embodiments, the elastic material layer 1706 may be a polymer layer, such as, but not limited to, a polysiloxane (or polysiloxane-like) material layer. In some specific examples, the elastic material layer 1706 may include polydimethylsiloxane (PDMS). Note the reference point 1702 in the illustration of step 1764. Because the elastic material layer 1706 "mates" with the crystalline structure array 1714, the shape of the elastic material layer 1706 is complementary to the shape of the crystalline structure array 1714. At step 1766, transfer wafer 1754 may be bonded to elastic material layer 1706.

At step 1768 , the semiconductor substrate 1704 and the array of crystalline structures 1714 may be removed from the layer of elastic material 1706 (physically separating the semiconductor substrate and array of crystalline structures from the layer of elastic material) to form a soft embossing tool 1700 . The embossing tool 1700 may include a layer of elastic material 1706 having a shape complementary to that of the waveguide array 1114 of Figure 11B. In some embodiments, the embossing tool may also include transfer wafer 1754 . In other embodiments, the layer of elastic material 1706 can be transferred to another rigid body (eg, another wafer). The vertical orientation of elastic material layer 1706 and transfer wafer 1754 has been flipped in the illustration of step 1768 for clarity. Because the embossing tool 1700 (eg, the layer of elastic material 1706 ) has a complementary shape to the waveguide array 1114 of FIG. 11B , the embossing tool 1700 is used to emboss a waveguide material (eg, a material with waveguide properties and/or a material that refracts light) ) will result in a waveguide shaped as the waveguide array 1114.

17B illustrates a method 1780 for fabricating the soft imprint tool 1700 of FIG. 17A, according to some embodiments. The method 1780 can include at least part of one or more steps of the semiconductor process 1760 of Figure 17A. Method 1780 begins at block 1782 with growing an array of crystalline structures on a layer of crystalline material deposited on a semiconductor substrate. For example, as in step 1762 of process 1760, the crystalline structure forming the crystalline structure array 1714 may be a layer of crystalline material 1750 grown. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (eg, crystal growth substrate 1704).

At block 1784 and similar to step 1764 of process 1760, an elastic material layer (eg, elastic material layer 1706) may be formed (or deposited) on the array of crystalline structures. At block 1786 and similar to step 1766 of process 1760, a transfer wafer (eg, transfer wafer 1754) may be bonded to the layer of elastic material. At block 1788 and similar to step 1768, a soft embossing tool (eg, soft embossing tool 1700) may be formed by removing the semiconductor substrate and the array of crystalline structures from the layer of elastic material. At block 1790, a soft embossing tool may be used to form an array of waveguides (eg, via a nanoimprint lithography process). At block 1792, an array of waveguides can be used to fabricate a light source.

18A illustrates a semiconductor process 1860 for fabricating a hard embossing tool 1800 for embossing waveguide arrays in amorphous materials, according to some embodiments. Portions of the discussion regarding semiconductor process 1860 will refer to the waveguide array 1114 of FIG. 11B and the process 1200 of FIG. 12A. Semiconductor process 1860 may begin at step 1862 where a layer 1850 of crystalline material is formed on semiconductor substrate 1804 . Similar to step 1202 of process 1200, an array of crystalline structures 1814 may be grown on a layer of crystalline material 1850 deposited on a semiconductor substrate 1804. Thus, the semiconductor material of substrate 1804 may be a crystal growth substrate. The shape of the array of crystalline structures 1814 is similar to the array of waveguides 1114 due to the crystal growth process. Therefore, the shape of the crystal structures is substantially uniform throughout the crystal structure array 1814 based on the crystal growth process. Process 1860 includes “transferring” the shape of crystalline structure array 1814 (and thus the shape of waveguide array 1114 ) to hard embossing tool 1800 . Accordingly, reference point 1802 is shown in the diagram of the steps of process 1860 to track the transfer of the shape of crystalline structure array 1804 to hard embossing tool 1800 .

At step 1864, a layer of photoresist material 1806 may be formed (deposited) on the array of crystalline structures 1814. Note the reference point 1802 in the illustration of step 1864. Because the photoresist layer 1806 "mates" with the crystalline structure array 1814, the shape of the photoresist layer 1806 is complementary to the shape of the crystalline structure array 1814. Instead of soft and/or elastic materials (eg, PDMS as used at step 1764 of process 1760 of FIG. 17A ), a photoresist material may be used at step 1864 such that one or more A "hard" layer (eg, a metal layer) (eg, see steps 1870 and 1874 of process 1860). At step 1866, the first transfer wafer 1854 can be bonded to the photoresist layer 1806.

At step 1868, the semiconductor substrate 1804 and the array of crystalline structures 1814 may be removed from the photoresist layer 1806 (or physically separated from the photoresist layer). It should be noted that the vertical orientation of the first transfer wafer 1854 and the photoresist layer 1806 has been flipped in the illustration of step 1868 . At step 1870 , a first “hard” material layer 1808 may be formed from the photoresist layer 1806 . The hard material of the first hard material layer 1808 may be a first metal, such as, but not limited to, copper (Cu). Therefore, the first hard layer 1808 may be the first metal layer. Because the first metal layer 1808 cooperates with the photoresist layer 1806 , the shape of the first hard metal layer 1808 can be complementary to the shape of the photoresist layer 1806 . That is, the shape of the first metal layer 1808 is complementary to the complementary shape of the array of crystalline structures 1814 , that is, the shape of the array of crystalline structures 1814 , which is the shape of the waveguide array fabricated by the hard embossing tool 1800 . In order to emboss the waveguide array, it may be necessary to emboss the shape of the tool similar to the shape of the waveguide array to be embossed. Accordingly, the shape of the photoresist layer 1806 may be required by the embossing tool 1800. Accordingly, the shape of the first metal layer 1808 can be transferred to the second metal layer (eg, see second metal layer 1810 of step 1874). Also at step 1870, the second transfer wafer 1856 can be bonded to the first metal layer 1808.

At step 1872, the first transfer wafer 1854 and the photoresist layer 1806 may be removed from the first metal layer 1808. It should be noted that in the illustration of step 1872, the vertical orientations of the second transfer wafer 1856 and the first metal layer 1808 have been flipped. At step 1874, the shape of the first metal layer can be transferred to the second metal layer. For example, the second metal layer 1810 may be formed from the first metal layer 1808 . In a non-limiting specific example, the second metal layer may include a second metal, such as, but not limited to, nickel. Because the second metal layer 1810 cooperates with the first metal layer 1808, the shape of the second metal layer 1810 is complementary to the shape of the first metal layer 1808 (eg, a shape complementary to the shape of the waveguide array to be embossed). Also at step 1874, the third transfer wafer 1858 can be bonded to the second metal layer 1810.

At step 1876 , a hard embossing tool 1800 may be formed by removing the second transfer wafer 1856 and the first metal layer 1808 from the second metal (or hard) layer 1810 . Again, the vertical orientations of the third transfer wafer 1858 and the second metal layer 1810 have been flipped for clarity. Thus, the hard transfer tool may include the second metal layer 1810 and the third transfer wafer 1858 (or another rigid body). A hard embossing tool can be used to emboss or imprint the waveguide array in a manner similar to that of the soft embossing tool 1700 .

18B illustrates a method 1880 for manufacturing the hard imprint tool 1800 of FIG. 18A , according to some embodiments. The method 1880 can include at least part of one or more steps of the semiconductor process 1860 of Figure 18A. Method 1880 begins at block 1882 with growing an array of crystalline structures on a layer of crystalline material deposited on a semiconductor substrate. For example, as in step 1862 of process 1860, the crystalline structure forming the array of crystalline structures 1814 may be a layer of crystalline material 1850 grown. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (eg, crystal growth substrate 1804).

At block 1884 and similar to step 1864 of process 1860, a photoresist layer (eg, elastic material layer 1806) may be formed (or deposited) on the array of crystalline structures. Thus, at block 1884, the complementary shape of the shape of the array of crystalline structures can be transferred to the photoresist layer. At block 1886 and similar to step 1866, a first transfer wafer (eg, first transfer wafer 1854) may be bonded to the photoresist layer. At block 1888 and similar to step 1868, the semiconductor substrate and array of crystalline structures may be removed from the resist layer. At block 1890 and similar to step 1870, a first metal layer (eg, first metal layer 1808) may be formed and/or deposited on the photoresist layer. Thus, at block 1890, a complementary shape to the shape of the layers of the photoresist layer can be transferred to the first metal layer. Also at block 1890, a second transfer wafer (eg, second transfer wafer 1856) may be bonded to the first metal layer. At block 1892 and similar to step 1872, the first transfer wafer and photoresist layer may be removed from the first metal layer.

At step 1894 and similar to step 1874, a second metal layer (eg, second metal layer 1810) may be formed on the first metal layer. Thus, at block 1894, the complementary shape of the shape of the first metal layer can be transferred to the second metal layer. Also at block 1894, a third transfer wafer (eg, third transfer wafer 1858) may be bonded to the second metal layer. At block 1896, a hard embossing tool (eg, hard embossing tool 1800) may be formed by removing the second transfer wafer and the first metal layer from the second metal layer. artificial reality system

The specific examples disclosed herein may be used to implement components of an artificial reality system, or may be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been adjusted in some way before being presented to the user, which may include, for example, virtual reality, augmented reality, mixed reality, mixed reality, or some combination thereof and/or derivative. Artificial reality content may include generated content entirely or in combination with captured (eg, real-world) content. The artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of these may be presented in a single channel or in multiple channels (such as stereo video with a three-dimensional effect to the viewer). Additionally, in some embodiments, artificial environments may also be associated with applications used, for example, to generate content in artificial environments and/or otherwise be used in artificial environments (eg, to perform activities in artificial environments). , products, accessories, services, or some combination thereof. An augmented reality system that provides augmented reality content may be implemented on a variety of platforms, including HMDs connected to host computer systems, stand-alone HMDs, mobile devices or computing systems or capable of providing augmented reality content to one or more viewers any other hardware platform.

19 is a simplified block diagram of an example electronic system 1900 for implementing an example near-eye display (eg, an HMD device) of some examples disclosed herein. The electronic system 1900 may be used as the electronic system of an HMD device or other near-eye displays described above. In this example, electronic system 1900 may include one or more processors 1910 and memory 1920. The processor 1910 may be configured to execute instructions for performing operations at several components, and may be, for example, a general-purpose processor or microprocessor suitable for implementation within a portable electronic device. The processor 1910 may be communicatively coupled with various components within the electronic system 1900. To achieve this communicative coupling, the processor 1910 can communicate across the bus 1940 with other illustrated components. Bus 1940 may be any subsystem suitable for communicating data within electronic system 1900. Bus 1940 may include a plurality of computer buses and additional circuitry to communicate data.

Memory 1920 may be coupled to processor 1910 . In some embodiments, memory 1920 can provide both short-term storage and long-term storage, and can be divided into cells. Memory 1920 may be volatile, such as static random access memory (SRAM) and/or dynamic random access memory (DRAM), and/or non-volatile, such as read-only memory Body (read-only memory; ROM), flash memory and the like. Additionally, the memory 1920 may include removable storage devices, such as secure digital (SD) cards. Memory 1920 may provide storage of computer-readable instructions, data structures, program modules, and other data for electronic system 1900. In some embodiments, memory 1920 may be distributed among different hardware modules. A set of instructions and/or code may be stored on memory 1920 . The instructions may be in the form of executable code executable by electronic system 1900, and/or may be in the form of source code and/or installable code that is compiled and/or installed /or may be in the form of executable code after being installed on electronic system 1900 (eg, using any of a variety of commonly used compilers, installers, compression/decompression utilities, etc.).

In some embodiments, memory 1920 may store a plurality of application modules 1922-1924, which may include any number of applications. Examples of applications may include gaming applications, conferencing applications, video playback applications, or other suitable applications. Such applications may include depth-sensing functionality or eye-tracking functionality. Application modules 1922-1924 may include specific instructions to be executed by processor 1910. In some embodiments, certain applications or portions of application modules 1922-1924 may be executed by other hardware modules 1980. In some embodiments, memory 1920 may additionally include secure memory, which may include additional security controls to prevent copying or other unauthorized access to secure information.

In some embodiments, memory 1920 may include an operating system 1925 loaded therein. Operating system 1925 is operable to initiate execution of instructions provided by application modules 1922-1924 and/or to manage other hardware modules 1980, and to interface with wireless communication subsystem 1930, which may include one or more wireless transceivers . Operating system 1925 may be adapted to perform other operations across components of electronic system 1900, including threading, resource management, data storage control, and other similar functionality.

Wireless communication subsystem 1930 may include, for example, infrared communication devices, wireless communication devices and/or chipsets (such as Bluetooth® devices, IEEE 802.11 devices, Wi-Fi devices, WiMax devices, cellular communication facilities, etc.) and/or similar communications interface. Electronic system 1900 may include one or more antennas 1934 for wireless communication, either as part of wireless communication subsystem 1930 or as a separate component coupled to any part of the system. Depending on the desired functionality, the wireless communication subsystem 1930 may include separate transceivers to communicate with base transceiver stations and other wireless devices and access points, which may include communication with, for example, a wireless wide-area network (WWAN) , wireless local area network (WLAN) or wireless personal area network (WPAN) communication over different data networks and/or network types. The WWAN may be, for example, a WiMax (IEEE 802.16) network. The WLAN may be, for example, an IEEE 802.11x network. The WPAN may be, for example, a Bluetooth network, IEEE 802.15x, or some other type of network. The techniques described herein may also be used for any combination of WWAN, WLAN, and/or WPAN. Wireless communication subsystem 1930 may permit the exchange of data with networks, other computer systems, and/or any other devices described herein. Wireless communication subsystem 1930 may include components for transmitting or receiving data, such as HMD device identifiers, location data, geographic maps, heat maps, photos, or video, using antenna 1934 and wireless link 1932. Wireless communication subsystem 1930, processor 1910, and memory 1920 may together include at least a portion of one or more of the components for performing some of the functions disclosed herein.

Embodiments of electronic system 1900 may also include one or more sensors 1990. Sensors 1990 may include, for example, image sensors, accelerometers, pressure sensors, temperature sensors, proximity sensors, magnetometers, gyroscopes, inertial sensors (eg, a combination of accelerometers and gyroscopes). module), ambient light sensor, or any other similar module operable to provide sensing output and/or receive sensing input, such as a depth sensor or a position sensor. For example, in some implementations, sensors 1990 may include one or more inertial measurement units (IMUs) and/or one or more position sensors. The IMU may generate calibration data indicative of the estimated position of the HMD device relative to the initial position of the HMD device based on measurement signals received from one or more of the position sensors. The position sensor may generate one or more measurement signals in response to movement of the HMD device. Examples of position sensors may include, but are not limited to, one or more accelerometers, one or more gyroscopes, one or more magnetometers, another suitable type of sensor that detects motion, errors for IMUs A type of sensor that is calibrated, or any combination thereof. The position sensors may be located external to the IMU, internal to the IMU, or any combination of external and internal. At least some sensors may use structured light patterns for sensing.

Electronic system 1900 may include display module 1960 . The display module 1960 can be a near-eye display and can graphically present information such as images, videos, and various commands from the electronic system 1900 to the user. This information may originate from one or more application modules 1922-1924, virtual reality engine 1926, one or more other hardware modules 1980, combinations thereof, or used to parse graphical content for the user (eg, by means of by any other suitable component of the operating system 1925). Display module 1960 may use LCD technology, LED technology (including, for example, OLED, ILED, μ-LED, AMOLED, TOLED, etc.), light emitting polymer display (LPD) technology, or some other display technology.

The electronic system 1900 may also include a user input/output module 1970 . The user input/output module 1970 may allow the user to send action requests to the electronic system 1900 . An action request may be a request to perform a specific action. For example, an action request can be to start or end an application or to perform a specific action within the application. User input/output module 1970 may include one or more input devices. Example input devices may include touchscreens, trackpads, microphones, buttons, dials, switches, keyboards, mice, game controllers, or any other means for receiving motion requests and communicating the received motion requests to electronic system 1900 other suitable devices. In some embodiments, the user input/output module 1970 can provide haptic feedback to the user according to instructions received from the electronic system 1900 . For example, haptic feedback may be provided when an action request is received or performed.

The electronic system 1900 may include a camera 1950, which may be used to capture a photo or video of the user, eg, for tracking the position of the user's eyes. The camera 1950 can also be used to capture photos or videos of the environment, such as for VR, AR or MR applications. Camera 1950 may include, for example, a complementary metal oxide semiconductor (CMOS) image sensor having millions or tens of millions of pixels. In some implementations, camera 1950 may include two or more cameras that may be used to capture 3D imagery.

In some embodiments, electronic system 1900 may include a plurality of other hardware modules 1980 . Each of the other hardware modules 1980 may be physical modules within the electronic system 1900 . While each of the other hardware modules 1980 may be permanently configured as a structure, some of the other hardware modules 1980 may be temporarily configured to perform specific functions or activated temporarily. Examples of other hardware modules 1980 may include, for example, audio output and/or input modules (eg, microphones or speakers), near field communication (NFC) modules, rechargeable batteries, battery management systems, wired /Wireless battery charging system, etc. In some embodiments, one or more functions of the other hardware modules 1980 may be implemented in software.

In some embodiments, the memory 1920 of the electronic system 1900 may also store the virtual reality engine 1926. The virtual reality engine 1926 executes applications within the electronic system 1900 and receives the HMD device's position information, acceleration information, velocity information, predicted future position, or any combination thereof from various sensors. In some embodiments, the information received by the virtual reality engine 1926 may be used to generate signals (eg, display commands) for the display module 1960. For example, if the received information indicates that the user has looked to the left, the virtual reality engine 1926 may generate content for the HMD device that reflects the user's movement in the virtual environment. Additionally, the virtual reality engine 1926 may perform in-application actions in response to action requests received from the user input/output module 1970 and provide feedback to the user. The feedback provided can be visual feedback, auditory feedback or haptic feedback. In some implementations, the processor 1910 may include one or more GPUs that can execute the virtual reality engine 1926.

In various implementations, the above-described hardware and modules can be implemented on a single device or on multiple devices that can communicate with each other using wired or wireless connections. For example, in some implementations, some components or modules such as the GPU, virtual reality engine 1926, and applications (eg, tracking applications) may be implemented on a console that is connected to a head-mounted display device separation. In some embodiments, one console can connect to or support more than one HMD.

In alternate configurations, different components and/or additional components may be included in electronic system 1900 . Similarly, the functionality of one or more of the components may be distributed among the components in ways other than those described above. For example, in some specific instances, electronic system 1900 may be modified to include other system environments, such as AR system environments and/or MR environments.

The methods, systems, and devices discussed above are examples. Various specific examples may omit, substitute or add various procedures or components as appropriate. For example, in alternate configurations, the methods described may be performed in an order different from that described, and/or various stages may be added, omitted, and/or combined. Also, features described with respect to certain specific examples may be combined in various other specific examples. Different aspects and elements of the specific examples may be combined in a similar manner. Also, technology evolves, and thus many elements are examples that do not limit the scope of the invention to those specific examples.

Specific details are given in the description to provide a thorough understanding of specific examples. However, specific examples may be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring specific examples. This specification provides example specifics only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the preceding description of specific examples will provide those of ordinary skill in the art with an enabling description for implementing various specific examples. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the invention.

Also, some specific examples are described as processes, which are depicted as flow diagrams or block diagrams. Although each may describe the operations as a sequential process, many of the operations may be performed in parallel or concurrently. Furthermore, the sequence of operations can be reconfigured. The process may have additional steps not included in the figures. Furthermore, embodiments of the methods may be implemented by hardware, software, firmware, intermediate software, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, intermediate software, or microcode, the code or code segments to perform the associated tasks may be stored in a computer-readable medium, such as a storage medium. A processor may perform associated tasks.

It will be apparent to those of ordinary skill in the art that substantial changes may be made to particular requirements. For example, custom or dedicated hardware may also be used, and/or particular elements may be implemented in hardware, software (including portable software such as applets, etc.), or both. Additionally, connections to other computing devices, such as network input/output devices, may be used.

Referring to the figures, components that may include memory may include non-transitory machine-readable media. The terms "machine-readable medium" and "computer-readable medium" may refer to any storage medium that participates in providing data that causes a machine to operate in a particular manner. In the specific examples provided above, various machine-readable media may be involved in providing instructions/code to processing units and/or other devices for execution. Additionally or alternatively, machine-readable media may be used to store and/or carry such instructions/code. In many implementations, the computer-readable medium is a physical and/or tangible storage medium. This medium can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and/or optical media, such as compact disk (CD) or digital versatile disk (DVD); punched cards; paper tape; any Other physical media; RAM; programmable read-only memory (PROM); erasable programmable read-only memory (EPROM); FLASH-EPROM; any other A memory chip or cartridge; a carrier wave as described below; or any other medium from which a computer can read instructions and/or code. A computer program product may include code and/or machine-executable instructions, which code and/or machine-executable instructions may represent programs, functions, subroutines, programs, routines, applications (Apps), subroutines , modules, packages, classes, or any combination of commands, data structures, or program statements.

Those of ordinary skill in the art would understand that the information and signals used to convey the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof and chips.

As used herein, the terms "and" and "or" can include a variety of meanings that are also intended to depend, at least in part, on the context in which these terms are used. Typically, "or", when used in relation to a list (such as A, B, or C), is intended to mean A, B, and C (used here in an inclusive sense), and A, B, or C (used here in an exclusive sense) meaning use). Also, as used herein, the term "one or more" may be used to describe any feature, structure or characteristic in the singular or may be used to describe some combination of features, structures or characteristics. It should be noted, however, that this is merely an illustrative example and the claimed subject matter is not limited to this example. Furthermore, the term "at least one of" when used in relation to a list (such as A, B, or C) can be interpreted to mean any combination of A, B, and/or C, such as A, AB, AC , BC, AA, ABC, AAB, AABBCCC, etc.

Additionally, while some specific examples have been described using specific combinations of hardware and software, it should be recognized that other combinations of hardware and software are possible. Certain specific examples may be implemented in hardware only, or only in software, or using a combination thereof. In one example, software may be implemented by a computer program product containing computer code or instructions executable by one or more processors for carrying out the descriptions in this disclosure Any or all of the steps, operations or processes, wherein the computer program can be stored on a non-transitory computer-readable medium. The various processes described herein can be implemented on the same processor or on different processors in any combination.

Where a device, system, component or module is described as being configured to perform certain operations or functions, this configuration can be achieved, for example, by designing electronic circuits to perform the operations, by programming programmable electronic circuits (such as a microprocessor) to perform operations (such as by executing computer instructions or code), or a processor or core programmed to execute code or instructions stored on a non-transitory memory medium, or any combination thereof. Processes may communicate using a variety of techniques, including but not limited to conventional techniques for inter-process communication, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense. It will be apparent, however, that additions, subtractions, deletions and other modifications and changes may be made to the present invention without departing from the broader spirit and scope as set forth in the scope of the claims. Therefore, although specific specific examples have been described, these specific examples are not intended to be limiting. Various modifications and equivalents are within the scope of the following claims.

From the foregoing, it will be seen that the present invention is an invention well suited to achieve all of the objects and objectives set forth above, along with other advantages which are evident and inherent in the system and method. It should be understood that certain features and subcombinations have utility and can be used without reference to other features and subcombinations. This situation is covered by and within the scope of the scope of the patent application.

The subject matter of the invention is described in detail herein to satisfy statutory requirements. However, the description itself is not intended to limit the scope of the invention. Rather, the inventors have contemplated that the claimed subject matter may also be embodied in other ways, to include different steps or combinations of steps similar to those described in this document, as well as other present or future technologies. Furthermore, although the terms "step" and/or "block" may be used herein to mean different elements of the methods used, these terms should not be interpreted to mean any of or between the various steps disclosed herein Any specific order except when the order of individual steps is explicitly described and except when the order of individual steps is explicitly described.

100: Artificial Reality System Environment 110: Console 112: App Store 114: Headphone Tracking Module 116: Artificial Reality Engine 118: Eye Tracking Module 120: Near-Eye Display 122: Display electronics 124: Display Optics 126: Locator 128: Position Sensor 130: Eye Tracking Unit 132: Inertial Measurement Unit (IMU) 140: Input/Output Interface 150: External Imaging Unit 200: HMD installation 220: Subject 223: Bottom Side 225: front side 227: Left 230: head strap 300: Near Eye Display 305: Frame 310: Display 330: Illuminator 340: High Resolution Camera 350a: Sensor 350b: Sensor 350c: Sensor 350d: Sensor 350e: Sensor 400: Optical Perspective Augmented Reality System 410: Projector 412: Light source/image source 414: Projector Optics 415: Combiner 420: Substrate 430: Input Coupler 440: Output coupler 450: Light 460: Extracted light 490: Eyes 495: eye socket 500: Near-Eye Display Device 510: Light source 512: red light emitter 514: Green light emitter 516: Blu-ray Emitter 520: Projection Optics 530: Waveguide Display 532: Coupler 540: light source 542: red light emitter 544: Green light emitter 546: Blu-ray Transmitter 550: Near Eye Display (NED) Devices 560: Freeform Optics 570: Scanning Mirror 580: Waveguide Display 582: Coupler 590: Eye of the User 600: Near-Eye Display System 610: Image source assembly 620: Controller 630: Image Processor 640: Display panel 642: light source 644: Driver circuit 650: Projector 700: LED 705: LED 710: Substrate 715: Substrate 720: Semiconductor layer 725: Semiconductor layer 730: Action Layer 732: Countertop Sidewall 735: Action Layer 740: Semiconductor layer 745: Semiconductor layer 750: heavily doped semiconductor layer 760: Conductive layer 765: electrical contacts 770: Passivation layer 775: Dielectric Layer 780: Contact Layer 785: electrical contacts 790: Contact Layer 795: Metal Layer 801: LED Array 802: First Wafer 803: Wafer 804: Substrate 805: Carrier substrate 806: first semiconductor layer 807: LED 808: Action Layer 809: Substrate 810: Second semiconductor layer 811: Driver circuit 812: Bonding Layer 813: Bonding Layer 815: Patterned Layer 905: Ion or fast atomic beam 910: Substrate 915: Ion or fast atomic beam 920: Passive or Active Circuits 922: Electrical Interconnects 925: Compression pressure 930: Contact pad 935: hot 940: Dielectric zone 950: Wafer 960: Dielectric Material Layer 970: Micro LED/LED Array 980:p contact 982: n contact 1000: LED array 1010: Substrate 1020: Integrated Circuits 1022: Interconnects 1030: Contact pad 1040: Dielectric Layer 1050: n-type layer 1060: Dielectric Layer 1070: Micro LED 1072: n contact 1074:p contact 1082: Spherical Microlens 1084: Raster 1086: Micro lens 1088: Anti-reflection layer 1102: Lambertian-like light-emitting device/light source/first LED 1104: Semiconductor Substrate/Crystal Growth Substrate 1106: Light/Arrow 1108: Lambert-like distribution 1110: Light source 1112: Light-emitting device array 1114: Waveguide Array 1120: Second semiconductor die 1122: first dielectric layer 1124: Second Dielectric Layer 1126: Luminous Surface (LES) 1130: Transparent substrate layer 1140: First Waveguide 1142: First waveguide surface 1144: Second waveguide surface 1146: Waveguide Body/Pyramid Crystalline Body 1148: Sidewall 1150: Semiconductor material layer/crystalline material layer 1152: Optical reflection layer 1154: Transfer Wafer 1160: Angular distribution 1200: Semiconductor Process 1202: Steps 1204: Steps 1206: Steps 1208: Steps 1210: Steps 1212: Steps 1214: Steps 1216: Steps 1218: Steps 1220: Method 1222: block 1224:block 1226:Block 1228:Block 1230:Block 1232: block 1234:block 1236: block 1238:Block 1302: Perspective 1304: Top View/Semiconductor Substrate/Crystal Growth Substrate 1306: Cross-sectional view 1314: High Fill Factor Waveguide Array 1322: First Dielectric Layer 1324: Second Dielectric Layer 1330: Transparent substrate layer 1340: First High Fill Factor Waveguide 1342: First waveguide surface 1344: Second Waveguide Surface 1346: Waveguide Body 1348: Waveguide Sidewall 1350: Crystalline Material Layer 1352: Reflector/Metalization 1354: Transfer Wafer 1356: Trench 1358: Luminous Structure 1400: Semiconductor Process 1402: Steps 1403: Steps 1404: Steps 1406: Steps 1408: Steps 1410: Steps 1412: Steps 1414: Steps 1416: Steps 1420: Method 1422: block 1423: block/step 1424:Block 1426:Block 1428:Block 1430: block/step 1432: block 1434:Block 1436:Block 1504: Semiconductor substrate 1514: Crystalline Ribbon Spacer Waveguide Array 1522: First Dielectric Layer 1524: Second Dielectric Layer 1540: First Waveguide 1542: First waveguide surface 1544: Second Waveguide Surface 1546: Waveguide Body 1548: Sidewall 1550: Semiconductor material layer/crystalline material layer 1552: Optical Reflective Layer / Metallized Layer 1560: Dielectric Lens Structure 1562: First lens surface 1564: Second Lens Surface 1582: First Baffle Structure 1584: Second Baffle Structure 1600: Semiconductor Process 1602: Steps 1604: Steps 1606: Steps 1608: Steps 1610: Steps 1620: Method 1622: Block 1624:Block 1626:Block 1628:Block 1630:Block 1700: Soft Embossing Tool 1702: Reference Point 1704: Semiconductor Substrates/Crystal Growth Substrates 1706: Elastic (or "soft") material layers 1714: Arrays of Crystalline Structures 1750: Crystalline Material Layer 1754: Transfer Wafer 1760: Semiconductor Process 1762: Steps 1764: Steps 1766: Steps 1768: Steps 1780: Processes/Methods 1782: Block 1784: Block 1786: Block 1788: Block 1790: Block 1792: Block 1800: Hard Embossing Tool 1802: Reference Point 1804: Semiconductor Substrates/Crystal Growth Substrates 1806: Photoresist layer 1808: First "hard" material layer/first hard metal layer 1810: Second Metal Layer 1814: Arrays of crystalline structures 1850: Crystalline Material Layer 1854: First transfer wafer 1856: Second Transfer Wafer 1858: Third Transfer Wafer 1860: Semiconductor Process 1862: Steps 1864: Steps 1866: Steps 1868: Steps 1870: Steps 1872: Steps 1874: Steps 1876: Steps 1880: Processes/Methods 1882: Block 1884: Blocks 1886: Blocks 1888: Blocks 1890: Blocks 1892: Blocks 1894: Steps/Blocks 1896: Blocks 1900: Electronic Systems 1910: Processor 1920: Memory 1922: Application modules 1924: Application modules 1925: Operating Systems 1926: Virtual Reality Engine 1930: Wireless Communication Subsystem 1932: Wireless Link 1934: Antenna 1940: Busbars 1950: Camera 1960: Display Module 1970: User Input/Output Module 1980: Hardware Mods 1990: Sensors

Illustrative specific examples are described in detail below with reference to the following figures.

[FIG. 1] is a simplified block diagram of an example of an artificial reality system environment including a near-eye display, according to some specific examples.

[ FIG. 2 ] is a perspective view of an example of a near-eye display in the form of a head-mounted display (HMD) device for implementing some examples disclosed herein.

[FIG. 3] is a perspective view of an example of a near-eye display in the form of a pair of glasses for implementing some of the examples disclosed herein.

[FIG. 4] shows an example of an optical see-through augmented reality system including a waveguide display according to some specific examples.

[FIG. 5A] shows an example of a near-eye display device including a waveguide display according to some specific examples.

[FIG. 5B] shows an example of a near-eye display device including a waveguide display according to some specific examples.

[FIG. 6] shows an example of an image source assembly in an augmented reality system according to some specific examples.

[ FIG. 7A ] shows an example of a light emitting diode (LED) having a vertical mesa structure according to some specific examples.

[ FIG. 7B ] is a cross-sectional view of an example of an LED having a parabolic mesa structure according to some specific examples.

[FIG. 8A] shows an example of a die-to-wafer bonding method for an LED array according to some specific examples.

[FIG. 8B] shows an example of an inter-wafer bonding method for an LED array according to some specific examples.

[ FIGS. 9A to 9D ] show an example of a hybrid bonding method for an LED array according to some specific examples.

[FIG. 10] shows an example of an LED array with a secondary optical component fabricated thereon according to some specific examples.

[FIG. 11A] shows an example angular distribution of light emitted by a Lambertian-like light-emitting device according to some specific examples.

[FIG. 11B] shows a cross-sectional view of a light source including a waveguide array as a beam collimating secondary optical component for an array of light emitting devices, according to some specific examples.

[FIG. 11C] shows an example angular distribution of light emitted by a Lambertian-like light emitting device using a waveguide as a secondary optical component, according to some specific examples.

[FIG. 12A] A semiconductor process for fabricating the waveguide array of FIG. 11B is shown according to some embodiments.

[FIG. 12B] A method for manufacturing the light source of FIG. 11B is shown according to some specific examples.

[ FIG. 13 ] shows a specific example of a high fill factor waveguide array.

[FIG. 14A] A semiconductor process for fabricating the high fill factor waveguide array of FIG. 13 is shown according to some embodiments.

[FIG. 14B] illustrates a method for fabricating the high fill factor waveguide array of FIG. 13 according to some specific examples.

[FIG. 15] A specific example of a crystalline strip spacer waveguide array is shown.

[FIG. 16A] A semiconductor process for fabricating the spacer waveguide array of FIG. 15 is shown according to some specific examples.

[FIG. 16B] A method for fabricating the spacer waveguide array of FIG. 15 is shown according to some specific examples.

[FIG. 17A] illustrates a semiconductor process for fabricating a soft embossing tool for embossing waveguide arrays in amorphous materials, according to some embodiments.

[FIG. 17B] A method for manufacturing the soft imprint tool of FIG. 17A is shown according to some specific examples.

[FIG. 18A] illustrates a semiconductor process for making a hard embossing tool 1800 for embossing waveguide arrays in amorphous materials, according to some embodiments.

[FIG. 18B] shows a method for manufacturing the hard imprint tool of FIG. 18A, according to some specific examples.

[FIG. 19] is a simplified block diagram of an electronic system of an example of a near-eye display according to some embodiments.

The figures depict specific examples of the invention for purposes of illustration only. Those of ordinary skill in the art will readily appreciate from the following description that alternative embodiments of the structures and methods shown may be used without departing from the principles or acclaimed benefits of the invention.

In the drawings, similar components and/or features may have the same reference signs. Additionally, various components of the same type may be distinguished by following the reference symbol with a dash and a second symbol to distinguish between similar components. If only the first reference sign is used in the description, the description applies to any of the similar components having the same first reference sign irrespective of the second reference sign.

400: Optical Perspective Augmented Reality System

410: Projector

412: Light source/image source

414: Projector Optics

415: Combiner

420: Substrate

430: Input Coupler

440: Output coupler

450: Light

460: Extracted light

490: Eyes

495: eye socket

Claims (20)

A light source comprising: a first semiconductor die including a light emitting device (LED) having a light emitting surface (LES) that emits light out of the light emitting device with a first beam divergence; and A second semiconductor die bonded to the first semiconductor die, the second semiconductor die including a waveguide including: a first waveguide surface configured to receive the light emitted by the light emitting surface of the light emitting device at the first beam divergence; the second waveguide surface; and A waveguide body comprising a transparent crystalline material that transmits the light received by the first waveguide surface to the second waveguide surface, wherein the second waveguide surface and the waveguide body are configured such that the second waveguide The surface emits the light received by the first waveguide surface out of the waveguide with a second beam divergence less than the first beam divergence. The light source of claim 1, wherein the waveguide body has a tapered shape having a taper angle associated with the growth process of the transparent crystalline material on the semiconductor substrate such that the first surface area of the first waveguide surface is less than the second surface area of the second waveguide surface. The light source of claim 1, wherein the waveguide body has a mesa shape formed at least in part by removing a portion of the transparent crystalline material from the second semiconductor die through an etching process. The light source of claim 1, wherein the waveguide further comprises: A reflective layer encapsulating a portion of the waveguide body and configured to reduce transmission losses associated with the waveguide body and reduce the beam divergence of the light received by the first waveguide surface. The light source of claim 1, wherein the second semiconductor die further comprises: A first dielectric layer encapsulating at least a portion of the waveguide body. The light source of claim 5, wherein the first dielectric layer covers the first waveguide surface and the second semiconductor die further comprises: a second dielectric layer covering the second waveguide surface; and A layer of the transparent crystalline material interposed between the first dielectric layer and the second dielectric layer. The light source of claim 1, wherein the second semiconductor die further comprises: an opaque spacer structure positioned around at least a portion of the perimeter of the second waveguide surface and extending beyond a plane of the second semiconductor die to define a columnar volume beyond the plane of the second semiconductor die, wherein the The spacer structure is configured to confine transmission of the light emitted from the second waveguide surface and out of the second semiconductor die within the columnar volume extending beyond the plane of the second semiconductor die. The light source of claim 1, wherein the second waveguide surface has a curved shape formed at least in part by removing a portion of the transparent crystalline material from the second semiconductor die through an etching process such that the second waveguide surface has a curved shape. The curved shape is configured to reduce the beam divergence of the light emitted from the second waveguide surface and exiting the second semiconductor die. The light source of claim 1, wherein the shape of the second waveguide surface is a flat shape and the second semiconductor die further comprises: a convex dielectric lens covering the second waveguide surface, the convex dielectric lens receiving the light emitted by the second waveguide surface with the second beam divergence, wherein the convex dielectric lens is less than the second beam divergence A third beam divergence of degrees emits the light received by the convex dielectric lens. The light source of claim 1, further comprising: A transparent glass substrate, which is bonded to the second semiconductor die and covers the surface of the second waveguide, so that the second semiconductor die is inserted between the first semiconductor die and the glass substrate. The light source of claim 1, wherein the transparent crystalline material is gallium nitride (GaN) grown on a semiconductor substrate. The light source of claim 1, wherein: The first semiconductor die includes an array of light emitting devices, the array of light emitting devices including the light emitting device; and The second semiconductor die includes an array of waveguides including the waveguide, wherein there is a one-to-one correspondence between each light-emitting device in the array of light-emitting devices and each waveguide in the array of waveguides such that the light-emitting device uniquely corresponds to this waveguide. The light source of claim 12, wherein the waveguide array is formed on a continuous layer of the transparent crystalline material, the waveguide body of each waveguide in the waveguide array protrudes from the continuous layer of the transparent crystalline material, each waveguide in the waveguide array The proximal surface of a waveguide includes a portion of the continuous layer of transparent crystalline material, and the distal surface of each waveguide in the array of waveguides is displaced from the continuous layer of transparent crystalline material. The light source of claim 12, wherein the waveguide array is formed on a discontinuous layer of the transparent crystalline material, the discontinuous layer includes a separate partial array of dielectric layers formed through an etching process, and the separate partial arrays of dielectric layers There is a one-to-one correspondence between each dielectric layer portion in and each waveguide in the waveguide array. The light source of claim 1, wherein the light source is included in a wearable device that generates at least one of a virtual reality environment or an augmented reality environment for a user wearing the wearable device. The light source of claim 1, wherein the optical coupling efficiency between the light emitting device and the waveguide is at least 0.70. The light source of claim 1, wherein each spatial dimension of each defect in the optical surfacing of the waveguide is less than 5 nanometers (nm). The light source of claim 1, wherein the light-emitting device is a micro light-emitting diode and the spatial dimension of the light-emitting surface of the light-emitting device is less than 10 microns. A method of manufacturing a light source, the method comprising: fabricating a first semiconductor die, the first semiconductor die including a light emitting device (LED) having a light emitting surface (LES) that emits light out of the light emitting device with a first beam divergence; fabricating a second semiconductor die comprising a waveguide having a first waveguide surface, a second waveguide surface, and a waveguide body comprising a transparent crystalline material; and bonding the second semiconductor die to the first semiconductor die such that the first waveguide surface is configured to receive the light emitted at the first beam divergence by the light emitting surface of the light emitting device, wherein the waveguide The body is configured to transmit the light received by the first waveguide surface to the second waveguide surface, and the second waveguide surface is configured to transmit the light received by the first waveguide surface to the second waveguide surface with a second beam divergence less than the first beam divergence The light received by the first waveguide surface is emitted out of the waveguide. An apparatus comprising: a first semiconductor die including a light emitting device (LED) having a light emitting surface (LES) that emits light out of the light emitting device with a first beam divergence; and A second semiconductor die bonded to the first semiconductor die, the second semiconductor die including a waveguide including: a first waveguide surface configured to receive the light emitted by the light emitting surface of the light emitting device at the first beam divergence; the second waveguide surface; and A waveguide body comprising a transparent crystalline material that transmits the light received by the first waveguide surface to the second waveguide surface, wherein the second waveguide surface and the waveguide body are configured such that the second waveguide surface is smaller than the A second beam divergence of the first beam divergence will emit the light received by the first waveguide surface out of the waveguide.

Images