TW202226557A - Semiconductor storage device - Google Patents

Abstract

A semiconductor storage device includes: a conductive layer and a second conductive layer that are arranged in a first direction; a plurality of first semiconductor layers facing the first conductive layer between the first conductive layer and the second conductive layer, the plurality of first semiconductor layers being arranged in a second direction that intersects the first direction; a first charge storage layer that is provided between the plurality of first semiconductor layers and the first conductive layer in the first direction, and extends in the second direction over a plurality of regions between the plurality of first semiconductor layers and the first conductive layer; and a first insulating layer provided between the plurality of first semiconductor layers and the first charge storage layer in the first direction. The first insulating layer includes a first region that faces one end of each of the first semiconductor layers in the second direction, in the first direction, a second region that faces the other end of each of the first semiconductor layers in the second direction, in the first direction, and a third region provided between the first region and the second region in the second direction. A nitrogen concentration in the first region and the second region is lower than a nitrogen concentration in the third region.

Description

semiconductor memory device

The embodiments described below relate to semiconductor memory devices. [connected application]

This application enjoys the priority of Japanese Patent Application No. 2020-149398 (filing date: September 4, 2020) and U.S. Patent Application No. 17/190865 (filing date: March 3, 2021) as basic applications. This application includes all the contents of the basic application by referring to the basic application.

The following general semiconductor memory device is known, which includes a substrate, a plurality of conductive layers laminated in a direction intersecting the surface of the substrate, and layers of the plurality of conductive layers. A semiconductor layer extending in the product direction and facing the plurality of conductive layers, and a gate insulating film provided between the conductive layer and the semiconductor layer. The gate insulating film includes, for example, a memory portion capable of storing data, such as a silicon nitride film (SiN) or a floating gate.

The problem to be solved by the present invention is to provide a semiconductor memory device that can operate appropriately.

A semiconductor memory device of one embodiment includes: a first conductive layer and a second conductive layer arranged in a first direction; and a plurality of first semiconductor layers formed on the first conductive layer and the second conductive layer The layers are opposite to the first conductive layer, and are arranged side by side in the second direction intersecting with the first direction; and the first charge accumulation layer is arranged in the first direction and is arranged in a plurality of Between the first semiconductor layer and the first conductive layer, and covering a plurality of regions between the plurality of first semiconductor layers and the first conductive layer, and extending in the second direction; and the first insulating layer, which is in the first It is provided between the plurality of first semiconductor layers and the first charge storage layers in the direction. The first insulating layer is provided with: a first region in the first direction, facing one end of the first semiconductor layer in the second direction; and a second region in the first direction, Opposing the other end portion of the first semiconductor layer in the second direction; and a third region in the second direction and provided between the first region and the second region. The nitrogen concentration in the first region and the second region is lower than the nitrogen concentration in the third region.

Next, the semiconductor memory device of the embodiment will be described in detail with reference to the drawings. In addition, these embodiments are merely examples, and are not intended to limit the scope of the present invention.

In addition, each drawing is a schematic, and a part of the structure etc. may be abbreviate|omitted. In addition, the same reference numerals are attached to the parts that are common to the respective embodiments, and the description thereof may be omitted.

Also, in this specification, a specific direction that is parallel to the surface of the substrate is referred to as the X direction, and a direction that is parallel to the surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and The direction perpendicular to the surface of the substrate is referred to as the Z direction.

In addition, in this specification, the direction along the specific surface is referred to as the first direction, the direction intersecting the first direction along the specific surface is referred to as the second direction, and the The direction in which this specific plane intersects is referred to as the case of the third direction. These 1st direction, 2nd direction, and 3rd direction may mutually correspond to any one of X direction, Y direction, and Z direction, and may not mutually correspond.

In addition, in this specification, expressions such as "up" or "down" are based on the substrate. For example, if the direction away from the board along the above-mentioned first direction is called upward, the direction approaching the board along the first direction is called downward. In addition, when referring to the lower end or the lower end of a certain structure, it refers to the surface or end of the substrate side of the structure, and when referring to the upper surface or the upper end, it refers to the surface or end of the structure on the opposite side of the substrate. face or end. In addition, the surface intersecting the second direction or the third direction is referred to as a side surface or the like.

In addition, in this specification, when referring to the "width" or "thickness" of a specific direction with respect to a composition, a component, etc., it will be represented by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy) The width or thickness of the section, etc. observed by microscopy) etc.

[First Embodiment] [Configuration] Fig. 1 is a schematic equivalent circuit diagram of the semiconductor memory device of the first embodiment.

The semiconductor memory device of the present embodiment includes a memory cell array MCA and a peripheral circuit PC that controls the memory cell array MCA.

The memory cell array MCA includes a plurality of memory cells MU. These plural memory units MU respectively have two memory strings MSa and MSb which are electrically independent from each other. One ends of these memory strings MSa, MSb are respectively connected to the drain side selection transistor STD, and are connected to the common bit line BL via these. The other ends of the memory strings MSa and MSb are connected to the common source side selection transistor STS, and are connected to the common source line SL via these.

The memory strings MSa and MSb each include a plurality of memory cells MC connected in series. The memory cell MC is a field-effect transistor having a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film is provided with a charge storage layer capable of storing data. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage layer. The gate electrode is a part of the word line WL.

Selective transistors (STD, STS) are field-effect transistors having a semiconductor layer, a gate insulating film and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the drain side selection transistor STD is a part of the drain side selection gate line SGD. The gate electrode of the source side selection transistor STS is a part of the source side selection gate line SGS.

Peripheral circuit PC, for example, generates voltages required for read operation, write operation, and delete operation, and applies it to bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS). The peripheral circuit PC, for example, is a circuit including a row decoder, a sense amplifier module, a voltage generating circuit, a sequencer, and various registers. The peripheral circuit PC is composed of, for example, a plurality of transistors and wirings provided on a semiconductor substrate.

Next, a schematic configuration example of the semiconductor memory device of the present embodiment will be described with reference to FIG. 2 and FIG. 3 . FIG. 2 is a schematic perspective view of the semiconductor memory device. Fig. 3(a) is a schematic plan view corresponding to the cross section of the portion shown by the line A-A' in Fig. 2. Fig. 3(b) is a schematic cross-sectional view corresponding to the cross-section of the portion indicated by the line B-B' in Fig. 3(a). In Figs. 2 and 3, a part of the configuration is omitted.

For example, as shown in FIG. 2 , the semiconductor memory device of the present embodiment includes a substrate 110 and a memory cell array MCA provided above the substrate 110 .

The substrate 110 is, for example, a semiconductor substrate such as single crystal silicon (Si). The substrate 110 has, for example, a double well structure having an n-type impurity layer on the upper surface of the semiconductor substrate, and a p-type impurity layer in the n-type impurity layer. In addition, on the surface of the substrate 110, for example, transistors, wirings, and the like that constitute the peripheral circuit PC may be provided.

The memory cell array MCA includes a plurality of laminate structures LS arranged in the Y direction. The laminated body structure LS includes a plurality of conductive layers 120 laminated in the Z direction. Between these laminated body structures LS, a memory trench structure MT is provided. The laminated body structure LS and the memory trench structure MT are alternately arranged in the Y direction. The memory trench structure MT includes, for example, as shown in FIG. 3( a ), a plurality of memory cell structures MUS and inter-memory cell structures IMUS arranged in the X direction. The memory cell structure MUS includes a semiconductor layer 130 , a part of the gate insulating layer 140 , and a part of the insulating layer 150 . The inter-memory structure IMUS includes a part of the gate insulating layer 140 and a part of the insulating layer 150 . Also, for example, as shown in FIG. 2 , the lower end of the semiconductor layer 130 is connected to the wiring layer 160 .

The conductive layer 120 is a slightly plate-shaped conductive layer extending in the X direction, and is, for example, a laminated film of titanium nitride (TiN) and tungsten (W) or a polysilicon (p) implanted with impurities. -Si) and other conductive layers. These conductive layers 120 function as gate electrodes for word lines WL and memory cells MC (FIG. 1), respectively.

Below the plurality of conductive layers 120, for example, a conductive layer 121 (FIG. 2) made of the same material as the conductive layer 120 is provided. The conductive layer 121 functions as the gate electrode of the source side selection gate line SGS and the source side selection transistor STS (FIG. 1).

An insulating layer 122 such as silicon oxide (SiO ₂ ) is provided between the plurality of conductive layers 120 , between the lowermost conductive layer 120 and the conductive layer 121 , and between the conductive layer 121 and the wiring layer 160 .

In addition, in the following description, one of the two layered body structures LS arranged side by side in the Y direction is referred to as a layered body structure LSa and the other is referred to as a layered body Construct the case for LSb. In addition, the conductive layer 120 included in the laminate structure LSa is referred to as a first conductive layer 120a, and the conductive layer 120 included in the laminate structure LSb is referred to as a second conductive layer 120b. Happening.

The semiconductor layer 130 is arranged in the X direction corresponding to the plurality of memory cell structures MUS arranged in the X direction, as shown in FIG. 3( a ), for example. The semiconductor layer 130 is, for example, a semiconductor layer such as non-dope polysilicon (Si). The semiconductor layer 130, for example, as shown in FIG. 2, includes a first semiconductor layer 130a provided between the laminate structure LSa and the insulating layer 150, and a first semiconductor layer 130a provided between the laminate structure LSb and the insulating layer The second semiconductor layer 130b between 150, the third semiconductor layer 130c provided at the lower ends of the first semiconductor bulk layer 130a and the second semiconductor layer 130b, and the first semiconductor layer 130a and the second semiconductor layer 130b The fourth semiconductor layer 130d at the upper end.

The first semiconductor layers 130a are arranged in parallel in the X direction, and extend in the Z direction to face the plurality of first conductive layers 120a, respectively. The first semiconductor layer 130a functions as a channel region of a plurality of memory cells MC included in the memory string MSa (FIG. 1).

The second semiconductor layers 130b are arranged in parallel in the X direction, and extend in the Z direction to face the plurality of second conductive layers 120b, respectively. The second semiconductor layer 130b functions as a channel region of a plurality of memory cells MC included in the memory string MSb (FIG. 1).

The fourth semiconductor layer 130d is connected to the first semiconductor layer 130a and the second semiconductor layer 130b, for example, as shown in FIG. 2 . The fourth semiconductor layer 130d is connected to bit line contacts BLC such as tungsten (W) and bit line BL such as copper (Cu).

Also, for example, as illustrated in FIG. 2 , a semiconductor layer 133 is provided below the semiconductor layer 130 . The semiconductor layer 133 is connected to the third semiconductor layer 130c. The semiconductor layer 133 is provided between the two conductive layers 121 adjacent to each other in the Y direction, and faces the two conductive layers 121 . The semiconductor layer 133 is a semiconductor layer such as polysilicon (p-Si), and functions as a channel region of the source side selection transistor STS (FIG. 1). An insulating layer 135 such as silicon oxide (SiO ₂ ) is provided between the semiconductor layer 133 and the conductive layer 121 .

The gate insulating layer 140 includes a first gate insulating layer 140a and a second gate insulating layer 140b.

The first gate insulating layer 140a is provided between the first semiconductor layer 130a and the plurality of first conductive layers 120a arranged in the Z direction, and is provided on one side of the Y direction of the laminate structure LS at the side and extending in the Z direction. In addition, the first gate insulating layer 140a covers a plurality of regions between the plurality of first semiconductor layers 130a and the first conductive layer 120a, and extends in the X direction. The first gate insulating layer 140a includes, for example, a first insulating layer 141a, a first charge storage layer 142a, and a first blocking insulating layer 143a as shown in FIG. 3(a), for example.

The second gate insulating layer 140b is provided between the second semiconductor layer 130b and the plurality of second conductive layers 120b arranged in the Z direction, and is provided on the other side in the Y direction of the laminate structure LS at the side and extending in the Z direction. In addition, the second gate insulating layer 140b covers a plurality of regions between the plurality of second semiconductor layers 130b and the second conductive layers 120b, and extends in the X direction. The second gate insulating layer 140b, for example, as shown in FIG. 3(a), includes a second insulating layer 141b, a second charge storage layer 142b, and a second blocking insulating layer 143b.

The first insulating layer 141a and the second insulating layer 141b are insulating layers made of, for example, silicon oxynitride (SiON). The first charge storage layer 142a and the second charge storage layer 142b are insulating layers made of, for example, silicon nitride (SiN). The first blocking insulating layer 143a and the second blocking insulating layer 143b are, for example, insulating layers including silicon oxide (SiO ₂ ).

Here, the first insulating layer 141a and the second insulating layer 141b will be described in detail using FIG. 4 . FIG. 4 is a schematic enlarged view of the memory cell structure MUS and its vicinity corresponding to FIG. 3(a) .

The first insulating layer 141a includes a plurality of high nitrogen concentration regions arranged corresponding to a plurality of memory cell structures MUS arranged in the X direction, and a plurality of high nitrogen concentration regions arranged in the X direction A plurality of low nitrogen concentration regions are arranged correspondingly to the structure IMUS between the memory cells. For example, in FIG. 4, as two low nitrogen concentration regions corresponding to two adjacent memory cell structure IMUS in the X direction, a first region 141a_1 and a second region 141a_2 are exemplified . In addition, the third region 141a_3 is exemplified as the high nitrogen concentration region provided between these. The width X _{141a_3} of each high nitrogen concentration region in the X direction is smaller than the width X _130a of the first semiconductor layer 130a in the X direction. In addition, the end in the X direction of each low nitrogen concentration region faces the side surface in the Y direction of the two adjacent first semiconductor layers 130a in the X direction. For example, in the memory cell structure MUS illustrated in FIG. 4, the end of the first region 141a_1 in the X direction is in the Y direction with one of the ends of the first semiconductor layer 130a in the X direction. sides meet. In addition, the position of the second region 141a_2 in the X direction is in contact with the side surface in the Y direction of the other end of the first semiconductor layer 130a in the X direction. The nitrogen concentration in the low nitrogen concentration region (eg, the first region 141a_1 and the second region 141a_2 ) is lower than the nitrogen concentration in the high nitrogen concentration region (eg, the third region 141a_3 ).

The low nitrogen concentration regions (eg, the first region 141a_1 and the second region 141a_2 ) may also include silicon oxynitride ( SiON). In addition, the low nitrogen concentration regions (for example, the first region 141a_1 and the second region 141a_2) may contain silicon oxide (SiO ₂ ).

The second insulating layer 141b includes a plurality of high nitrogen concentration regions arranged corresponding to a plurality of memory cell structures MUS arranged in the X direction, and a plurality of high nitrogen concentration regions arranged in the X direction A plurality of low nitrogen concentration regions are arranged correspondingly to the structure IMUS between the memory cells. For example, in FIG. 4, as two low nitrogen concentration regions corresponding to two adjacent memory cell structure IMUS in the X direction, a fourth region 141b_4 and a fifth region 141b_5 are exemplified . In addition, the sixth region 141b_6 is exemplified as the high nitrogen concentration region provided between these regions. The width X _{141b_6} of each high nitrogen concentration region in the X direction is smaller than the width X _130b of the second semiconductor layer 130b in the X direction. In addition, the end in the X direction of each low nitrogen concentration region faces the side surface in the Y direction of the two adjacent second semiconductor layers 130b in the X direction. For example, in the memory cell structure MUS illustrated in FIG. 4, the end of the fourth region 141b_4 in the X direction is in the Y direction with one of the ends of the second semiconductor layer 130b in the X direction. sides meet. In addition, the position of the fifth region 141b_5 in the X direction is in contact with the side surface in the Y direction of the other end of the second semiconductor layer 130b in the X direction. The nitrogen concentration in the low nitrogen concentration region (eg, the fourth region 141b_4 and the fifth region 141b_5 ) is lower than the nitrogen concentration in the high nitrogen concentration region (eg, the sixth region 141b_6 ).

The low nitrogen concentration regions (eg, the fourth region 141b_4 and the fifth region 141b_5 ) may also include silicon oxynitride ( SiON). In addition, the low nitrogen concentration regions (eg, the fourth region 141b_4 and the fifth region 141b_5 ) may contain silicon oxide (SiO ₂ ).

In addition, the position and range of the high nitrogen concentration region and the low nitrogen concentration region, and the nitrogen concentration in these regions can be determined by using EDS (Energy Dispersive X-ray Spectroscopy) method or the like. And analyze its composition to determine it.

The insulating layer 150 is provided at the central portion of the memory trench structure MT in the Y direction, and extends in the X direction and the Z direction. For example, as shown in FIG. 3(b), the width in the Y direction of the portion of the insulating layer 150 included in the memory cell structure MUS is larger than that of the insulating layer 150. The portion included in the inter-cell structure IMUS is smaller in width in the Y direction. The insulating layer 150 is, for example, an insulating layer of silicon oxide (SiO ₂ ).

The wiring layer 160 (FIG. 2) is a plate-shaped conductive layer extending in the X direction and the Y direction. The wiring layer 160 is, for example, a conductive layer in which an impurity-implanted polysilicon (Si) or the like is implanted, and functions as a source line SL (FIG. 1). In addition, the structure of the source line SL can be appropriately changed. For example, the source line SL can also be a part of the surface of the substrate 110 . In addition, the source line SL may include a metal layer such as titanium nitride (TiN) and tungsten (W). In addition, the source line SL can also be connected to the lower end of the semiconductor layer 130, and can also be connected to the side surface of the semiconductor layer 130 in the Y direction.

[Manufacturing method] Next, the manufacturing method of the semiconductor memory device of the present embodiment will be described with reference to FIGS. 5 to 19 . Fig. 5 to Fig. 19 (a) are schematic plan views for explaining the manufacturing method. Fig. 5 to Fig. 19(b) are schematic cross-sectional views for explaining the manufacturing method, and D in Fig. 5 to Fig. 19 (a) is shown. -D' line corresponds to the profile.

In addition, in the following description, the 1st insulating layer 141a and the 2nd insulating layer 141b may be called the insulating layer 141 in some cases. In addition, the first charge storage layer 142a and the second charge storage layer 142b may be referred to as the charge storage layer 142 in some cases. In addition, the 1st block insulating layer 143a and the 2nd block insulating layer 143b may be called the block insulating layer 143 in some cases.

In this manufacturing method, as shown in FIG. 5, the wiring layer 160 is formed on the upper part of the substrate which is not shown. In addition, on the wiring layer 160, a plurality of insulating layers 122 and a sacrificial layer 120A are alternately laminated. In addition, an insulating layer 152 is formed on the uppermost sacrificial layer 120A. The sacrificial layer 120A is made of, for example, silicon nitride (SiN). The insulating layer 152 is made of, for example, silicon oxide (SiO ₂ ). The wiring layer 160 , the insulating layer 122 , the sacrificial layer 120A, and the insulating layer 152 are formed by, for example, CVD (Chemical Vapor Deposition).

Next, as shown in FIG. 6 , an opening MTa is formed in the insulating layer 122 , the sacrificial layer 120A, and the insulating layer 152 . The opening MTa, for example, is formed on the upper surface of the structure shown in FIG. 5, and an insulating layer having an opening is formed at a portion corresponding to the opening MTa, and this is used as a mask to perform RIE (reactive ion etching, Reactive Ion Etching: RIE), etc., to form it.

The opening MTa extends in the Z direction, and divides the insulating layer 122 , the sacrificial layer 120A and the insulating layer 152 in the Y direction, and exposes the upper surface of the wiring layer 160 .

Next, as shown in FIG. 7, a semiconductor layer 133 is formed on the bottom surface of the opening MTa. The semiconductor layer 133 is formed by, for example, epitaxial growth or the like.

Next, as shown in FIG. 8, on the upper surface of the insulating layer 152 and the bottom and side surfaces of the opening MTa, the blocking insulating layer 143, the charge storage layer 142, the insulating layer 141 and the amorphous silicon film 130A are formed. This process is performed, for example, by a method such as CVD.

Next, as shown in FIG. 9, a portion of the blocking insulating layer 143, the charge accumulating layer 142, the insulating layer 141, and the amorphous silicon film 130A provided at the bottom surface of the opening MTa is removed, so that the The semiconductor layer 133 is exposed. This process is performed by, for example, RIE or the like.

Next, as shown in FIG. 10, an amorphous silicon film is formed on the upper surface of the semiconductor layer 133 and on the side and upper surfaces of the amorphous silicon film 130A. This process is performed, for example, by a method such as CVD. Next, a heat treatment or the like is performed to modify the crystal structure of the amorphous silicon film 130A, and to form a semiconductor layer 130B of polycrystalline silicon (Si) or the like.

Next, as shown in FIG. 11, a carbon film 200 is formed inside the opening MTa, and then a hard mask HM such as an oxide film is formed on the carbon film 200, and an opening AH is formed at the hard mask HM . The carbon film 200 is formed, for example, by spin coating or the like of a coating-type carbon film material. The formation of the hard mask HM is performed, for example, by CVD or the like. The openings AH are formed, for example, by methods such as photolithography and wet etching.

Next, as shown in FIG. 12, the portion of the carbon film 200 provided at the position corresponding to the opening AH is removed. This process is performed by, for example, RIE or the like. In addition, in this process, a part of the semiconductor layer 130B, a part of the insulating layer 141, a part of the charge storage layer 142 and a part of the blocking insulating layer 143 are also removed, and a part of the insulating layer 152 is exposed.

Next, as shown in FIG. 13, the portion of the semiconductor layer 130B exposed at the opening AH is removed. This process is performed by, for example, isotropic etching by RIE or the like. Through this process, the portion of the semiconductor layer 130B provided in the opening MTa is divided in the X direction, and the first semiconductor layer 130a and the second semiconductor layer 130b are formed in the X direction.

Next, as shown in FIG. 14, the exposed part of the insulating layer 141 exposed at the opening AH and the non-exposed part of the part not exposed at the opening AH are oxidized. This process is performed by, for example, introducing an oxidizing agent through the opening AH, and performing an oxidation treatment or the like. In addition, this oxidation starts from the exposed portion of the insulating layer 141 exposed at the opening AH, and proceeds to the non-exposed portion that is not exposed at the opening AH. A region where oxidation is performed in this process becomes a low nitrogen concentration region (for example, the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5 described with reference to FIG. 4). Moreover, the area|region which did not perform oxidation in this process becomes a high nitrogen concentration area (for example, the 3rd area|region 141a_3 and the 6th area|region 141b_6 demonstrated with reference to FIG. 4).

Next, as shown in FIG. 15, the hard mask HM and the carbon film 200 are removed, the insulating layer 150 is formed inside the opening MTa, and the opening is filled. The removal of the hard mask HM is performed, for example, by wet etching or the like. The removal of the carbon film 200 is performed, for example, by ashing or the like. The insulating layer 150 is formed, for example, by CVD or the like.

Next, as shown in FIG. 16, from the upper surface of the structure shown in FIG. 15, the insulating layer 150, the first semiconductor layer 130a and the second semiconductor layer 130b, the insulating layer 141, and the charge storage layer 142 are and a portion of the blocking insulating layer 143 is removed, after which the insulating layer 153 is formed on the structure. This removal process is performed, for example, by RIE or the like. The insulating layer 153 is formed, for example, by CVD or the like.

Next, as shown in FIG. 17, the plurality of sacrificial layers 120A are removed through openings not shown. This process is performed, for example, by wet etching or the like.

Next, as shown in FIG. 18, an insulating layer 135 is formed on the side surface of the semiconductor layer 133 through an opening not shown. This process is performed, for example, by oxidation treatment or the like.

Next, as shown in FIG. 19 , a conductive layer 120 and a conductive layer 121 are formed between the insulating layers 122 arranged in the Z direction through openings not shown. This process is performed by, for example, CVD and wet etching.

After that, the upper ends of the first semiconductor layer 130a and the second semiconductor layer 130b are removed, and a fourth semiconductor layer 130d is formed on the removed portion. After that, bit line contacts BLC such as tungsten (W) and copper are formed. (Cu) etc. bit line BL. Thereby, the general configuration described with reference to FIG. 2 is formed.

[Effect] In Fig. 20, the structure of the semiconductor memory device of the comparative example is shown. The semiconductor memory device of the comparative example has a memory trench structure MT' instead of the memory trench structure MT. The memory trench structure MT' includes a plurality of memory cell structures MUS' and an inter-memory cell structure IMUS' arranged in the X direction. The memory cell structure MUS' includes a first semiconductor layer 130a' and a second semiconductor layer 130b instead of the first semiconductor layer 130a, the second semiconductor layer 130b, a part of the gate insulating layer 140, and a part of the insulating layer 150 ', the gate insulating layer 140' and the insulating layer 150'. The inter-memory structure IMUS' is provided with an insulating layer 151' instead of a part of the gate insulating layer 140 and a part of the insulating layer 150.

The gate insulating layer 140' includes a first gate insulating layer 140a' and a second gate insulating layer 140b'.

Here, the first gate insulating layer 140a of the first embodiment covers a plurality of regions between the plurality of first semiconductor layers 130a and the first conductive layer 120a, and extends in the X direction. On the other hand, the first gate insulating layers 140a' of the comparative example are individually disposed in plural regions between the plural first semiconductor layers 130a' and the first conductive layers 120a, and are separated by the memory cells. Construct IMUS' separate from each other.

In addition, the second gate insulating layer 140b of the first embodiment covers a plurality of regions between the plurality of second semiconductor layers 130b and the second conductive layers 120b, and extends in the X direction. On the other hand, the second gate insulating layers 140b' of the comparative example are individually disposed in plural regions between the plural second semiconductor layers 130b' and the second conductive layers 120b, and are separated between the memory cells. Construct IMUS' separate from each other.

In addition, the first gate insulating layer 140a' and the second gate insulating layer 140b' are provided with the first insulating layer 141a' and the second insulating layer 141b instead of the first insulating layer 141a and the second insulating layer 141b, respectively. '. The width X _141a' of the first insulating layer 141a' in the X direction is approximately the same as the width X _130a' of the first semiconductor layer 130a' in the X direction. The width X _141b' of the second insulating layer 141b' in the X direction is approximately the same as the width X _130b' of the second semiconductor layer 130b' in the X direction.

The insulating layers 150' are individually provided at the plurality of memory cell structures MUS' that are arranged in the X direction, and are separated from each other by the inter-memory cell structure IMUS'.

The insulating layers 151' are individually disposed at the plurality of memory cell structures IMUS' that are juxtaposed in the X direction, and are separated from each other by the memory cell structures MUS'. In addition, the width Y _{151 ′} of the insulating layer 151 ′ in the Y direction is larger than the width Y _MUS′ of the memory cell structure MUS′ in the Y direction.

In manufacturing the semiconductor memory device of the comparative example, for example, after the process described with reference to FIG. 10, an insulating layer 150' is formed in the opening MTa. Furthermore, on the upper surface of this structure, a hard mask HM having openings AH formed thereon is formed (FIG. 11). Furthermore, through-holes are formed at the portions corresponding to the openings AH by means of RIE or the like using the hard mask HM, and the semiconductor layer 130B, the insulating layer 141 , and the charge storage layer 142 in the openings MTa are formed. , the blocking insulating layer 143 and the insulating layer 150' are divided in the X direction. In addition, an insulating layer 151' is formed in the through hole.

According to such a structure, two electrically independent memory strings MS can be formed in the memory trench structure MT, and a semiconductor memory device having a large memory capacity can be provided.

However, in the manufacture of such a structure, when the openings AH are patterned, there may be cases where the alignment shift in the Y direction occurs. As shown in FIG. 20, when there is a misalignment in the Y direction, for example, the second semiconductor layer 130b has a width X _130a' in the X direction relative to the first semiconductor layer 130a'. 'The width X _130b' in the X direction is shortened, and the characteristics of the two memory strings MS formed on the two sides of the memory trench structure MT will be different, which will lead to different memory characteristics. important factor of variance.

Furthermore, if the margin of the alignment offset of the opening AH relative to the Y direction of the memory trench structure MT is considered, the separation distance of the adjacent memory trench structures MT cannot be designed. for short. Therefore, in the general structure of the comparative example, the miniaturization and high integration of the memory structure are difficult.

Therefore, in the process of manufacturing the semiconductor memory device of the first embodiment, in the process described with reference to FIG. 13, the gate insulating layer 140 is not divided in the X direction, but only the semiconductor layer is divided 130 is selectively disconnected. In such a structure, it is not necessary to take into account the margin of the alignment shift in the Y direction with respect to the memory trench structure MT, so that the memory trench structures adjacent in the Y direction can be arranged The separation distance of the MT is designed to be small, so that the miniaturization of the memory cell size can be achieved.

Also, in the case of a structure in which the first semiconductor layer 130a and the second semiconductor layer 130b are divided toward the X direction as in the present embodiment, if a gate is applied to the first conductive layer 120a and the second conductive layer 120b If the polar voltage is high, a high-intensity electric field will be concentrated at both ends of the first semiconductor layer 130a and the second semiconductor layer 130b in the X direction, and these ends may become so-called parasitic transistors. That is, the "threshold voltage of the parasitic transistor corresponding to both ends in the X direction" may be lower than the "threshold voltage of the transistor corresponding to other parts". In this case, the "parasitic transistor corresponding to both ends in the X direction" will be turned on at a lower voltage than the "transistor corresponding to the other part". "The ON characteristic with respect to the gate voltage application of the memory cell MC becomes two-stage".

Therefore, in the present embodiment, as shown in FIG. 4, the position between the first insulating layer 141a and the second insulating layer 141b and the “first semiconductor layer 130a and the second semiconductor layer 130b in the X direction” The nitrogen concentration in the opposing portion (including the high nitrogen concentration region including the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) is formed to be higher than that of the first The opposing portion between the insulating layer 141a and the second insulating layer 141b and “the other parts of the first semiconductor layer 130a and the second semiconductor layer 130b” (including the low nitrogen concentration regions of the third region 141a_3 and the sixth region 141b_6 ) and lower.

The electron implantation efficiency in the low nitrogen concentration region is smaller than the electron implantation efficiency in the higher nitrogen concentration region. Therefore, according to the semiconductor memory device of the first embodiment, it is possible to avoid a situation where a high-intensity electric field is concentrated at both ends of the first semiconductor layer 130a and the second semiconductor layer 130b in the X direction, and can Parasitic transistor action is suppressed. In this way, the two-step characterization of the memory cell MC with respect to the voltage is suppressed, and a semiconductor memory device that operates appropriately can be provided.

[Modification of the first embodiment] Fig. 21 shows a modification of the configuration of the first embodiment. FIG. 21 is a schematic plan view illustrating the configuration of a part of the semiconductor memory device of this modification.

The memory cell structure MUS and the inter-memory cell structure IMUS of the present modification are basically constructed in the same manner as in the first embodiment. However, the semiconductor memory device of this modification is provided with the first charge storage layer 142a" and the second charge storage layer 142b" instead of the first charge storage layer 142a and the second charge storage layer 142b.

The first charge storage layer 142a" is provided with a plurality of high nitrogen concentration regions arranged corresponding to a plurality of memory cell structures MUS arranged in the X direction, and a plurality of high nitrogen concentration regions arranged in the X direction. Plural number of low nitrogen concentration regions are arranged in correspondence with the structure IMUS between the plurality of memory cells. For example, in FIG. 21, as the structure IMUS between two memory cells adjacent to the X direction The corresponding two low nitrogen concentration regions are exemplified by the seventh region 142a"_7 and the eighth region 142a"_8. The ninth region is exemplified as the high nitrogen concentration region provided between these regions. 142a"_9. The width X _{142a"_9} of each high nitrogen concentration region in the X direction is smaller than the width X 130a of the first semiconductor layer 130a in the X direction. Furthermore, the width X _130a of each low nitrogen concentration region is smaller in the X direction The upper end faces the side surfaces in the Y direction of the two adjacent first semiconductor layers 130a in the X direction. For example, in the memory cell structure MUS illustrated in FIG. The end of the region 142a"_7 in the X direction is opposed to the side surface in the Y direction of one end of the first semiconductor layer 130a in the X direction. In addition, the position of the eighth region 142a"-8 in the X direction is opposite to the side surface in the Y direction of the other end of the first semiconductor layer 130a in the X direction. In the low nitrogen concentration region (for example, The nitrogen concentration in the seventh region 142a"_7 and the eighth region 142a"_8) is lower than that in the high nitrogen concentration region (eg, the ninth region 142a"_9).

The low nitrogen concentration region (eg, the seventh region 142a"-7 and the eighth region 142a"-8) may also include a lower nitrogen content than the high nitrogen concentration region (eg, the ninth region 142a"-9) Silicon oxynitride (SiON). Also, the low nitrogen concentration regions (eg, the seventh region 142a"_7 and the eighth region 142a"_8) may also include silicon oxide (SiO ₂ ).

The second charge storage layer 142b" is provided with a plurality of high nitrogen concentration regions arranged in correspondence with a plurality of memory cell structures MUS arranged in the X direction, and a plurality of high nitrogen concentration regions arranged in the X direction. Plural number of low nitrogen concentration regions are arranged in correspondence with the structure IMUS between the plurality of memory cells. For example, in FIG. 21, as the structure IMUS between two memory cells adjacent to the X direction The corresponding two low nitrogen concentration regions are exemplified by the tenth region 142b"_10 and the eleventh region 142b"_11. The twelfth region is exemplified as the high nitrogen concentration region provided between these regions. 142b"_12. The width X _{142b"_12} of each high nitrogen concentration region in the X direction is smaller than the width X 130b of the second semiconductor layer 130b in the X direction. Moreover, the width X _130b of each low nitrogen concentration region is smaller in the X direction The upper end faces the side surfaces in the Y direction of the two adjacent second semiconductor layers 130b in the X direction. For example, in the memory cell structure MUS illustrated in FIG. The end of the 10 region 142b"_10 in the X direction is opposed to the side surface in the Y direction of one end of the second semiconductor layer 130b in the X direction. In addition, the position of the 11th region 142b''-11 in the X direction is opposite to the side surface in the Y direction of the other end of the second semiconductor layer 130b in the X direction. In the low nitrogen concentration region (for example, The nitrogen concentration in the 10th region 142b"_10 and the 11th region 142b"_11) is lower than that in the high nitrogen concentration region (eg, the 12th region 142b"_12).

The low nitrogen concentration region (eg, the 10th region 142b"_10 and the 11th region 142b"_11) may also include a lower nitrogen content than the high nitrogen concentration region (eg, the 12th region 142b"_12) Silicon oxynitride (SiON). Also, the low nitrogen concentration regions (eg, the 10th region 142b"_10 and the 11th region 142b"_11) may also contain silicon oxide (SiO ₂ ).

[Other Embodiments] Above, the semiconductor memory device according to the first embodiment has been exemplified. However, the above configuration is merely an example, and the specific configuration and the like can be appropriately adjusted.

For example, in the first embodiment and its modification examples, "the low nitrogen concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_4 and the fifth The region 141b_5)" is shown as an example formed by oxidation treatment through the opening AH in the process described with reference to FIG. 14 . However, the timing of performing the oxidation treatment for forming the low nitrogen concentration region can be appropriately adjusted. For example, the process described with reference to FIG. 14 may be omitted, and an oxidation treatment for forming a low nitrogen concentration region may be performed in a process subsequent to the process shown in FIG. 14 .

Also, for example, in the first embodiment and its modification, in the process described with reference to FIG. 14, the low nitrogen concentration region is formed by the oxidation treatment through the opening AH (the first The example of the area 141a_1, the second area 141a_2, the fourth area 141b_4, and the fifth area 141b_5)” is shown. However, the low nitrogen concentration region may be formed by a method other than the oxidation treatment. For example, after performing the process described with reference to FIG. 13, a part of the insulating layer 141 may be removed by a method such as wet etching through the opening AH. In addition, the buried nitrogen concentration at the positions corresponding to the low nitrogen concentration regions (the first region 141a_1, the second region 141a_2, the fourth region 141b_4, and the fifth region 141b_5) may be A material with a lower nitrogen concentration than the high nitrogen concentration regions (the third region 141a_3 and the sixth region 141b_6).

[Others] Although several embodiments of the present invention have been described, these embodiments are merely presented as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are also included in the scope and gist of the invention, and are also included in the inventions described in the claims and their equivalents.

110: substrate 120: conductive layer 120a: first conductive layer 120b: second conductive layer 130: semiconductor layer 130a: first semiconductor layer 130b: second semiconductor layer 141: insulating layer 141a: first insulating layer 141b: second insulating layer layer 142: charge storage layer 142a: first charge storage layer 142b: second charge storage layer 143: barrier insulating layer 150: insulating layer 160: wiring layer

[FIG. 1] is a schematic equivalent circuit diagram of the semiconductor memory device of the first embodiment. [Fig. 2] is a schematic perspective view of the semiconductor memory device. [FIG. 3] (a) is a schematic plan view corresponding to the cross section of the part indicated by the AA' line in FIG. 2, and (b) is a BB' corresponding to (a) A schematic sectional view of the section of the portion shown by the line. [FIG. 4] is a schematic enlarged view of the memory cell structure MUS and its vicinity corresponding to FIG. 3(a). [Fig. 5] is a schematic plan view and a cross-sectional view showing the manufacturing method of the semiconductor memory device. [Fig. 6] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 7] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 8] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 9] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 10] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 11] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 12] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 13] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 14] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 15] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 16] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 17] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 18] is a schematic plan view and a cross-sectional view showing the manufacturing method. [Fig. 19] is a schematic plan view and a cross-sectional view showing the manufacturing method. [FIG. 20] is a schematic plan view showing the structure of a part of the semiconductor memory device of the comparative example. [FIG. 21] is a schematic plan view showing the structure of a part of a semiconductor memory device of a modification.

120: Conductive layer

120a: first conductive layer

120b: second conductive layer

130a: first semiconductor layer

130b: second semiconductor layer

140a: 1st gate insulating layer

140b: 2nd gate insulating layer

141a: 1st insulating layer

141a_1: Region 1

141a_2: Region 2

141a_3: Region 3

141b: 2nd insulating layer

141b_4: Region 4

141b_5: Region 5

141b_6: Region 6

142a: first charge accumulation layer

142b: second charge accumulation layer

143a: 1st barrier insulating layer

143b: 2nd barrier insulating layer

150: Insulation layer

LS: Laminated Body Structure

LSa: Laminated Structure

LSb: Laminated Body Structure

MT: Memory Trench Structure

IMUS: Inter-Cell Structure

MUS: Memory Cell Structure

Claims (10)

A semiconductor memory device is provided with: a first conductive layer and a second conductive layer, which are arranged side by side in a first direction; and a plurality of first semiconductor layers, which are located between the first conductive layer and the second conductive layer Opposed to the first conductive layer from time to time, and arranged side by side in a second direction intersecting with the first direction; and a first charge storage layer, which is arranged in the first direction on the aforementioned Between the plurality of first semiconductor layers and the first conductive layer, and covering the plurality of regions between the plurality of first semiconductor layers and the first conductive layer, it extends in the second direction; and the first insulation The layer is arranged between the plurality of first semiconductor layers and the first charge storage layer in the first direction, and the first insulating layer includes: a first region, which is in the first direction on one end of the first semiconductor layer in the second direction opposite; and the second region, in the first direction, and the other end of the first semiconductor layer in the second direction one end is opposite; and the third area is in the second direction, is arranged between the first area and the second area, and the nitrogen concentration in the first area and the second area is lower than the nitrogen concentration in the aforementioned third region. The semiconductor memory device according to claim 1, wherein a substrate is provided, and the first conductive layer is formed in a third direction intersecting the surface of the substrate and intersecting the first direction and the second direction , are set as plurals side by side. The semiconductor memory device according to claim 2, wherein a substrate is provided, and the first semiconductor layer is formed in a third direction intersecting the surface of the substrate and intersecting the first direction and the second direction extending upward and facing the plurality of first conductive layers in the first direction. The semiconductor memory device according to claim 3, wherein the first insulating layer includes silicon oxynitride (SiON). The semiconductor memory device according to claim 4, wherein the first charge accumulation layer includes silicon nitride (SiN). The semiconductor memory device according to any one of Claims 1 to 5, further comprising: a plurality of second semiconductor layers between the plurality of first semiconductor layers and the second conductive layer and The second conductive layers are opposite to each other and are arranged side by side in the second direction; and the second charge accumulation layer is arranged on the plurality of second semiconductor layers and the second semiconductor layers in the first direction. between the conductive layers and extending in the second direction so as to cover the plurality of regions between the second semiconductor layers and the second conductive layers; and the second insulating layer, extending in the first direction The second insulating layer is provided between the plurality of second semiconductor layers and the second charge storage layer, and the second insulating layer includes: a fourth region, which is located in the first direction and is located between the second semiconductor layer and the second semiconductor layer. One of the ends in the second direction is opposite; and the fifth region is in the first direction and is opposite to the other end of the second semiconductor layer in the second direction; and the sixth region, It is arranged between the fourth region and the fifth region in the second direction, and the concentration of nitrogen in the fourth region and the fifth region is higher than that of the nitrogen in the sixth region. concentration and lower. The semiconductor memory device according to claim 6, wherein: a substrate is provided, and the second conductive layer is formed in a third direction intersecting the surface of the substrate and intersecting the first direction and the second direction , are set as plurals side by side. The semiconductor memory device according to claim 7, wherein a substrate is provided, and the second semiconductor layer is formed in a third direction intersecting the surface of the substrate and intersecting the first direction and the second direction extending upward and facing the plurality of second conductive layers in the first direction. The semiconductor memory device according to claim 8, wherein the second insulating layer includes silicon oxynitride (SiON). The semiconductor memory device according to claim 9, wherein the second charge accumulation layer includes silicon nitride (SiN).

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