TW202226238A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device can appropriately control operation timing, according to the changes in the environment (for example, power supply voltage and temperature, etc.) when in use. A semiconductor memory device includes a temperature sensor 18 that detects the temperature of the semiconductor memory device, a voltage detection portion (ring oscillator 14 and counter 15) that detects the power supply voltage of the semiconductor memory device, and a control portion 10 that controls the operation timing in the semiconductor memory device to meet the specific conditions, according to the temperature detected by the temperature sensor 18 after the power is applied, and the voltage detected by the voltage detection unit after the power is applied.

Description

semiconductor memory device

The present invention relates to semiconductor memory devices.

In a semiconductor memory device, such as a dynamic random access memory (DRAM), as the transmission speed of a signal increases, it is necessary to properly control the operation timing.

For example, in the technique described in Patent Document 1, after the power is turned on, a signal output from a ring oscillator having a PVT (Process/Power Voltage/Temperature) variation correlation characteristic of a semiconductor memory device follows the rising edge and falling edge of the output signal. The number of edges can control the operation timing (start time and hold time) of the internal clock. [Prior Technology Literature] [Patent Literature]

[Patent Document 1] US Patent Application Publication No. 2018/0144781.

[Problems solved by the invention]

By the way, the ring oscillator has the following characteristics. When the power supply voltage is higher or the temperature is higher, the number of rising or falling edges of the output signal becomes more; when the power supply voltage of the ring oscillator is lower or the temperature is lower, the rising edge or falling edge of the output signal becomes more The number of edges becomes less. Therefore, based on the number of rising edges or falling edges of the output signal from the ring oscillator, for various situations (eg, low voltage at low temperature, high voltage at low temperature) of the environment (eg, temperature and power supply voltage, etc.) when the semiconductor memory device is used , low voltage at high temperature, high voltage at high temperature, etc.), it is difficult to control the operation sequence to meet the performance requirements (specifications).

Furthermore, in the technique described in Patent Document 1, since the operation sequence of the internal clock is controlled only once after the power is turned on, it is necessary to appropriately control the operation sequence according to the time change of the environment in which the semiconductor memory device is used. Doubt that becomes difficult.

In view of the above-mentioned problems, the present invention aims to obtain a semiconductor memory device capable of appropriately controlling the operation timing according to the environment during use.

In order to solve the above problems, the present invention provides a semiconductor memory device, comprising a temperature sensor for detecting the temperature of the semiconductor memory device, a voltage detection part for detecting the power supply voltage of the semiconductor memory device, and The temperature detected by the temperature sensor and the power supply voltage detected by the voltage detection section after the power is turned on are used to control the operation sequence in the semiconductor memory device, so as to satisfy the control section of specific conditions.

According to the present invention (Invention 1), the temperature inside the semiconductor memory device is controlled according to the temperature detected by the temperature sensor after the power is turned on and the power supply voltage detected by the voltage detection section after the power is turned on. Therefore, for various scenarios of temperature and power supply voltage (for example, low voltage at low temperature, high voltage at low temperature, low voltage at high temperature, high voltage at high temperature, etc.), the operation sequence can be controlled to meet the Certain conditions (eg, performance requirements, etc.). Therefore, for example, compared with the case of controlling the operation timing based only on the number of rising edges or falling edges of the signal output from the ring oscillator, the operation timing according to the environment at the time of use can be more appropriately controlled, and therefore, the application can be realized. A semiconductor memory device with improved performance such as increased transmission speed. Furthermore, according to the present invention (Invention 1), for example, since the operation timing can be controlled at any timing after each power-on, the operation can be appropriately controlled in accordance with the time change of the environment when the semiconductor memory device is used. timing.

In the above invention (Invention 1), in the power-on sequence executed when the power of the semiconductor memory device is turned on, the operation sequence of the semiconductor memory device can be controlled (Invention 2).

According to the present invention (Invention 2), the operation sequence can be appropriately controlled based on the temperature and the power supply voltage of the semiconductor memory device during the period from the power-on to the start of normal operation of the semiconductor memory device.

In the above inventions (Inventions 1 to 2), when a specific command is input to the semiconductor memory device, the control unit can control the operation sequence of the semiconductor memory device (Invention 3).

According to the present invention (Invention 3), for example, since each time a specific command is input to the above-mentioned semiconductor memory device, the operation timing is appropriately controlled based on the temperature and the power supply voltage of the semiconductor memory device when the command is input, and therefore, according to the semiconductor memory device The time change of the environment in which the device is used can appropriately control the operation sequence.

In the above invention (Invention 3), the control section may control the operation sequence of the semiconductor memory device before executing the specific command (Invention 4).

According to the present invention (Invention 4), since a specific instruction can be executed based on the controlled operation timing, the instruction can be appropriately executed in accordance with the environment at the time of use.

In the above inventions (Inventions 1 to 4), when the semiconductor memory device includes a memory that requires an update operation, the control section may control the operation sequence of the semiconductor memory device during the update operation of the memory (Invention 5) .

According to the present invention (Invention 5), for example, each time an update operation of the memory is performed, the operation sequence is appropriately controlled based on the temperature and the power supply voltage of the conductor memory device when the update command is executed, so that the operation sequence is appropriately controlled according to the use time of the semiconductor memory device. The time change of the environment can properly control the operation sequence. Furthermore, according to the present invention (Invention 5), since the operation timing can be controlled during the execution of the update operation (that is, when a specific command (for example, a valid command such as a read command and a write command, etc.) is not executed, etc., The timing of operations can be controlled without interfering with specific instructions being executed.

In the above inventions (Inventions 1 to 5), the temperature detected by the temperature sensor, the power supply voltage detected by the voltage detection section, and the query corresponding to the delay amount of the operation sequence in the semiconductor memory device are used The above-mentioned control unit can control the above-mentioned operation sequence (Invention 6).

According to the present invention (Invention 6), the delay amount of the operation sequence corresponding to the detected temperature and power supply voltage is extracted from the look-up table, and based on the extracted delay amount of the operation sequence, the operation sequence can be simply and appropriately controlled.

In the above invention (Invention 6), the voltage detection section can detect the power supply voltage (Invention 7) based on the switching times of the signal output from a specific ring oscillator operated by the power supply voltage.

According to the present invention (Invention 7), for example, since the more switching times of the signal output from the ring oscillator, the higher the detected power supply voltage; the less the signal switching times, the lower the detected power supply voltage, so using The signal switching times can appropriately control the operation timing.

Here, the high power supply voltage of the semiconductor memory device has the same effect as the high processing speed of the semiconductor memory device; the low power supply voltage of the semiconductor memory device has the same effect as the slow processing speed of the semiconductor memory device. Therefore, detecting that the power supply voltage of the semiconductor memory device is high actually means that the processing speed of the semiconductor memory device is fast; detecting that the power supply voltage of the semiconductor memory device is low is actually detecting that the processing speed of the semiconductor memory device is slow. Furthermore, it should be noted in the following description that the processing of the semiconductor memory device (eg, high speed, medium speed or low speed) may be described in conjunction with the corresponding supply voltage (eg high voltage, medium voltage or low voltage). [Inventive effect]

According to the semiconductor memory device of the present invention, the operation sequence can be more appropriately controlled according to the environment during use.

Hereinafter, the semiconductor memory device related to the embodiment of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to these Examples. [Example 1]

FIG. 1 is a block diagram showing the configuration of the control unit of the semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device related to the embodiment of the present invention includes a control unit 10 for sending and receiving signals (eg, chip selection signal, data signal, data strobe signal, etc.) between external devices (eg, memory controller, etc.). A clock signal, etc.) interface portion (not shown), and a memory array (not shown) having a plurality of memory cells arranged in a matrix. The control part 10 , the interface part, and the memory array are respectively composed of specialized hardware devices and logic circuits.

Based on the write request received from the external device of the interface part, the control part 10 controls the data writing to the memory array. Furthermore, based on the read request received from the external device of the interface part, the control part 10 controls the data read to the memory array. Further, according to the temperature detected by the temperature sensor 18 (described below) after the power is turned on, and the power supply voltage detected by the voltage detection section (described below) after the power is turned on, The control unit 10 controls the operation timing in the semiconductor memory device to satisfy specific conditions (eg, performance requirements).

Furthermore, the control unit 10 may control the operation sequence in the semiconductor memory device in the power-on sequence executed when the semiconductor memory device is powered on. Therefore, the operation sequence can be appropriately controlled based on the temperature and the power supply voltage of the semiconductor memory device during the period from when the power is turned on to when the normal operation of the semiconductor memory device starts.

Further, when a specific command (for example, a valid command such as a read command and a write command, etc.) is input to the semiconductor memory device, the control section 10 controls the operation sequence in the semiconductor memory device. Therefore, each time a specific command is input to the semiconductor memory device, the operation sequence is appropriately controlled based on the temperature and power supply voltage of the semiconductor memory device when the command is input. Control the operation timing appropriately.

Furthermore, before executing a specific command, the control unit 10 can control the operation sequence in the semiconductor memory device. Thereby, since a specific instruction can be executed based on the controlled operation sequence, the instruction can be appropriately executed according to the environment at the time of use.

Furthermore, using the temperature detected by the temperature sensor 18, the power supply voltage detected by the voltage detection section (which will be described below), and the look-up table 16 ( As will be described below), the control section 10 can control the operation timing. Therefore, the delay amount of the operation timing corresponding to the detected temperature and the power supply voltage is extracted from the look-up table 16, and based on the extracted delay amount of the operation timing, the operation timing can be simply and appropriately controlled.

Furthermore, the voltage detection section (described below) can detect the power supply voltage based on the number of signal switching times output by a particular ring oscillator 14 (described below) operating in accordance with the power supply voltage. Thereby, for example, since the more times the signal output from the ring oscillator 14 is switched, the higher the detected power supply voltage; and the less the number of times the signal is switched, the lower the detected power supply voltage, so the number of the signal to be switched is used. The operation timing can be appropriately controlled.

Furthermore, in this embodiment, when the control unit 10 requests data writing, the setting time (Write leveling setup time, tWLS) and the holding time (Write leveling hold time, tWLH) of the clock signal are controlled as follows: example to illustrate.

Referring to FIG. 1, the configuration of the control section 10 will be described. The control section 10 includes a power-on timing control section 11 , a timing control section 12 , a first oscillator 13 , a ring oscillator 14 , a counter 15 , a look-up table 16 , a timing setting section 17 , and a temperature sensor 18 . In addition, here is a brief description, and the peripheral configuration in the semiconductor memory device (for example, the configuration of the control command decoder, the memory array, and the interface portion, etc.) is not shown.

When the semiconductor memory device is powered on and the external power supply voltage VDD is applied, the power-on sequence control unit 11 executes a specific power-on sequence. Here, the power-on sequence includes, for example, generating an initial internal power supply based on the external power supply voltage VDD, reading a trim code for adjusting the internal power supply voltage, and adjusting the internal power supply voltage based on the external power supply voltage VDD and the trim code, etc. . Furthermore, when the execution of the power-on sequence is completed, the power-on sequence control unit 11 outputs a pre-chip preparation signal PCHRDY indicating the end of the power-on sequence to the sequence control unit 12 .

When the pre-chip preparation signal PCHRDY is input, the timing control section 12 outputs the signal TRMEN for effective timing control processing to the first oscillator 13 . Furthermore, the timing control unit 12 outputs the signal CNTEN for detecting the temperature and the power supply voltage of the semiconductor memory device to the ring oscillator 14 and the temperature sensor 18 . Furthermore, the timing control unit 12 outputs the signal CALC to the look-up table 16 according to the operation timing required by the temperature and the power supply voltage of the semiconductor memory device.

Furthermore, the timing control unit 12 outputs the signal CHG for setting the required operation timing to the timing setting unit 17 . Furthermore, when the signal CHG is output to the timing setting unit 17 , the timing control unit 12 outputs a chip ready signal CHRDY indicating that the semiconductor memory device is in an access state (die ready state (standby state)) to other components in the control unit 10 . device or circuit (illustration omitted).

Furthermore, the timing control unit 12 outputs the signal CHG to the timing setting unit 17 when the signal PACT from the command decoder (not shown) indicating that a specific command has been input to the semiconductor memory device is input.

During the period in which the high-level signal TRMEN is input from the timing control unit 12 , the first oscillator 13 generates an oscillation signal OSC at specific intervals, and outputs the oscillation signal OSC to the timing control unit 12 and the ring oscillator 14 .

The ring oscillator 14 is configured to be operated by an external power supply or an internal power supply voltage (power supply voltage), and outputs an oscillation signal RINGO whose frequency corresponds to the power supply voltage to the counter during the period in which the high-level signal TRMEN is input from the timing control unit 12 15. Here, the ring oscillator 14 is configured to output a high frequency (ie, a high number of switching times) oscillation signal RINGO when the power supply voltage is higher. Furthermore, in order to control the correct operation timing, the ring oscillator 14 can also be controlled by a device or circuit that becomes the control object of the operation timing (for example, an input buffer in the interface or a circuit to which a signal output from the input buffer is input, etc. ) and the same device or circuit and operate from the same power source.

When the oscillating signal RINGO is input from the ring oscillator 14, the counter 15 counts the switching times of the oscillating signal RINGO. Then, the counter 15 outputs to the look-up table 16 a signal CNT<4:0> indicating the specific number of bits (here, 5 bits) of the count value. Furthermore, the value of the signal CNT<4:0> can be maintained in the counter 15 during the period from the timing control unit 12 to the ring oscillator 14 when the high-level signal CNTEN is newly input. Furthermore, in this embodiment, the ring oscillator 14 and the counter 15 are examples of the "voltage detection section" of the present invention.

During the period when the high-level signal TRMEN is input from the timing control unit 12, according to the signal CNT<4:0> input from the counter 15, and the specific number of bits representing the temperature range input from the temperature sensor 18 (here, 2 bit) signal TMP<1:0>, the look-up table 16 will indicate the delay amount of the operation timing (here, set time (tWLS) and hold time (tWLH)) for a specific number of bits (here, 5 bits) The signal PTIM<4:0> is output to the timing setting unit 17 . Furthermore, the configuration example of the lookup table will be as follows.

When the high level signal TRMEN is input from the timing control unit 12, the timing setting unit 17 uses the signal PTIM<4:0> input from the look-up table 16 as a specific number of bits for setting the operation timing (here, 5 bits ) signal TIM<4:0>, which is output to a device or circuit (eg, a delay circuit, etc.) for controlling the operation sequence of the device or circuit that becomes the control object of the operation sequence.

When the high-level signal TRMEN is input from the timing control unit 12, the temperature sensor 18 detects the temperature of the semiconductor memory device, and sets a specific bit of a temperature range (eg, high temperature, medium temperature, low temperature, etc.) corresponding to the detected temperature The signal TMP<1:0> of the number (here, 2 bits) is output to the timing setting unit 17 . Furthermore, when the signal PACT from the command decoder (not shown) is input to indicate that a specific command has been input to the semiconductor memory device, the temperature sensor 18 detects the temperature of the semiconductor memory device, and sets the signal TMP< 1:0> input to the timing setting unit 17 . Furthermore, the value of the signal TMP<1:0> can be maintained at the temperature sensor 18 during the period from the timing control unit 12 to the new input of the high-level signal CNTEN.

Next, the operation of the semiconductor memory device of this embodiment will be described with reference to FIG. 2 . Fig. 2 is a time-varying graph of the voltage of each signal in the control unit.

First, when the pre-chip preparation signal PCHRDY indicating the end of the power-on sequence is input, the timing control unit 12 outputs the high-level signal TRMEN to the first oscillator 13 . During the period in which the high level signal TRMEN is input, the first oscillator 13 generates an oscillation signal OSC at specific intervals, and outputs the oscillation signal OSC to the timing control unit 12 and the ring oscillator 14 .

At time t1 , the timing control unit 12 outputs the high-level signal CNTEN to the ring oscillator 14 and the temperature sensor 18 . During the period of outputting the high level signal CNTEN, the ring oscillator 14 outputs to the counter 15 an oscillation signal RINGO with a frequency corresponding to the power supply voltage. Furthermore, the counter 15 counts the switching times of the oscillation signal RINGO, and the signal CNT<4:0> representing the count value is output to the look-up table 16 .

Here, in this embodiment, according to the temperature range corresponding to the temperature of the semiconductor memory device detected by the temperature sensor 18, the switching times of the oscillation signal RINGO are classified into a specific number (here, three) of temperatures one of the ranges. In the example of Fig. 2, when the signal CNT<4:0> value is 12, the power supply voltage of the semiconductor memory device is classified as low voltage (low speed processing), when the signal CNT<4:0> value is At 16:00, the power supply voltage of the semiconductor memory device is classified as medium voltage (medium-speed processing), and when the signal CNT<4:0> value is 21, the power supply voltage of the semiconductor memory device is high voltage (high-speed processing).

Furthermore, when the high-level signal CNTEN is input from the timing control unit 12, the temperature sensor 18 detects the temperature of the semiconductor memory device, and will indicate the temperature range corresponding to the detected temperature (eg, high temperature, medium temperature, low temperature). ) signal TMP<1:0> is output to the lookup table 16 .

Then, at time t2 , the timing control unit 12 outputs a high-level signal CALC to the look-up table 16 . The look-up table 16 determines the delay amount according to the signal CNT<4:0> input from the counter 15 and the signal TMP<4:0> representing the temperature range input from the temperature sensor 18 .

Here, with reference to FIG. 3, an example of a delay amount determination method will be described. Figures 3 (a) to (c) are diagrams showing the configuration of the look-up table 16 . As shown in FIG. 3(a), each signal PTIM<4:0> value (0~31 in FIG. 3(a)) in the look-up table 16 corresponds to a delay amount. In the example of Figure 3(a), the higher the value of the follower signal PTIM<4:0> from 0 to 15, the higher the delay amount; the higher the value of the follower signal PTIM<4:0> from 16 to 31 High, the amount of delay increases in the negative direction. Furthermore, in Fig. 3 (a), x is an arbitrary positive number. Furthermore, in this embodiment, the setting time (tWLS) of the clock signal is improved according to the delay in the positive direction; the holding time (tWLH) of the clock signal is improved according to the delay in the negative direction.

Furthermore, as shown in FIG. 3(b), the temperature range of each specified number (here, 3) and the voltage range of each specified number (here, 3) in the look-up table 16, and the signal CNT <4:0> values correspond. In addition, in FIG. 3 (b), y1, y2, y3, and y4 (y1<y2<y3<y4) are arbitrary numbers. Here, for example, when the value of the signal TMP<1:0> is 0b01, and the value of the signal CNT<4:0> is 16, the power supply voltage is determined to be a medium voltage. Furthermore, when the value of the signal TMP<1:0> is 0b11, and the value of the signal CNT<4:0> is 21, the power supply voltage is determined to be a high voltage.

Furthermore, as shown in FIG. 3(c), the temperature range of each specified number (here, 3) and the voltage range of each specified number (here, 3) in the look-up table 16, and the signal PTIM <4:0> values correspond. In Figure 3(c), when the temperature of the semiconductor memory device is low (signal TMP<1:0> value is 0b00), the lower the power supply voltage, the greater the absolute value of the delay; When the temperature is high (when the signal TMP<1:0> value is 0b11), the higher the power supply voltage, the greater the absolute value of the delay amount.

Here, as above, when the value of the signal TMP<1:0> is 0b01, and the value of the signal CNT<4:0> is 16 (that is, when the voltage is in the middle), it is determined that the value of the signal PTIM<4:0> is 0 ( In Fig. 3(a), 0 ps). Furthermore, when the value of the signal TMP<1:0> is 0b11, and the value of the signal CNT<4:0> is 21 (that is, when the voltage is high), the value of the signal PTIM<4:0> is determined to be 5 (Fig. 3). (a), +5x ps).

Therefore, the delay amount is determined based on the signal CNT<4:0> input from the counter 15 and the signal TMP<1:0> representing the temperature range input from the temperature sensor 18 .

Returning to FIG. 2 , at time t3 , the timing control unit 12 outputs the high-level signal CHG to the timing setting unit 17 . The timing setting unit 17 outputs the signal PTIM<4:0> input from the look-up table 16 as the signal TIM<4:0> for setting the operation timing to the device or circuit for controlling the control object that becomes the operation timing A device or circuit (eg, a delay circuit, etc.) that operates in a sequential manner.

Furthermore, the timing control unit 12 outputs a chip ready signal CHRDY indicating that the semiconductor memory device is in an access state (chip ready state (standby state)) to other devices or circuits (not shown) in the control unit 10 .

Therefore, in the power-on sequence executed when the power of the semiconductor memory device is turned on, the operation sequence in the semiconductor memory device can be controlled.

Next, an example of controlling the operation sequence in the semiconductor memory device when a designated command is input will be described with reference to FIG. 4 . Fig. 4 is a timing chart showing the voltage change of the signals of each part in the control part when a specific finger is input.

First, it is assumed that the semiconductor memory device is in a standby state. In this state, the timing control unit 12 outputs the high-level signal CNTEN to the temperature sensor 18 at arbitrary intervals.

At time t11 , when the signal PACT from the command decoder (not shown) indicating that a specific command has been input to the semiconductor memory device is input, the timing control unit 12 outputs the high-level signal CALC to the look-up table 16 . According to the signal CNT<4:0> input from the counter 15 and the signal TMP<4:0> representing the temperature range input from the temperature sensor 18, the lookup table 16 will indicate the signal PTIM of the determined delay amount <4:0> is output to the timing setting unit 17 .

Next, at time t12 , the timing control unit 12 outputs the high-level signal CHG to the timing setting unit 17 . The timing setting unit 17 outputs the signal TIM<4:0> to a device or circuit (eg, a delay circuit, etc.) for controlling the operation timing of the device or circuit that is the control target of the operation timing.

Furthermore, at time t13, the timing control unit 12 may control other devices or circuits in the control unit 10 when starting to execute the specified command.

Therefore, when a designated command is input, the operation timing in the semiconductor memory device can be controlled.

FIG. 5 shows an example of a control aspect at the operation timing of the semiconductor memory device related to the first embodiment. Figure 5(a)~(b) is an example diagram of the control state of the operation sequence corresponding to the power supply voltage at high temperature, and Figure 5(c)~(d) is the operation sequence corresponding to the power supply voltage at low temperature An example diagram of the control state.

As shown in FIG. 5( a ), when the semiconductor memory device is at a high temperature, assuming that the power supply voltage is higher, the set time tWLS cannot meet the performance requirements. Here, as described above, at high temperature, by controlling the operation sequence so that the absolute value of the delay amount increases as the power supply voltage becomes higher, the set time tWLS can satisfy the performance requirement even if the power supply voltage becomes higher. Here, as shown in Fig. 5(b), the holding time tWLH can also satisfy the performance requirement.

Furthermore, as shown in FIG. 5(d), when the semiconductor memory device is at a low temperature, the holding time tWLH cannot meet the performance requirements, assuming that the voltage supply is lower. Here, as described above, at low temperature, by controlling the operation timing so that the absolute value of the delay amount becomes larger as the power supply voltage becomes lower, the hold time tWLH can satisfy the performance requirement even if the power supply voltage becomes lower. Here, as shown in Fig. 5(c), the set time tWLS can also satisfy the performance requirement.

As described above, according to the semiconductor memory device of the present embodiment, since the temperature detected by the temperature sensor 18 after the power is turned on, and the temperature detected by the ring oscillator 14 and the counter 15 (voltage detected after the power is turned on) The power supply voltage detected by the part) is used to control the operation sequence in the semiconductor memory device to meet the performance requirements (specific conditions). Therefore, for various situations of temperature and power supply voltage (for example, low voltage at low temperature, high voltage at low temperature, Low voltage at high temperature, high voltage at high temperature, etc.), the sequence of operations can be controlled to meet specific conditions (eg, performance requirements, etc.). Therefore, for example, compared to the case where the operation timing is controlled only based on the number of rising edges or falling edges of the signal output from the ring oscillator 14, the operation timing according to the environment at the time of use can be more appropriately controlled, and therefore, it is possible to achieve It is used in semiconductor memory devices for performance improvement such as increasing transmission speed. Furthermore, according to the semiconductor memory device of the present embodiment, for example, since the operation sequence can be controlled at any timing after each power-on, the operation sequence can be appropriately controlled according to the time change of the environment when the semiconductor memory device is used. .

Furthermore, according to the semiconductor memory device of the present embodiment, for example, since the operation sequence can be controlled after the power is turned on, the process of presetting the operation sequence can be omitted in the test process during manufacture. In this way, the testing process when manufacturing the semiconductor memory device can be simplified. [Example 2]

Hereinafter, Embodiment 2 concerning the present invention will be explained. The difference between the semiconductor memory device of the present embodiment and the first embodiment is that the operation timing is controlled when a predefined command is input. Hereinafter, a configuration different from that of Embodiment 1 will be explained.

FIG. 6 shows a configuration diagram of the semiconductor memory device according to this embodiment. In the example of FIG. 6, the signal CMD indicating that a predefined command is input to the semiconductor memory device is input to the timing control unit 12 from a command decoder (not shown).

Here, the pre-defined command may be, for example, an instruction only for executing the control operation sequence, or an instruction combining the instruction for executing the control operation sequence and a designated command. Furthermore, the specified commands included in the predefined commands may be, for example, read commands, write commands, or commands requiring relatively high timing accuracy (eg, read leveling and write leveling, etc.).

In this embodiment, when the signal CMD is input from the command decoder (not shown), the timing control unit 12 outputs the signal TRMEN for effective timing control processing to the first oscillator 13 . Furthermore, the timing control unit 12 outputs the signal CNTEN for detecting the temperature and power supply voltage of the semiconductor memory device to the ring oscillator 14 and the temperature sensor 18 . Furthermore, the timing control unit 12 outputs the signal CALC for requesting the operation timing corresponding to the temperature and the power supply voltage of the semiconductor memory device to the look-up table 16 .

Furthermore, the timing control unit 12 outputs the signal CHG for setting the required operation timing to the timing setting unit 17 . Furthermore, when the signal CHG is output to the timing setting unit 17, the timing control unit 12 executes other commands (eg, read command, write command, read equalization, and write equalization, etc.) included in the pre-defined commands to Control other devices or circuits in the control unit 10 .

Therefore, according to the semiconductor memory device of the present embodiment, the same effects as those of the first embodiment described above can be exhibited. [Example 3]

Hereinafter, Example 3 concerning the present invention will be explained. The difference between the semiconductor memory device of this embodiment and the above-mentioned embodiments is that when there is a memory that needs an update operation, the operation sequence in the semiconductor memory device is controlled during the execution of the memory update operation. Hereinafter, descriptions will be made regarding configurations different from those of the above-described embodiments.

Furthermore, the semiconductor memory device of this embodiment may be a semiconductor memory device (eg, DRAM, pSRAM, etc.) that requires a memory refresh operation.

FIG. 7 is a configuration diagram of the control unit 10 of the semiconductor memory device according to the present embodiment. In this embodiment, the control section 10 includes a second oscillator 19 in addition to the above-described sections 11 to 18 . Furthermore, in the present embodiment, the timing control unit 12 and the temperature sensor 18 are configured to input a signal SREF from a command decoder (omitted from the figure) indicating that a refresh operation is required.

When the chip preparation signal CHRDY is input from the timing control unit 12 , the second oscillator 19 generates a signal SRTRIG for triggering the refresh operation at specific intervals, and outputs the signal to the timing control unit 12 .

Furthermore, when there are no characteristics related to the temperature and power supply voltage of the semiconductor memory device, the first oscillator 13 and the second oscillator 19 may set any one of the first oscillator 13 and the second oscillator 19 to perform the first oscillator 13 and the second oscillator 19. The respective functions of the first oscillator 13 and the second oscillator 19.

Next, the operation of the semiconductor memory device of this embodiment will be described with reference to FIG. 8 . FIG. 8 is a timing chart of signal voltage changes of various parts in the control part 10 . Here, it is assumed that each time the signal SRTRIG is switched four times, the operation timing is determined at the falling edge of the fourth signal SRTRIG, and every time the signal SRTRIG is switched twice, at the rising edge of the second signal SRTRIG, the input high level is The signal SREF is sent to the timing control unit 12 .

First, at time t21 , when the operation timing starts to be determined, the timing control unit 12 outputs the signal TRMEN of the effective timing control processing to the first oscillator 13 . Furthermore, the timing control unit 12 outputs the signal CNTEN for detecting the temperature and power supply voltage of the semiconductor memory device to the ring oscillator 14 and the temperature sensor 18 . Furthermore, the timing control unit 12 outputs the signal CALC to the look-up table 16 according to the operation timing required by the temperature and the power supply voltage of the semiconductor memory device.

Then, at time t22, when the high level signal SREF is input to the timing control unit 12, the timing control unit 12 sets the operation timing when the update operation starts.

FIG. 9 shows a timing chart of signal voltage changes of various parts in the control part 10 when the update operation is performed. At time t31, when the high-level signal SREF is input from the command decoder (not shown), the timing control unit 12 outputs the high-level signal CALC to the look-up table. The look-up table 16 determines the delay amount according to the signal CNT<4:0> input from the counter 15 and the signal TMP<4:0> representing the temperature range input from the temperature sensor 18, and the output indicates the determined delay The signal PTIM<4:0> of the delay amount is sent to the timing setting unit 17 .

Next, at time t32 , the timing control unit 12 outputs the high-level signal CHG to the timing control unit 17 . Then, the timing control unit 17 outputs the signal of TIM<4:0> to a device or circuit (eg, a delay circuit, etc.) for controlling the operation timing of the device or circuit that is the control target of the operation timing. Furthermore, the timing control unit 12 performs an update operation to control other devices or circuits in the control unit 10 .

Furthermore, the timing control unit 12 performs an update operation to control other devices or circuits in the control unit 10 .

Returning to FIG. 8, at time t23, when a signal indicating the input of the read or write command is input from the command decoder (not shown), the timing control unit 12 executes the read or write command to control the control other devices or circuits within section 10. In the above case, during the period from time t22 to time t23, the read or write command is executed according to the controlled operation timing.

Next, at time t24, when the high-level quasi-signal SREF is input to the timing control unit 12, the timing control unit 12 sets the operation timing when starting to perform the update operation.

Then, at time t25 , when starting to determine the operation timing, the timing control section 12 outputs the signal TRMEN for effective timing control processing to the first oscillator 13 . Furthermore, the timing control unit 12 outputs the signal CNTEN for detecting the temperature and power supply voltage of the semiconductor memory device to the ring oscillator 14 and the temperature sensor 18 . Furthermore, the timing control unit 12 outputs the signal CALC to the look-up table 16 according to the operation timing required by the temperature and the power supply voltage of the semiconductor memory device.

Here, before inputting the high-level signal SREF to the timing control unit 12, when a signal indicating that a read or write command has been input is input from a command decoder (not shown), the timing control unit 12 keeps the signal SREF at a high level standard, and execute read or write commands to control other devices or circuits in the control unit 10 . Then, at time t26 after the execution of the read or write command ends, the sequence control unit 12 starts to execute the update operation (as shown in FIG. 9 , including the set operation sequence).

Next, at time t27, when the high-level quasi-signal SREF is input to the timing control unit 12, the timing control unit 12 starts to perform the update operation (as shown in FIG. 9, including the setting operation sequence). Here, during the execution of the update operation, when a signal indicating that a read or write command has been input is input from a command decoder (not shown), at time t28 after the execution of the update operation, the timing control section 12 executes the read or write command. Fetch or write commands to control other devices or circuits within the control unit 10 .

As described above, according to the semiconductor memory device of the present embodiment, for example, since the refresh operation of the memory is performed each time, the operation timing can be appropriately controlled according to the temperature and the power supply voltage of the semiconductor memory device performed by the refresh operation, so according to The time change of the environment in which the semiconductor memory device is used can appropriately control the operation sequence. Furthermore, according to the semiconductor memory device of the present embodiment, since the operation timing can be controlled during the execution of the update operation (that is, when a specific command (for example, a valid command such as a read command and a write command, etc.) is not executed), the operation timing can be controlled. It is thus possible to control the timing of operations without interfering with the specific instructions being executed.

The above-described respective embodiments are for the simple understanding of the present invention, and are not described to limit the present invention. Therefore, each feature shown in each of the above-described embodiments is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

For example, in the above embodiments, the case of controlling the setting time (tWLS) and holding time (tWLH) of the clock signal when data writing is required has been described as an example, but the present invention is not limited to this case. For example, when data reading is required, the set time and hold time of the clock signal can be controlled, and other operation timings can also be controlled (for example, low word line activation timing, sense amplifier activation timing, field element line activation timing, etc.) .

Furthermore, in each of the above-described embodiments, the temperature of the semiconductor memory device is classified into any one of the three temperature ranges, and the power supply voltage of the semiconductor memory device is classified into any one of the three voltage ranges. However, the present invention is not limited to this case. For example, the temperature of the semiconductor memory device can be classified into any one of plural temperature ranges other than three, and the power supply voltage of the semiconductor memory device can be classified into any one of the plural other than three power supply ranges.

In addition, in each of the above-described embodiments, the configuration of the control unit 10 is an example, and may be appropriately changed or various other configurations may be employed.

10: Control Department 11: Power on sequence control part 12: Timing Control Department 13: First oscillator 14: Ring Oscillator 15: Counter 16: Lookup table 17: Timing setting section 18: Ring temperature sensor 19: Second oscillator VDD: Power supply voltage PCHRDY: Pre-chip preparation signal OSC: Oscillation signal CHRDY: Chip ready signal CNTEN: Signal output to ring oscillator 14 PACT: A signal from the command decoder indicating that a specific command has been input to the semiconductor memory device TRMEN: Signal for effective timing control processing CALC: A signal for requesting operation timing corresponding to the temperature and power supply voltage of the semiconductor memory device TMP<1:0>: Signal representing the temperature range input from the temperature sensor 18 CHG: Signal output to the timing setting section 17 RINGO: oscillating signal CNT＜4:0＞: Signal representing count value PTIM<4:0>: Signal input from lookup table 16 TIM＜4:0＞: Signal for setting operation timing tWLS: set time tWLH: hold time SRTRIG: The signal used to trigger the update operation SREF: A signal indicating a request to perform an update operation

FIG. 1 is a block diagram showing the configuration of the control unit of the semiconductor memory device according to the first embodiment of the present invention. Fig. 2 is a timing chart of voltage changes of signals of various parts in the control part. (a)~(c) in Figure 3 are examples of the configuration of the lookup table. Fig. 4 is a graph showing the time change of the signal voltage of each part in the control part when a specific command is input. (a)~(b) of FIG. 5 are examples of the control state of the operation sequence corresponding to the power supply voltage at high temperature, and (c)~(d) are the control states of the operation sequence corresponding to the power supply voltage at low temperature example image. FIG. 6 is a diagram showing a configuration example of a semiconductor memory device according to Embodiment 2 of the present invention. FIG. 7 is a diagram showing a configuration example of a semiconductor memory device according to Embodiment 3 of the present invention. FIG. 8 is a timing chart of voltage changes of signals of various parts in the control part. FIG. 9 is a timing chart of voltage changes of signals of various parts in the control part when the update operation is performed.

10: Control Department

11: Power on sequence control part

12: Timing Control Department

13: First oscillator

14: Ring Oscillator

15: Counter

16: Lookup table

17: Timing setting section

18: Ring temperature sensor

VDD: Power supply voltage

PCHRDY: Pre-chip preparation signal

OSC: Oscillation signal

CHRDY: Chip ready signal

CNTEN: Signal output to ring oscillator 14

PACT: A signal from the command decoder indicating that a specific command has been input to the semiconductor memory device

TRMEN: Signal for effective timing control processing

CALC: A signal for requesting operation timing corresponding to the temperature and power supply voltage of the semiconductor memory device

TMP<1:0>: Signal representing the temperature range input from the temperature sensor 18

CHG: Signal output to the timing setting section 17

RINGO: oscillating signal

CNT<4:0>: Signal representing count value

PTIM<4:0>: Signal input from lookup table 16

TIM<4:0>: Signal for setting operation timing

Claims (7)

A semiconductor memory device, comprising: a temperature sensor to detect the temperature of the semiconductor memory device; a voltage detection part, which detects the power supply voltage of the semiconductor memory device; and The control part controls the operation sequence in the semiconductor memory device according to the temperature detected by the temperature sensor 18 after the power is turned on and the power supply voltage detected by the voltage detection part after the power is turned on , to meet certain conditions. The semiconductor memory device of claim 1, wherein the control section controls the operation sequence in a power-on sequence performed when the semiconductor memory device is powered on. The semiconductor memory device of claim 1, wherein the control section controls the operation sequence when a specific command is input to the semiconductor memory device. The semiconductor memory device of claim 1, wherein the control section controls the operation sequence before the specific instruction is executed. The semiconductor memory device of claim 1, wherein when the semiconductor memory device has a memory that needs an update operation, the control unit controls the operation timing during the execution of the memory update operation. The semiconductor memory device of claim 1, wherein the control section utilizes the temperature detected by the temperature sensor, the power supply voltage detected by the voltage detection section, and operations within the semiconductor memory device A look-up table corresponding to the delay amount of the timing controls the operation timing. The semiconductor memory device of claim 1, wherein the voltage detection section detects the power supply voltage according to the switching times of the signal output by a specific ring oscillator operated by the power supply voltage.

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