TW202225453A - Tensile nitride deposition systems and methods - Google Patents
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Abstract
Description
本申請案主張2020年10月23日申請之題為「TENSILE NITRIDE DEPOSITION SYSTEMS AND METHODS」的美國專利申請案第17/078,793號的權益及優先權,其以全文引用的方式併入本文中。This application claims the benefit of and priority to US Patent Application Serial No. 17/078,793, filed October 23, 2020, entitled "TENSILE NITRIDE DEPOSITION SYSTEMS AND METHODS," which is incorporated herein by reference in its entirety.
本技術係關於半導體系統及製程。更特定言之,本技術係關於可形成拉伸的氮化矽層的沉積系統及方法。This technology relates to semiconductor systems and processes. More particularly, the present technology relates to deposition systems and methods that can form stretched silicon nitride layers.
積體電路係藉由在基板表面上產生複雜圖案化材料層的製程實現的。在基板上產生圖案化材料需要可控的用於形成及移除曝露材料的方法。材料特性可影響器件操作的方式,且亦可影響彼此相對移除膜的方式。電漿增強沉積可產生具有某些特性的膜。形成的許多膜需要進行額外的處理,以調整或增強膜的材料特性,以便提供合適的性質。Integrated circuits are realized by processes that create complex patterned layers of material on the surface of a substrate. Creating patterned material on a substrate requires a controlled method for forming and removing the exposed material. Material properties can affect how the device operates, and can also affect how the films are removed relative to each other. Plasma enhanced deposition can produce films with certain properties. Many films formed require additional processing to adjust or enhance the material properties of the film in order to provide suitable properties.
由此,需要能用於產生高品質器件及結構的改進的系統及方法。本技術滿足此等及其他需要。Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology meets these and other needs.
本技術的實施例包括在基板上形成拉伸的氮化矽層的系統及方法。在一些實施例中,拉伸的氮化物層在前段製程或中段製程的半導體製造製程中可充當蝕刻終止層、CMP終止層或硬遮罩層。氮化物層的高拉伸應力可減小形成於在拉伸的氮化物層上或下方沉積的一或多個圖案化層中的孔、通道、溝槽及其他類型的開口的線邊緣粗糙度(line edge roughness; LER)及線寬度粗糙度(line width roughness; LWR)。由於半導體器件結構(例如nMOS電晶體)的關鍵尺寸持續減小,對於此等精確圖案化的開口的需要可增加。Embodiments of the present technology include systems and methods for forming a stretched silicon nitride layer on a substrate. In some embodiments, the stretched nitride layer may serve as an etch stop layer, CMP stop layer, or hard mask layer in front-end or mid-line semiconductor fabrication processes. The high tensile stress of the nitride layer can reduce the line edge roughness of holes, channels, trenches and other types of openings formed in one or more patterned layers deposited on or under the stretched nitride layer (line edge roughness; LER) and line width roughness (line width roughness; LWR). As the critical dimensions of semiconductor device structures, such as nMOS transistors, continue to decrease, the need for such precisely patterned openings may increase.
本技術的實施例可包括半導體處理方法,該等處理方法可包括使包含含氮前驅物、含矽前驅物及載體氣體的沉積氣體流至基板處理腔室的基板處理區域中。含氮前驅物與含矽前驅物的流率比可大於或約為1:1。方法可進一步包括由沉積氣體產生沉積電漿,以在半導體處理腔室中的基板上形成含矽及氮的層。可用處理電漿處理含矽及氮的層,在無含矽前驅物的情況下由載體氣體形成該處理電漿。處理電漿中載體氣體的流率可大於沉積電漿中載體氣體的流率。Embodiments of the present technology may include semiconductor processing methods that may include flowing a deposition gas including a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas into a substrate processing region of a substrate processing chamber. The flow rate ratio of nitrogen-containing precursor to silicon-containing precursor may be greater than or about 1:1. The method may further include generating a deposition plasma from a deposition gas to form a silicon and nitrogen containing layer on the substrate in the semiconductor processing chamber. The silicon and nitrogen containing layer may be treated with a processing plasma formed from a carrier gas in the absence of a silicon containing precursor. The flow rate of the carrier gas in the processing plasma may be greater than the flow rate of the carrier gas in the deposition plasma.
在示例性實施例中,含氮前驅物可包括氨,且含矽前驅物可包括矽烷。含氮前驅物可表徵為大於或約100 sccm的流率,且含矽前驅物可表徵為大於或約50 sccm的流率。在其他實施例中,載體氣體可包括分子氮(N 2)及氬氣中之至少一者。載體氣體中的分子氮可表徵為大於或約5000 sccm的流率,且載體氣體中的氬氣可表徵為大於或約2000 sccm的流率。在其他實施例中,處理腔室可表徵為在沉積含矽及氮層期間的沉積腔室壓力小於處理含矽及氮層期間的處理腔室壓力。在其他實施例中,可藉由向沉積氣體提供小於或約60瓦特的電漿功率產生沉積電漿。在其他實施例中,可藉由在無含矽前驅物的情況下向載體氣體提供大於或約100瓦特的電漿功率產生處理電漿。 In an exemplary embodiment, the nitrogen-containing precursor may include ammonia, and the silicon-containing precursor may include silane. The nitrogen-containing precursor can be characterized by a flow rate of greater than or about 100 seem, and the silicon-containing precursor can be characterized by a flow rate of greater than or about 50 seem. In other embodiments, the carrier gas may include at least one of molecular nitrogen ( N2 ) and argon. Molecular nitrogen in the carrier gas can be characterized as a flow rate greater than or about 5000 seem, and argon in the carrier gas can be characterized as a flow rate greater than or about 2000 seem. In other embodiments, the processing chamber may be characterized as the deposition chamber pressure during deposition of the silicon and nitrogen containing layer is less than the processing chamber pressure during processing of the silicon and nitrogen containing layer. In other embodiments, the deposition plasma may be generated by supplying the deposition gas with a plasma power of less than or about 60 watts. In other embodiments, the process plasma may be generated by supplying greater than or about 100 watts of plasma power to the carrier gas in the absence of a silicon-containing precursor.
在進一步示例性實施例中,可按小於或約10 Å/秒的沉積速率形成含矽及氮層。在其他實施例中,處理方法可產生處理後含矽及氮層,其為氮化矽層,表徵為大於或約1 GPa的拉伸應力以及小於或約20Å/分的濕蝕刻速率。In further exemplary embodiments, the silicon and nitrogen containing layer may be formed at a deposition rate of less than or about 10 Å/sec. In other embodiments, the processing method can produce a processed silicon and nitrogen containing layer that is a silicon nitride layer characterized by a tensile stress of greater than or about 1 GPa and a wet etch rate of less than or about 20 Å/min.
本技術的實施例亦可包括半導體處理方法,其包括在基板處理腔室的基板處理區域中的基板上沉積含矽及氮層。可用以第一電漿功率自沉積氣體產生的沉積電漿沉積含矽及氮層,該沉積氣體包括含氮前驅物及含矽前驅物。在一些實施例中,含氮前驅物與含矽前驅物的流率比大於或約為1:1。在其他實施例中,可按小於或約10 Å/秒的沉積速率形成含矽及氮層。方法可進一步包括用處理電漿處理含矽及氮層。可用大於第一電漿功率的第二電漿功率形成處理電漿。處理方法可產生含矽及氮層,其表徵為大於或約1 GPa的拉伸應力以及小於或約20Å/分的濕蝕刻速率。Embodiments of the present technology may also include semiconductor processing methods that include depositing a silicon and nitrogen containing layer on a substrate in a substrate processing region of a substrate processing chamber. The silicon- and nitrogen-containing layers may be deposited using a first plasma power from a deposition plasma generated from a deposition gas, the deposition gas including a nitrogen-containing precursor and a silicon-containing precursor. In some embodiments, the flow rate ratio of nitrogen-containing precursor to silicon-containing precursor is greater than or about 1:1. In other embodiments, the silicon and nitrogen containing layer may be formed at a deposition rate of less than or about 10 Å/sec. The method may further include treating the silicon and nitrogen containing layer with a treating plasma. The treatment plasma may be formed with a second plasma power greater than the first plasma power. The processing method can produce a silicon and nitrogen containing layer characterized by a tensile stress of greater than or about 1 GPa and a wet etch rate of less than or about 20 Å/min.
在示例性實施例中,可自無含矽前驅物或含氮前驅物的處理氣體形成處理電漿。在進一步實施例中,可由包括分子氮(N 2)的處理氣體形成處理電漿。在其他實施例中,可按大於或約10000 sccm的氮氣流率將分子氮輸送至半導體處理腔室。處理方法可產生含矽及氮層,其為表徵為小於或約3 at.%的氫的氮化矽層。 In an exemplary embodiment, the process plasma may be formed from a process gas without a silicon-containing precursor or a nitrogen-containing precursor. In further embodiments, the process plasma may be formed from a process gas comprising molecular nitrogen ( N2 ). In other embodiments, molecular nitrogen may be delivered to the semiconductor processing chamber at a nitrogen gas flow rate greater than or about 10,000 seem. The processing method can produce a silicon and nitrogen containing layer, which is a silicon nitride layer characterized by less than or about 3 at. % hydrogen.
本技術的實施例包括半導體處理方法,該等方法可包括在兩個或兩個以上循環中形成氮化矽層,該等循環可包括在基板處理腔室的基板處理區域中的基板上沉積氮化矽層的一部分,以及用處理電漿處理氮化矽層的一部分。可將氮化矽層的一部分沉積至小於或約15 Å的厚度。在一些實施例中,可按小於或約10 Å/秒的沉積速率形成氮化矽層的每一部分。在其他實施例中,對於剛沉積的氮化矽層的每一部分的處理操作可在小於或約15秒中發生。相比於剛沉積的部分,處理電漿可提高氮化矽層的經處理部分的拉伸應力及濕蝕刻速率。氮化矽層的經處理部分亦可表徵為小於或約3 at.%的氫位準。Embodiments of the present technology include semiconductor processing methods, which may include forming a silicon nitride layer in two or more cycles, which may include depositing nitrogen on a substrate in a substrate processing region of a substrate processing chamber A portion of the silicon nitride layer, and a portion of the silicon nitride layer is treated with a treatment plasma. A portion of the silicon nitride layer can be deposited to a thickness of less than or about 15 Å. In some embodiments, each portion of the silicon nitride layer may be formed at a deposition rate of less than or about 10 Å/sec. In other embodiments, processing operations for each portion of the just-deposited silicon nitride layer may occur in less than or about 15 seconds. Treating the plasma may increase the tensile stress and wet etch rate of the treated portion of the silicon nitride layer compared to the as-deposited portion. The processed portion of the silicon nitride layer may also be characterized by a hydrogen level of less than or about 3 at. %.
在示例性實施例中,可自沉積電漿沉積氮化矽層的部分,該沉積電漿自輸送至基板處理腔室的沉積氣體產生。沉積氣體可包括含氮前驅物及含矽前驅物。在一些實施例中,含氮前驅物可具有小於或約200 sccm的流率,且含矽前驅物可具有小於100 sccm的流率。處理方法可產生氮化矽層,其表徵為大於或約1 GPa的拉伸應力以及小於或約20Å/分的濕蝕刻速率。In an exemplary embodiment, portions of the silicon nitride layer may be deposited from a deposition plasma generated from deposition gases delivered to a substrate processing chamber. The deposition gas may include nitrogen-containing precursors and silicon-containing precursors. In some embodiments, the nitrogen-containing precursor may have a flow rate of less than or about 200 seem, and the silicon-containing precursor may have a flow rate of less than 100 seem. The processing method can produce a silicon nitride layer characterized by a tensile stress of greater than or about 1 GPa and a wet etch rate of less than or about 20 Å/min.
相比於常規的系統及形成氮化矽層的方法,此類技術可提供許多益處。舉例而言,在當自沉積過渡至處理操作時提高載體氣體的流率的實施例中,相比於常規的沉積-處理方法中觀察到的結果,基板上沉積的所處理含矽及氮材料中的拉伸應力可在較短的時間段內增加較大量。另外,在產生處理電漿的處理電漿功率的量大於產生沉積電漿的沉積電漿功率的量的實施例中,含矽及氮材料中的最終拉伸應力位準亦可得以提高。在其他實施例中,相比於常規的沉積-處理方法中觀察到的結果,本技術可產生具有較小原子百分比氫的含矽及氮層。較低原子百分比的氫可進一步提高拉伸應力位準,且減小含矽及氮層的濕蝕刻速率。結合以下描述和附圖更詳細地描述本技術的實施例以及其許多優點和特徵。Such techniques may provide many benefits over conventional systems and methods of forming silicon nitride layers. For example, in embodiments where the flow rate of the carrier gas is increased when transitioning from deposition to processing operations, the processed silicon and nitrogen containing materials deposited on the substrate are compared to the results observed in conventional deposition-processing methods Tensile stress in can increase by a larger amount in a shorter period of time. Additionally, in embodiments where the amount of process plasma power that generates the process plasma is greater than the amount of deposition plasma power that generates the deposition plasma, the final tensile stress level in the silicon- and nitrogen-containing material may also be increased. In other embodiments, the present techniques can produce silicon and nitrogen containing layers with smaller atomic percent hydrogen than those observed in conventional deposition-processing methods. Lower atomic percent hydrogen can further increase tensile stress levels and reduce wet etch rates for silicon and nitrogen containing layers. Embodiments of the present technology, along with its many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.
本技術包括在半導體基板上形成拉伸的氮化矽層的系統及處理方法的實施例。除其他功能以外,此等拉伸的氮化物層解決了在基板上的圖案化材料中形成愈來愈精確的通道、觸點、通孔、溝槽及其他類型的開口的難題。基板的圖案化材料與半導體材料之間的常規的低應力氮化物層缺少將圖案化開口的側壁保持為高度對準且光滑的力。因此,此等低應力氮化物層的圖案化操作產生粗糙的開口,該等開口係表徵為沿圖案化光阻層與氮化物蝕刻終止層之間的圖案化材料中形成的側壁的大的線邊緣粗糙度(LER)及線寬度粗糙度(LWR),或由於硬遮罩尺寸畸變。隨著半導體器件(例如nMOS電晶體)的關鍵尺寸持續減小,此等開口中的粗糙量變為更大的問題。此等常規形成的開口中的粗糙度程度越來越超過穩定、正常運行的積體電路所需的基板特徵關鍵尺寸的公差。The present technology includes embodiments of systems and processing methods for forming stretched silicon nitride layers on semiconductor substrates. Among other functions, these stretched nitride layers solve the challenge of forming increasingly precise channels, contacts, vias, trenches, and other types of openings in patterned materials on substrates. Conventional low stress nitride layers between the patterned material of the substrate and the semiconductor material lack the force to keep the sidewalls of the patterned openings highly aligned and smooth. Thus, patterning of these low stress nitride layers produces rough openings characterized by large lines along sidewalls formed in the patterned material between the patterned photoresist layer and the nitride etch stop layer Edge Roughness (LER) and Line Width Roughness (LWR), or dimensional distortion due to hard masks. As the critical dimensions of semiconductor devices, such as nMOS transistors, continue to decrease, the amount of roughness in these openings becomes a greater problem. The degree of roughness in these conventionally formed openings increasingly exceeds the tolerances of the critical dimensions of substrate features required for stable, functioning integrated circuits.
降低此等開口中粗糙度的一種方法是在具有增加拉伸應力的氮化矽層上形成開口。增加的拉伸應力增強相鄰圖案化材料的特性,此舉減小材料在側向方向上以不均勻速率蝕刻的趨勢。圖案化材料中形成的開口的特徵在於沿其側壁的線邊緣粗糙度(LER)及線寬度粗糙度(LWR)減小。可惜,形成具有增加拉伸應力的氮化矽層比形成常規的低應力氮化物層大體而言更難。藉由減少剛沉積氮化物層中Si-H及N-H鍵的數量且增加Si-N鍵的數量,可增大利用含矽氮及氫前驅物的電漿增強化學氣相沉積所沉積的氮化物層中的拉伸應力。Si-H及N-H鍵的數量減小可起因於自剛沉積的層移除氫。由於Si及N原子進入移除氫原子後留下的空間並且形成更多Si-N鍵,氮化物層中的總拉伸應力增大。形成高拉伸應力氮化物層的更多困難在於自剛沉積層移除氫原子的額外操作。One way to reduce the roughness in these openings is to form openings in the silicon nitride layer with increased tensile stress. The increased tensile stress enhances the properties of the adjacent patterned material, which reduces the tendency of the material to etch at non-uniform rates in the lateral direction. The openings formed in the patterned material are characterized by reduced line edge roughness (LER) and line width roughness (LWR) along their sidewalls. Unfortunately, forming silicon nitride layers with increased tensile stress is generally more difficult than forming conventional low stress nitride layers. By reducing the number of Si-H and N-H bonds and increasing the number of Si-N bonds in the as-deposited nitride layer, it is possible to increase the number of nitrides deposited by plasma enhanced chemical vapor deposition using silicon-nitrogen- and hydrogen-containing precursors Tensile stress in the layer. The reduction in the number of Si-H and N-H bonds may result from the removal of hydrogen from the just-deposited layer. The overall tensile stress in the nitride layer increases as the Si and N atoms enter the space left by the removal of the hydrogen atoms and form more Si-N bonds. A further difficulty in forming a high tensile stress nitride layer is the additional operation of removing hydrogen atoms from the as-deposited layer.
處理剛沉積氮化矽層的一種方法是提升其拉伸應力,以將剛沉積的層曝露於紫外光。可惜,UV處理可具有若干缺點,包括UV光穿過剛沉積層的低穿透,並且產生光且將光聚焦於基板上需要額外的設備。在許多情況下,在氮化物沉積腔室中併入UV處理設備不切實際,且必須將具有剛沉積的氮化物材料的基板轉移至獨立的腔室以用於UV處理。由於通常UV處理設備經設計以穿透剛沉積氮化物的小於或約5至10Å,可在氮化物沉積及UV處理腔室之間來回多次傳送基板,以製造整個層。這可令使用UV處理操作在基板上形成拉伸的氮化矽層的時間及複雜度顯著增加。One method of treating the as-deposited silicon nitride layer is to elevate its tensile stress to expose the as-deposited layer to ultraviolet light. Unfortunately, UV processing can have several disadvantages, including low penetration of UV light through the just-deposited layer, and the need for additional equipment to generate and focus the light on the substrate. In many cases, it is impractical to incorporate UV processing equipment in the nitride deposition chamber, and the substrate with the freshly deposited nitride material must be transferred to a separate chamber for UV processing. Since typically UV processing equipment is designed to penetrate less than or about 5 to 10 Å of just-deposited nitride, the substrate can be passed back and forth between the nitride deposition and UV processing chambers multiple times to fabricate the entire layer. This can significantly increase the time and complexity of forming stretched silicon nitride layers on substrates using UV processing operations.
本技術的實施例藉由在單一處理腔室中的基板上沉積且處理含矽及氮層,來解決形成拉伸的含矽及氮層的常規系統及方法的此等及其他問題。處理方法的實施例可包括提高在基板上沉積較小應力的含矽及氮層與用處理電漿處理剛沉積氮化物之間的載體氣體的流率,以形成拉伸應力大於或約為1 GPa的拉伸應力的含矽及氮層。在此等實施例中,可減小或終止一或多種沉積前驅物的流率,同時增加沉積前驅物所包括的載體氣體的流率。在一些實施例中,在沉積及處理操作期間載體氣體可連續流至處理腔室中,且在沉積操作期間載體氣體流率不可下降至初始流率之下,直至處理操作完成。在沉積與處理操作之間的載體氣體流率增大的實施例中,相比於常規的沉積-處理方法中觀察到的結果,經處理的含矽及氮材料中的拉伸應力可在較短的時間段內增加較大量。Embodiments of the present technology address these and other problems with conventional systems and methods of forming stretched silicon and nitrogen containing layers by depositing and processing silicon and nitrogen containing layers on a substrate in a single processing chamber. Embodiments of the processing method may include increasing the flow rate of the carrier gas between the deposition of the less stressed silicon and nitrogen containing layer on the substrate and the treatment of the just deposited nitride with a processing plasma to form a tensile stress greater than or about 1 GPa tensile stress of silicon and nitrogen containing layers. In such embodiments, the flow rate of one or more deposition precursors may be reduced or terminated while increasing the flow rate of the carrier gas included in the deposition precursor. In some embodiments, the carrier gas may flow continuously into the processing chamber during deposition and processing operations, and the carrier gas flow rate may not drop below the initial flow rate during the deposition operation until the processing operation is complete. In embodiments where the carrier gas flow rate between deposition and processing operations is increased, tensile stress in the treated silicon and nitrogen-containing materials may be lower than that observed in conventional deposition-processing methods A larger increase in a short period of time.
在處理方法的其他實施例中,可在自沉積含矽及氮層的沉積電漿至增加層中拉伸應力的處理電漿的過渡中提高電漿功率。在一些實施例中,在自沉積至處理電漿的過渡期間使電漿功率不中斷。這可減少形成拉伸應力的含矽及氮層的每一沉積-處理循環的時間。在執行若干沉積-處理循環以完成層的形成的實施例中,處理時間的累積減少可為實質性的。在其他實施例中,電漿功率的增大亦可提高完全形成的含矽及氮層中的拉伸應力位準。In other embodiments of the processing method, the plasma power may be increased in the transition from the deposition plasma for depositing the silicon- and nitrogen-containing layer to the processing plasma for increasing tensile stress in the layer. In some embodiments, the plasma power is uninterrupted during the transition from deposition to processing plasma. This can reduce the time per deposition-processing cycle to form a tensile-stressed silicon and nitrogen-containing layer. In embodiments where several deposition-processing cycles are performed to complete the formation of layers, the cumulative reduction in processing time may be substantial. In other embodiments, the increase in plasma power may also increase the tensile stress level in the fully formed silicon and nitrogen containing layer.
在本技術的其他實施例中,相比於常規方法產生的拉伸層,由系統及方法的實施例產生的拉伸的含矽及氮層可具有減少的氫含量。在實施例中,拉伸的含矽及氮層可具有小於或約3 at.%的原子氫。含矽及氮層中低位準的氫可減少層中的Si-H及N-H鍵的數量,同時增加Si-N鍵的數量。在實施例中,Si-N鍵與Si-H及N-H鍵的莫耳比增大可提高層中的拉伸應力的量。在其他實施例中,提高莫耳比亦可降低含矽及氮層的濕蝕刻速率,在一些實施例中,這使得含矽及氮層在半導體製造製程中作為蝕刻終止層或硬遮罩更有效。In other embodiments of the present technology, the stretched silicon and nitrogen-containing layers produced by embodiments of the systems and methods may have reduced hydrogen content compared to stretched layers produced by conventional methods. In embodiments, the stretched silicon and nitrogen containing layer may have less than or about 3 at. % atomic hydrogen. Low levels of hydrogen in the silicon and nitrogen containing layers can reduce the number of Si-H and N-H bonds in the layer while increasing the number of Si-N bonds. In embodiments, an increase in the molar ratio of Si-N bonds to Si-H and N-H bonds may increase the amount of tensile stress in the layer. In other embodiments, increasing the molar ratio can also reduce the wet etch rate of the silicon and nitrogen containing layers, which in some embodiments makes the silicon and nitrogen containing layers more useful as etch stop layers or hard masks in semiconductor manufacturing processes efficient.
在描述腔室(其經配置以根據可執行電漿處理的本技術之實施例執行操作)的總體態樣之後,可論述具體的方法及部件配置。應理解本技術不意欲限於所討論的具體的膜及處理,因為可使用所描述的技術改良多個膜形成製程,且其可應用於各種處理腔室及操作。After describing a general aspect of a chamber configured to perform operations in accordance with embodiments of the present technology in which plasma processing may be performed, specific methods and component configurations may be discussed. It should be understood that the present techniques are not intended to be limited to the specific films and processes discussed, as a number of film formation processes can be modified using the described techniques, and they can be applied to a variety of processing chambers and operations.
第1A 圖展示根據實施例的具有沉積、處理、蝕刻、烘烤及硬化腔室的處理系統10之一個實施例的俯視平面圖。在圖中,一對前開式晶圓傳送盒12提供具有多種尺寸的基板,此等基板為機械手臂14所接收,並且放置於低壓保持區域16中,然後放置於基板處理腔室18a-f中的一者中,此等基板處理腔室安置於串列部件19a-c中。第二機械手臂11可用於將基板晶圓自保持區域16輸送至基板處理腔室18a-f並返回。每一基板處理製程18a-f可經配置以執行多個基板處理操作,此等基板處理操作包括形成本文描述的半導體材料堆疊,以及電漿增強化學氣相沉積、原子層沉積、物理氣相沉積、蝕刻、預清潔、除氣、定向及包括電漿處理、退火、灰化等的其他基板製程。
FIG . 1A shows a top plan view of one embodiment of a
基板處理腔室18a-f可包括用於沉積、電漿處理、硬化及/或蝕刻基板上的介電質或其他膜的一或多個系統組件。在一個配置中,可使用兩對處理腔室(例如18c至18d及18e至18f)在基板上沉積介電材料,並且可使用第三對處理腔室(例如18a至18b)處理所沉積介電質。在另一配置中,所有三對腔室(例如18a-f)可經設置以在基板上沉積並且處理交替介電膜的堆疊。所描述的製程中的任何一或多者可在與不同實施例中展示的製造系統分離的腔室中進行。應將瞭解,系統10涵蓋用於介電膜的沉積、處理、蝕刻、退火及硬化腔室的其他配置。The
第1B 圖展示根據本技術的一些實施例的示例性處理腔室100的橫截面圖。圖式可說明系統的概況,該系統併入了本技術的一或多個態樣,及/或可經特定配置以執行根據本技術的實施例的一或多個操作。下文進一步描述腔室100的其他細節或所執行的方法。根據本技術的一些實施例可使用腔室100形成拉伸的氮化物膜,但應理解,可在發生膜形成的任何腔室中類似地執行方法。處理腔室100可包括:腔室主體102;基板支撐件104,其安置於腔室主體102內;蓋組件106,其與腔室主體102耦接,並且將基板支撐件104封入於處理容積120中。可經由開口126將基板103提供至處理容積120,可使用狹縫閥門或門常規地密封該開口126以用於處理。在處理期間,基板103可位於基板支撐件的表面105上。基板支撐件104可如箭頭145所示圍繞軸線147旋轉,其中基板支撐件104的軸144可位於軸線147上。另外,在沉積製程期間,可升高基板支撐件104以按需要旋轉。
FIG . 1B shows a cross-sectional view of an
可在處理腔室100中安置電漿剖面調變器111,以控制安置於基板支撐件104上的基板103上的電漿分配。電漿剖面調變器111可包括第一電極108,其安置於腔室主體102附近,且可將腔室主體102與蓋組件106的其他部件分隔。第一電極108可為蓋組件106的一部分,或可為單獨的側壁電極。第一電極108可為環形或環狀元件,且可為環形電極。第一電極108可為沿包圍處理容積120的處理腔室100的圓周的連續環,或者如需要,在選定的位置可不連續。第一電極108亦可為諸如多孔環或網狀電極的多孔電極,或可為諸如二次氣體分配器的板狀電極。
一或多個隔離器110a、110b可為諸如陶瓷或金屬氧化物的介電材料(例如氧化鋁及/或氮化鋁),其可接觸第一電極108,且將第一電極108與氣體分配器112及腔室主體102電性或熱分隔。氣體分配器112可界定用於將製程前驅物分配至處理容積120中的孔口118。氣體分配器112可與第一電力源142耦接,例如RF產生器、RF電源、DC電源、脈衝DC電源、脈衝RF電源或可與處理腔室耦接的任何其他電源。在一些實施例中,第一電力源142可為RF電源。The one or
氣體分配器112可為導電的氣體分配器或不導電的氣體分配器。氣體分配器112亦可由導電及不導電的部件形成。舉例而言,氣體分配器112的主體可為導電的,而氣體分配器112的面板可為不導電的。可(例如)藉由第1圖所示的第一電力源142為氣體分配器112提供電力,或在一些實施例中氣體分配器112可耦接接地。The
第一電極108可與第一調諧電路128耦接,該第一調諧電路128可控制處理腔室100的接地路徑。第一調諧電路128可包括第一感測器130及第一電子控制器134。第一電子控制器134可為或包括可變電容器或其他電路元件。第一調諧電路128可為或包括一或多個電感器132。第一調諧電路128可為在處理期間在處理容積120中存在的電漿條件下實現可變或可控阻抗的任何電路。在所說明的一些實施例中,第一調諧電路128可包括在地面與第一電子感測器130之間並聯耦接的第一電路支路及第二電路支路。第一電路支路可包括第一電感器132A。第二電路支路可包括與第一電子控制器134串聯耦接的第二電感器132B。第二電感器132B可安置於第一電子控制器134及一節點之間,該節點將第一及第二電路支路連接至第一電子感測器130。第一電子感測器130可為電壓或電流感測器,且可與第一電子控制器134耦接,該第一電子控制器134可對處理容積120內的電漿條件進行一定程度的閉環控制。The
可將第二電極122與基板支撐件104耦接。第二電極122可嵌入於基板支撐件104內,或與基板支撐件104的表面耦接。第二電極122可為板、多孔板、網、線濾網或導電元件的任何其他分散式佈置。第二電極122可為調諧電極,可藉由導管146與第二調諧電路136耦接,該導管146例如安置於基板支撐件104的軸144中的具有選定電阻(例如50歐姆)的電纜。第二調諧電路136可有第二電子感測器138及第二電子控制器140,其可為第二可變電容器。第二電子感測器138可為電壓或電流感測器,且可與第二電子控制器140耦接以提供對處理容積120中的電漿條件的進一步控制。The
第三電極124可為偏壓電極及/或靜電夾持電極,其可與基板支撐件104耦接。第三電極可經由濾波器148與第二電力源150耦接,其可為阻抗匹配電路。第二電力源150可為DC電源、脈衝DC電源、RF偏壓電源、脈衝RF源或偏壓電源,或此等或其他電源的組合。在一些實施例中,第二電力源150可為RF偏壓電源。The
第1B 圖的蓋組件106及基板支撐件104可與用於電漿或熱處理的任何處理腔室一起使用。在操作中,處理腔室100可即時控制處理容積120中的電漿條件。可將基板103安置於基板支撐件104上,且可根據任何所要的流程圖使用入口114使製程氣體流過蓋組件106。氣體可經由出口152離開處理腔室100。可使電源與氣體分配器112耦接,以在處理容積120中產生電漿。在一些實施例中可使用第三電極124對基板進行電偏壓。
The
一旦在處理容積120中激勵電漿,可在電壓與第一電極108之間產生電位差。亦可在電漿與第二電極122之間產生電位差。隨後可使用電子控制器134、140以調整由兩個調諧電路128及136表示的接地路徑的流動性質。可將設定點輸送至第一調諧電路128及第二調諧電路136,以獨立控制沉積速率及中心至邊緣的電漿密度均勻性。在電子控制器可均為可變電容器的實施例中,電子感測器可調整可變電容器,以獨立地最大化沉積速率且最小化厚度不均勻性。Once the plasma is energized in the
調諧電路128、136中之每一者可具有可變阻抗,可使用各別的電子控制器134、140調整該可變阻抗。當電子控制器134、140為可變電容器時,可選擇可變電容器中之每一者的電容範圍,及第一電感器132A及第二電感器132B的電感以提供阻抗範圍。此範圍可取決於電漿的頻率及電壓特性,其可在每一可變電容器的電容範圍中具有最小值。因此,當第一電子控制器134的電容為最小值或最大值時,第一調諧電路128的阻抗可高,產生在基板支撐件上具有最小的空中或側向覆蓋範圍的電漿形狀。當第一電子控制器134的電容接近最小化第一調諧電路128阻抗的一值時,電漿的空中覆蓋範圍可增加至最大值,有效地覆蓋基板支撐件104的整個工作區域。由於第一電子控制器134的電容偏離最小阻抗設定,電漿形狀可自腔室壁收縮,且基板支撐件的空中覆蓋範圍可下降。第二電子控制器140可具有類似的效應,隨著第二電子控制器140的電容改變而增加或減少電漿在基板支撐件上方的空中覆蓋範圍。Each of the tuning
可使用電子感測器130、138在閉環中調諧各別的電路128、136。取決於所使用感測器的類型,可在每一感測器中安裝電流或電壓的設定點,且可為感測器設置控制軟體,其確定對每一各別的電子控制器134、140的調整以最小化與設定點的偏離。因此,在處理期間可選定且動態地控制電漿形狀。應理解,雖然前文的論述基於可為可變電容器的電子控制器134、140,但可使用具有可調整特性的任何電子部件來為調諧電路128及136提供可調整阻抗。The
第2 圖展示根據本技術之一些實施例的沉積方法200的示例性操作。可在多種處理腔室(包括上文描述的處理腔室100)中執行方法。方法可包括在沉積之後執行淨化操作,其可限制基板上的顆粒沉積。方法200可包括多個可選的操作,該等操作可與根據本技術的方法的一些實施例具體相關聯或不相關。舉例而言,描述許多操作以提供結構形成的更廣泛範疇,但這並非技術的關鍵,或可藉由將容易地理解的替代方法執行該等操作。
FIG . 2 shows an exemplary operation of a
方法200可包括在啟動所列出的操作之前進行額外的操作。舉例而言,額外的處理操作可包括在半導體基板上形成結構,其可包括形成及移除材料。可在執行方法200的腔室中執行先前的處理操作,或可在將基板輸送至執行方法200的半導體處理腔室中之前在一或多個其他處理腔室中執行處理。無論如何,方法200可視情況包括將半導體基板輸送至半導體處理腔室的處理區域,例如上文描述的處理腔室100或可包括上文描述的部件的其他腔室。基板可安置於基板支撐件上,其可為諸如基板支撐件104的底座,且可駐留在腔室的處理區域中,例如上文描述的處理容積120。
形成拉伸的含矽及氮層的處理方法200的實施例可包括使沉積前驅物流至基板處理腔室的基板處理區域中205。沉積前驅物的實施例可包括至少一種含矽前驅物及至少一種含氮前驅物。含矽前驅物的實施例可包括矽烷、二矽烷及其他含矽前驅物。含氮前驅物的實施例可包括氨(NH
3)、及分子氮與氫的混合物(N
2+ H
2)以及其他含氮前驅物。在其他實施例中,沉積前驅物亦可包括至少一種載體氣體。載體氣體的實施例可包括分子氮(N
2)及氬氣以及其他載體氣體。
Embodiments of the
在一些實施例中,可按大於或約為含矽沉積前驅物的流率的流率將含氮沉積前驅物引入至處理腔室的基板處理區域。舉例而言,含氮前驅物與含矽前驅物的流率比可大於或約為1:1,大於或約為2:1,大於或約為3:1,大於或約為4:1,大於或約為5:1或更大。在其他實例中,含氮前驅物與含矽前驅物的流率比可為富矽的。在實施例中,含氮前驅物與含矽前驅物的流率比可小於或約為1:5,小於或約為1:10或更小。在其他實施例中,可按大於或約為含氮及含矽沉積前驅物的組合流率的流率將沉積載體氣體引入至處理腔室的基板處理區域。舉例而言,載體氣體與含氮及含矽前驅物的流率比可大於或約為30:1,大於或約為40:1,大於或約為50:1,大於或約為60:1,大於或約為70:1或更大。In some embodiments, the nitrogen-containing deposition precursor may be introduced into the substrate processing region of the processing chamber at a flow rate greater than or about the flow rate of the silicon-containing deposition precursor. For example, the flow rate ratio of nitrogen-containing precursor to silicon-containing precursor may be greater than or about 1:1, greater than or about 2:1, greater than or about 3:1, greater than or about 4:1, Greater than or about 5:1 or greater. In other examples, the flow rate ratio of nitrogen-containing precursor to silicon-containing precursor may be silicon-rich. In embodiments, the flow rate ratio of nitrogen-containing precursor to silicon-containing precursor may be less than or about 1:5, less than or about 1:10, or less. In other embodiments, the deposition carrier gas may be introduced to the substrate processing region of the processing chamber at a flow rate greater than or about the combined flow rate of the nitrogen- and silicon-containing deposition precursors. For example, the ratio of flow rates of carrier gas to nitrogen- and silicon-containing precursors may be greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, greater than or about 60:1 , greater than or about 70:1 or greater.
在實施例中,一或多種含氮沉積前驅物的流率可大於或約為100 sccm,大於或約為125 sccm,大於或約為150 sccm,大於或約為175 sccm,大於或約為200 sccm,大於或約為225 sccm,大於或約為250 sccm或更大。在其他實施例中,一或多種含矽沉積前驅物的流率可小於或約為100 sccm,小於或約為90 sccm,小於或約為80 sccm,小於或約為70 sccm,小於或約為60 sccm,小於或約為50 sccm,小於或約為40 sccm或更小。在其他實施例中,載體氣體的流率可大於或約為8000 sccm,大於或約為9000 sccm,大於或約為10000 sccm,大於或約為11000 sccm,大於或約為12000 sccm或更大。在其他實施例中,沉積前驅物向基板處理腔室中的流動可提高腔室中的壓力。在實施例中,沉積前驅物流動期間基板腔室中的壓力可大於或約為1 Torr,大於或約為2 Torr,大於或約為3 Torr,大於或約為4 Torr,大於或約為5 Torr,大於或約為6 Torr,大於或約為7 Torr或更大。In embodiments, the flow rate of the one or more nitrogen-containing deposition precursors may be greater than or about 100 sccm, greater than or about 125 sccm, greater than or about 150 sccm, greater than or about 175 sccm, greater than or about 200 sccm sccm, greater than or about 225 sccm, greater than or about 250 sccm or greater. In other embodiments, the flow rate of the one or more silicon-containing deposition precursors may be less than or about 100 seem, less than or about 90 seem, less than or about 80 seem, less than or about 70 seem, less than or about 60 sccm, less than or about 50 sccm, less than or about 40 sccm or less. In other embodiments, the flow rate of the carrier gas may be greater than or about 8000 sccm, greater than or about 9000 sccm, greater than or about 10,000 sccm, greater than or about 11,000 sccm, greater than or about 12,000 sccm or greater. In other embodiments, the flow of deposition precursors into the substrate processing chamber may increase the pressure in the chamber. In embodiments, the pressure in the substrate chamber during the flow of the deposition precursor may be greater than or about 1 Torr, greater than or about 2 Torr, greater than or about 3 Torr, greater than or about 4 Torr, greater than or about 5 Torr Torr, greater than or about 6 Torr, greater than or about 7 Torr or greater.
處理方法200的實施例可進一步包括在處理腔室的基板處理區域中產生沉積電漿210。可藉由向已流至基板處理區域中的沉積前驅物輸送電漿功率產生沉積電漿。在一些實施例中,可藉由電耦接至處理腔室內至少一個電極的射頻(RF)電源輸送電漿功率。在實施例中,RF電源可向至少一個電極輸送電力,該至少一個電極在處理腔室的基板處理區域中產生電場,其激勵沉積前驅物以形成沉積電漿。在其他實施例中,輸送至沉積前驅物的電漿功率可小於或約為60瓦特,小於或約為55瓦特,小於或約為50瓦特,小於或約為45瓦特,小於或約為40瓦特,小於或約為35瓦特,小於或約為30瓦特或更小。在其他實施例中,輸送至沉積前驅物的RF功率的頻率在一個非限制性實例中可為13.56 MHz。在一些實施例中,可連續提供輸送至沉積前驅物的電漿功率,而在其他實施例中,電漿功率可為脈衝的。在脈衝的實施例中,所輸送的RF電漿功率可具有可小於或約為10 kHz,且可小於或約為9 kHz,小於或約為8 kHz,小於或約為7 kHz,小於或約為6 kHz,小於或約為5 kHz,小於或約為4 kHz,小於或約為3 kHz,小於或約為2 kHz,小於或約為1 kHz或更小的脈衝頻率。在一些脈衝的實施例中,電漿功率的工作週期的關閉部分可允許電漿流出物在剛沉積的含矽及氮材料中更多地擴散。在其他實施例中,電漿流出物擴散更長時間可形成更均勻的剛沉積材料。Embodiments of the
處理方法200的實施例可進一步包括由沉積電漿在基板處理腔室中的基板上沉積含矽及氮材料215。在一些實施例中,剛沉積的含矽及氮材料可為氮化矽。在其他實施例中,剛沉積的含矽及氮材料可表徵為所併入氫的量。在實施例中,剛沉積材料中所併入氫的量可大於或約為5 at.%,大於或約為6 at.%,大於或約為7 at.%,大於或約為8 at.%,大於或約為9 at.%,大於或約為10 at.%或更大。剛沉積的含矽及氮材料中所併入氫的量可影響低應力材料的沉積。在一些實施例中,剛沉積的含矽及氮材料可具有小於或約0.5 GPa、小於或約0.1 GPa、小於或約0.05 GPa、小於或約0.01 GPa、小於或約-0.01 GPa、小於或約-0.1 GPa、小於或約-1 GPa或更小的拉伸應力。Embodiments of the
在實施例中,可在影響材料的沉積速率的沉積溫度下在基板上進行含矽及氮材料的沉積。在其他實施例中,處理腔室的半導體處理區域可表徵為低於或約550℃、低於或約500℃、低於或約475℃、低於或約450℃、低於或約425℃、低於或約400℃、低於或約375℃、低於或約350℃或低於或約300℃或更低的沉積溫度。藉由在低於或約500℃的溫度下沉積,本技術相比於常規的高溫沉積可保護器件熱預算。在其他實施例中,可按低於或約20 Å/秒、低於或約15 Å/秒、低於或約12 Å/秒、低於或約10 Å/秒、低於或約8 Å/秒、低於或約5 Å/秒、低於或約2 Å/秒或更低的沉積速率沉積含矽及氮材料。In an embodiment, the deposition of the silicon and nitrogen containing material on the substrate may be performed at a deposition temperature that affects the deposition rate of the material. In other embodiments, the semiconductor processing region of the processing chamber may be characterized as being below or about 550°C, below or about 500°C, below or about 475°C, below or about 450°C, below or about 425°C , a deposition temperature below or about 400°C, below or about 375°C, below or about 350°C or below or about 300°C or below. By depositing at temperatures below or about 500°C, the present technique preserves the device thermal budget compared to conventional high temperature deposition. In other embodiments, below or about 20 Å/sec, below or about 15 Å/sec, below or about 12 Å/sec, below or about 10 Å/sec, below or about 8 Å/sec Silicon and nitrogen containing materials are deposited at deposition rates of less than or about 5 Å/second, less than or about 2 Å/second or less.
如下文所進一步討論,沉積含矽及氮材料的實施例可包括最終含矽及氮層中的所有材料,或少於整個層的最終含矽及氮層的一部分。在實施例中,基板上剛沉積的含矽及氮材料的厚度可小於或約為500 Å,小於或約為400 Å,小於或約為350 Å,小於或約為300 Å,小於或約為250 Å,小於或約為200 Å,小於或約為150 Å,小於或約為100 Å,小於或約為50 Å,小於或約為40 Å,小於或約為30 Å,小於或約為20 Å,小於或約為15 Å,小於或約為10 Å或更小。在其他實施例中,沉積操作花費的時間可少於或約為100秒,少於或約為75秒,少於或約為60秒,少於或約為30秒,少於或約為15秒,少於或約為10秒,少於或約為5秒,少於或約為2秒,少於或約為1秒或更少。As discussed further below, embodiments of depositing the silicon and nitrogen containing material may include all of the material in the final silicon and nitrogen containing layer, or less than a portion of the final silicon and nitrogen containing layer of the entire layer. In embodiments, the thickness of the as-deposited silicon and nitrogen-containing material on the substrate may be less than or about 500 Å, less than or about 400 Å, less than or about 350 Å, less than or about 300 Å, less than or about 250 Å, less than or about 200 Å, less than or about 150 Å, less than or about 100 Å, less than or about 50 Å, less than or about 40 Å, less than or about 30 Å, less than or about 20 Å Å, less than or about 15 Å, less than or about 10 Å or less. In other embodiments, the deposition operation may take less than or about 100 seconds, less than or about 75 seconds, less than or about 60 seconds, less than or about 30 seconds, less than or about 15 seconds seconds, less than or about 10 seconds, less than or about 5 seconds, less than or about 2 seconds, less than or about 1 second or less.
處理方法200的實施例可另外包括使一或多種處理前驅物流至基板處理腔室的基板處理區域中220。處理前驅物的實施例可包括諸如N
2的含氮前驅物及諸如氦氣、氬氣及氖氣的鈍氣前驅物。在一些實施例中,處理前驅物可為無氦的。在其他實施例中,處理前驅物可包括亦用作沉積前驅物的載體氣體中之一些或全部。舉例而言,實施例包括減少或停止在沉積操作期間使用的含氮及含矽沉積前驅物的流動,同時繼續使沉積前驅物中的載體氣體中之至少一者流動。在一些實施例中,在自沉積操作過渡至處理操作期間提高載體氣體的流率。在實施例中,處理前驅物在處理腔室的基板處理區域中的流率可大於或約為20,000 sccm,大於或約為22,500 sccm,大於或約為25,000 sccm,大於或約為27,500 sccm,大於或約為30,000 sccm或更大。在實施例中,處理前驅物可包括流率大於或約為15,000 sccm,大於或約為16,000 sccm,大於或約為17,000 sccm,大於或約為18,000 sccm,大於或約為19,000 sccm,大於或約為20,000 sccm或更大的分子氮(N
2)。較高的N
2流率可在含矽及氮材料中形成額外的Si-N鍵。在實施例中,相比於剛沉積的材料,經處理的含矽及氮材料中Si-N鍵的數量可增加多於或約1%、多於或約2%、多於或約3%、多於或約4%、多於或約5%或更多。在其他實施例中,較高的N
2流率可降低經處理的含矽及氮材料的蝕刻速率。在實施例中,相比於剛沉積的材料,經N
2處理的含矽及氮材料的蝕刻速率可降低多於或約1%、多於或約2%、多於或約5%、多於或約10%、多於或約15%或更多。
Embodiments of the
在更多實施例中,處理前驅物可包括流率大於或約為3000 sccm,大於或約為4000 sccm,大於或約為5000 sccm,大於或約為6000 sccm,大於或約為7000 sccm,大於或約為8000 sccm或更大的氬氣。在實施例中,相比於剛沉積的材料,經氬氣處理的含矽及氮材料的蝕刻速率可降低多於或約1%、多於或約2%、多於或約5%、多於或約10%、多於或約15%或更多。In further embodiments, treating the precursor may include a flow rate of greater than or about 3000 seem, greater than or about 4000 seem, greater than or about 5000 seem, greater than or about 6000 seem, greater than or about 7000 seem, greater than Or about 8000 sccm or more of argon. In embodiments, the etch rate of the argon treated silicon and nitrogen containing material may be reduced by more than or about 1%, more than or about 2%, more than or about 5%, more than At or about 10%, more than or about 15% or more.
在其他實施例中,處理前驅物向基板處理腔室中的流動可增加腔室中的壓力。在一些實施例中,處理操作期間處理腔室中的壓力可大於沉積操作期間處理腔室中的壓力。在實施例中,處理前驅物流動期間基板腔室中的壓力可表徵為大於或約為3 Torr,大於或約為4 Torr,大於或約為5 Torr,大於或約為6 Torr,大於或約為7 Torr,大於或約為8 Torr,大於或約為9 Torr,大於或約為10 Torr或更大。在實施例中,增加的腔室壓力可增加經處理的含矽及氮材料的應力。在一些實施例中,相比於剛沉積的材料,增加的腔室壓力可使經處理的含矽及氮材料中的應力增加多於或約2%、多於或約5%、多於或約10%、多於或約25%、多於或約50%或更多。在其他實施例中,增加的腔室壓力亦可增加經處理的含矽及氮材料的蝕刻速率。在實施例中,相比於剛沉積的材料,增加的腔室壓力可使經處理的含矽及氮材料中的蝕刻速率增加多於或約1%、多於或約2%、多於或約5%、多於或約10%、多於或約25%或更多。In other embodiments, the flow of processing precursors into the substrate processing chamber may increase the pressure in the chamber. In some embodiments, the pressure in the processing chamber during processing operations may be greater than the pressure in the processing chamber during deposition operations. In embodiments, the pressure in the substrate chamber during processing precursor flow may be characterized as greater than or about 3 Torr, greater than or about 4 Torr, greater than or about 5 Torr, greater than or about 6 Torr, greater than or about 7 Torr, greater than or about 8 Torr, greater than or about 9 Torr, greater than or about 10 Torr or greater. In embodiments, the increased chamber pressure may increase the stress of the processed silicon and nitrogen containing material. In some embodiments, the increased chamber pressure can increase the stress in the processed silicon and nitrogen-containing material by more than or about 2%, more than or about 5%, more than or about 5%, compared to the as-deposited material About 10%, more than or about 25%, more than or about 50% or more. In other embodiments, the increased chamber pressure may also increase the etch rate of the processed silicon and nitrogen containing materials. In embodiments, the increased chamber pressure may increase the etch rate in the processed silicon and nitrogen containing material by more than or about 1%, more than or about 2%, more than or about 2%, compared to the as-deposited material About 5%, more than or about 10%, more than or about 25% or more.
在實施例中,處理前驅物的流率大於沉積前驅物的流率。舉例而言,在處理前驅物包括沉積前驅物中的載體氣體中之一或多者的實施例中,處理前驅物中的載體氣體中之一或多者的流率大於沉積前驅物中的載體氣體的流率。在實施例中,處理前驅物與沉積前驅物的流率比可大於或約為1:1,大於或約為1.25:1,大於或約為1.5:1,大於或約為1.75:1,大於或約為2:1或更大。在沉積與處理操作之間的前驅物流率增大的實施例中,相比於常規的沉積-處理方法中觀察到的結果,經處理的含矽及氮材料中的拉伸應力可在較短的時間段內增加較大量。In embodiments, the flow rate of the processing precursor is greater than the flow rate of the deposition precursor. For example, in embodiments where the processing precursor includes one or more of the carrier gases in the deposition precursor, the flow rate of the one or more of the carrier gases in the processing precursor is greater than the carrier gas in the deposition precursor gas flow rate. In embodiments, the flow rate ratio of processing precursor to deposition precursor may be greater than or about 1:1, greater than or about 1.25:1, greater than or about 1.5:1, greater than or about 1.75:1, greater than or about 2:1 or greater. In embodiments with increased precursor flow rates between deposition and processing operations, tensile stress in treated silicon and nitrogen-containing materials can be increased significantly over the period of time.
處理方法200的實施例可進一步包括在處理腔室的基板處理區域中產生處理電漿225。可藉由向已流至基板處理區域中的處理前驅物輸送電漿功率產生處理電漿。在一些實施例中,可藉由用於輸送沉積電漿功率的相同的射頻(RF)電源及經由相同的系統電極輸送處理電漿功率。在其他實施例中,處理電漿功率可大於激勵沉積電漿的沉積電漿功率。在實施例中,處理電漿功率可大於60瓦,大於或約為70瓦,大於或約為80瓦,大於或約為90瓦,大於或約為100瓦,大於或約為110瓦,大於或約為120瓦,大於或約為130瓦,大於或約為140瓦,大於或約為150瓦或更大。提高電漿功率可增加解離及在膜中轟擊且分配的可用自由基。在其他實施例中,輸送至處理前驅物的RF功率的頻率在一個非限制性實例中可為13.56 MHz。在一些實施例中,可連續提供輸送至沉積前驅物的電漿功率,而在其他實施例中,電漿功率可為脈衝的。Embodiments of the
在一些實施例中,在自沉積至處理電漿的過渡期間按連續波輸送電漿。這可減少形成拉伸應力的含矽及氮層的每一沉積-處理循環的時間。在執行若干沉積-處理循環以完成層的形成的實施例中,處理時間的累積減少可為實質性的。在其他實施例中,處理操作期間電漿功率的增大亦可增加完全形成的含矽及氮層中的拉伸應力位準。In some embodiments, the plasma is delivered as a continuous wave during the transition from deposition to treatment plasma. This can reduce the time per deposition-processing cycle to form a tensile-stressed silicon and nitrogen-containing layer. In embodiments where several deposition-processing cycles are performed to complete the formation of layers, the cumulative reduction in processing time may be substantial. In other embodiments, an increase in plasma power during processing operations may also increase the tensile stress level in the fully formed silicon and nitrogen containing layer.
處理方法200的實施例可進一步包括用處理電漿在基板處理腔室中的基板上處理剛沉積的含矽及氮材料230。在一些實施例中,處理電漿曝露時間可大於或約為1秒,大於或約為2秒,大於或約為5秒,大於或約為10秒,大於或約為15秒,大於或約為30秒,大於或約為45秒,大於或約為60秒或更長。在實施例中,剛沉積的含矽及氮材料曝露於處理電漿的曝露時間可取決於剛沉積材料的厚度。在其他實施例中,曝露時間可大於或約為每埃沉積材料0.1秒(0.1 sec/Å)。在其他實施例中,曝露時間可大於或約為0.2 sec/Å,大於或約為0.3 sec/Å,大於或約為0.4 sec/Å,大於或約為0.5 sec/Å,大於或約為0.6 sec/Å,大於或約為0.7 sec/Å,大於或約為0.8 sec/Å,大於或約為0.9 sec/Å,大於或約為1 sec/Å,大於或約為2 sec/Å或更長。Embodiments of the
在實施例中,可在影響材料的處理速率的處理溫度下在基板上進行含矽及氮材料的處理。在其他實施例中,處理腔室的半導體處理區域可表徵為低於或約550℃、低於或約500℃、低於或約475℃、低於或約450℃、低於或約425℃、低於或約400℃、低於或約375℃、低於或約350℃或低於或約300℃或更低的處理溫度。在一些實施例中,增加的腔室壓力可降低經處理的含矽及氮材料中氫的原子百分比。在實施例中,相比於剛沉積的材料,經處理的含矽及氮材料中氫的原子百分比可降低多於或約1%、多於或約2.5%、多於或約5%、多於或約7.5%、多於或約10%或更多。In an embodiment, the processing of the silicon and nitrogen containing material may be performed on the substrate at a processing temperature that affects the processing rate of the material. In other embodiments, the semiconductor processing region of the processing chamber may be characterized as being below or about 550°C, below or about 500°C, below or about 475°C, below or about 450°C, below or about 425°C , less than or about 400°C, less than or about 375°C, less than or about 350°C or less than or about 300°C or less. In some embodiments, the increased chamber pressure can reduce the atomic percentage of hydrogen in the processed silicon and nitrogen-containing material. In embodiments, the atomic percentage of hydrogen in the treated silicon and nitrogen-containing material may be reduced by more than or about 1%, more than or about 2.5%, more than or about 5%, more than At or about 7.5%, more than or about 10% or more.
在實施例中,處理操作可產生拉伸的含矽及氮材料。在其他實施例中,經處理的含矽及氮材料可具有大於或約0.8 GPa、大於或約0.9 GPa、大於或約1 GPa、大於或約1.1 GPa、大於或約1.2 GPa、大於或約1.3 GPa、大於或約1.4 GPa、大於或約1.5 GPa或更大的拉伸應力。在實施例中,處理操作亦可產生所併入氫位準降低的經處理的含矽及氮材料。在實施例中,經處理材料中併入的氫的量可小於或約為3 at.%,小於或約為2 at.%,小於或約為1 at.%,小於或約為0.5 at.%,小於或約為0.2 at.%,小於或約為0.1 at.%或更小。減少經處理的含矽及氮材料中所併入的氫的量可影響用較高拉伸應力沉積材料。在其他實施例中,減少的所併入的氫的量亦可降低含矽及氮層的濕蝕刻速率。In an embodiment, the processing operation can produce a stretched silicon and nitrogen-containing material. In other embodiments, the treated silicon and nitrogen-containing material may have greater than or about 0.8 GPa, greater than or about 0.9 GPa, greater than or about 1 GPa, greater than or about 1.1 GPa, greater than or about 1.2 GPa, greater than or about 1.3 GPa GPa, greater than or about 1.4 GPa, greater than or about 1.5 GPa or greater tensile stress. In embodiments, the processing operations may also produce processed silicon and nitrogen-containing materials with reduced levels of incorporated hydrogen. In embodiments, the amount of hydrogen incorporated in the treated material may be less than or about 3 at. %, less than or about 2 at. %, less than or about 1 at. %, less than or about 0.5 at. %, less than or about 0.2 at.%, less than or about 0.1 at.% or less. Reducing the amount of hydrogen incorporated in the processed silicon- and nitrogen-containing materials can affect deposition of materials with higher tensile stress. In other embodiments, the reduced amount of hydrogen incorporated may also reduce the wet etch rate of the silicon and nitrogen containing layers.
在本技術的實施例中,對沉積處理腔室中剛沉積的含矽及氮材料的電漿處理操作使得不需要將基板移動至UV處理腔室並對材料執行UV處理。排除UV處理操作降低形成拉伸的含矽及氮層的處理方法及系統的複雜度,並且減少處理時間。本技術的此等及其他態樣提供更快、更具生產能力且更經濟的在半導體基板上形成拉伸的含矽及氮層的處理方法及系統。In embodiments of the present technology, the plasma processing operation of the just deposited silicon and nitrogen containing material in the deposition processing chamber eliminates the need to move the substrate to the UV processing chamber and perform UV processing on the material. The exclusion of UV processing operations reduces the complexity of the processing method and system for forming the stretched silicon and nitrogen containing layers and reduces processing time. These and other aspects of the present technology provide faster, more productive, and more economical processing methods and systems for forming stretched silicon and nitrogen containing layers on semiconductor substrates.
用本技術的實施例達成的生產能力增加可為在兩個或兩個以上循環中形成含矽及氮層的實施例的累加增加。處理方法200的此等實施例可進一步包括在沉積且處理含矽及氮材料的兩個或兩個以上循環中形成拉伸的含矽及氮層。額外的循環可開始於使額外的沉積前驅物流至基板處理腔室的基板處理區域中,由沉積前驅物產生沉積電漿210,以及在基板上沉積含矽及氮材料的額外的部分。額外的循環亦可包括使一或多種處理前驅物流至處理腔室的基板處理區域中,產生處理電漿,以及處理含矽及氮材料的剛沉積的額外部分,以製成拉伸的含矽及氮層的額外部分。The throughput increase achieved with embodiments of the present technology may be a cumulative increase for embodiments that form silicon and nitrogen containing layers in two or more cycles. These embodiments of the
當形成拉伸的含矽及氮層的一部分時,可判定其是否完成了拉伸的含矽及氮層的形成235。若拉伸的含矽及氮層的一部分完成層的形成,則處理方法可終止240。若拉伸的含矽及氮層的一部分未完成層的形成,則沉積且處理含矽及氮材料的另一循環可開始。在實施例中,當拉伸的含矽及氮層的厚度大於或約為50Å,大於或約為100Å,大於或約為150Å,大於或約為200Å,大於或約為250Å,大於或約為300Å,大於或約為400Å或更大時,則完整的該層形成。When a portion of the stretched silicon and nitrogen-containing layer is formed, it can be determined whether it completes the formation of the stretched silicon and nitrogen-containing
藉由處理方法200製成的完成的拉伸的含矽及氮層的實施例可具有大於或約0.8 GPa、大於或約0.9 GPa、大於或約1 GPa、大於或約1.1 GPa、大於或約1.2 GPa、大於或約1.3 GPa、大於或約1.4 GPa、大於或約1.5 GPa或更大的拉伸應力。在其他實施例中,完成的拉伸的含矽及氮層可具有小於或約20 Å/min、小於或約17.5 Å/min、小於或約15 Å/min、小於或約12.5 Å/min、小於或約10 Å/min或更小的濕蝕刻速率。在實施例中,拉伸的含矽及氮層的此等特性可使其成為有效的氮化矽蝕刻終止層或硬遮罩,其亦為相鄰圖案化材料中精確開口的形成提供支援。如上文所指出,較高的氮化物層中拉伸應力減小在材料中形成開口期間相鄰圖案化材料以不均勻速率蝕刻的趨勢。因此,與拉伸的氮化物層相鄰的圖案化材料中形成的開口具有較小的粗糙度,其表徵為開口沿側壁的線邊緣粗糙度(LER)及線寬度粗糙度(LWR)較小。Embodiments of the finished stretched silicon and nitrogen-containing layer made by processing
第3A 圖至
第 3B 圖展示根據本技術的實施例的示例性半導體結構300的橫截面圖。結構300所示的實施例包括藉由根據本技術的實施例的處理方法及系統形成的拉伸的含矽及氮層308。在
第 3A 圖所示的實施例中,結構300亦可包括一層圖案化光阻材料302,其與第一及第二圖案化材料層304及306相鄰。在所示的實施例中,第二層圖案化材料306與拉伸的含矽及氮層308直接接觸。
3A - 3B show cross-sectional views of an
在
第 3A 圖所示的結構300的實施例中,將拉伸的含矽及氮層308的相對側上的層圖示為圖案化材料層304及306。在實施例中,與圖案化材料相對的層308一側上的此等層可包括介電層310,該介電層310可與拉伸的含矽及氮層308直接接觸。介電層可表徵為大於或約800 Å的厚度,且可表徵為含矽及氧的介電層,例如氧化矽層。在其他實施例中,結構300可包括與介電層310相鄰的襯墊層312。襯墊層312可表徵為大於或約200 Å的厚度,且可為緻密的介電材料層,例如藉由原子層沉積而沉積的氮化矽層。在其他實施例中,結構300可包括與襯墊層312相鄰的多晶矽層314。多晶矽層可表徵為大於或約900 Å的厚度,且可用作諸如nMOS電晶體(未展示)的半導體器件結構的基板。
In the embodiment of
在
第 3A 圖所示的結構300的實施例中,圖案化的光阻材料302可經圖案化以允許在第一及第二圖案化材料層304及306中形成開口(未展示)。在實施例中,此等開口可延伸穿過第一圖案化材料層304,其可為表徵為大於或約300 Å的厚度的含矽氧及碳層,其可藉由旋轉製程形成。在其他實施例中,此等開口亦可延伸穿過第二圖案化材料層306,其可為表徵為大於或約500 Å的厚度的含矽氧及碳層,其可藉由化學氣相沉積製程形成。在其他實施例中,拉伸的含矽及氮層308可用作蝕刻終止層,其可形成開口的底側。
In the embodiment of the
第3B 圖展示結構350的另一實施例,開口316a至316c形成於第一及第二圖案化材料層304及306中。此等開口316a至316c可具有基本上垂直於底側的側壁,該底側包括拉伸的含矽及氮層308的曝露表面。開口316a至316c的側壁可表徵為平均偏差小於或約為10 Å、小於或約為5 Å、小於或約為3 Å、小於或約為1 Å或更小的線邊緣粗糙度。相比於具有常規的低應力氮化矽層的結構中形成的開口的LER/LWR值,表徵結構350的實施例中開口的側壁的LER/LWR值可小至少10%。本處理方法及系統不僅在不需要耗時的UV處理操作的情況下提供拉伸的含矽及氮層,其亦提供諸如結構350的半導體結構,其中與拉伸的含矽及氮層相鄰的圖案化材料中的開口更精確,且相比於常規結構中形成的開口具有較小的線邊緣粗糙度/線寬度粗糙度。
FIG . 3B shows another embodiment of a
在前文的描述中,出於解釋的目的,已闡述許多細節,以便理解本技術的各個實施例。然而,對於熟習此項技術者顯而易見的是,可在無此等細節中的一些者或存在額外細節的情況下實踐某些實施例。In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.
雖然已揭示若干實施例,但熟習此項技術者應瞭解可在不脫離實施例精神的情況下使用各種修改、替代構造或等效物。另外,未描述許多已知的製程及要素,以便避免不必要地使本技術難以理解。因此,不應認為以上描述限制本技術的範疇。另外,本文按順序或按步驟描述方法或製程,但應理解可同時執行操作或按與所列出的次序不同的次序執行操作。Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, or equivalents may be used without departing from the spirit of the embodiments. Additionally, many well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be considered to limit the scope of the present technology. Additionally, methods or processes are described herein sequentially or in steps, but it should be understood that operations may be performed concurrently or in an order different from that listed.
在提供數值範圍的情況下,應理解除非上下文另有明確規定,亦具體地揭示彼範圍的上限及下限之間的小至下限單位最小分數的每一中介值。涵蓋所說明範圍中的任何所說明值或未說明中介值與任何其他所說明或中介值之間的任何較窄的範圍。彼等較小範圍的上限及下限可獨立地包括於範圍或自範圍中排除,並且本技術亦涵蓋每一範圍(上限及下限均不包括於較小的範圍中,或其中一者或兩者均包括於較小的範圍中),其中每一範圍受到所說明範圍中的具體排除的限值的限制。在所說明範圍包括限值中的一者或兩者,亦包括排除彼等所包括限值中之一者或兩者的範圍。Where a numerical range is provided, it is to be understood that unless the context clearly dictates otherwise, each intervening value between the upper and lower limits of that range, down to the minimum fraction of the lower unit, is also specifically disclosed. Any stated value in the stated range or any narrower range between an unspecified intervening value and any other stated or intervening value is encompassed. The upper and lower limits of those smaller ranges may independently be included in or excluded from the range, and each range is also encompassed by the present technology (neither the upper and lower limits are included in the smaller ranges, or either or both) are included in smaller ranges), where each range is limited by the specifically excluded limit in the stated range. The stated range includes one or both of the limits, as well as ranges excluding either or both of those included limits.
如本文及所附請求項所使用,除非上下文另有明確指出,單數形式的「一(a)」、「一(an)」及「該(the)」包括複數種提法。由此,舉例而言,提及「一前驅物」包括複數個此類前驅物,提及「該層」包括提及熟習此項技術者已知的一或多個層及其等效物,諸如此類。As used herein and in the appended claims, the singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, and reference to "the layer" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so on.
此外,當用於本說明書及以下請求項中時,用詞「包含(comprise(s))」、「包含(comprising)」、「含有(contain(s))」、「含有(containing)」、「包括(include(s))」及「包括(including)」意欲指明所說明特徵、整數、組件或操作的存在,但其不排除一或多個其他特徵、整數、組件、操作、行為或群組的存在或添加。In addition, when used in this specification and the following claims, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)" and "including" are intended to indicate the presence of the stated feature, integer, component or operation, but it does not exclude one or more other features, integers, components, operations, acts or groups Group presence or addition.
10:處理系統 11:第二機械手臂 12:前開式晶圓傳送盒 14:機械手臂 16:保持區域 18a:基板處理腔室 18b:基板處理腔室 18c:基板處理腔室 18d:基板處理腔室 18e:基板處理腔室 18f:基板處理腔室 19a:串列部件 19b:串列部件 19c:串列部件 100:處理腔室 102:腔室主體 103:基板 104:基板支撐件 105:表面 106:蓋組件 108:第一電極 110a:隔離器 110b:隔離器 111:電漿剖面調變器 112:氣體分配器 114:入口 118:孔口 120:處理容積 122:第二電極 124:第三電極 126:開口 128:第一調諧電路 130:第一感測器 132A:第一電感器 132B:第二電感器 134:第一電子控制器 136:第二調諧電路 138:第二電子感測器 140:第二電子控制器 142:第一電力源 144:軸 145:箭頭 146:導管 147:軸線 148:濾波器 150:第二電力源 200:方法 205:步驟 210:步驟 215:步驟 220:步驟 225:步驟 230:步驟 235:步驟 240:步驟 300:半導體結構 302:光阻材料 304:第一圖案化材料層 306:第二圖案化材料層 308:含矽及氮層 310:介電層 312:襯墊層 314:多晶矽層 316a:開口 316b:開口 316c:開口 350:結構 10: Handling System 11: The second robotic arm 12: Front opening wafer transfer box 14: Robotic Arm 16: Keep Area 18a: Substrate processing chamber 18b: Substrate processing chamber 18c: Substrate processing chamber 18d: Substrate processing chamber 18e: Substrate processing chamber 18f: Substrate processing chamber 19a: Tandem Parts 19b: Tandem Parts 19c: Tandem Parts 100: Processing Chamber 102: Chamber body 103: Substrate 104: Substrate support 105: Surface 106: Cover assembly 108: First electrode 110a: Isolator 110b: Isolator 111: Plasma Profile Modulator 112: Gas distributor 114: Entrance 118: Orifice 120: Processing volume 122: Second electrode 124: Third electrode 126: Opening 128: First Tuning Circuit 130: First sensor 132A: First Inductor 132B: Second Inductor 134: The first electronic controller 136: Second Tuning Circuit 138: Second electronic sensor 140: Second electronic controller 142: First Power Source 144: Shaft 145: Arrow 146: Catheter 147: Axis 148: Filter 150: Second power source 200: Method 205: Steps 210: Steps 215: Steps 220: Steps 225: Steps 230: Steps 235: Steps 240: Steps 300: Semiconductor Structure 302: Photoresist 304: first patterned material layer 306: Second patterned material layer 308: Silicon and Nitrogen Layer 310: Dielectric layer 312: Liner Layer 314: polysilicon layer 316a: Opening 316b: Opening 316c: Opening 350: Structure
可參考說明書及附圖的剩餘部分進一步理解所揭示技術的性質及優點。A further understanding of the nature and advantages of the disclosed technology may be obtained by reference to the remainder of the specification and drawings.
第1A圖展示根據本技術之一些實施例的示例性處理系統的俯視圖。Figure 1A shows a top view of an exemplary processing system in accordance with some embodiments of the present technology.
第1B圖展示根據本技術之一些實施例的示例性處理系統的示意性部分橫截面圖。FIG. 1B shows a schematic partial cross-sectional view of an exemplary processing system in accordance with some embodiments of the present technology.
第2圖展示根據本技術之一些實施例的示例性半導體處理方法的操作。FIG. 2 shows the operation of an exemplary semiconductor processing method in accordance with some embodiments of the present technology.
第3A圖至第3B圖展示根據本技術之一些實施例的示例性半導體結構的橫截面圖。3A-3B show cross-sectional views of exemplary semiconductor structures in accordance with some embodiments of the present technology.
包括若干附圖作為示意圖。應理解,附圖係用於說明的目的,且除非明確指出為按比例的,否則不應認為其為按比例的。另外,提供作為示意圖的附圖以幫助理解,且附圖可能不包括與實際表現相比的所有態樣或資訊,且可為了說明性目的而包括誇示的材料。Several figures are included as schematic representations. It is to be understood that the drawings are for illustrative purposes and should not be considered to be to scale unless explicitly indicated to be to scale. Additionally, the drawings are provided as schematic diagrams to aid understanding and may not include all aspects or information as compared to actual representations and may include exaggerated material for illustrative purposes.
在附圖中,相似的組件及/或特徵可具有相同的元件符號。另外,可藉由在元件符號後添加區分相似組件的字母來區分同一類型的各個組件。若說明書中僅使用第一元件符號,則不管字母為何,描述適用於具有相同第一元件符號的相似組件中的任一者。In the drawings, similar components and/or features may have the same reference numerals. In addition, components of the same type can be distinguished by adding a letter after the reference symbol that distinguishes similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the letter.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none
200:方法 200: Method
205:步驟 205: Steps
210:步驟 210: Steps
215:步驟 215: Steps
220:步驟 220: Steps
225:步驟 225: Steps
230:步驟 230: Steps
235:步驟 235: Steps
240:步驟 240: Steps
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