TW202225453A - Tensile nitride deposition systems and methods - Google Patents

Abstract

Exemplary semiconductor processing methods may include flowing deposition gases that may include a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas, into a substrate processing region of a substrate processing chamber. The flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor may be greater than or about 1:1. The methods may further include generating a deposition plasma from the deposition gases to form a silicon-and-nitrogen containing layer on a substrate in the substrate processing chamber. The silicon-and-nitrogen-containing layer may be treated with a treatment plasma, where the treatment plasma is formed from the carrier gas without the silicon-containing precursor. The flow rate of the carrier gas in the treatment plasma may be greater than a flow rate of the carrier gas in the deposition plasma.

Description

Drawn nitride deposition system and method

This application claims the benefit of and priority to US Patent Application Serial No. 17/078,793, filed October 23, 2020, entitled "TENSILE NITRIDE DEPOSITION SYSTEMS AND METHODS," which is incorporated herein by reference in its entirety.

This technology relates to semiconductor systems and processes. More particularly, the present technology relates to deposition systems and methods that can form stretched silicon nitride layers.

Integrated circuits are realized by processes that create complex patterned layers of material on the surface of a substrate. Creating patterned material on a substrate requires a controlled method for forming and removing the exposed material. Material properties can affect how the device operates, and can also affect how the films are removed relative to each other. Plasma enhanced deposition can produce films with certain properties. Many films formed require additional processing to adjust or enhance the material properties of the film in order to provide suitable properties.

Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology meets these and other needs.

Embodiments of the present technology include systems and methods for forming a stretched silicon nitride layer on a substrate. In some embodiments, the stretched nitride layer may serve as an etch stop layer, CMP stop layer, or hard mask layer in front-end or mid-line semiconductor fabrication processes. The high tensile stress of the nitride layer can reduce the line edge roughness of holes, channels, trenches and other types of openings formed in one or more patterned layers deposited on or under the stretched nitride layer (line edge roughness; LER) and line width roughness (line width roughness; LWR). As the critical dimensions of semiconductor device structures, such as nMOS transistors, continue to decrease, the need for such precisely patterned openings may increase.

Embodiments of the present technology may include semiconductor processing methods that may include flowing a deposition gas including a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas into a substrate processing region of a substrate processing chamber. The flow rate ratio of nitrogen-containing precursor to silicon-containing precursor may be greater than or about 1:1. The method may further include generating a deposition plasma from a deposition gas to form a silicon and nitrogen containing layer on the substrate in the semiconductor processing chamber. The silicon and nitrogen containing layer may be treated with a processing plasma formed from a carrier gas in the absence of a silicon containing precursor. The flow rate of the carrier gas in the processing plasma may be greater than the flow rate of the carrier gas in the deposition plasma.

In an exemplary embodiment, the nitrogen-containing precursor may include ammonia, and the silicon-containing precursor may include silane. The nitrogen-containing precursor can be characterized by a flow rate of greater than or about 100 seem, and the silicon-containing precursor can be characterized by a flow rate of greater than or about 50 seem. In other embodiments, the carrier gas may include at least one of molecular nitrogen ( _N2 ) and argon. Molecular nitrogen in the carrier gas can be characterized as a flow rate greater than or about 5000 seem, and argon in the carrier gas can be characterized as a flow rate greater than or about 2000 seem. In other embodiments, the processing chamber may be characterized as the deposition chamber pressure during deposition of the silicon and nitrogen containing layer is less than the processing chamber pressure during processing of the silicon and nitrogen containing layer. In other embodiments, the deposition plasma may be generated by supplying the deposition gas with a plasma power of less than or about 60 watts. In other embodiments, the process plasma may be generated by supplying greater than or about 100 watts of plasma power to the carrier gas in the absence of a silicon-containing precursor.

In further exemplary embodiments, the silicon and nitrogen containing layer may be formed at a deposition rate of less than or about 10 Å/sec. In other embodiments, the processing method can produce a processed silicon and nitrogen containing layer that is a silicon nitride layer characterized by a tensile stress of greater than or about 1 GPa and a wet etch rate of less than or about 20 Å/min.

Embodiments of the present technology may also include semiconductor processing methods that include depositing a silicon and nitrogen containing layer on a substrate in a substrate processing region of a substrate processing chamber. The silicon- and nitrogen-containing layers may be deposited using a first plasma power from a deposition plasma generated from a deposition gas, the deposition gas including a nitrogen-containing precursor and a silicon-containing precursor. In some embodiments, the flow rate ratio of nitrogen-containing precursor to silicon-containing precursor is greater than or about 1:1. In other embodiments, the silicon and nitrogen containing layer may be formed at a deposition rate of less than or about 10 Å/sec. The method may further include treating the silicon and nitrogen containing layer with a treating plasma. The treatment plasma may be formed with a second plasma power greater than the first plasma power. The processing method can produce a silicon and nitrogen containing layer characterized by a tensile stress of greater than or about 1 GPa and a wet etch rate of less than or about 20 Å/min.

In an exemplary embodiment, the process plasma may be formed from a process gas without a silicon-containing precursor or a nitrogen-containing precursor. In further embodiments, the process plasma may be formed from a process gas comprising molecular nitrogen ( _N2 ). In other embodiments, molecular nitrogen may be delivered to the semiconductor processing chamber at a nitrogen gas flow rate greater than or about 10,000 seem. The processing method can produce a silicon and nitrogen containing layer, which is a silicon nitride layer characterized by less than or about 3 at. % hydrogen.

Embodiments of the present technology include semiconductor processing methods, which may include forming a silicon nitride layer in two or more cycles, which may include depositing nitrogen on a substrate in a substrate processing region of a substrate processing chamber A portion of the silicon nitride layer, and a portion of the silicon nitride layer is treated with a treatment plasma. A portion of the silicon nitride layer can be deposited to a thickness of less than or about 15 Å. In some embodiments, each portion of the silicon nitride layer may be formed at a deposition rate of less than or about 10 Å/sec. In other embodiments, processing operations for each portion of the just-deposited silicon nitride layer may occur in less than or about 15 seconds. Treating the plasma may increase the tensile stress and wet etch rate of the treated portion of the silicon nitride layer compared to the as-deposited portion. The processed portion of the silicon nitride layer may also be characterized by a hydrogen level of less than or about 3 at. %.

In an exemplary embodiment, portions of the silicon nitride layer may be deposited from a deposition plasma generated from deposition gases delivered to a substrate processing chamber. The deposition gas may include nitrogen-containing precursors and silicon-containing precursors. In some embodiments, the nitrogen-containing precursor may have a flow rate of less than or about 200 seem, and the silicon-containing precursor may have a flow rate of less than 100 seem. The processing method can produce a silicon nitride layer characterized by a tensile stress of greater than or about 1 GPa and a wet etch rate of less than or about 20 Å/min.

Such techniques may provide many benefits over conventional systems and methods of forming silicon nitride layers. For example, in embodiments where the flow rate of the carrier gas is increased when transitioning from deposition to processing operations, the processed silicon and nitrogen containing materials deposited on the substrate are compared to the results observed in conventional deposition-processing methods Tensile stress in can increase by a larger amount in a shorter period of time. Additionally, in embodiments where the amount of process plasma power that generates the process plasma is greater than the amount of deposition plasma power that generates the deposition plasma, the final tensile stress level in the silicon- and nitrogen-containing material may also be increased. In other embodiments, the present techniques can produce silicon and nitrogen containing layers with smaller atomic percent hydrogen than those observed in conventional deposition-processing methods. Lower atomic percent hydrogen can further increase tensile stress levels and reduce wet etch rates for silicon and nitrogen containing layers. Embodiments of the present technology, along with its many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

The present technology includes embodiments of systems and processing methods for forming stretched silicon nitride layers on semiconductor substrates. Among other functions, these stretched nitride layers solve the challenge of forming increasingly precise channels, contacts, vias, trenches, and other types of openings in patterned materials on substrates. Conventional low stress nitride layers between the patterned material of the substrate and the semiconductor material lack the force to keep the sidewalls of the patterned openings highly aligned and smooth. Thus, patterning of these low stress nitride layers produces rough openings characterized by large lines along sidewalls formed in the patterned material between the patterned photoresist layer and the nitride etch stop layer Edge Roughness (LER) and Line Width Roughness (LWR), or dimensional distortion due to hard masks. As the critical dimensions of semiconductor devices, such as nMOS transistors, continue to decrease, the amount of roughness in these openings becomes a greater problem. The degree of roughness in these conventionally formed openings increasingly exceeds the tolerances of the critical dimensions of substrate features required for stable, functioning integrated circuits.

One way to reduce the roughness in these openings is to form openings in the silicon nitride layer with increased tensile stress. The increased tensile stress enhances the properties of the adjacent patterned material, which reduces the tendency of the material to etch at non-uniform rates in the lateral direction. The openings formed in the patterned material are characterized by reduced line edge roughness (LER) and line width roughness (LWR) along their sidewalls. Unfortunately, forming silicon nitride layers with increased tensile stress is generally more difficult than forming conventional low stress nitride layers. By reducing the number of Si-H and N-H bonds and increasing the number of Si-N bonds in the as-deposited nitride layer, it is possible to increase the number of nitrides deposited by plasma enhanced chemical vapor deposition using silicon-nitrogen- and hydrogen-containing precursors Tensile stress in the layer. The reduction in the number of Si-H and N-H bonds may result from the removal of hydrogen from the just-deposited layer. The overall tensile stress in the nitride layer increases as the Si and N atoms enter the space left by the removal of the hydrogen atoms and form more Si-N bonds. A further difficulty in forming a high tensile stress nitride layer is the additional operation of removing hydrogen atoms from the as-deposited layer.

One method of treating the as-deposited silicon nitride layer is to elevate its tensile stress to expose the as-deposited layer to ultraviolet light. Unfortunately, UV processing can have several disadvantages, including low penetration of UV light through the just-deposited layer, and the need for additional equipment to generate and focus the light on the substrate. In many cases, it is impractical to incorporate UV processing equipment in the nitride deposition chamber, and the substrate with the freshly deposited nitride material must be transferred to a separate chamber for UV processing. Since typically UV processing equipment is designed to penetrate less than or about 5 to 10 Å of just-deposited nitride, the substrate can be passed back and forth between the nitride deposition and UV processing chambers multiple times to fabricate the entire layer. This can significantly increase the time and complexity of forming stretched silicon nitride layers on substrates using UV processing operations.

Embodiments of the present technology address these and other problems with conventional systems and methods of forming stretched silicon and nitrogen containing layers by depositing and processing silicon and nitrogen containing layers on a substrate in a single processing chamber. Embodiments of the processing method may include increasing the flow rate of the carrier gas between the deposition of the less stressed silicon and nitrogen containing layer on the substrate and the treatment of the just deposited nitride with a processing plasma to form a tensile stress greater than or about 1 GPa tensile stress of silicon and nitrogen containing layers. In such embodiments, the flow rate of one or more deposition precursors may be reduced or terminated while increasing the flow rate of the carrier gas included in the deposition precursor. In some embodiments, the carrier gas may flow continuously into the processing chamber during deposition and processing operations, and the carrier gas flow rate may not drop below the initial flow rate during the deposition operation until the processing operation is complete. In embodiments where the carrier gas flow rate between deposition and processing operations is increased, tensile stress in the treated silicon and nitrogen-containing materials may be lower than that observed in conventional deposition-processing methods A larger increase in a short period of time.

In other embodiments of the processing method, the plasma power may be increased in the transition from the deposition plasma for depositing the silicon- and nitrogen-containing layer to the processing plasma for increasing tensile stress in the layer. In some embodiments, the plasma power is uninterrupted during the transition from deposition to processing plasma. This can reduce the time per deposition-processing cycle to form a tensile-stressed silicon and nitrogen-containing layer. In embodiments where several deposition-processing cycles are performed to complete the formation of layers, the cumulative reduction in processing time may be substantial. In other embodiments, the increase in plasma power may also increase the tensile stress level in the fully formed silicon and nitrogen containing layer.

In other embodiments of the present technology, the stretched silicon and nitrogen-containing layers produced by embodiments of the systems and methods may have reduced hydrogen content compared to stretched layers produced by conventional methods. In embodiments, the stretched silicon and nitrogen containing layer may have less than or about 3 at. % atomic hydrogen. Low levels of hydrogen in the silicon and nitrogen containing layers can reduce the number of Si-H and N-H bonds in the layer while increasing the number of Si-N bonds. In embodiments, an increase in the molar ratio of Si-N bonds to Si-H and N-H bonds may increase the amount of tensile stress in the layer. In other embodiments, increasing the molar ratio can also reduce the wet etch rate of the silicon and nitrogen containing layers, which in some embodiments makes the silicon and nitrogen containing layers more useful as etch stop layers or hard masks in semiconductor manufacturing processes efficient.

After describing a general aspect of a chamber configured to perform operations in accordance with embodiments of the present technology in which plasma processing may be performed, specific methods and component configurations may be discussed. It should be understood that the present techniques are not intended to be limited to the specific films and processes discussed, as a number of film formation processes can be modified using the described techniques, and they can be applied to a variety of processing chambers and operations.

FIG . 1A shows a top plan view of one embodiment of a processing system 10 having deposition, processing, etch, bake, and hardening chambers, according to an embodiment. In the figures, a pair of front-loading pods 12 provide substrates of various sizes that are received by robotic arms 14 and placed in low pressure holding area 16 and then placed in substrate processing chambers 18a-f In one of these, the substrate processing chambers are disposed in tandem components 19a-c. The second robotic arm 11 may be used to transport substrate wafers from the holding area 16 to the substrate processing chambers 18a-f and back. Each substrate processing process 18a-f may be configured to perform a plurality of substrate processing operations including forming the semiconductor material stacks described herein, as well as plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition , etching, pre-cleaning, degassing, orientation and other substrate processes including plasma treatment, annealing, ashing, etc.

The substrate processing chambers 18a-f may include one or more system components for depositing, plasma processing, curing, and/or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers (eg, 18c-18d and 18e-18f) may be used to deposit dielectric material on the substrate, and a third pair of processing chambers (eg, 18a-18b) may be used to process the deposited dielectric quality. In another configuration, all three pairs of chambers (eg, 18a-f) may be configured to deposit and process stacks of alternating dielectric films on a substrate. Any one or more of the described processes may be performed in a separate chamber from the fabrication system shown in the various embodiments. It will be appreciated that system 10 encompasses other configurations of chambers for deposition, processing, etching, annealing and hardening of dielectric films.

FIG . 1B shows a cross-sectional view of an exemplary processing chamber 100 in accordance with some embodiments of the present technology. The drawings may illustrate an overview of a system that incorporates one or more aspects of the present technology and/or may be specifically configured to perform one or more operations in accordance with an embodiment of the present technology. Additional details of the chamber 100 or the method performed are described further below. Stretched nitride films may be formed using chamber 100 in accordance with some embodiments of the present technology, although it should be understood that methods may be similarly performed in any chamber where film formation occurs. The processing chamber 100 may include: a chamber body 102; a substrate support 104 disposed within the chamber body 102; a lid assembly 106 coupled with the chamber body 102 and enclosing the substrate support 104 within the processing volume 120 middle. Substrate 103 may be provided to processing volume 120 via opening 126, which may be conventionally sealed for processing using a slit valve or gate. During processing, the substrate 103 may lie on the surface 105 of the substrate support. The substrate support 104 can be rotated about an axis 147 as indicated by arrow 145, where the axis 144 of the substrate support 104 can be located. Additionally, during the deposition process, the substrate support 104 can be raised to rotate as needed.

Plasma profile modulators 111 may be positioned in processing chamber 100 to control the distribution of plasma on substrates 103 disposed on substrate supports 104 . Plasma profile modulator 111 may include a first electrode 108 disposed adjacent chamber body 102 and may separate chamber body 102 from other components of lid assembly 106 . The first electrode 108 may be part of the lid assembly 106, or may be a separate sidewall electrode. The first electrode 108 may be a ring-shaped or ring-shaped element, and may be a ring-shaped electrode. The first electrode 108 may be a continuous ring along the circumference of the processing chamber 100 surrounding the processing volume 120, or may be discontinuous at selected locations, if desired. The first electrode 108 may also be a porous electrode such as a porous ring or mesh electrode, or may be a plate electrode such as a secondary gas distributor.

The one or more separators 110a, 110b can be a dielectric material such as a ceramic or metal oxide (eg, aluminum oxide and/or aluminum nitride), which can contact the first electrode 108 and distribute the first electrode 108 with the gas The device 112 and the chamber body 102 are electrically or thermally separated. Gas distributor 112 may define orifices 118 for distributing process precursors into processing volume 120 . The gas distributor 112 may be coupled to the first power source 142, such as an RF generator, RF power source, DC power source, pulsed DC power source, pulsed RF power source, or any other power source that may be coupled to the processing chamber. In some embodiments, the first power source 142 may be an RF power source.

The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, for example, by the first power source 142 shown in FIG. 1, or in some embodiments the gas distributor 112 may be coupled to ground.

The first electrode 108 can be coupled to a first tuning circuit 128 that can control the ground path of the processing chamber 100 . The first tuning circuit 128 may include a first sensor 130 and a first electronic controller 134 . The first electronic controller 134 may be or include a variable capacitor or other circuit element. The first tuning circuit 128 may be or include one or more inductors 132 . The first tuning circuit 128 may be any circuit that achieves a variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some of the illustrated embodiments, the first tuning circuit 128 may include a first circuit branch and a second circuit branch coupled in parallel between ground and the first electronic sensor 130 . The first circuit branch may include a first inductor 132A. The second circuit branch may include a second inductor 132B coupled in series with the first electronic controller 134 . The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting the first and second circuit branches to the first electronic sensor 130 . The first electronic sensor 130 can be a voltage or current sensor, and can be coupled to a first electronic controller 134 that can perform some degree of closed-loop control of the plasma conditions within the processing volume 120 control.

The second electrode 122 may be coupled with the substrate support 104 . The second electrode 122 may be embedded within the substrate support 104 or coupled to the surface of the substrate support 104 . The second electrode 122 may be a plate, perforated plate, mesh, wire mesh, or any other distributed arrangement of conductive elements. The second electrode 122 can be a tuning electrode that can be coupled to the second tuning circuit 136 by a conduit 146 , such as a cable having a selected resistance (eg, 50 ohms) disposed in the shaft 144 of the substrate support 104 . The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor, and may be coupled with the second electronic controller 140 to provide further control of the plasma conditions in the processing volume 120 .

The third electrode 124 can be a bias electrode and/or an electrostatic clamping electrode, which can be coupled with the substrate support 104 . The third electrode may be coupled to the second power source 150 via the filter 148, which may be an impedance matching circuit. The second power source 150 may be a DC power source, a pulsed DC power source, an RF bias power source, a pulsed RF source or a bias voltage source, or a combination of these or other power sources. In some embodiments, the second power source 150 may be an RF bias power source.

The lid assembly 106 and substrate support 104 of FIG . 1B can be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 can control the plasma conditions in the processing volume 120 on-the-fly. Substrate 103 can be placed on substrate support 104 and process gases can be flowed through lid assembly 106 using inlet 114 according to any desired flow diagram. Gases may exit processing chamber 100 via outlet 152 . A power source can be coupled to the gas distributor 112 to generate plasma in the processing volume 120 . The third electrode 124 may be used to electrically bias the substrate in some embodiments.

Once the plasma is energized in the processing volume 120 , a potential difference can be created between the voltage and the first electrode 108 . A potential difference can also be created between the plasma and the second electrode 122 . The electronic controllers 134 , 140 can then be used to adjust the flow properties of the ground paths represented by the two tuning circuits 128 and 136 . Setpoints can be fed to the first tuning circuit 128 and the second tuning circuit 136 to independently control deposition rate and center-to-edge plasma density uniformity. In embodiments where the electronic controllers may both be variable capacitors, the electronic sensors may adjust the variable capacitors to independently maximize deposition rate and minimize thickness non-uniformity.

Each of the tuning circuits 128, 136 may have a variable impedance that may be adjusted using the respective electronic controller 134, 140. When the electronic controllers 134, 140 are variable capacitors, the capacitance range of each of the variable capacitors, and the inductances of the first inductor 132A and the second inductor 132B can be selected to provide the impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value in the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum value, the impedance of the first tuning circuit 128 can be high, resulting in a plasma shape with minimal airborne or lateral coverage on the substrate support. As the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128 , the air coverage of the plasma can be increased to a maximum value, effectively covering the entire working area of the substrate support 104 . As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may retract from the chamber walls and the aerial coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect, increasing or decreasing the airborne coverage of the plasma over the substrate support as the capacitance of the second electronic controller 140 changes.

The respective circuits 128, 136 may be tuned in closed loop using electronic sensors 130, 138. Depending on the type of sensor used, a set point for current or voltage may be installed in each sensor, and control software may be provided for the sensor that determines the control of each individual electronic controller 134, 140 adjustment to minimize deviation from the set point. Thus, the plasma shape can be selectively and dynamically controlled during processing. It should be understood that while the foregoing discussion is based on electronic controllers 134, 140, which may be variable capacitors, any electronic component having adjustable characteristics may be used to provide adjustable impedances for tuning circuits 128 and 136.

FIG . 2 shows an exemplary operation of a deposition method 200 in accordance with some embodiments of the present technology. The method may be performed in a variety of processing chambers, including the processing chamber 100 described above. The method may include performing a cleaning operation after deposition, which may limit particle deposition on the substrate. Method 200 may include a number of optional operations, which may or may not be specifically associated with some embodiments of methods in accordance with the present technology. For example, many operations are described to provide a broader scope of structure formation, but are not critical to the art, or may be performed by alternative methods that will be readily understood.

Method 200 may include performing additional operations prior to initiating the listed operations. For example, additional processing operations may include forming structures on the semiconductor substrate, which may include forming and removing materials. Previous processing operations may be performed in the chamber where method 200 is performed, or processing may be performed in one or more other processing chambers prior to transferring the substrate into the semiconductor processing chamber where method 200 is performed. In any event, method 200 may optionally include delivering a semiconductor substrate to a processing area of a semiconductor processing chamber, such as processing chamber 100 described above or other chambers that may include the components described above. The substrates may be disposed on a substrate support, which may be a base such as substrate support 104, and may reside in a processing area of a chamber, such as processing volume 120 described above.

Embodiments of the processing method 200 for forming an elongated silicon and nitrogen-containing layer may include flowing 205 a deposition precursor into a substrate processing region of a substrate processing chamber. Embodiments of deposition precursors may include at least one silicon-containing precursor and at least one nitrogen-containing precursor. Examples of silicon-containing precursors may include silanes, disilanes, and other silicon-containing precursors. Examples of nitrogen-containing precursors may include ammonia ( _NH3 ), and mixtures of molecular nitrogen and hydrogen ( _N2 + _H2 ), as well as other nitrogen-containing precursors. In other embodiments, the deposition precursor may also include at least one carrier gas. Examples of carrier gases may include molecular nitrogen ( _N2 ) and argon as well as other carrier gases.

In some embodiments, the nitrogen-containing deposition precursor may be introduced into the substrate processing region of the processing chamber at a flow rate greater than or about the flow rate of the silicon-containing deposition precursor. For example, the flow rate ratio of nitrogen-containing precursor to silicon-containing precursor may be greater than or about 1:1, greater than or about 2:1, greater than or about 3:1, greater than or about 4:1, Greater than or about 5:1 or greater. In other examples, the flow rate ratio of nitrogen-containing precursor to silicon-containing precursor may be silicon-rich. In embodiments, the flow rate ratio of nitrogen-containing precursor to silicon-containing precursor may be less than or about 1:5, less than or about 1:10, or less. In other embodiments, the deposition carrier gas may be introduced to the substrate processing region of the processing chamber at a flow rate greater than or about the combined flow rate of the nitrogen- and silicon-containing deposition precursors. For example, the ratio of flow rates of carrier gas to nitrogen- and silicon-containing precursors may be greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, greater than or about 60:1 , greater than or about 70:1 or greater.

In embodiments, the flow rate of the one or more nitrogen-containing deposition precursors may be greater than or about 100 sccm, greater than or about 125 sccm, greater than or about 150 sccm, greater than or about 175 sccm, greater than or about 200 sccm sccm, greater than or about 225 sccm, greater than or about 250 sccm or greater. In other embodiments, the flow rate of the one or more silicon-containing deposition precursors may be less than or about 100 seem, less than or about 90 seem, less than or about 80 seem, less than or about 70 seem, less than or about 60 sccm, less than or about 50 sccm, less than or about 40 sccm or less. In other embodiments, the flow rate of the carrier gas may be greater than or about 8000 sccm, greater than or about 9000 sccm, greater than or about 10,000 sccm, greater than or about 11,000 sccm, greater than or about 12,000 sccm or greater. In other embodiments, the flow of deposition precursors into the substrate processing chamber may increase the pressure in the chamber. In embodiments, the pressure in the substrate chamber during the flow of the deposition precursor may be greater than or about 1 Torr, greater than or about 2 Torr, greater than or about 3 Torr, greater than or about 4 Torr, greater than or about 5 Torr Torr, greater than or about 6 Torr, greater than or about 7 Torr or greater.

Embodiments of the processing method 200 may further include generating a deposition plasma 210 in a substrate processing region of the processing chamber. The deposition plasma can be generated by delivering plasma power to deposition precursors that have flowed into the substrate processing region. In some embodiments, plasma power may be delivered by a radio frequency (RF) power source electrically coupled to at least one electrode within the processing chamber. In an embodiment, the RF power supply can deliver power to at least one electrode that generates an electric field in the substrate processing region of the processing chamber that excites the deposition precursor to form a deposition plasma. In other embodiments, the plasma power delivered to the deposition precursor may be less than or about 60 watts, less than or about 55 watts, less than or about 50 watts, less than or about 45 watts, less than or about 40 watts , less than or about 35 watts, less than or about 30 watts or less. In other embodiments, the frequency of the RF power delivered to the deposition precursor may be 13.56 MHz in one non-limiting example. In some embodiments, the plasma power delivered to the deposition precursor may be provided continuously, while in other embodiments, the plasma power may be pulsed. In pulsed embodiments, the delivered RF plasma power may have a power that may be less than or about 10 kHz, and may be less than or about 9 kHz, less than or about 8 kHz, less than or about 7 kHz, less than or about 6 kHz, less than or about 5 kHz, less than or about 4 kHz, less than or about 3 kHz, less than or about 2 kHz, less than or about 1 kHz or less pulse frequency. In some pulsed embodiments, the off portion of the duty cycle of the plasma power may allow more diffusion of the plasma effluent in the just-deposited silicon and nitrogen containing material. In other embodiments, the plasma effluent diffuses for a longer time to form a more uniform as-deposited material.

Embodiments of the processing method 200 may further include depositing a silicon and nitrogen-containing material 215 on the substrate in the substrate processing chamber from a deposition plasma. In some embodiments, the as-deposited silicon and nitrogen containing material may be silicon nitride. In other embodiments, the as-deposited silicon and nitrogen-containing material can be characterized by the amount of hydrogen incorporated. In embodiments, the amount of hydrogen incorporated in the as-deposited material may be greater than or about 5 at. %, greater than or about 6 at. %, greater than or about 7 at. %, greater than or about 8 at. %, greater than or about 9 at.%, greater than or about 10 at.% or greater. The amount of hydrogen incorporated in the as-deposited silicon and nitrogen containing material can affect the deposition of the low stress material. In some embodiments, the as-deposited silicon and nitrogen-containing material may have less than or about 0.5 GPa, less than or about 0.1 GPa, less than or about 0.05 GPa, less than or about 0.01 GPa, less than or about -0.01 GPa, less than or about -0.1 GPa, less than or about -1 GPa or less tensile stress.

In an embodiment, the deposition of the silicon and nitrogen containing material on the substrate may be performed at a deposition temperature that affects the deposition rate of the material. In other embodiments, the semiconductor processing region of the processing chamber may be characterized as being below or about 550°C, below or about 500°C, below or about 475°C, below or about 450°C, below or about 425°C , a deposition temperature below or about 400°C, below or about 375°C, below or about 350°C or below or about 300°C or below. By depositing at temperatures below or about 500°C, the present technique preserves the device thermal budget compared to conventional high temperature deposition. In other embodiments, below or about 20 Å/sec, below or about 15 Å/sec, below or about 12 Å/sec, below or about 10 Å/sec, below or about 8 Å/sec Silicon and nitrogen containing materials are deposited at deposition rates of less than or about 5 Å/second, less than or about 2 Å/second or less.

As discussed further below, embodiments of depositing the silicon and nitrogen containing material may include all of the material in the final silicon and nitrogen containing layer, or less than a portion of the final silicon and nitrogen containing layer of the entire layer. In embodiments, the thickness of the as-deposited silicon and nitrogen-containing material on the substrate may be less than or about 500 Å, less than or about 400 Å, less than or about 350 Å, less than or about 300 Å, less than or about 250 Å, less than or about 200 Å, less than or about 150 Å, less than or about 100 Å, less than or about 50 Å, less than or about 40 Å, less than or about 30 Å, less than or about 20 Å Å, less than or about 15 Å, less than or about 10 Å or less. In other embodiments, the deposition operation may take less than or about 100 seconds, less than or about 75 seconds, less than or about 60 seconds, less than or about 30 seconds, less than or about 15 seconds seconds, less than or about 10 seconds, less than or about 5 seconds, less than or about 2 seconds, less than or about 1 second or less.

Embodiments of the processing method 200 may additionally include flowing 220 one or more processing precursors into the substrate processing region of the substrate processing chamber. Examples of processing precursors may include nitrogen-containing precursors such as N ₂ and passive gas precursors such as helium, argon, and neon. In some embodiments, the processing precursor may be helium-free. In other embodiments, the process precursors may include some or all of the carrier gases that are also used as deposition precursors. For example, embodiments include reducing or stopping the flow of nitrogen- and silicon-containing deposition precursors used during deposition operations while continuing to flow at least one of the carrier gases in the deposition precursors. In some embodiments, the flow rate of the carrier gas is increased during the transition from the deposition operation to the processing operation. In embodiments, the flow rate of the processing precursor in the substrate processing region of the processing chamber may be greater than or about 20,000 seem, greater than or about 22,500 seem, greater than or about 25,000 seem, greater than or about 27,500 seem, greater than or equal to Or about 30,000 sccm or more. In embodiments, treating the precursor may include a flow rate of greater than or about 15,000 seem, greater than or about 16,000 seem, greater than or about 17,000 seem, greater than or about 18,000 seem, greater than or about 19,000 seem, greater than or about Molecular nitrogen (N ₂ ) of 20,000 seem or greater. Higher _N2 flow rates can form additional Si-N bonds in silicon- and nitrogen-containing materials. In embodiments, the number of Si-N bonds in the treated silicon and nitrogen containing material may be increased by more than or about 1%, more than or about 2%, more than or about 3% compared to the as-deposited material , more than or about 4%, more than or about 5% or more. In other embodiments, higher N ₂ flow rates can reduce the etch rate of processed silicon and nitrogen containing materials. In embodiments, the etch rate of _N2 treated silicon and nitrogen containing materials may be reduced by more than or about 1%, more than or about 2%, more than or about 5%, more than At or about 10%, more than or about 15% or more.

In further embodiments, treating the precursor may include a flow rate of greater than or about 3000 seem, greater than or about 4000 seem, greater than or about 5000 seem, greater than or about 6000 seem, greater than or about 7000 seem, greater than Or about 8000 sccm or more of argon. In embodiments, the etch rate of the argon treated silicon and nitrogen containing material may be reduced by more than or about 1%, more than or about 2%, more than or about 5%, more than At or about 10%, more than or about 15% or more.

In other embodiments, the flow of processing precursors into the substrate processing chamber may increase the pressure in the chamber. In some embodiments, the pressure in the processing chamber during processing operations may be greater than the pressure in the processing chamber during deposition operations. In embodiments, the pressure in the substrate chamber during processing precursor flow may be characterized as greater than or about 3 Torr, greater than or about 4 Torr, greater than or about 5 Torr, greater than or about 6 Torr, greater than or about 7 Torr, greater than or about 8 Torr, greater than or about 9 Torr, greater than or about 10 Torr or greater. In embodiments, the increased chamber pressure may increase the stress of the processed silicon and nitrogen containing material. In some embodiments, the increased chamber pressure can increase the stress in the processed silicon and nitrogen-containing material by more than or about 2%, more than or about 5%, more than or about 5%, compared to the as-deposited material About 10%, more than or about 25%, more than or about 50% or more. In other embodiments, the increased chamber pressure may also increase the etch rate of the processed silicon and nitrogen containing materials. In embodiments, the increased chamber pressure may increase the etch rate in the processed silicon and nitrogen containing material by more than or about 1%, more than or about 2%, more than or about 2%, compared to the as-deposited material About 5%, more than or about 10%, more than or about 25% or more.

In embodiments, the flow rate of the processing precursor is greater than the flow rate of the deposition precursor. For example, in embodiments where the processing precursor includes one or more of the carrier gases in the deposition precursor, the flow rate of the one or more of the carrier gases in the processing precursor is greater than the carrier gas in the deposition precursor gas flow rate. In embodiments, the flow rate ratio of processing precursor to deposition precursor may be greater than or about 1:1, greater than or about 1.25:1, greater than or about 1.5:1, greater than or about 1.75:1, greater than or about 2:1 or greater. In embodiments with increased precursor flow rates between deposition and processing operations, tensile stress in treated silicon and nitrogen-containing materials can be increased significantly over the period of time.

Embodiments of the processing method 200 may further include generating a processing plasma 225 in a substrate processing region of the processing chamber. The processing plasma can be generated by delivering plasma power to processing precursors that have flowed into the substrate processing region. In some embodiments, the processing plasma power may be delivered by the same radio frequency (RF) power source used to deliver the deposition plasma power and delivered through the same system electrodes. In other embodiments, the processing plasma power may be greater than the deposition plasma power that excites the deposition plasma. In embodiments, the processing plasma power may be greater than or about 60 watts, greater than or about 70 watts, greater than or about 80 watts, greater than or about 90 watts, greater than or about 100 watts, greater than or about 110 watts, greater than or equal to or about 120 watts, greater than or about 130 watts, greater than or about 140 watts, greater than or about 150 watts or greater. Increasing the plasma power increases the free radicals available for dissociation and bombardment and partitioning in the membrane. In other embodiments, the frequency of the RF power delivered to the process precursor may be 13.56 MHz in one non-limiting example. In some embodiments, the plasma power delivered to the deposition precursor may be provided continuously, while in other embodiments, the plasma power may be pulsed.

In some embodiments, the plasma is delivered as a continuous wave during the transition from deposition to treatment plasma. This can reduce the time per deposition-processing cycle to form a tensile-stressed silicon and nitrogen-containing layer. In embodiments where several deposition-processing cycles are performed to complete the formation of layers, the cumulative reduction in processing time may be substantial. In other embodiments, an increase in plasma power during processing operations may also increase the tensile stress level in the fully formed silicon and nitrogen containing layer.

Embodiments of the processing method 200 may further include processing the as-deposited silicon and nitrogen-containing material 230 on the substrate in the substrate processing chamber with a processing plasma. In some embodiments, the treatment plasma exposure time may be greater than or about 1 second, greater than or about 2 seconds, greater than or about 5 seconds, greater than or about 10 seconds, greater than or about 15 seconds, greater than or about 30 seconds, greater than or about 45 seconds, greater than or about 60 seconds or more. In an embodiment, the exposure time of the as-deposited silicon and nitrogen-containing material to the processing plasma may depend on the thickness of the as-deposited material. In other embodiments, the exposure time may be greater than or about 0.1 seconds per Angstrom of deposited material (0.1 sec/Å). In other embodiments, the exposure time can be greater than or about 0.2 sec/Å, greater than or about 0.3 sec/Å, greater than or about 0.4 sec/Å, greater than or about 0.5 sec/Å, greater than or about 0.6 sec/Å sec/Å, greater than or about 0.7 sec/Å, greater than or about 0.8 sec/Å, greater than or about 0.9 sec/Å, greater than or about 1 sec/Å, greater than or about 2 sec/Å or more long.

In an embodiment, the processing of the silicon and nitrogen containing material may be performed on the substrate at a processing temperature that affects the processing rate of the material. In other embodiments, the semiconductor processing region of the processing chamber may be characterized as being below or about 550°C, below or about 500°C, below or about 475°C, below or about 450°C, below or about 425°C , less than or about 400°C, less than or about 375°C, less than or about 350°C or less than or about 300°C or less. In some embodiments, the increased chamber pressure can reduce the atomic percentage of hydrogen in the processed silicon and nitrogen-containing material. In embodiments, the atomic percentage of hydrogen in the treated silicon and nitrogen-containing material may be reduced by more than or about 1%, more than or about 2.5%, more than or about 5%, more than At or about 7.5%, more than or about 10% or more.

In an embodiment, the processing operation can produce a stretched silicon and nitrogen-containing material. In other embodiments, the treated silicon and nitrogen-containing material may have greater than or about 0.8 GPa, greater than or about 0.9 GPa, greater than or about 1 GPa, greater than or about 1.1 GPa, greater than or about 1.2 GPa, greater than or about 1.3 GPa GPa, greater than or about 1.4 GPa, greater than or about 1.5 GPa or greater tensile stress. In embodiments, the processing operations may also produce processed silicon and nitrogen-containing materials with reduced levels of incorporated hydrogen. In embodiments, the amount of hydrogen incorporated in the treated material may be less than or about 3 at. %, less than or about 2 at. %, less than or about 1 at. %, less than or about 0.5 at. %, less than or about 0.2 at.%, less than or about 0.1 at.% or less. Reducing the amount of hydrogen incorporated in the processed silicon- and nitrogen-containing materials can affect deposition of materials with higher tensile stress. In other embodiments, the reduced amount of hydrogen incorporated may also reduce the wet etch rate of the silicon and nitrogen containing layers.

In embodiments of the present technology, the plasma processing operation of the just deposited silicon and nitrogen containing material in the deposition processing chamber eliminates the need to move the substrate to the UV processing chamber and perform UV processing on the material. The exclusion of UV processing operations reduces the complexity of the processing method and system for forming the stretched silicon and nitrogen containing layers and reduces processing time. These and other aspects of the present technology provide faster, more productive, and more economical processing methods and systems for forming stretched silicon and nitrogen containing layers on semiconductor substrates.

The throughput increase achieved with embodiments of the present technology may be a cumulative increase for embodiments that form silicon and nitrogen containing layers in two or more cycles. These embodiments of the processing method 200 may further include forming a stretched silicon and nitrogen containing layer in two or more cycles of depositing and processing the silicon and nitrogen containing material. Additional cycles may begin by flowing additional deposition precursors into the substrate processing region of the substrate processing chamber, generating deposition plasma 210 from the deposition precursors, and depositing additional portions of silicon and nitrogen-containing materials on the substrate. Additional cycles may also include flowing one or more processing precursors into the substrate processing region of the processing chamber, generating a processing plasma, and processing additional portions of just-deposited silicon- and nitrogen-containing materials to produce stretched silicon-containing materials and an additional portion of the nitrogen layer.

When a portion of the stretched silicon and nitrogen-containing layer is formed, it can be determined whether it completes the formation of the stretched silicon and nitrogen-containing layer 235 . If a portion of the stretched silicon and nitrogen containing layer completes formation of the layer, the processing method may terminate 240 . If a portion of the stretched silicon and nitrogen-containing layer does not complete the formation of the layer, another cycle of depositing and processing the silicon and nitrogen-containing material may begin. In embodiments, when the thickness of the stretched silicon and nitrogen-containing layer is greater than or about 50 Å, greater than or about 100 Å, greater than or about 150 Å, greater than or about 200 Å, greater than or about 250 Å, greater than or about 300 Å, greater than or about 400 Å or greater, the complete layer is formed.

Embodiments of the finished stretched silicon and nitrogen-containing layer made by processing method 200 may have greater than or about 0.8 GPa, greater than or about 0.9 GPa, greater than or about 1 GPa, greater than or about 1.1 GPa, greater than or about A tensile stress of 1.2 GPa, greater than or about 1.3 GPa, greater than or about 1.4 GPa, greater than or about 1.5 GPa or greater. In other embodiments, the finished stretched silicon and nitrogen-containing layer may have a thickness of less than or about 20 Å/min, less than or about 17.5 Å/min, less than or about 15 Å/min, less than or about 12.5 Å/min, Wet etch rates of less than or about 10 Å/min or less. In embodiments, these properties of the stretched silicon and nitrogen containing layers can make them effective silicon nitride etch stop layers or hard masks that also support the formation of precise openings in adjacent patterned material. As noted above, the higher tensile stress in the nitride layer reduces the tendency of adjacent patterned materials to etch at non-uniform rates during the formation of openings in the material. As a result, the openings formed in the patterned material adjacent to the stretched nitride layer have less roughness, which is characterized by less line edge roughness (LER) and line width roughness (LWR) along the sidewalls of the openings .

3A - 3B show cross-sectional views of an exemplary semiconductor structure 300 in accordance with embodiments of the present technology. The illustrated embodiment of structure 300 includes a stretched silicon and nitrogen containing layer 308 formed by processing methods and systems in accordance with embodiments of the present technology. In the embodiment shown in FIG . 3A , the structure 300 may also include a layer of patterned photoresist material 302 adjacent to the first and second layers 304 and 306 of patterned material. In the embodiment shown, the second layer of patterned material 306 is in direct contact with the stretched silicon and nitrogen containing layer 308 .

In the embodiment of structure 300 shown in FIG . 3A , the layers on opposite sides of the stretched silicon and nitrogen containing layer 308 are illustrated as patterned material layers 304 and 306 . In an embodiment, the layers on the side of layer 308 opposite the patterned material may include a dielectric layer 310 that may be in direct contact with the stretched silicon and nitrogen containing layer 308 . The dielectric layer can be characterized as a thickness greater than or about 800 Å, and can be characterized as a silicon and oxygen containing dielectric layer, such as a silicon oxide layer. In other embodiments, structure 300 may include a liner layer 312 adjacent to dielectric layer 310 . The liner layer 312 can be characterized by a thickness of greater than or about 200 Å, and can be a dense layer of dielectric material, such as a layer of silicon nitride deposited by atomic layer deposition. In other embodiments, structure 300 may include polysilicon layer 314 adjacent to liner layer 312 . The polysilicon layer can be characterized as greater than or about 900 Å thick and can be used as a substrate for semiconductor device structures such as nMOS transistors (not shown).

In the embodiment of the structure 300 shown in FIG . 3A , the patterned photoresist material 302 may be patterned to allow openings (not shown) to be formed in the first and second patterned material layers 304 and 306 . In an embodiment, these openings may extend through the first patterned material layer 304, which may be a silicon-oxygen- and carbon-containing layer characterized by a thickness greater than or about 300 Å, which may be formed by a spin process. In other embodiments, these openings may also extend through the second patterned material layer 306, which may be a silicon-oxygen- and carbon-containing layer characterized by a thickness greater than or about 500 Å, which may be deposited by chemical vapor deposition Process formation. In other embodiments, the stretched silicon and nitrogen containing layer 308 can be used as an etch stop layer, which can form the bottom side of the opening.

FIG . 3B shows another embodiment of a structure 350 with openings 316a-316c formed in the first and second patterned layers 304 and 306 of material. The openings 316a - 316c may have sidewalls that are substantially perpendicular to the bottom side that includes the exposed surface of the stretched silicon and nitrogen containing layer 308 . The sidewalls of openings 316a-316c can be characterized as having an average deviation of less than or about 10 Å, less than or about 5 Å, less than or about 3 Å, less than or about 1 Å or less of line edge roughness. The LER/LWR values of the sidewalls of the openings in embodiments characterizing structure 350 may be at least 10% less than the LER/LWR values of openings formed in structures with conventional low stress silicon nitride layers. Not only does the present processing method and system provide a stretched silicon and nitrogen containing layer without the need for time-consuming UV processing operations, it also provides a semiconductor structure such as structure 350, which is adjacent to the stretched silicon and nitrogen containing layer The openings in the patterned material are more precise and have less line edge roughness/line width roughness than openings formed in conventional structures.

In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, or equivalents may be used without departing from the spirit of the embodiments. Additionally, many well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be considered to limit the scope of the present technology. Additionally, methods or processes are described herein sequentially or in steps, but it should be understood that operations may be performed concurrently or in an order different from that listed.

Where a numerical range is provided, it is to be understood that unless the context clearly dictates otherwise, each intervening value between the upper and lower limits of that range, down to the minimum fraction of the lower unit, is also specifically disclosed. Any stated value in the stated range or any narrower range between an unspecified intervening value and any other stated or intervening value is encompassed. The upper and lower limits of those smaller ranges may independently be included in or excluded from the range, and each range is also encompassed by the present technology (neither the upper and lower limits are included in the smaller ranges, or either or both) are included in smaller ranges), where each range is limited by the specifically excluded limit in the stated range. The stated range includes one or both of the limits, as well as ranges excluding either or both of those included limits.

As used herein and in the appended claims, the singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, and reference to "the layer" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so on.

In addition, when used in this specification and the following claims, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)" and "including" are intended to indicate the presence of the stated feature, integer, component or operation, but it does not exclude one or more other features, integers, components, operations, acts or groups Group presence or addition.

10: Handling System 11: The second robotic arm 12: Front opening wafer transfer box 14: Robotic Arm 16: Keep Area 18a: Substrate processing chamber 18b: Substrate processing chamber 18c: Substrate processing chamber 18d: Substrate processing chamber 18e: Substrate processing chamber 18f: Substrate processing chamber 19a: Tandem Parts 19b: Tandem Parts 19c: Tandem Parts 100: Processing Chamber 102: Chamber body 103: Substrate 104: Substrate support 105: Surface 106: Cover assembly 108: First electrode 110a: Isolator 110b: Isolator 111: Plasma Profile Modulator 112: Gas distributor 114: Entrance 118: Orifice 120: Processing volume 122: Second electrode 124: Third electrode 126: Opening 128: First Tuning Circuit 130: First sensor 132A: First Inductor 132B: Second Inductor 134: The first electronic controller 136: Second Tuning Circuit 138: Second electronic sensor 140: Second electronic controller 142: First Power Source 144: Shaft 145: Arrow 146: Catheter 147: Axis 148: Filter 150: Second power source 200: Method 205: Steps 210: Steps 215: Steps 220: Steps 225: Steps 230: Steps 235: Steps 240: Steps 300: Semiconductor Structure 302: Photoresist 304: first patterned material layer 306: Second patterned material layer 308: Silicon and Nitrogen Layer 310: Dielectric layer 312: Liner Layer 314: polysilicon layer 316a: Opening 316b: Opening 316c: Opening 350: Structure

A further understanding of the nature and advantages of the disclosed technology may be obtained by reference to the remainder of the specification and drawings.

Figure 1A shows a top view of an exemplary processing system in accordance with some embodiments of the present technology.

FIG. 1B shows a schematic partial cross-sectional view of an exemplary processing system in accordance with some embodiments of the present technology.

FIG. 2 shows the operation of an exemplary semiconductor processing method in accordance with some embodiments of the present technology.

3A-3B show cross-sectional views of exemplary semiconductor structures in accordance with some embodiments of the present technology.

Several figures are included as schematic representations. It is to be understood that the drawings are for illustrative purposes and should not be considered to be to scale unless explicitly indicated to be to scale. Additionally, the drawings are provided as schematic diagrams to aid understanding and may not include all aspects or information as compared to actual representations and may include exaggerated material for illustrative purposes.

In the drawings, similar components and/or features may have the same reference numerals. In addition, components of the same type can be distinguished by adding a letter after the reference symbol that distinguishes similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the letter.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

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205: Steps

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Claims (20)

A semiconductor processing method comprising the steps of: flowing a deposition gas comprising a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas into a substrate processing region of a substrate processing chamber, wherein a flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor greater than or approximately 1:1; generating a deposition plasma from the deposition gases to form a silicon and nitrogen containing layer on a substrate in the substrate processing chamber; and treating the silicon- and nitrogen-containing layer with a processing plasma, wherein the processing plasma is formed from the carrier gas in the absence of the silicon-containing precursor, and wherein the flow rate of the carrier gas in the processing plasma is greater than the deposition The flow rate of the carrier gas in the plasma. The semiconductor processing method of claim 1, wherein the nitrogen-containing precursor comprises ammonia, and wherein the ammonia has a flow rate of greater than or about 100 seem. The semiconductor processing method of claim 1, wherein the silicon-containing precursor comprises a silane, and wherein the silane has a flow rate of greater than or about 50 seem. The semiconductor processing method of claim 1, the carrier gas comprising molecular nitrogen (N ₂ ) and argon, wherein the molecular nitrogen has a flow rate of greater than or about 5000 sccm, and the argon gas has a flow rate of greater than or about 2000 sccm Rate. The semiconductor processing method of claim 1, wherein the silicon and nitrogen-containing layer can be formed at a deposition rate of less than or about 10 Å/sec. The semiconductor processing method of claim 1, wherein the step of generating the deposition plasma further comprises the step of: delivering a plasma power of less than or about 60 watts to the deposition gases. The semiconductor processing method of claim 1, wherein a semiconductor processing chamber is characterized by a deposition chamber pressure during the step of depositing the silicon and nitrogen-containing layer being less than the pressure during the step of processing the silicon and nitrogen-containing layer Process chamber pressure. The semiconductor processing method of claim 1, wherein a processed silicon and nitrogen-containing layer comprises a silicon nitride layer characterized by a tensile stress greater than or about 1 GPa and a wetness less than or about 20 Å/min etch rate. A semiconductor processing method comprising the steps of: A silicon and nitrogen containing layer is deposited on a substrate in a substrate processing region of a substrate processing chamber using a deposition plasma generated from a deposition gas comprising a nitrogen containing precursor and a silicon containing precursor the silicon and nitrogen containing layer, and wherein the deposition plasma is formed with a first plasma power; and treating the silicon and nitrogen containing layer with a process plasma, wherein the process plasma is formed with a second plasma power greater than the first plasma power, and wherein the silicon and nitrogen containing layer is characterized by greater than or about 1 GPa and a wet etch rate of less than or about 20 Å/min. The semiconductor processing method of claim 9, wherein the first plasma power is less than or about 60 watts, and the second plasma power is greater than or about 100 watts. The semiconductor processing method of claim 9, wherein the silicon and nitrogen containing layer comprises a silicon nitride layer with a hydrogen level of less than or about 3 at.%. The semiconductor processing method of claim 9, wherein the processing plasma is formed from a processing gas in the absence of the silicon-containing precursor or the nitrogen-containing precursor. The semiconductor processing method of claim 9, wherein the processing plasma is formed from a processing gas comprising molecular nitrogen (N ₂ ), and wherein the molecular nitrogen is delivered to the processing plasma at a nitrogen flow rate of greater than or about 10,000 sccm Semiconductor processing chamber. The semiconductor processing method of claim 9, wherein the silicon and nitrogen containing layer can be formed at a deposition rate of less than or about 10 Å/sec. A semiconductor processing method comprising the steps of: forming a silicon nitride layer, wherein the silicon nitride layer is formed by two or more cycles, the cycles comprising: forming a portion of a silicon nitride layer on a substrate in a substrate processing region of a substrate processing chamber, wherein the portion of the silicon nitride layer is deposited to a thickness of less than or about 15 Å, and treating the portion of the silicon nitride layer with a treatment plasma, wherein the treatment plasma increases a tensile stress and wet etch rate of the treated portion of the silicon nitride layer compared to the as-deposited portion, and wherein the processed portion of the silicon nitride layer is characterized by a hydrogen level of less than or about 3 at. %. The semiconductor processing method of claim 15, wherein the entire silicon nitride layer has a thickness of greater than or about 300 Å. The semiconductor processing method of claim 15, wherein the portion of the silicon nitride layer is processed with the processing plasma for less than or about 15 seconds. The semiconductor processing method of claim 15, wherein the portion of the silicon nitride layer is deposited with a deposition plasma generated from deposition gases delivered to the substrate processing chamber, and wherein the deposition gases comprise a nitrogen-containing The precursor, a silicon-containing precursor, and further wherein the nitrogen-containing precursor has a flow rate of less than or about 200 seem, and the silicon-containing precursor has a flow rate of less than 100 seem. The semiconductor processing method of claim 15, wherein the portion of the silicon nitride layer can be formed at a deposition rate of less than or about 10 Å/sec. The semiconductor processing method of claim 15, wherein the entire silicon nitride layer is characterized by a tensile stress of greater than or about 1 GPa and a wet etch rate of less than or about 20 Å/min.

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