TW202220166A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

A semiconductor device and manufacturing method of the same are provided. The semiconductor device includes a substrate, a low-voltage device, a medium-voltage device and high-voltage devices. The low-voltage device includes a first gate oxide located in the substrate, the medium-voltage device includes a second gate oxide located in the substrate, and each of the high-voltage devices includes a third gate oxide located in the substrate. The top surface of the first gate oxide, the top surface of the second gate oxide, and the top surface of the third gate oxide are on the same planar level. The thickness of the first gate oxide is smaller than the thickness of the second gate oxide, and the thickness of the second gate oxide is smaller than the thickness of the third gate oxide.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor technology, and more particularly, to a semiconductor device and a method of manufacturing the same.

With the development of science and technology, the demand for component size reduction and high performance is also increasing. At present, a gate-last process has been developed, which uses a metal gate to replace the polysilicon gate to solve the electrical problem caused by the reduction of the gate size.

However, in the post-gate process of the high-k dielectric layer/metal gate (HKMG), when the semiconductor device integrates components with different operating voltages, due to the gate oxidation of the different components Due to different layer thicknesses, in order to replace the dummy polysilicon gate in the post-gate process with a metal gate, the gate height of some components will be sacrificed during the planarization process, resulting in poor stability of the semiconductor device. Therefore, how to solve the problem that the heights of gate oxide layers of different voltage elements in a semiconductor device are not uniform is an important issue.

The present invention provides a semiconductor device, which can improve the stability of the semiconductor device.

The present invention also provides a manufacturing method of a semiconductor device, which can simplify the process, make the top surfaces of the gate oxide layers of each voltage element at the same level, improve the stability of the semiconductor device, and provide a more flexible selection of gate materials.

The semiconductor device of the present invention includes: a substrate, a low voltage element, a medium voltage element and a plurality of high voltage elements. A low-voltage component includes a first gate oxide layer located in the substrate; a medium-voltage component includes a second gate oxide layer located in the substrate; each high-voltage component includes a third gate oxide layer located in the substrate, The top surface of the first gate oxide layer, the top surface of the second gate oxide layer and the top surface of the third gate oxide layer are at the same level, and the thickness of the first gate oxide layer is smaller than the thickness of the first gate oxide layer. The thickness of the second gate oxide layer, the thickness of the second gate oxide layer is smaller than the thickness of the third gate oxide layer.

In an embodiment of the present invention, the above-mentioned low-voltage device includes a metal gate formed on the first gate oxide layer.

In an embodiment of the present invention, the above-mentioned medium voltage device includes a metal gate or a polysilicon gate formed on the second gate oxide layer.

In an embodiment of the present invention, the above-mentioned high-voltage device includes a metal gate or a polysilicon gate formed on the second gate oxide layer.

In an embodiment of the present invention, different third gate oxide layers in the above-mentioned plurality of high-voltage components have different thicknesses, respectively.

In an embodiment of the present invention, the above-mentioned semiconductor device may further include a plurality of element isolation structures located in the substrate for separating the low voltage element, the medium voltage element and the plurality of high voltage elements.

The manufacturing method of the semiconductor device of the present invention includes: forming a plurality of element isolation structures in a substrate to define a low voltage element region, a medium voltage element region and a plurality of high voltage element regions. Next, a patterned mask having a first opening is formed on the substrate, and the first opening exposes a surface of the substrate in one of the high-voltage element regions. Using the patterned mask as an etching mask, the substrate in the first opening is removed to a first depth, and a coating layer is formed in the first opening. Repeat the following steps a to c: a. Form an nth opening in the patterned mask, and the nth opening exposes the surface of the substrate of the nth one of the plurality of high-voltage element regions, where n is greater than A positive integer of 1; b. Using the patterned mask as an etching mask, remove the substrate in the nth opening to an nth depth; c. Form the coating in the nth opening cloth layer. After the above steps are all completed in the plurality of high-voltage device regions, the coating layer is removed, and a high-voltage device gate oxide layer is formed on the substrate to fill the first opening and the nth opening, and use The patterned mask acts as a stop layer and planarizes the gate oxide layer of the high voltage device. Next, a (n+1)th opening is formed in the patterned mask, and the (n+1)th opening exposes the surface of the substrate in the medium voltage device region, and the patterned mask is used as the etching the mask, removing the substrate in the (n+1)th opening to a (n+1)th depth, then removing the patterned mask, and removing the substrate in the (n+1)th opening A gate oxide layer of the medium voltage element is formed in the opening. Next, a protective layer is formed on the surface of the gate oxide layer of the medium voltage element, and the surface of the substrate in the low voltage element region is exposed, and then a gate oxide layer of the low voltage element is formed on the surface of the substrate in the low voltage element region, The top surface of the gate oxide layer of the low voltage element, the top surface of the gate oxide layer of the medium voltage element and the top surface of the gate oxide layer of the high voltage element are at the same level.

In another embodiment of the present invention, the step of forming the patterned mask includes: forming a pad oxide layer on the surface of the substrate, then forming a mask layer on the pad oxide layer, and then patterning the the mask layer to form the patterned mask with the first opening.

In another embodiment of the present invention, after forming the protective layer, the remaining pad oxide layer may be removed by a wet process.

In an embodiment of the present invention, the above-mentioned first depth is different from the nth depth.

In another embodiment of the present invention, before removing the patterned mask, a sacrificial oxide layer may be formed on the surface of the substrate in the medium voltage device region to improve the interface of the substrate, and The sacrificial oxide layer and a portion of the substrate below it are removed by a wet process.

In another embodiment of the present invention, the above-mentioned protective layer includes a photoresist layer.

In another embodiment of the present invention, the method for forming the gate oxide layer of the high voltage device includes: forming a thermal oxide layer on the surface of the substrate by a thermal oxidation method, and then forming a chemical vapor phase on the thermal oxide layer Deposit an oxide layer.

In another embodiment of the present invention, the method for forming the gate oxide layer of the medium voltage element includes an in situ vapor generation (ISSG) method or a dry oxidation method.

Based on the above, the semiconductor device and the manufacturing method thereof of the present invention can integrate at least one low-voltage element, one medium-voltage element and two or more high-voltage elements on the substrate. Since the top surfaces of the gate oxide layers of the plurality of voltage elements are at the same level, Therefore, the height of the gate of the high-voltage device will not be affected by the gate post-processing process, which can improve the stability of the semiconductor device formed subsequently, and can provide a more flexible selection of gate materials by adjusting the thickness of the gate oxide layer. .

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

The following examples are described in detail with the accompanying drawings, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn in full scale. In order to facilitate understanding, the same elements in the following description will be described with the same symbols.

In addition, the terms such as "include", "include", "have", etc. used in the text are all open-ended terms, that is, "including but not limited to".

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer," or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

In addition, the directional terms mentioned in the text, such as "up", "down", etc., are only used to refer to the direction of the drawings, and are not used to limit the present invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device 10 includes a substrate 100 , a low voltage element 110 , a medium voltage element 120 , and a plurality of high voltage elements 130 . The substrate 100 further includes a plurality of element isolation structures 102 for separating the low voltage element 110 , the medium voltage element 120 and the plurality of high voltage elements 130 . The material of the substrate 100 includes silicon. The low voltage device 110 includes a first gate oxide layer 112 located in the substrate 100 and a gate electrode 114 located on the first gate oxide layer 112; the medium voltage device 120 includes a second gate oxide layer 122 located on the The substrate 100 and the gate electrode 124 are located on the second gate oxide layer 122; each of the high-voltage elements 130 includes a third gate oxide layer 132 located in the substrate 100 and the gate electrode 134 is located on the second gate oxide layer 122. on the third gate oxide layer 132 .

In the semiconductor device 10 , the material of the gate electrode 114 of the low voltage element 110 includes metal, the material of the gate electrode 124 of the medium voltage element 120 may be metal or polysilicon, and the material of the gate electrode 134 of the high voltage element 130 may be be metal or polysilicon.

In the semiconductor device 10, the top surface of the first gate oxide layer 112, the top surface of the second gate oxide layer 122, and the top surface of the third gate oxide layer 132 are at the same level, and the first gate oxide layer 132 is at the same level. The thickness t1 of the gate oxide layer 112 is smaller than the thickness t2 of the second gate oxide layer 122 , the thickness t2 of the second gate oxide layer 122 is smaller than the thicknesses t31 and t32 of the plurality of third gate oxide layers 132 , wherein the Different third gate oxide layers 132 in the plurality of high-voltage components 130 may have different thicknesses. For example, the plurality of high-voltage components 130 in FIG. 1 include a first high-voltage component 130a and a second high-voltage component 130b. The thickness t31 of the third gate oxide layer 132a of a high voltage element 130a is different from the thickness t32 of the third gate oxide layer 132b of the second high voltage element 130b.

2A to 2P are schematic cross-sectional views of a semiconductor device according to another embodiment of the present invention, wherein the same reference numerals as in the previous embodiment are used to represent the same or similar components, and some technical descriptions are omitted, such as layers or The location, size, material, etc. of the regions can all be referred to the content of the previous embodiment, and thus will not be described in detail below.

2A, a substrate 100 is provided, and a plurality of device isolation structures 102 are formed in the substrate 100 to define a low voltage device region 110', a medium voltage device region 120' and a plurality of high voltage device regions 130'. The plurality of high-voltage element regions 130 ′ can be more than two high-voltage element regions. Taking the embodiment of the present invention as an example, the plurality of high-voltage element regions 130 ′ include a first high-voltage element region 130 a ′ and a second high-voltage element region 130 b ', but the present invention is not limited to this. Next, in order to form a patterned mask layer on the substrate 100, a pad oxide layer 104 may be formed on the surface of the substrate 100, and a mask layer 106 may be formed on the pad oxide layer 104. The mask layer The thickness of the layer 106 is, for example, 300 Å, and the material of the mask layer 106 includes silicon nitride.

Then, referring to FIG. 2B , in order to pattern the mask layer 106 , a first patterned photoresist layer PR1 may be formed on the substrate 100 . Here, the first patterned photoresist layer PR1 has a first photoresist opening O1 exposing the surface of the mask layer (106 in FIG. 2A ) of the first high voltage device region 130a'. Next, using the first patterned photoresist layer PR1 as an etching mask, the mask layer is patterned to form a patterned mask layer 106p having a first opening 105a. After that, using the patterned mask layer 106p as an etching mask, the exposed pad oxide layer 104 is removed until the surface of the substrate 100 of the first high voltage device region 130a' is exposed.

Then, referring to FIG. 2C, using the patterned mask layer 106p as an etching mask, the substrate 100 in the first opening 105a is removed to a first depth h1.

2D, the first patterned photoresist layer PR1 in FIG. 2C is removed, and then a coating layer 105 is formed in the first opening 105a. The coating layer 105 is an organic substance and fills the first opening 105a to make the surface of the patterned mask layer 106p flat.

Then, referring to FIG. 2E , in order to continue to fabricate the gate oxide layers of high voltage devices for high voltage devices with different operating voltages, a second patterned photoresist layer PR2 may be formed on the substrate 100 first. Here, the second patterned photoresist layer PR2 has a second photoresist opening O2 exposing the surface of the patterned mask layer 106p in the second high voltage device region 130b'. Next, using the second patterned photoresist layer PR2 as an etching mask, the patterned mask layer 106p is etched to form a second opening 105b therein. After that, using the patterned mask layer 106p as an etching mask, the exposed pad oxide layer 104 is removed until the surface of the substrate 100 of the second high voltage device region 130b' is exposed.

Then, referring to FIG. 2F, using the patterned mask 106p as an etching mask, the substrate 100 in the second opening 105b is removed to a second depth h2, wherein the second depth h2 is the same as the first depth h1 is different.

Next, referring to FIG. 2G, the first patterned photoresist layer PR2 in FIG. 2F is removed, and another coating layer 105 is formed in the second opening 105b. The coating layer 105 fills the second opening 105b, wherein the coating layer 105 is also an organic substance.

The method for manufacturing a semiconductor device in this embodiment takes two high-voltage components as an example. If there are more than three high-voltage components, the above steps in FIGS. 2D to 2G can be repeated until each high-voltage component area is filled with coating The opening of layer 105 .

Then, referring to FIG. 2H, all the coating layers 105 in FIG. 2G are removed to expose the substrate 100 of all the high voltage device regions 130'. Next, a high voltage device gate oxide layer 132' is formed on the substrate 100 to fill the first opening 105a and the second opening 105b. The method for forming the gate oxide layer 132' of the high voltage device is, for example, forming a sacrificial oxide layer (not shown) on the surface of the substrate 100 to improve the interface of the substrate 100, and then using a wet process to remove the sacrificial oxide layer. remove. Next, a thermal oxide layer is formed on the surface of the substrate 100 by means of a thermal oxidation method, and a chemical vapor deposition (CVD) oxide layer is formed on the thermal oxide layer, so as to obtain a high-density composite material. The gate oxide layer 132' of the high voltage element is described.

Next, referring to FIG. 2I, using the patterned mask layer 106p as a stop layer, the gate oxide layer 132' of the high voltage device is planarized. Since the patterned mask layer 106p is used as the stop layer, the planarization process can be better controlled. Then, In order to manufacture the gate oxide layer of the medium voltage device, a third patterned photoresist layer PR3 may be formed on the substrate 100 first. Here, the third patterned photoresist layer PR3 has a third photoresist opening O3 exposing the surface of the patterned mask layer 106p in the medium voltage device region 120'. Then, using the third patterned photoresist layer PR3 as an etching mask, the patterned mask layer 106p is etched to form a third opening 105c therein. After that, using the patterned mask layer 106p as an etching mask, the exposed pad oxide layer 104 is removed until the surface of the substrate 100 in the medium voltage device region 120' is exposed.

Then, referring to FIG. 2J, using the patterned mask 106p as an etching mask, the substrate 100 in the third opening 105c is removed to a third depth h3.

Next, referring to FIG. 2K , the third patterned photoresist layer PR3 in FIG. 2J is removed, and from the viewpoint of improving the interface of the substrate 100 , the substrate 100 in the medium voltage device region 120 ′ can be first A sacrificial oxide layer 108 is formed on the surface, and the thickness of the sacrificial oxide layer 108 is, for example, 70 Å.

Next, referring to FIG. 2L, the sacrificial oxide layer 108 can be removed by a wet process, and the thickness removed by the wet process is about 1.3 times the thickness of the sacrificial oxide layer 108, for example, 91 Å; Part of the substrate 100 under the sacrificial oxide layer 108 is also removed during the wet process, and the thickness of the gate oxide layer 132' of the high voltage device is also reduced accordingly. Next, the patterned mask layer 106p is removed.

Then, referring to FIG. 2M, a gate oxide layer 122' of a medium voltage device is formed in the third opening 105c. The method for forming the gate oxide layer 122' of the medium voltage device is, for example, an In-Situ Steam Generation (ISSG) method, a dry oxidation method or other methods, but the present invention is not limited thereto.

Then, referring to FIG. 2N, a protective layer PR4 is formed on the surface of the gate oxide layer 122' of the medium voltage element to protect the gate oxide layer 122' of the medium voltage element, and the protective layer PR4 is, for example, a photoresist layer. Next, the surface of the low-voltage device region 110' and the high-voltage device region 130' can be selectively removed by a wet process, such as the remaining pad oxide layer 104 and part of the device isolation structure in FIG. 2M. 102 and part of the high voltage device gate oxide layer 132' to expose the surface of the substrate 100 in the low voltage device region 110'.

Then, referring to FIG. 2O, a thin low-voltage device gate oxide layer 112' is formed on the surface of the substrate 100 in the low-voltage device region 110', and then the protective layer PR4 in FIG. 2N is removed, wherein the low-voltage device The top surface 112t of the gate oxide layer 112' of the device, the top surface 122t of the gate oxide layer 122' of the medium voltage device and the top surface 132t of the gate oxide layer 132' of the high voltage device are substantially at the same level, and the low voltage device The thickness t1 of the gate oxide layer 112' is smaller than the thickness t2 of the gate oxide layer 122' of the medium voltage element, and the thickness t2 of the gate oxide layer 122' of the medium voltage element is smaller than the thickness t31 of the gate oxide layer 132' of the high voltage element, t32.

Next, referring to FIG. 2P , gate electrodes 114 , 124 , 134 a and 134 b are respectively formed on the gate oxide layer 112 ′ of the low voltage device, the gate oxide layer 122 ′ of the medium voltage device and the gate oxide layer 132 ′ of the high voltage device, so as to be on the substrate 100 A low voltage element 110, a medium voltage element 120, and a high voltage element 130 are formed. The gate formation method is, for example, a traditional polysilicon gate process or a gate post process. In the polysilicon gate process, for example, a polysilicon layer is first formed, and then a gate is formed in a region with a lower operating voltage (eg, the low-voltage device region 110') using a lithography etching technique. In the post-gate process, a polysilicon layer can be formed first, and a lithography etching technique is also used to form sacrificial sacrificial electrodes at the locations where the metal gates are to be formed (eg, in the high-voltage device region 130' and/or the medium-voltage device region 120'). The gate is then activated by high temperature doping of the source and drain (not shown), and then an insulating layer is covered on the sacrificial gate, and the insulating layer is planarized until the top surface of the sacrificial gate is exposed, and then the exposed The sacrificial gate is removed and replaced with a metal gate. However, the present invention is not limited thereto. The gate 114 of the low voltage element 110 of the present invention may be a metal gate, the gate 124 of the medium voltage element 120 may be a metal gate or a polysilicon gate, and the gates 134a and 134b of the high voltage element 130 may be Each is independently a metal gate electrode or a polysilicon gate electrode, and the aforementioned gate electrode material can be selected according to the thickness of the gate oxide layer.

To sum up, the semiconductor device and the manufacturing method thereof of the present invention can integrate at least one low voltage element, one medium voltage element and two or more high voltage elements on the substrate, since the top surfaces of the gate oxide layers of the plurality of voltage elements are on the same Therefore, the height of the gate of the high-voltage device is not affected by the post-gate process, which can improve the stability of the subsequent semiconductor device, and can provide a more flexible gate material by adjusting the thickness of the gate oxide layer. s Choice.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Semiconductor device 100: base 102: Component isolation structure 104: Pad oxide layer 105: coating layer 105a, 105b, 105c, O1, O2, O3: opening 106: Curtain layer 106p: Patterned Overlay 108: Sacrificial oxide layer 110: Low Voltage Components 110': low voltage component area 112: first gate oxide layer 112': gate oxide layer of low voltage components 112t, 122t, 132t: top surface 114, 124, 134, 134a, 134b: gate 120: Medium voltage components 120': medium voltage component area 122: The second gate oxide layer 122': gate oxide layer of medium voltage components 130: High Voltage Components 130': High voltage component area 130a': The first high-voltage component area 130b': The second high voltage element area 130a: first high voltage element 130b: Second high voltage element 132, 132a, 132b: the third gate oxide layer 132': gate oxide layer of high voltage components h1: first depth h2: second depth h3: the third depth PR1: first patterned photoresist layer PR2: Second patterned photoresist layer PR3: Third patterned photoresist layer PR4: Protective Layer t1, t2, t31, t32: Thickness

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2P are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention.

10: Semiconductor device

100: base

102: Component isolation structure

110: Low Voltage Components

120: Medium voltage components

130: High Voltage Components

130a: first high voltage element

130b: Second high voltage element

112: first gate oxide layer

122: The second gate oxide layer

132, 132a, 132b: the third gate oxide layer

114, 124, 134, 134a, 134b: gate

t1, t2, t31, t32: Thickness

Claims (14)

A semiconductor device, comprising: a base; a low-voltage device including a first gate oxide layer in the substrate; a medium voltage device including a second gate oxide layer in the substrate; and a plurality of high-voltage components, each of the high-voltage components includes a third gate oxide layer located in the substrate, wherein the top surface of the first gate oxide layer, the top surface of the second gate oxide layer and the top surface of the third gate oxide layer are at the same level, and The thickness of the first gate oxide layer is smaller than the thickness of the second gate oxide layer, and the thickness of the second gate oxide layer is smaller than the thickness of the third gate oxide layer. The semiconductor device of claim 1, wherein the low-voltage element includes a metal gate formed on the first gate oxide layer. The semiconductor device of claim 1, wherein the medium voltage element comprises a metal gate or a polysilicon gate formed on the second gate oxide layer. The semiconductor device of claim 1, wherein the high voltage element comprises a metal gate or a polysilicon gate formed on the second gate oxide layer. The semiconductor device of claim 1, wherein different third gate oxide layers in the plurality of high-voltage elements have different thicknesses, respectively. The semiconductor device of claim 1, further comprising a plurality of element isolation structures located in the substrate for separating the low voltage element, the medium voltage element and the plurality of high voltage elements. A method of manufacturing a semiconductor device, comprising: forming a plurality of device isolation structures in a substrate to define a low voltage device region, a medium voltage device region and a plurality of high voltage device regions; forming a patterned mask on the substrate, having a first opening exposing the surface of the substrate in one of the plurality of high voltage element regions; using the patterned mask as an etching mask, removing the substrate in the first opening to a first depth; forming a coating layer in the first opening; Repeat steps a to c below: a. forming an nth opening in the patterned mask to expose the surface of the substrate of the nth one of the plurality of high-voltage element regions, where n is a positive integer greater than 1; b. using the patterned mask as an etching mask, removing the substrate in the nth opening to an nth depth; c. forming the coating layer in the nth opening; removing the coating layer; forming a gate oxide layer of a high voltage element on the substrate to fill the first opening and the nth opening; Using the patterned mask as a stop layer, planarizing the gate oxide layer of the high-voltage device; forming a (n+1)th opening in the patterned mask, exposing the surface of the substrate in the medium voltage element region; using the patterned mask as an etching mask, removing the substrate in the (n+1)th opening to a (n+1)th depth; removing the patterned mask; forming an intermediate voltage device gate oxide layer in the (n+1)th opening; A protective layer is formed on the surface of the gate oxide layer of the medium voltage element, and the surface of the substrate in the low voltage element region is exposed; and A low-voltage device gate oxide layer is formed on the surface of the substrate in the low-voltage device region, so that the top surface of the low-voltage device gate oxide layer, the top surface of the medium-voltage device gate oxide layer, and the high-voltage device gate oxide layer are formed. The top surface is at the same level. The method for manufacturing a semiconductor device according to claim 7, wherein the step of forming the patterned mask comprises: forming a pad oxide layer on the surface of the substrate; forming a mask layer on the pad oxide layer; and The mask layer is patterned to form the patterned mask having the first opening. The method for manufacturing a semiconductor device according to claim 8, wherein after forming the protective layer, the method further comprises: removing the remaining pad oxide layer by a wet process. The method of manufacturing a semiconductor device according to claim 7, wherein the first depth is different from the nth depth. The method for manufacturing a semiconductor device as claimed in claim 7, before removing the patterned mask, further comprising: A sacrificial oxide layer is formed on the surface of the substrate in the medium voltage device region to improve the interface of the substrate; and The sacrificial oxide layer and a portion of the substrate below it are removed by a wet process. The method of manufacturing a semiconductor device according to claim 7, wherein the protective layer includes a photoresist layer. The method for manufacturing a semiconductor device according to claim 7, wherein the method for forming the gate oxide layer of the high voltage element comprises: forming a thermal oxide layer on the surface of the substrate by thermal oxidation; and A chemical vapor deposition oxide layer is formed on the thermal oxide layer. The method of manufacturing a semiconductor device according to claim 7, wherein the method of forming the gate oxide layer of the medium voltage element includes an in situ vapor generation (ISSG) method or a dry oxidation method.

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