TW202218307A - Power supplying apparatus - Google Patents

Power supplying apparatus Download PDF

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TW202218307A
TW202218307A TW110104974A TW110104974A TW202218307A TW 202218307 A TW202218307 A TW 202218307A TW 110104974 A TW110104974 A TW 110104974A TW 110104974 A TW110104974 A TW 110104974A TW 202218307 A TW202218307 A TW 202218307A
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power supply
voltage
power
voltage level
type transistor
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TW110104974A
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Chinese (zh)
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TWI744190B (en
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周娛
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啓碁科技股份有限公司
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1203—Circuits independent of the type of conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/10—Current supply arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A power supplying apparatus is provided. The power supplying apparatus includes a power-supplying chip and a power supplying control circuit. The power supplying chip is configured to convert an input voltage to a first voltage, and generates an indication signal and a sensing voltage, wherein the indication signal indicates a connection status and a power supplying status of a powered device connected to the power supplying apparatus. The power supplying circuit includes: a current limiter, configured to generate a first reset signal in response to a comparison result of the sensing voltage and a threshold voltage; a logic circuit, configured to generate a control signal in response to the indication signal and the input voltage; and a switch circuit, configured to determine whether to provide the first voltage to the current limiter according to the control signal. In response to the first reset signal being in a first logic state, the power supplying chip turns off power to the powered device.

Description

電源供應裝置power supply device

本發明之實施例係有關於電源控制，特別是有關於一種電源供應裝置。Embodiments of the present invention relate to power control, and more particularly, to a power supply device.

對於具備電源供應設備(Power supplying equipment，PSE)功能的網路設備，因為輸入功率有限，所以需要控制對所連接之受電裝置(powered device)的輸出功率。For a network device with a power supplying equipment (PSE) function, since the input power is limited, it is necessary to control the output power to the connected powered device.

然而，當有受電裝置連接至傳統的網路設備時，傳統的網路設備容易受到連接時所產生的衝擊電流的影響而導致供電功能誤操作。However, when a power receiving device is connected to the conventional network equipment, the conventional network equipment is easily affected by the inrush current generated during the connection, which leads to the malfunction of the power supply function.

有鑑於此，本發明係提出一種電源供應裝置以解決上述問題。In view of this, the present invention proposes a power supply device to solve the above problems.

本發明係提供一種電源供應裝置，該電源供應裝置包括一供電晶片及一供電控制電路。供電晶片用以將一輸入電壓轉換為一第一電壓，並且產生一指示信號及一感測電壓，其中該指示信號係表示該電源供應裝置的一受電裝置之連接狀態。供電控制電路包括：一限流電路，用以因應於該感測電壓與一閾值電壓之比較結果以產生一第一重置信號；一邏輯電路，用以依據該指示信號及該輸入電壓以產生一控制信號；以及一開關電路，用以依據該控制信號以決定是否提供該第一電壓至該限流電路。因應於該第一重置信號處於一第一邏輯狀態，該供電晶片係關閉提供至該受電裝置之電源。The present invention provides a power supply device, which includes a power supply chip and a power supply control circuit. The power supply chip is used for converting an input voltage into a first voltage, and generating an indication signal and a sensing voltage, wherein the indication signal represents the connection state of a power receiving device of the power supply device. The power supply control circuit includes: a current limiting circuit for generating a first reset signal in response to the comparison result between the sensing voltage and a threshold voltage; a logic circuit for generating according to the indication signal and the input voltage a control signal; and a switch circuit for determining whether to provide the first voltage to the current limiting circuit according to the control signal. In response to the first reset signal being in a first logic state, the power supply chip turns off the power supplied to the power receiving device.

以下說明係為完成發明的較佳實現方式，其目的在於描述本發明的基本精神，但並不用以限定本發明。實際的發明內容必須參考之後的權利要求範圍。The following descriptions are preferred implementations for completing the invention, and are intended to describe the basic spirit of the invention, but are not intended to limit the invention. Reference must be made to the scope of the following claims for the actual inventive content.

必須了解的是，使用於本說明書中的"包含"、"包括"等詞，係用以表示存在特定的技術特徵、數值、方法步驟、作業處理、元件以及/或組件，但並不排除可加上更多的技術特徵、數值、方法步驟、作業處理、元件、組件，或以上的任意組合。It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, elements and/or components, but do not exclude the possibility of Plus more technical features, values, method steps, job processes, elements, components, or any combination of the above.

於權利要求中使用如"第一"、"第二"、"第三"等詞係用來修飾權利要求中的元件，並非用來表示之間具有優先權順序，先行關係，或者是一個元件先於另一個元件，或者是執行方法步驟時的時間先後順序，僅用來區別具有相同名字的元件。The use of words such as "first", "second", "third", etc. in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority order, an antecedent relationship between them, or an element Prior to another element, or chronological order in which method steps are performed, is only used to distinguish elements with the same name.

第1圖係顯示依據本發明一實施例中之電源供應裝置的示意圖。FIG. 1 is a schematic diagram of a power supply device according to an embodiment of the present invention.

電源供應裝置10例如為一無線存取點(access point，AP)裝置，且亦為乙太網路供電(Power over Ethernet，PoE)裝置。電源供應裝置10包括：處理器110、供電晶片120、供電控制電路130、一電源輸入埠150及一電源輸出埠160。The power supply device 10 is, for example, a wireless access point (AP) device, and is also a Power over Ethernet (PoE) device. The power supply device 10 includes a processor 110 , a power supply chip 120 , a power supply control circuit 130 , a power input port 150 and a power output port 160 .

電源輸入埠150係用以接收來自一電源的直流電壓(例如為48伏特之電壓)或是來自電源供應端(未繪示)經由乙太網路供電(PoE)之直流電壓。電源輸出埠160係用以讓一受電裝置(powered device，PD)20連接至電源供應裝置10。電源供應裝置10中之供電晶片120係用以將來自電源輸入埠150的直流電壓轉換為輸出電壓，並經由纜線161(例如為RJ45纜線)透過乙太網路對受電裝置20進行供電。處理器110係用以控制通信裝置10之運作，並且可控制供電晶片120提供或關閉輸出電壓至電源輸出埠160。The power input port 150 is used to receive a DC voltage (eg, a voltage of 48 volts) from a power source or a DC voltage from a power supply terminal (not shown) via Power over Ethernet (PoE). The power output port 160 is used for connecting a powered device (PD) 20 to the power supply device 10 . The power supply chip 120 in the power supply device 10 is used to convert the DC voltage from the power input port 150 into an output voltage, and supply power to the power receiving device 20 through the cable 161 (eg, RJ45 cable) through the Ethernet. The processor 110 is used to control the operation of the communication device 10 , and can control the power supply chip 120 to provide or turn off the output voltage to the power output port 160 .

供電控制電路130係用以控制供電晶片120之輸出功率，且可避免讓供電晶片120因為受電裝置20剛連接至電源供應裝置10時所產生的衝擊電流而關閉輸出。此外，供電控制電路130所產生的重置信號RESET(例如為第一重置信號)及處理器110所產生的重置信號CPU_RST互不干擾，其中處理器110所產生的重置信號CPU_RST可經由光耦合器112以產生重置信號RESET(例如為第二重置信號)，第一重置信號或第二重置信號均可使供電晶片120關閉提供至受電裝置20的電源。在一些實施例中，第一重置信號及第二重置信號係輸入至一邏輯或(OR)閘以產生重置信號RESET。光耦合器(light coupler)111及112係設置於在處理器110及供電晶片120之間，用以隔離電磁干擾及電壓暫態。The power supply control circuit 130 is used to control the output power of the power supply chip 120 , and can prevent the power supply chip 120 from turning off the output due to the inrush current generated when the power receiving device 20 is just connected to the power supply device 10 . In addition, the reset signal RESET (eg, the first reset signal) generated by the power supply control circuit 130 and the reset signal CPU_RST generated by the processor 110 do not interfere with each other, wherein the reset signal CPU_RST generated by the processor 110 can be generated via The optocoupler 112 generates a reset signal RESET (eg, a second reset signal). Either the first reset signal or the second reset signal can cause the power supply chip 120 to turn off the power provided to the power receiving device 20 . In some embodiments, the first reset signal and the second reset signal are input to a logic OR (OR) gate to generate the reset signal RESET. Light couplers 111 and 112 are disposed between the processor 110 and the power supply chip 120 to isolate electromagnetic interference and voltage transients.

供電控制電路130包括邏輯電路131、開關電路132及限流電路133。邏輯電路131係用以控制開關電路132，且開關電路132係依據邏輯電路131之控制信號以決定是否要供電至限流電路133。限流電路133係將來自供電晶片120之感測電壓VSENSE與一閾值電壓VSET進行比較，並依據比較結果以決定重置信號RESET之邏輯位準，且供電晶片120係依據重置信號RESET以決定是否關閉提供至受電裝置20之電源。The power supply control circuit 130 includes a logic circuit 131 , a switch circuit 132 and a current limiting circuit 133 . The logic circuit 131 is used to control the switch circuit 132 , and the switch circuit 132 determines whether to supply power to the current limiting circuit 133 according to the control signal of the logic circuit 131 . The current limiting circuit 133 compares the sensing voltage VSENSE from the power supply chip 120 with a threshold voltage VSET, and determines the logic level of the reset signal RESET according to the comparison result, and the power supply chip 120 determines according to the reset signal RESET Whether to turn off the power supplied to the power receiving device 20 .

第2圖為依據本發明一實施例中之供電晶片之輸入信號及輸出信號的示意圖。請同時參考第1圖及第2圖。FIG. 2 is a schematic diagram of input signals and output signals of a power supply chip according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 at the same time.

如第2圖所示，供電晶片120之輸入信號包括輸入電壓Vin及重置信號RESET，其中輸入電壓Vin係來自電源接收埠150並傳送至供電晶片120之V_MAIN腳位，且重置信號RESET可來自供電控制電路130的第一重置信號或是由處理器110所輸出的CPU重置信號CPU_RST經過光耦合器112所產生的第二重置信號。為了便於說明，輸入電壓Vin亦可視為電壓V_MAIN。此外，供電晶片120更包括電壓轉換電路(未繪示)用以將輸入電壓Vin轉換為電壓VAUX3P3及感測電壓VSENSE。此外，供電晶片120更可依據受電裝置20之連接狀態及供電狀態以產生指示信號LED0。供電晶片120並依據受電裝置20之負載情況(例如可串接一或多個受電裝置20)以產生相應的感測電壓VSENSE。當受電裝置20負載愈高，則感測電壓VSENSE則愈高。當受電裝置20負載愈低，則感測電壓VSENSE則愈低。供電晶片120需優先保證可提供電源至電源供應裝置10之內部元件，當負載過高時，則需依據重置信號RESET以關閉提供至受電裝置20的電源。As shown in FIG. 2, the input signal of the power supply chip 120 includes the input voltage Vin and the reset signal RESET, wherein the input voltage Vin is sent from the power receiving port 150 to the V_MAIN pin of the power supply chip 120, and the reset signal RESET can be The first reset signal from the power supply control circuit 130 or the second reset signal generated by the CPU_RST output from the processor 110 via the optical coupler 112 . For the convenience of description, the input voltage Vin can also be regarded as the voltage V_MAIN. In addition, the power supply chip 120 further includes a voltage conversion circuit (not shown) for converting the input voltage Vin into the voltage VAUX3P3 and the sensing voltage VSENSE. In addition, the power supply chip 120 can further generate the indication signal LED0 according to the connection state and the power supply state of the power receiving device 20 . The power supply chip 120 generates the corresponding sensing voltage VSENSE according to the load condition of the power receiving device 20 (for example, one or more power receiving devices 20 can be connected in series). When the load of the power receiving device 20 is higher, the sensing voltage VSENSE is higher. When the load of the power receiving device 20 is lower, the sensing voltage VSENSE is lower. The power supply chip 120 needs to ensure that the power supply chip 120 can provide power to the internal components of the power supply device 10 first, and when the load is too high, the power supply to the power receiving device 20 needs to be turned off according to the reset signal RESET.

舉例來説，電壓VAUX3P3(例如為3.3伏特)係提供至供電控制電路130，且供電晶片120之操作電流ICC係限定在1mA以下。此外，光耦合器111及112的操作電流約為5mA，故供電晶片120所產生的電壓VAUX3P3並不足以驅動光耦合器111，且會導致光耦合器111無法正常操作。在此實施例中，光耦合器111係由電壓V_MAIN所驅動，且光耦合器112係由處理器110所產生的重置信號CPU_RST所驅動。舉例來説，處理器110係依據供電判斷信號PSE_DET來判斷受電裝置20是否已連接至電源供應裝置10且已正常供電。當供電判斷信號PSE_DET為低邏輯狀態，表示受電裝置20已連接至電源供應裝置10且已正常供電，在此情況下，處理器110可依據軟體之設定條件以輸出重置信號CPU_RST來控制供電晶片120是否輸出電源至受電裝置20。光耦合器112之二極體的陽極及陰極係分別連接至處理器110及接地，光耦合器112之光電晶體之射極係連接至電壓源VSS(例如為接地=0V)，且光耦合器112之光電晶體之集極係輸出第二重置信號至供電晶片120。For example, the voltage VAUX3P3 (eg, 3.3 volts) is provided to the power supply control circuit 130, and the operating current ICC of the power supply chip 120 is limited to be less than 1 mA. In addition, the operating current of the optocouplers 111 and 112 is about 5 mA, so the voltage VAUX3P3 generated by the power supply chip 120 is not enough to drive the optocoupler 111 , and the optocoupler 111 cannot operate normally. In this embodiment, the optocoupler 111 is driven by the voltage V_MAIN, and the optocoupler 112 is driven by the reset signal CPU_RST generated by the processor 110 . For example, the processor 110 determines whether the power receiving device 20 has been connected to the power supply device 10 and has been powered normally according to the power supply determination signal PSE_DET. When the power supply determination signal PSE_DET is in a low logic state, it means that the power receiving device 20 has been connected to the power supply device 10 and has supplied power normally. In this case, the processor 110 can output the reset signal CPU_RST to control the power supply chip according to the setting conditions of the software 120 Whether to output power to the power receiving device 20 . The anode and cathode of the diode of the optocoupler 112 are connected to the processor 110 and ground, respectively, the emitter of the phototransistor of the optocoupler 112 is connected to a voltage source VSS (eg, ground=0V), and the optocoupler 112 is connected to a voltage source VSS (eg, ground=0V) The collector of the phototransistor of 112 outputs the second reset signal to the power supply chip 120 .

在一實施例中，當電源供應裝置10啟動後，供電晶片120會偵測電壓輸出埠160之連接狀態，例如受電裝置20是否連接至電壓輸出埠160。當供電晶片120判斷受電裝置20未連接至電源供應裝置10或是判斷受電裝置20已連接至電源供應裝置10且供電晶片120檢測通過但尚未供電至受電裝置20時，供電晶片120所產生的指示信號LED0係處於高電壓位準(或稱為高邏輯狀態)。當供電晶片120判斷受電裝置20已連接至電源供應裝置10且已正常供電至受電裝置20，供電晶片120所產生的指示信號LED0係處於低電壓位準(或稱為低邏輯狀態)。In one embodiment, after the power supply device 10 is activated, the power supply chip 120 detects the connection status of the voltage output port 160 , such as whether the power receiving device 20 is connected to the voltage output port 160 . When the power supply chip 120 determines that the power receiving device 20 is not connected to the power supply device 10 or that the power receiving device 20 is connected to the power supply device 10 and the power supply chip 120 has passed the detection but has not yet supplied power to the power receiving device 20, the indication generated by the power supply chip 120 Signal LED0 is at a high voltage level (or high logic state). When the power supply chip 120 determines that the power receiving device 20 is connected to the power supply device 10 and supplies power to the power receiving device 20 normally, the indication signal LED0 generated by the power supply chip 120 is at a low voltage level (or referred to as a low logic state).

指示信號LED0會再經過光耦合器111以輸出供電判斷信號PSE_DET。當供電判斷信號PSE_DET為高電壓位準，則處理器110可得知受電裝置20尚未連接或是已連接但尚未供電。當供電判斷信號PSE_DET為低電壓位準，則處理器110可得知受電裝置20已連接且已正常供電。The indicator signal LED0 will then pass through the optocoupler 111 to output the power supply determination signal PSE_DET. When the power supply determination signal PSE_DET is at a high voltage level, the processor 110 can know that the power receiving device 20 is not connected or is connected but not powered. When the power supply determination signal PSE_DET is at a low voltage level, the processor 110 can know that the power receiving device 20 is connected and has been powered normally.

第3A～3D圖為依據本發明不同實施例中之供電控制電路的電路圖。請同時參考第1圖及第3A～3D圖。FIGS. 3A to 3D are circuit diagrams of power supply control circuits according to different embodiments of the present invention. Please also refer to Figure 1 and Figures 3A to 3D.

如第3A圖所示，邏輯電路131係包括電晶體Q2及Q3，其中電晶體Q2為NPN雙極性接面電晶體(bipolar junction transistor，BJT)，且電晶體Q3為PNP雙極性接面電晶體。電晶體Q3之射極(emitter)係連接至節點N5，且供電晶片120所輸出的電壓V_MAIN係提供至節點N5。電晶體Q3之基極(base)係透過電阻R7而連接至節點N6，且供電晶片120所輸出的指示信號LED0係提供至節點N6。電晶體Q3之集極(collector)係透過電阻R6而連接至節點N4，其中節點N4連接至電晶體Q2之基極，且節點N4係透過電阻R5而連接至電壓源VSS(例如為接地＝0V)。電晶體Q2之射極係連接至電壓源VSS，且電晶體Q2之集極係連接至電晶體Q1之閘極(gate)，並且透過電阻R4以連接至節點N2，其中供電晶片120所產生之電壓VAUX3P3係提供至節點N2。As shown in FIG. 3A, the logic circuit 131 includes transistors Q2 and Q3, wherein the transistor Q2 is an NPN bipolar junction transistor (BJT), and the transistor Q3 is a PNP bipolar junction transistor . The emitter of the transistor Q3 is connected to the node N5, and the voltage V_MAIN output by the power supply chip 120 is provided to the node N5. The base of the transistor Q3 is connected to the node N6 through the resistor R7, and the indication signal LED0 output by the power supply chip 120 is provided to the node N6. The collector of transistor Q3 is connected to node N4 through resistor R6, wherein node N4 is connected to the base of transistor Q2, and node N4 is connected to voltage source VSS (eg ground=0V) through resistor R5 ). The emitter of the transistor Q2 is connected to the voltage source VSS, and the collector of the transistor Q2 is connected to the gate of the transistor Q1, and is connected to the node N2 through the resistor R4, wherein the voltage generated by the power chip 120 is connected. Voltage VAUX3P3 is provided to node N2.

開關電路132例如可用電晶體Q1所實現，其中電晶體Q1為P型場效電晶體。電晶體Q1之源極係連接至節點N2，且供電晶片120所產生之電壓VAUX3P3係提供至節點N2。電晶體Q1之汲極係連接至節點N1，其中節點N1為比較電路134之電壓輸入端V+。限流電路133包括比較電路134及電阻R1～R3，其中電阻R1及R2係構成一分壓電路，並且產生一閾值電壓VSET。The switch circuit 132 can be implemented by, for example, a transistor Q1, wherein the transistor Q1 is a P-type field effect transistor. The source of the transistor Q1 is connected to the node N2, and the voltage VAUX3P3 generated by the power supply chip 120 is supplied to the node N2. The drain of the transistor Q1 is connected to the node N1 , where the node N1 is the voltage input terminal V+ of the comparison circuit 134 . The current limiting circuit 133 includes a comparison circuit 134 and resistors R1-R3, wherein the resistors R1 and R2 form a voltage divider circuit and generate a threshold voltage VSET.

在第一情境中，若供電晶片120為低位有效重置(low active reset)之設計，則閾值電壓VSET係連接至比較電路134之正輸入端+IN，且供電晶片120所產生之感測電壓VSENSE係連接至比較電路134之負輸入端－IN。當供電晶片120提供至受電裝置20的輸出電流未超過預定值時，感測電壓VSENSE＜電壓VSET，故比較電路134所輸出的重置信號RESET為高電壓位準。此時，供電晶片120不會關閉受電裝置20之電源，並繼續提供電源至受電裝置。當供電晶片120提供至受電裝置20的輸出電流大於或等於預定值時，感測電壓VSENSE＞=電壓VSET，故比較電路134所輸出的重置信號RESET為低電壓位準。此時，供電晶片120係關閉受電裝置20之電源。In the first situation, if the power supply chip 120 is designed for low active reset, the threshold voltage VSET is connected to the positive input terminal +IN of the comparison circuit 134, and the sensing voltage generated by the power supply chip 120 VSENSE is connected to the negative input terminal -IN of the comparison circuit 134 . When the output current provided by the power supply chip 120 to the power receiving device 20 does not exceed the predetermined value, the sensing voltage VSENSE<voltage VSET, so the reset signal RESET output by the comparison circuit 134 is at a high voltage level. At this time, the power supply chip 120 does not turn off the power of the power receiving device 20 and continues to provide power to the power receiving device. When the output current provided by the power supply chip 120 to the power receiving device 20 is greater than or equal to the predetermined value, the sensing voltage VSENSE>=the voltage VSET, so the reset signal RESET output by the comparison circuit 134 is at a low voltage level. At this time, the power supply chip 120 turns off the power of the power receiving device 20 .

在第二情境中，若供電晶片120為高位有效重置(high active reset)之設計，則閾值電壓VSET係連接至比較電路134之負輸入端-IN，且供電晶片120所產生之感測電壓VSENSE係連接至比較電路134之正輸入端+IN。當供電晶片120提供至受電裝置20的輸出電流未超過預定值時，感測電壓VSENSE＜電壓VSET，故比較電路134所輸出的重置信號RESET為低電壓位準。此時，供電晶片120不會關閉受電裝置20之電源，並繼續提供電源至受電裝置。當供電晶片120提供至受電裝置20的輸出電流大於或等於預定值時，感測電壓VSENSE＞=電壓VSET，故比較電路134所輸出的重置信號RESET為高電壓位準。此時，供電晶片120係關閉受電裝置20之電源。In the second situation, if the power supply chip 120 is designed for high active reset, the threshold voltage VSET is connected to the negative input terminal -IN of the comparison circuit 134, and the sensing voltage generated by the power supply chip 120 VSENSE is connected to the positive input terminal +IN of the comparison circuit 134 . When the output current provided by the power supply chip 120 to the power receiving device 20 does not exceed a predetermined value, the sensing voltage VSENSE<voltage VSET, so the reset signal RESET output by the comparison circuit 134 is at a low voltage level. At this time, the power supply chip 120 does not turn off the power of the power receiving device 20 and continues to provide power to the power receiving device. When the output current provided by the power supply chip 120 to the power receiving device 20 is greater than or equal to a predetermined value, the sensing voltage VSENSE>=the voltage VSET, so the reset signal RESET output by the comparison circuit 134 is at a high voltage level. At this time, the power supply chip 120 turns off the power of the power receiving device 20 .

在一些實施例中，在第二情境之限流電路130中之元件的連接方式係類似於第一情境，但在限流電路130之輸出端可設置一反向器(inverter)以改變重置信號RESET之邏輯狀態。為了便於說明，在後述實施例中係使用第一情境為例。此外，指示信號LED0在高電壓位準時的電壓係等於電壓V_MAIN。In some embodiments, the connection of the components in the current limiting circuit 130 in the second scenario is similar to that in the first scenario, but an inverter can be set at the output end of the current limiting circuit 130 to change the reset The logic state of signal RESET. For the convenience of description, the first scenario is used as an example in the following embodiments. In addition, the voltage of the indication signal LED0 at the high voltage level is equal to the voltage V_MAIN.

如第3A圖所示，當供電晶片120判斷受電裝置20未連接至電源供應裝置10或是判斷受電裝置20已連接至電源供應裝置10且供電晶片120檢測通過但尚未供電至受電裝置20時，供電晶片120所產生的指示信號LED0係處於高電壓位準。此時，因為電晶體Q3之射極及基極均為高電壓位準，故電晶體Q3不導通。因此，電晶體Q2之基極及射極均處於電壓源VSS(例如為接地=0V)之低電壓位準，故電晶體Q2不導通。此外，Q1電晶體之閘極及源極此時係處於高電壓位準，故電晶體Q1不導通，且此時比較電路134之電壓輸入端V+會接地，故比較電路134不工作。因為電晶體Q3之射極及基極均為高電壓位準，故光耦合器111之二極體不導通，此時，供電判斷信號PSE_DET會被拉昇(pull high)至高電壓位準，故處理器110可得知受電裝置20尚未連接或是已連接但尚未供電。As shown in FIG. 3A , when the power supply chip 120 determines that the power receiving device 20 is not connected to the power supply device 10 or determines that the power receiving device 20 is connected to the power supply device 10 and the power supply chip 120 passes the test but has not yet supplied power to the power receiving device 20 , The indication signal LED0 generated by the power supply chip 120 is at a high voltage level. At this time, since the emitter and base of the transistor Q3 are both at high voltage levels, the transistor Q3 is not turned on. Therefore, both the base and the emitter of the transistor Q2 are at the low voltage level of the voltage source VSS (eg, ground=0V), so the transistor Q2 is not turned on. In addition, the gate and source of the transistor Q1 are at high voltage level at this time, so the transistor Q1 is not conducting, and the voltage input terminal V+ of the comparison circuit 134 is grounded at this time, so the comparison circuit 134 does not work. Because the emitter and base of the transistor Q3 are both at high voltage levels, the diodes of the optocoupler 111 are not turned on. At this time, the power supply determination signal PSE_DET will be pulled high to a high voltage level, so The processor 110 can know that the powered device 20 is not yet connected or is connected but not powered.

當供電晶片120判斷受電裝置20已連接至電源供應裝置10且已正常供電至受電裝置20，供電晶片120所產生的指示信號LED0係處於低電壓位準。此時，因為電晶體Q3之射極為高電壓位準且其基極為低電壓位準，故電晶體Q3導通。因此，電晶體Q2之基極電壓為高電壓位準且其射極電壓為低電壓位準，故電晶體Q2導通。此外，Q1電晶體之閘極係處於低電壓位準且其源極電壓係處於高電壓位準，故電晶體Q1導通，且此時電壓VAUX3P3係提供至比較電路134之電壓輸入端V+，故比較電路134正常工作。因為電壓V_MAIN為高電壓位準且指示信號LED0為低電壓位準，故光耦合器111之二極體導通，此時，供電判斷信號PSE_DET為低電壓位準，故處理器110可得知受電裝置20已連接且正常供電。When the power supply chip 120 determines that the power receiving device 20 has been connected to the power supply device 10 and has supplied power to the power receiving device 20 normally, the indication signal LED0 generated by the power supply chip 120 is at a low voltage level. At this time, since the emitter of the transistor Q3 is at a high voltage level and its base is at a low voltage level, the transistor Q3 is turned on. Therefore, the base voltage of the transistor Q2 is at a high voltage level and its emitter voltage is at a low voltage level, so the transistor Q2 is turned on. In addition, the gate of the transistor Q1 is at a low voltage level and its source voltage is at a high voltage level, so the transistor Q1 is turned on, and the voltage VAUX3P3 is supplied to the voltage input terminal V+ of the comparison circuit 134 at this time, so The comparison circuit 134 operates normally. Since the voltage V_MAIN is at a high voltage level and the indication signal LED0 is at a low voltage level, the diode of the optocoupler 111 is turned on. At this time, the power supply determination signal PSE_DET is at a low voltage level, so the processor 110 can know that the power is received Device 20 is connected and powered normally.

請參考第3B圖，第3B圖中之限流電路130係類似於第3A圖，但是第3B圖中之邏輯電路131的電晶體Q2及Q3係分別用N型場效電晶體及P型場效電晶體所實現。電晶體Q3之源極係連接至節點N5，且供電晶片120所輸出的電壓V_MAIN係提供至節點N5。電晶體Q3之閘極係透過電阻R7而連接至節點N6，且供電晶片120所輸出的指示信號LED0係提供至節點N6。電晶體Q3之汲極係透過電阻R6而連接至節點N4，其中節點N4連接至電晶體Q2之閘極，且節點N4係透過電阻R5而連接至電壓源VSS(例如為接地＝0V)。電晶體Q2之汲極係連接至電晶體Q1之閘極，並且透過電阻R4以連接至節點N2，其中供電晶片120所產生之電壓VAUX3P3係提供至節點N2。Please refer to FIG. 3B. The current limiting circuit 130 in FIG. 3B is similar to that in FIG. 3A, but the transistors Q2 and Q3 of the logic circuit 131 in FIG. 3B use N-type field effect transistors and P-type field effect transistors, respectively. realized by an efficient transistor. The source of the transistor Q3 is connected to the node N5, and the voltage V_MAIN output by the power supply chip 120 is provided to the node N5. The gate of the transistor Q3 is connected to the node N6 through the resistor R7, and the indicator signal LED0 output by the power supply chip 120 is provided to the node N6. The drain of transistor Q3 is connected to node N4 through resistor R6, wherein node N4 is connected to the gate of transistor Q2, and node N4 is connected to voltage source VSS (eg ground=0V) through resistor R5. The drain of the transistor Q2 is connected to the gate of the transistor Q1, and is connected to the node N2 through the resistor R4, wherein the voltage VAUX3P3 generated by the power supply chip 120 is provided to the node N2.

如第3B圖所示，當供電晶片120判斷受電裝置20未連接至電源供應裝置10或是判斷受電裝置20已連接至電源供應裝置10且供電晶片120檢測通過但尚未供電至受電裝置20時，供電晶片120所產生的指示信號LED0係處於高電壓位準。此時，因為電晶體Q3之閘極及源極均為高電壓位準，故電晶體Q3不導通。因此，電晶體Q2之閘極及源極均處於電壓源VSS(例如為接地=0V)之低電壓位準，故電晶體Q2不導通。此外，Q1電晶體之閘極及源極此時係處於高電壓位準，故電晶體Q1不導通，且此時比較電路134之電壓輸入端V+會接地，故比較電路134不工作。因為電晶體Q3之閘極及汲極均為高電壓位準，故光耦合器111之二極體不導通，且光耦合器111之光電晶體不導通，故供電判斷信號PSE_DET會被拉昇(pull high)為高電壓位準，因此處理器110可得知受電裝置20尚未連接或是已連接但尚未供電。As shown in FIG. 3B , when the power supply chip 120 determines that the power receiving device 20 is not connected to the power supply device 10 or that the power receiving device 20 is connected to the power supply device 10 and the power supply chip 120 passes the test but has not yet supplied power to the power receiving device 20 , The indication signal LED0 generated by the power supply chip 120 is at a high voltage level. At this time, since the gate electrode and the source electrode of the transistor Q3 are both at high voltage levels, the transistor Q3 is not turned on. Therefore, the gate electrode and the source electrode of the transistor Q2 are both at the low voltage level of the voltage source VSS (eg, ground=0V), so the transistor Q2 is not turned on. In addition, the gate and source of the transistor Q1 are at high voltage level at this time, so the transistor Q1 is not conducting, and the voltage input terminal V+ of the comparison circuit 134 is grounded at this time, so the comparison circuit 134 does not work. Because the gate and drain of the transistor Q3 are at high voltage levels, the diode of the optocoupler 111 is not conducting, and the phototransistor of the optocoupler 111 is not conducting, so the power supply judgment signal PSE_DET will be pulled up ( pull high) is a high voltage level, so the processor 110 can know that the powered device 20 is not yet connected or is connected but not powered.

當供電晶片120判斷受電裝置20已連接至電源供應裝置10且已正常供電至受電裝置20，供電晶片120所產生的指示信號LED0係處於低電壓位準。此時，因為電晶體Q3之源極為高電壓位準且其閘極為低電壓位準，故電晶體Q3導通。因此，電晶體Q2之閘極為高電壓位準且其源極電壓為低電壓位準，故電晶體Q2導通。此外，Q1電晶體之閘極係處於低電壓位準且其源極電壓係處於高電壓位準，故電晶體Q1導通，且此時比較電路134之電壓輸入端V+會連接至電壓VAUX3P3，故比較電路134正常工作。因為電壓V_MAIN為高電壓位準且指示信號LED0為低電壓位準，故光耦合器111之二極體導通，此時，光耦合器111之光電晶體會導通而使供電判斷信號PSE_DET接地並處於低電壓位準，故處理器110可得知受電裝置20已連接且正常供電。When the power supply chip 120 determines that the power receiving device 20 has been connected to the power supply device 10 and has supplied power to the power receiving device 20 normally, the indication signal LED0 generated by the power supply chip 120 is at a low voltage level. At this time, since the source of the transistor Q3 is at a high voltage level and its gate is at a low voltage level, the transistor Q3 is turned on. Therefore, the gate of the transistor Q2 is at a high voltage level and its source voltage is at a low voltage level, so the transistor Q2 is turned on. In addition, the gate of the transistor Q1 is at a low voltage level and its source voltage is at a high voltage level, so the transistor Q1 is turned on, and the voltage input terminal V+ of the comparison circuit 134 is connected to the voltage VAUX3P3 at this time, so The comparison circuit 134 operates normally. Since the voltage V_MAIN is at a high voltage level and the indication signal LED0 is at a low voltage level, the diode of the optocoupler 111 is turned on. At this time, the phototransistor of the optocoupler 111 is turned on, so that the power supply judgment signal PSE_DET is grounded and at Since the voltage level is low, the processor 110 can know that the power receiving device 20 is connected and powered normally.

請參考第3C圖，第3C圖中之限流電路130係類似於第3A圖，但是第3C圖中之邏輯電路131的電晶體Q2及Q3係被光耦合器135所取代。光耦合器135之二極體1351的陽極(anode)及陰極(cathode)係分別連接至節點N5及N6，且供電晶片120所輸出的電壓V_MAIN及指示信號LED0係分別提供至節點N5及N6。光耦合器135之光電晶體1352的集極及射極係分別連接至節點N3及電壓源VSS，其中節點N3係連接至電晶體Q1之閘極，並且透過電阻R4以連接至節點N2，其中供電晶片120所產生之電壓VAUX3P3係提供至節點N2。Please refer to FIG. 3C , the current limiting circuit 130 in FIG. 3C is similar to that in FIG. 3A , but the transistors Q2 and Q3 of the logic circuit 131 in FIG. 3C are replaced by the optocoupler 135 . The anode and cathode of the diode 1351 of the optocoupler 135 are connected to the nodes N5 and N6, respectively, and the voltage V_MAIN and the indication signal LED0 output by the power supply chip 120 are respectively provided to the nodes N5 and N6. The collector and emitter of the phototransistor 1352 of the optocoupler 135 are connected to the node N3 and the voltage source VSS, respectively, wherein the node N3 is connected to the gate of the transistor Q1, and is connected to the node N2 through the resistor R4, wherein the power supply The voltage VAUX3P3 generated by the chip 120 is provided to the node N2.

如第3C圖所示，當供電晶片120判斷受電裝置20未連接至電源供應裝置10或是判斷受電裝置20已連接至電源供應裝置10且供電晶片120檢測通過但尚未供電至受電裝置20時，供電晶片120所產生的指示信號LED0係處於高電壓位準。此時，因為光耦合器135之二極體1351之陽極及陰極均為高電壓位準，故光耦合器135之二極體1351不導通，且光耦合器135之光電晶體1352亦不導通。因此，節點N3係被拉昇至電壓VAUX3P3的高電壓位準。此外，電晶體Q1之閘極及源極此時係處於高電壓位準，故電晶體Q1不導通，且此時比較電路134之電壓輸入端V+會接地，故比較電路134不工作。因為節點N5及N6均為高電壓位準，故光耦合器111之二極體不導通，且光耦合器111之光電晶體亦不導通，故供電判斷信號PSE_DET會被後級電路(處理器110)拉昇(pull high)至高電壓位準，因此處理器110可得知受電裝置20尚未連接或是已連接但尚未供電。As shown in FIG. 3C , when the power supply chip 120 determines that the power receiving device 20 is not connected to the power supply device 10 or determines that the power receiving device 20 is connected to the power supply device 10 and the power supply chip 120 passes the test but has not yet supplied power to the power receiving device 20 , The indication signal LED0 generated by the power supply chip 120 is at a high voltage level. At this time, since both the anode and the cathode of the diode 1351 of the optocoupler 135 are at high voltage levels, the diode 1351 of the optocoupler 135 is non-conductive, and the phototransistor 1352 of the optocoupler 135 is also non-conductive. Therefore, the node N3 is pulled up to the high voltage level of the voltage VAUX3P3. In addition, the gate and source of the transistor Q1 are at a high voltage level at this time, so the transistor Q1 is not conducting, and the voltage input terminal V+ of the comparison circuit 134 is grounded at this time, so the comparison circuit 134 does not work. Because the nodes N5 and N6 are both at high voltage levels, the diode of the optocoupler 111 is non-conductive, and the phototransistor of the optocoupler 111 is also non-conductive, so the power supply judgment signal PSE_DET will be transmitted by the subsequent circuit (the processor 110 ). ) is pulled high to a high voltage level, so the processor 110 can know that the powered device 20 is not connected or is connected but not powered.

當供電晶片120判斷受電裝置20已連接至電源供應裝置10且已正常供電至受電裝置20，供電晶片120所產生的指示信號LED0係處於低電壓位準。此時，因為光耦合器135之二極體1351的陽極及陰極分別為高電壓位準及低電壓位準，故光耦合器135之二極體1351導通，且光耦合器135之光電晶體1352亦導通。因此，節點N3(即電晶體Q1之閘極)亦被拉低至電壓源VSS的低電壓位準。因為電晶體Q1之閘極係處於低電壓位準且其源極電壓係處於高電壓位準，故電晶體Q1導通，且此時比較電路134之電壓輸入端V+會連接至電壓VAUX3P3，故比較電路134正常工作。因為電壓V_MAIN為高電壓位準且指示信號LED0為低電壓位準，故光耦合器111之二極體導通，此時，光耦合器111之光電晶體會導通而使供電判斷信號PSE_DET接地並處於低電壓位準，故處理器110可得知受電裝置20已連接且正常供電。When the power supply chip 120 determines that the power receiving device 20 has been connected to the power supply device 10 and has supplied power to the power receiving device 20 normally, the indication signal LED0 generated by the power supply chip 120 is at a low voltage level. At this time, since the anode and cathode of the diode 1351 of the optocoupler 135 are at high voltage level and low voltage level, respectively, the diode 1351 of the optocoupler 135 is turned on, and the phototransistor 1352 of the optocoupler 135 is turned on. also on. Therefore, the node N3 (ie the gate of the transistor Q1) is also pulled down to the low voltage level of the voltage source VSS. Because the gate of the transistor Q1 is at a low voltage level and its source voltage is at a high voltage level, the transistor Q1 is turned on, and the voltage input terminal V+ of the comparison circuit 134 is connected to the voltage VAUX3P3 at this time, so the comparison Circuit 134 operates normally. Since the voltage V_MAIN is at a high voltage level and the indication signal LED0 is at a low voltage level, the diode of the optocoupler 111 is turned on. At this time, the phototransistor of the optocoupler 111 is turned on, so that the power supply judgment signal PSE_DET is grounded and at Since the voltage level is low, the processor 110 can know that the power receiving device 20 is connected and powered normally.

請參考第3D圖，第3D圖中之限流電路130係類似於第3A圖，但是第3D圖中之邏輯電路131的電晶體Q2及Q3係被電壓位準轉換(voltage level conversion)晶片136所取代，其中電壓位準轉換晶片136之左側及右側分別為低邏輯準位輸入端(例如低電壓輸入端(VCC[A]腳位)及低電壓資料端(A腳位))及高邏輯準位輸入端(高電壓輸入端(VCC[B]腳位)及高電壓資料端(B腳位))。舉例來説，電壓位準轉換晶片136之低電壓輸入端(VCC[A]腳位)及高電壓輸入端(VCC[B]腳位)例如分別連接至電壓VAUX3P3(節點N2)及電壓V_MAIN(節點N5)，其中電壓V_MAIN(例如可為48V、12V或5V)係高於電壓VAUX3P3(3.3V)。電壓位準轉換晶片136之低電壓資料端(A腳位)係連接至電晶體Q1之閘極，透過電阻R4以連接至節點N2，其中供電晶片120所產生之電壓VAUX3P3係提供至節點N2。電壓位準轉換晶片136之高電壓資料端(B腳位)係連接至指示信號LED0(節點N6)。此外，電壓位準轉換晶片136之GND腳位係連接至電壓源VSS，且DIR腳位係透過電阻R7接地，例如可用於控制電壓轉換方向為B腳位至A腳位。Please refer to FIG. 3D. The current limiting circuit 130 in FIG. 3D is similar to FIG. 3A, but the transistors Q2 and Q3 of the logic circuit 131 in FIG. 3D are converted by a voltage level conversion chip 136. Instead, the left and right sides of the voltage level conversion chip 136 are respectively a low logic level input terminal (eg, a low voltage input terminal (VCC[A] pin) and a low voltage data terminal (A pin)) and a high logic level. Level input terminal (high voltage input terminal (VCC[B] pin) and high voltage data terminal (B pin)). For example, the low voltage input terminal (VCC[A] pin) and the high voltage input terminal (VCC[B] pin) of the voltage level conversion chip 136 are respectively connected to the voltage VAUX3P3 (node N2 ) and the voltage V_MAIN ( node N5), where the voltage V_MAIN (for example, may be 48V, 12V or 5V) is higher than the voltage VAUX3P3 (3.3V). The low-voltage data terminal (pin A) of the voltage level conversion chip 136 is connected to the gate of the transistor Q1, and is connected to the node N2 through the resistor R4, wherein the voltage VAUX3P3 generated by the power supply chip 120 is provided to the node N2. The high voltage data terminal (B pin) of the voltage level conversion chip 136 is connected to the indication signal LED0 (node N6). In addition, the GND pin of the voltage level conversion chip 136 is connected to the voltage source VSS, and the DIR pin is grounded through the resistor R7, for example, it can be used to control the voltage conversion direction from the B pin to the A pin.

如第3D圖所示，當供電晶片120判斷受電裝置20未連接至電源供應裝置10或是判斷受電裝置20已連接至電源供應裝置10且供電晶片120檢測通過但尚未供電至受電裝置20時，供電晶片120所產生的指示信號LED0係處於高電壓位準。此時，電壓位準轉換晶片136係將高電壓資料端(B腳位)之第一高電壓位準(電壓V_MAIN)轉換為在低電壓資料端(A腳位)輸出的第二高電壓位準(例如電壓VAUX3P3)。因此，電晶體Q1之閘極及源極此時係處於高電壓位準，故電晶體Q1不導通，且此時比較電路134之電壓輸入端V+會接地，故比較電路134不工作。因為節點N5及N6均為高電壓位準，故光耦合器111之二極體不導通，且光耦合器111之光電晶體亦不導通，故供電判斷信號PSE_DET會被後級電路(處理器110)拉昇(pull high)至高電壓位準，因此處理器110可得知受電裝置20尚未連接或是已連接但尚未供電。As shown in FIG. 3D, when the power supply chip 120 determines that the power receiving device 20 is not connected to the power supply device 10 or determines that the power receiving device 20 is connected to the power supply device 10 and the power supply chip 120 passes the test but has not yet supplied power to the power receiving device 20, The indication signal LED0 generated by the power supply chip 120 is at a high voltage level. At this time, the voltage level conversion chip 136 converts the first high voltage level (voltage V_MAIN) of the high voltage data terminal (B pin) to the second high voltage level outputted at the low voltage data terminal (A pin). standard (eg voltage VAUX3P3). Therefore, the gate and source of the transistor Q1 are at a high voltage level at this time, so the transistor Q1 is not turned on, and the voltage input terminal V+ of the comparison circuit 134 is grounded at this time, so the comparison circuit 134 does not work. Because the nodes N5 and N6 are both at high voltage levels, the diode of the optocoupler 111 is non-conductive, and the phototransistor of the optocoupler 111 is also non-conductive, so the power supply judgment signal PSE_DET will be transmitted by the subsequent circuit (the processor 110 ). ) is pulled high to a high voltage level, so the processor 110 can know that the powered device 20 is not connected or is connected but not powered.

當供電晶片120判斷受電裝置20已連接至電源供應裝置10且已正常供電至受電裝置20，供電晶片120所產生的指示信號LED0係處於低電壓位準。此時，電壓位準轉換晶片136係將高電壓資料端(B腳位)之第一低電壓位準轉換為在低電壓資料端(A腳位)輸出的第二低電壓位準。因為電晶體Q1之閘極係處於低電壓位準且其源極電壓係處於高電壓位準，故電晶體Q1導通，且此時比較電路134之電壓輸入端V+會連接至電壓VAUX3P3，故比較電路134正常工作。因為電壓V_MAIN為高電壓位準且指示信號LED0為低電壓位準，故光耦合器111之二極體導通，此時，光耦合器111之光電晶體會導通而使供電判斷信號PSE_DET接地並處於低電壓位準，故處理器110可得知受電裝置20已連接且正常供電。When the power supply chip 120 determines that the power receiving device 20 has been connected to the power supply device 10 and has supplied power to the power receiving device 20 normally, the indication signal LED0 generated by the power supply chip 120 is at a low voltage level. At this time, the voltage level conversion chip 136 converts the first low voltage level of the high voltage data terminal (B pin) to the second low voltage level outputted at the low voltage data terminal (A pin). Because the gate of the transistor Q1 is at a low voltage level and its source voltage is at a high voltage level, the transistor Q1 is turned on, and the voltage input terminal V+ of the comparison circuit 134 is connected to the voltage VAUX3P3 at this time, so the comparison Circuit 134 operates normally. Since the voltage V_MAIN is at a high voltage level and the indication signal LED0 is at a low voltage level, the diode of the optocoupler 111 is turned on. At this time, the phototransistor of the optocoupler 111 is turned on, so that the power supply judgment signal PSE_DET is grounded and at Since the voltage level is low, the processor 110 can know that the power receiving device 20 is connected and powered normally.

綜上所述，本發明係提供一種電源供應裝置，其可在連接受電裝置的情況下，控制其輸出功率不超過預定功率，且可避免受電裝置剛連接至電源供應裝置時所產生的瞬間衝擊電流導致供電晶片之誤動作。此外，電源供應裝置更包括邏輯電路以實現外部電源供電，避免因為內部電源供電不足而導致光耦合器之工作異常的情況。In summary, the present invention provides a power supply device, which can control its output power not to exceed a predetermined power when the power receiving device is connected, and can avoid the instantaneous impact when the power receiving device is just connected to the power supply device The current causes malfunction of the power supply chip. In addition, the power supply device further includes a logic circuit to implement external power supply, so as to avoid the situation that the optical coupler works abnormally due to insufficient internal power supply.

本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the appended patent application.

10:電源供應裝置 20:受電裝置 110:處理器 111、112:光耦合器 120:供電晶片 130:供電控制電路 131:邏輯電路 132:開關電路 133:限流電路 135:光耦合器 1351:二極體 1352:光電晶體 136:電壓位準轉換晶片 150:電源輸入埠 160:電源輸出埠 161:纜線 Q1-Q3:電晶體 R1-R9:電阻 Vin:輸入電壓 VSET:閾值電壓 VSENSE:感測電壓 CPU_RST:重置信號 RESET:重置信號 V_MAIN:電壓 VAUX3P3:電壓 VSS:電壓源 LED0:指示信號 PSE_DET:供電判斷信號 N1-N6:節點 V+、V-:電壓輸入端 +IN:正輸入端 -IN:負輸入端 OUT:輸出腳位 10: Power supply device 20: Power receiving device 110: Processor 111, 112: Optical coupler 120: Power supply chip 130: Power supply control circuit 131: Logic Circuits 132: switch circuit 133: Current limiting circuit 135: Optocoupler 1351: Diode 1352: Phototransistor 136: Voltage level conversion chip 150: Power input port 160: Power output port 161: Cable Q1-Q3: Transistor R1-R9: Resistors Vin: input voltage VSET: Threshold Voltage VSENSE: sense voltage CPU_RST: reset signal RESET: reset signal V_MAIN: Voltage VAUX3P3: Voltage VSS: Voltage Source LED0: Indication signal PSE_DET: Power supply judgment signal N1-N6: Nodes V+, V-: voltage input terminals +IN: positive input terminal -IN: negative input terminal OUT: output pin

第1圖係顯示依據本發明一實施例中之電源供應裝置的示意圖。 第2圖為依據本發明一實施例中之供電晶片之輸入信號及輸出信號的示意圖。 第3A～3D圖為依據本發明不同實施例中之供電控制電路的電路圖。 FIG. 1 is a schematic diagram of a power supply device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of input signals and output signals of a power supply chip according to an embodiment of the present invention. FIGS. 3A to 3D are circuit diagrams of power supply control circuits according to different embodiments of the present invention.

10:電源供應裝置 10: Power supply device

20:受電裝置 20: Power receiving device

110:處理器 110: Processor

111、112:光耦合器 111, 112: Optical coupler

120:供電晶片 120: Power supply chip

130:供電控制電路 130: Power supply control circuit

131:邏輯電路 131: Logic Circuits

132:開關電路 132: switch circuit

133:限流電路 133: Current limiting circuit

150:電源輸入埠 150: Power input port

160:電源輸出埠 160: Power output port

161:纜線 161: Cable

Vin:輸入電壓 Vin: input voltage

VSENSE:感測電壓 VSENSE: sense voltage

CPU_RST:重置信號 CPU_RST: reset signal

RESET:重置信號 RESET: reset signal

VAUX3P3:電壓 VAUX3P3: Voltage

LED0:指示信號 LED0: Indication signal

PSE_DET:供電判斷信號 PSE_DET: Power supply judgment signal

Claims (10)

一種電源供應裝置，包括： 一供電晶片，用以將一輸入電壓轉換為一第一電壓，並且產生一指示信號及一感測電壓，其中該指示信號係表示該電源供應裝置的一受電裝置之連接狀態及供電狀態；以及 一供電控制電路，包括： 一限流電路，用以因應於該感測電壓與一閾值電壓之比較結果以產生一第一重置信號； 一邏輯電路，用以依據該指示信號及該輸入電壓以產生一控制信號；以及 一開關電路，用以依據該控制信號以決定是否提供該第一電壓至該限流電路， 其中，因應於該第一重置信號處於一第一邏輯狀態，該供電晶片係關閉提供至該受電裝置之電源。 A power supply device, comprising: a power supply chip for converting an input voltage into a first voltage and generating an indication signal and a sensing voltage, wherein the indication signal represents the connection state and power supply state of a power receiving device of the power supply device; and a power supply control circuit, comprising: a current limiting circuit for generating a first reset signal in response to a comparison result between the sensing voltage and a threshold voltage; a logic circuit for generating a control signal according to the indication signal and the input voltage; and a switch circuit for determining whether to provide the first voltage to the current limiting circuit according to the control signal, Wherein, in response to the first reset signal being in a first logic state, the power supply chip turns off the power supplied to the power receiving device. 如請求項1之電源供應裝置，其中，當該供電晶片判斷該受電裝置未連接至該電源供應裝置時或是判斷該受電裝置已連接至該電源供應裝置且該供電晶片檢測通過但尚未供電至該受電裝置時，該供電晶片所產生的該指示信號係處於高電壓位準， 其中，當該供電晶片判斷該受電裝置已連接至該電源供應裝置且已正常供電至該受電裝置，該供電晶片所產生的該指示信號係處於低電壓位準。 The power supply device of claim 1, wherein when the power supply chip determines that the power receiving device is not connected to the power supply device or determines that the power receiving device is connected to the power supply device and the power supply chip has passed the test but has not supplied power to the power supply device When the power receiving device is used, the indication signal generated by the power supply chip is at a high voltage level, Wherein, when the power supply chip determines that the power receiving device has been connected to the power supply device and has supplied power to the power receiving device normally, the indication signal generated by the power supply chip is at a low voltage level. 如請求項2之電源供應裝置，其中該開關電路包括一第一P型電晶體，其中該第一P型電晶體之閘極、源極及汲極係分別連接至該控制信號、該第一電壓及該限流電路之電壓輸入端。The power supply device of claim 2, wherein the switch circuit comprises a first P-type transistor, wherein the gate, source and drain of the first P-type transistor are respectively connected to the control signal, the first P-type transistor voltage and the voltage input terminal of the current limiting circuit. 如請求項3之電源供應裝置，其中因應於該指示信號處於高電壓位準，該邏輯電路所產生的該控制信號係位於高電壓位準， 其中因應於該指示信號處於低電壓位準，該邏輯電路所產生的該控制信號係位於低電壓位準。 The power supply device of claim 3, wherein in response to the indicating signal being at a high voltage level, the control signal generated by the logic circuit is at a high voltage level, The control signal generated by the logic circuit is at a low voltage level in response to the indication signal being at a low voltage level. 如請求項4之電源供應裝置，其中該限流電路包括： 一分壓電路，用以將該第一電壓分壓以產生該閾值電壓；以及 一比較電路，用以比較該閾值電壓及該感測電壓， 其中當該感測電壓大於或等於該閾值電壓，該比較電路所輸出的該第一重置信號係位於該第一邏輯狀態， 其中當該感測電壓小於該閾值電壓，該比較電路所輸出的該第一重置信號係位於相對於該第一邏輯狀態之一第二邏輯狀態。 The power supply device of claim 4, wherein the current limiting circuit comprises: a voltage divider circuit for dividing the first voltage to generate the threshold voltage; and a comparison circuit for comparing the threshold voltage and the sensing voltage, wherein when the sensing voltage is greater than or equal to the threshold voltage, the first reset signal output by the comparison circuit is in the first logic state, When the sensing voltage is less than the threshold voltage, the first reset signal output by the comparison circuit is in a second logic state relative to the first logic state. 如請求項4之電源供應裝置，其中該邏輯電路包括： 一第一PNP雙極性接面電晶體，其中該第一PNP雙極性接面電晶體之基極係透過一第一電阻連接至該指示信號，該第一PNP雙極性接面電晶體之射極係連接至該輸入電壓；以及 一第一NPN雙極性接面電晶體，其中該第一NPN雙極性接面電晶體之基極係透過一第二電阻以連接至該第一PNP雙極性接面電晶體之集極，該第一NPN雙極性接面電晶體之射極係接地，且該第一NPN雙極性接面電晶體之集極係連接至該第一P型電晶體之閘極，並透過一第三電阻連接至該第一電壓。 The power supply device of claim 4, wherein the logic circuit comprises: a first PNP bipolar junction transistor, wherein the base of the first PNP bipolar junction transistor is connected to the indication signal through a first resistor, and the emitter of the first PNP bipolar junction transistor is connected to the input voltage; and a first NPN bipolar junction transistor, wherein the base of the first NPN bipolar junction transistor is connected to the collector of the first PNP bipolar junction transistor through a second resistor, the first The emitter of an NPN bipolar junction transistor is connected to ground, and the collector of the first NPN bipolar junction transistor is connected to the gate of the first P-type transistor through a third resistor to the first voltage. 如請求項4之電源供應裝置，其中該邏輯電路包括： 一第二P型電晶體，其中該第二P型電晶體之閘極係透過一第四電阻以連接至該指示信號，該第二P型電晶體之源極係連接至該輸入電壓；以及 一第一N型電晶體，其中該第一N型電晶體之閘極係透過一第五電阻以連接至該第二P型電晶體之汲極並且透過一第六電阻接地，該第一N型電晶體之源極係接地，且該第一N型電晶體之汲極係連接至該第一P型電晶體之閘極並且透過一第七電阻連接至該第一電壓。 The power supply device of claim 4, wherein the logic circuit comprises: a second P-type transistor, wherein the gate of the second P-type transistor is connected to the indication signal through a fourth resistor, and the source of the second P-type transistor is connected to the input voltage; and A first N-type transistor, wherein the gate of the first N-type transistor is connected to the drain of the second P-type transistor through a fifth resistor and grounded through a sixth resistor, the first N-type transistor The source of the type transistor is grounded, and the drain of the first N-type transistor is connected to the gate of the first P-type transistor and is connected to the first voltage through a seventh resistor. 如請求項4之電源供應裝置，其中該邏輯電路包括一第一光耦合器，該第一光耦合器包括一第一二極體及一第一光電晶體， 其中，該第一二極體之陽極及陰極係分別連接至該輸入電壓及該指示信號，該光電晶體之射極係接地，且該光電晶體之集極係連接至該第一P型電晶體之閘極並透過一第八電阻連接至該第一電壓。 The power supply device of claim 4, wherein the logic circuit includes a first optocoupler, the first optocoupler includes a first diode and a first phototransistor, The anode and cathode of the first diode are respectively connected to the input voltage and the indication signal, the emitter of the phototransistor is grounded, and the collector of the phototransistor is connected to the first P-type transistor The gate is connected to the first voltage through an eighth resistor. 如請求項4之電源供應裝置，其中該邏輯電路包括一電壓位準轉換晶片，其中該電壓位準轉換晶片之高電壓輸入端及高電壓資料端係連接至該輸入電壓及該指示信號，該電壓位準轉換晶片之低電壓輸入端係連接至該第一電壓並透過一第九電阻連接至該第一P型電晶體之閘極，該電壓位準轉換晶片之低電壓資料端係連接至該第一P型電晶體之閘極，該電壓位準轉換晶片之接地端係接地，且該電壓位準轉換晶片之方向端係透過一第十電阻接地。The power supply device of claim 4, wherein the logic circuit comprises a voltage level conversion chip, wherein a high voltage input terminal and a high voltage data terminal of the voltage level conversion chip are connected to the input voltage and the indication signal, the The low voltage input terminal of the voltage level conversion chip is connected to the first voltage and is connected to the gate of the first P-type transistor through a ninth resistor, and the low voltage data terminal of the voltage level conversion chip is connected to The gate of the first P-type transistor, the ground terminal of the voltage level conversion chip is grounded, and the direction end of the voltage level conversion chip is grounded through a tenth resistor. 如請求項1之電源供應裝置，更包括： 一處理器； 一第二光耦合器，包括一第二二極體及一第二光電晶體，其中該第二二極體之陽極係透過一第十一電阻連接至該輸入電壓，且該第二二極體之陰極係連接至該指示信號，該第二光電晶體之射極係接地，且該第二光電晶體之集極係輸出一供電判斷信號至該處理器；以及 一第三光耦合器，包括一第三二極體及一第三光電晶體，其中該第三二極體之陽極及陰極係分別連接至該處理器及接地，該第三光電晶體之射極係接地，且該第三光電晶體之集極係輸出一第二重置信號至該供電晶片， 其中因應於該第一重置信號或該第二重置信號處於該第一邏輯狀態，該供電晶片係關閉提供至該受電裝置之電源。 As in the power supply device of claim 1, it further includes: a processor; A second optocoupler including a second diode and a second phototransistor, wherein the anode of the second diode is connected to the input voltage through an eleventh resistor, and the second diode The cathode of the second phototransistor is connected to the indication signal, the emitter of the second phototransistor is grounded, and the collector of the second phototransistor outputs a power supply judgment signal to the processor; and A third optocoupler including a third diode and a third phototransistor, wherein the anode and cathode of the third diode are connected to the processor and ground, respectively, and the emitter of the third phototransistor is grounded, and the collector of the third phototransistor outputs a second reset signal to the power supply chip, In response to the first reset signal or the second reset signal being in the first logic state, the power supply chip turns off the power supplied to the power receiving device.
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