TW202218171A - A silicon carbide semiconductor element comprising a semiconductor substrate, a trench MOSFET and a trench Schottky diode - Google Patents

Abstract

A silicon carbide semiconductor element is disclosed. More particularly, the invention is referred to a monolithic integrated structure which integrating trench Schottky diodes and trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and comprises a semiconductor substrate, a trench MOSFET and a trench Schottky diode. The trench Schottky diodes has a trench vertically disposed and passing through along a first horizontal direction, a metal electrode filled in the trench, and a plurality of doped regions that is segmentally disposed and extended along a second direction and surrounds the trench. The first horizontal direction is substantially orthogonal to the second horizontal direction. The metal electrode forms a Schottky junction on a side wall and a bottom wall of the trench, and the current flowing out of the metal electrode is limited between the adjacent doped regions.

Description

A silicon carbide semiconductor device

The present invention relates to a semiconductor device, and particularly to a silicon carbide semiconductor device.

In terms of characteristics, semiconductor power devices usually require high breakdown voltage (Breakdown voltage), and have as small as possible on-resistance, low reverse leakage current and fast switching speed to reduce conduction loss during operation (Conduction loss) and Switching loss (Switching loss). Because of its wide energy gap (Bandgap Eg=3.26eV), high critical collapse electric field strength (2.2MV/cm) and high thermal conductivity (4.9W/cm-K), silicon carbide (SiC) is considered to be It is an excellent material for power switching components. Under the same breakdown voltage condition, the thickness of the withstand voltage layer (Drift layer with low doping concentration) of the power device made of silicon carbide is only one tenth of the thickness of the silicon (Si) power device. One, and the theoretical on-resistance can reach several hundredths of that of silicon.

However, due to the wide energy gap of silicon carbide, the threshold voltage for the conduction of the body diode of the silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) is about 3V, which causes the reverse current to flow back during switching. Large power loss and limiting switching speed. In addition, the epitaxial basal plane dislocation (Basal plane dislocation) generated by silicon carbide during deposition of the drift layer will expand into stacking defects due to carrier recombination when the body diode is turned on. fault), and in severe cases, the SiC MOSFET will fail. Therefore, when manufacturing SiC MOSFETs, semiconductor manufacturers will design an additional Schottky diode in parallel to improve operation speed, reduce power loss and avoid reliability problems caused by the expansion of accumulation defects. Similar prior art can be found in US Pat. Nos. 9,209,293, 9,246,016, 10,418,476, US 2018/0358463, and the like.

The present invention relates to a semiconductor device, and particularly to a silicon carbide semiconductor device.

The present invention discloses a silicon carbide semiconductor device, comprising: a first silicon carbide semiconductor layer having a first conductivity type; a second silicon carbide semiconductor layer having the first conductivity type, the second silicon carbide semiconductor layer being disposed on on the first silicon carbide semiconductor layer; a third silicon carbide semiconductor layer with a second conductivity type disposed on an upper surface of the second silicon carbide semiconductor layer; a first semiconductor region with the first conductivity type, disposed in the third silicon carbide semiconductor layer; a first trench, vertically penetrating the first semiconductor region and the third silicon carbide semiconductor layer to the second silicon carbide semiconductor layer, and along a The first horizontal direction extends; a second trench is spaced apart from the first trench, the second trench vertically penetrates the third silicon carbide semiconductor layer into the second silicon carbide semiconductor layer, and extends along the the first horizontal direction extends; a second semiconductor region with the second conductivity type, the second semiconductor region includes a plurality of first portions extending along a second horizontal direction and a a second portion in the second silicon carbide semiconductor layer below the first trench; a gate portion including a gate insulating layer disposed in the first trench and a gate electrode buried in the first trench a compound gate electrode in the trench and formed on the gate insulating layer; and a metal electrode, in contact with the first semiconductor region and the gate portion, and buried in the second trench and The second semiconductor region and the third silicon carbide semiconductor layer are in electrical contact, and a side wall and a bottom wall of the metal electrode form a Schottky junction with the second silicon carbide semiconductor layer in the second trench ; wherein, the first portion of the second semiconductor region defines a pickup area surrounding the first trench and connected to the second portion and a segment area surrounding the second trench and connected to the pickup area, to Let the current flowing from the metal electrode be confined between adjacent segments.

The present invention also provides an element for integrating the inter-section surrounding trench Schottky diode and the trench metal oxide semiconductor field effect transistor, comprising: a semiconductor substrate; a trench type formed on the semiconductor substrate a metal oxide semiconductor field effect transistor; and a trench Schottky diode formed on the semiconductor substrate, the trench Schottky diode having a vertically disposed and along a first horizontal direction The penetrating trench, a metal electrode filling the trench, and a plurality of interspaces are arranged in sections and extend along a second horizontal direction surrounding the doped region of the trench, the first horizontal direction being substantially orthogonal In the second horizontal direction, the metal electrode forms a Schottky junction on a side wall and a bottom wall of the trench, and the current flowing from the metal electrode is restricted between the adjacent doped regions.

The terminology used in the description of the various embodiments herein is for the purpose of describing particular examples only and is not intended to be limiting.

As used herein, the singular forms "a," "an," and "the" include the plural forms as well, unless the context clearly dictates otherwise, or the number of elements is not intended to be limited. On the other hand, the terms "comprising" and "comprising" are intended to be inclusive, meaning that there may be additional elements other than the listed elements; when one element is described as "connected" or "coupled" to another When an element is referred to as being "on" another element, the element can be connected or coupled directly or through intervening elements to the other element; when an element describing a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element An intervening element may be present on an element or between each other. In contrast, when an element is referred to as being "directly on" another element, the intervening element is not present; in addition, the order of description of the embodiments should not To be interpreted as implying that operations or steps must be literally ordered, alternative embodiments may perform steps, operations, methods, etc. using a different order than that described herein.

In this context, each layer and/or region is characterized as having a conductivity type such as n-type or p-type, which refers to the majority carrier species in the layer and/or region, n-type materials include an equilibrium excess of electrons, and p-type materials The type material includes a balanced excess of holes. Some materials may be labeled with "+" or "-" (eg, n+, n-, p+, p-) to indicate a relatively greater (+) or lesser (-) majority carrier concentration compared to another layer or region , the symbol does not represent the specific concentration of the carrier. In the drawings, the thicknesses of layers and/or regions are exaggerated for clarity.

The present invention provides a silicon carbide semiconductor element, in particular a structure of a monolithically integrated trench MOSFET with segmentally surrounded Schottky diode and a trench metal oxide semiconductor field effect transistor. diode), please refer to "FIG. 1A" and "FIG. 1B", which are schematic diagrams of the three-dimensional structure of an embodiment of the present invention. For convenience of understanding, "FIG. 1A" omits some components of "FIG. 1B", and "FIG. 1B" 』 will display some components with dotted lines. The silicon carbide semiconductor device includes a first silicon carbide semiconductor layer 10 , a second silicon carbide semiconductor layer 20 , a third silicon carbide semiconductor layer 30 , a first semiconductor region 40 , a second semiconductor region 50 , and a gate electrode part 60 and a metal electrode 70 .

The first silicon carbide semiconductor layer 10 has a first conductivity type, in this embodiment, the first conductivity type is n-type, and the first silicon carbide semiconductor layer 10 is an n+ silicon carbide substrate, the first carbide A buffer layer 11 is provided above the silicon semiconductor layer 10 , a metal drain layer 12 is provided below the first silicon carbide semiconductor layer 10 , the second silicon carbide semiconductor layer 20 is provided on the buffer layer 11 , and the second silicon carbide semiconductor layer 10 is provided on the buffer layer 11 . The layer 20 includes an n-drift layer 20a and an n-type current spreading layer 20b, the third silicon carbide semiconductor layer 30 is provided on the n-type current spreading layer 20b, and the third silicon carbide semiconductor layer 30 is a p-type base A pole region is disposed on an upper surface 21 of the second silicon carbide semiconductor layer 20, the first semiconductor region 40 is formed in the third silicon carbide semiconductor layer 30, and the first semiconductor region 40 is an n+ source region . The n− drift layer 20a has a doping concentration between 5E14 and 5E16, the n-type current diffusion layer has a doping concentration between 1E16 and 5E18, and the p-type base region has a doping concentration between 1E17 and 5E19. The n+ source region has a doping concentration between 1E18 and 5E20. In one embodiment, the buffer layer 11 , the second silicon carbide semiconductor layer 20 , and the third silicon carbide semiconductor layer 30 are epitaxially grown to form an epitaxial layer.

The silicon carbide semiconductor device includes a plurality of trenches T. The trenches T are formed by an etching process. The trenches T include a first trench T1 and a second trench T2. The first trench T1 and the first trench T1 The two trenches T2 are spaced apart and extend through a first horizontal direction. In this embodiment, the first horizontal direction is the Y axis in the figure, and the first trench T1 penetrates the first semiconductor vertically. Region 40 and the third silicon carbide semiconductor layer 30 to the second silicon carbide semiconductor layer 20, and the second trench T1 vertically penetrates the third silicon carbide semiconductor layer 30 to the second silicon carbide semiconductor layer 20. The depth and width of the first trench T1 and the second trench T2 may be the same or different depending on the application or the choice of the manufacturing method. For example, the first trench T1 has a thickness between 1 μm and 2.5 μm The second trench T2 has a depth between 1 um and 2.5 um and a width between 0.5 um and 2 um. In addition, in this embodiment, the first semiconductor region 40 is formed on a part of the upper surface of the third silicon carbide semiconductor layer 30 by ion implantation, as shown in "FIG. 1A" and "FIG. 1B".

Further referring to "Fig. 2" and "Fig. 3", respectively, are the schematic front view of "Fig. 1B" and the schematic plan view of "Fig. 1A"; and "Fig. 5", "Fig. 6A", and "Fig. 7", respectively " Figure 1A" is a schematic three-dimensional cross-sectional view along A-A, B-B, and C-C. The second semiconductor region 50 includes a first portion 51 and a second portion 52. The first portion 51 is a segmental implant region arranged at intervals, implanted segmentally and formed in the In the third silicon carbide semiconductor layer 30 and the second silicon carbide semiconductor layer 20 , the first portion 51 extends along a second horizontal direction. In this embodiment, the second horizontal direction is the X axis in the figure. Further, the first portion 51 of each of the second semiconductor regions 50 respectively defines a plurality of pickup regions 51a and a plurality of slice regions 51b. The first portion 51 surrounding the first trench T1 is the pickup area 51a, the first portion 51 surrounding the second trench T2 is the segment area 51b, and the second semiconductor region 50 has a An upper surface 31 of the silicon carbide semiconductor layer 30 (see "FIG. 1A") to the implantation depth of the second silicon carbide semiconductor layer 20 (in some respects, the upper surface 31 may correspond to the first the top surface of the semiconductor region 40), the implantation depth is between 0.8 um and 3.0 um.

In the embodiments of "FIG. 1A" to "FIG. 3", a width 511a and a depth 512a of the pickup area 51a are the same as a width 511b and a depth 512b of the segment area 51b. In one embodiment, the width 511a and the width 511b are between 0.5 um and 1.5 um, and the depth 512a and the depth 512b are between 0.8 um and 2.5 um; however, in other embodiments, the width 511a of the pick-up area 51a may be different. Different from the width 511b of the segment region 51b, such as "FIG. 4", the width 511b is larger than the width 511a, thereby further limiting leakage. However, according to different applications, the width 511a can also be smaller than the width 511b, and the depth 512a of the pickup region 51a can be larger or smaller than the depth 512b, in addition, the doping concentration of the pickup region 51a can be equal, larger or smaller than In the segment region 51b, the doping concentration is between 1E18 and 5E20. In addition, the pickup regions 51a have a distance D1 between each other, the distance D1 is between 0.5 um and 3 um, and the segment regions 51b have a distance D2 between each other, and the distance D2 is between 0.5 um and 3 um.

The second portion 52 is formed in the region of the second silicon carbide semiconductor layer 20 below the first trench T1 and extends along the first horizontal direction, the second portion 52 has a lowermost portion from the upper surface 31 The depth 521 at , the depth 521 is between 1.3 and 3 um, the second part 52 is used as a p+ shield region (p+ shield), the second part 52 has a doping between 1E18 and 5E20 It is understood that the depth 521 of the second portion 52 is greater than the depth 512a of the pickup area 51a and/or the depth 512b of the segment area 51b. Referring to "FIG. 1B" and "FIG. 2", a metal silicide layer 80 is formed on the surface of the third silicon carbide semiconductor layer 30 and the first semiconductor region 40, and the metal silicide layer 80 and A metal layer 81 is formed on the inner wall of the second trench T2. In this embodiment, the metal silicide layer 80 is nickel silicide (NiSi), and the metal layer 81 is an alloy such as Ti/TiN , and the metal electrode 70 is AuCu. The gate portion 60 includes a gate insulating layer 61 and a poly gate 62 . The gate insulating layer 61 is formed on a part of the surface of the first semiconductor region 40 along the first trench. The sidewall of the trench T1 extends longitudinally and covers part of the surface of the third silicon carbide semiconductor layer 30 and the second silicon carbide semiconductor layer 20 , the complex gate 62 is formed on the gate insulating layer 61 , and the metal The electrode 70 covers the gate insulating layer 61 and the upper surface of the metal layer 81, and fills the second trench T2. A sidewall and a bottom wall of the metal layer 81 are in the second trench T2 with each other. The second silicon carbide semiconductor layer 20 forms a Schottky junction, and the metal electrode 70 covers the metal layer 81 .

Referring to "FIG. 6B" and "FIG. 6C", in the present invention, a first area A1 may be defined on the inner wall surface of the second trench T2 below the upper surface 21 of the second silicon carbide semiconductor layer 20 (including part of the surface of the segment area 51b), and the Schottky junction is a second area A2 (excluding part of the surface of the segment area 51b), the second area A2 is smaller than the first area A1. Returning to FIG. 3 , it can be seen that a first region R1 of the silicon carbide semiconductor element corresponds to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and a second region R2 corresponds to a Junction Barrier Schottky diode (JBS). In addition, the position where the first semiconductor region 40 is formed on the third silicon carbide semiconductor layer 30 is determined according to the setting of the MOSFET.

In the prior art, the leakage current of JBS occurs in the above-mentioned first area A1. However, according to the present invention, the integrated inter-segment-surrounded trench Schottky diode and trench metal-oxide-semiconductor field effect current For crystal elements (A monolithically integrated trench MOSFET with segmentally surrounded Schottky diode), the leakage of JBS will be limited to occur only in the second area A2 mentioned above. Therefore, under the same size condition, the leakage current of the device of the present invention can be improved, and the reverse diode conduction voltage (Vsd) can be relatively low; on the other hand, the silicon carbide semiconductor device of the present invention can increase the cell density, That is, the cell pitch is reduced.

"FIG. 8A" to "FIG. 8H" are schematic diagrams of a manufacturing process according to an embodiment of the present invention. Referring to "FIG. 8A", a semiconductor substrate 90 is provided first, and a drift layer 90a and a current spreading layer 90b are formed in the semiconductor substrate 90 and a base layer 90c, the drift layer 90a and the current spreading layer 90b have a first conductivity type, the base layer 90c has a second conductivity type, in this embodiment, the first conductivity type and the second conductivity type are respectively n-type and p-type, and the drift layer 90a, the current spreading layer 90b and the base layer 90c are obtained by epitaxial growth. Next, referring to FIG. 8B , a plurality of first doped regions 91 arranged segmentally and extending along a second horizontal direction are implanted on the semiconductor substrate 90 . The first doped regions 91 have at least one doped region 91 . Through the depth 911 of the base layer 90c, and the first doped regions 91 are separated from each other by a distance 912, the parameters of the depth 911 and the distance 912 can refer to the foregoing embodiments. The first doped region 91 can be pre-defined to include a plurality of pick-up regions 91a and a plurality of segment regions 91b, the pick-up regions 91a correspond to the MOSFET region, and the segment region 91b corresponds to the JBS region. Referring to "FIG. 8C", a source region 90d is formed on a part of the upper surface region of the base layer 90c, that is, the region corresponding to the MOSFET, and the source region 90d has the first conductivity type.

Referring to "FIG. 8D", a first trench T1 is formed on the semiconductor substrate 90 by etching, the first trench T1 is spaced apart along the second horizontal direction and passes through a first horizontal direction, the The first horizontal direction is substantially orthogonal to the second horizontal direction, and the first trench T1 penetrates vertically to the current spreading layer 90b. Next, referring to "FIG. 8E", a second doped region 92 is implanted on the current spreading layer 90b under the first trench T1, and the second doped region 92 and the first doped region 91 have the same Conductivity type. Then, a gate portion is formed in the first trench T1. Referring to FIG. 8F , a gate portion is first formed on the bottom wall, sidewall and the source region 90d of the first trench T1 adjacent to the upper surface of the first trench T1. A first gate insulating layer 61a, and then a complex gate 62 is formed on the first gate insulating layer 61a in the first trench T1, see FIG. 8G. Referring to "FIG. 8H", a second trench T2 is formed on the semiconductor substrate 90, the second trench T2 and the first trench T1 are spaced apart along the second horizontal direction and along the first horizontal direction Passing through, the second trench T2 penetrates vertically to the current spreading layer 90b. After that, elements such as the metal silicide layer 80 , the metal layer 81 , and the metal electrode 70 are formed. Please refer to the above-mentioned “ FIG. 1A ” and “ FIG. 1B ”.

According to the above manufacturing method, the first doped region 91 is the first portion 51 of the second semiconductor region 50 , and the second doped region 92 is the second portion 52 of the second semiconductor region 50 . In this embodiment, the MOS transistor and the first doping region 91 of the junction barrier Schottky diode can be ion implanted through the same mask, which can improve the process and device configuration accuracy.

10: The first silicon carbide semiconductor layer 11: Buffer layer 12: Metal drain layer 20: The second silicon carbide semiconductor layer 20a:n−drift layer 20b: n-type current spreading layer 21: Upper surface 30: The third silicon carbide semiconductor layer 31: Upper surface 40: The first semiconductor region 50: Second semiconductor region 51: Part One 51a: Pickup area 511a: width 512a: Depth 51b: fragment area 511b: width 512b: Depth 52: Part Two 521: Depth 60: Gate part 61: gate insulating layer 61a: first gate insulating layer 62: Complex thyristor gate 70: Metal electrode 80: Metal silicide layer 81: Metal layer 90: Semiconductor substrate 90a: Drift layer 90b: Current spreading layer 90c: base layer 90d: source area 91: first doped region 91a: Pickup area 91b: Fragment area 911: Depth 912: Spacing 92: the second doped region A1: The first area A2: Second area D1: Interval D2: Interval R1: The first area R2: The second area T: groove T1: First trench T2: Second trench

"FIG. 1A" to "FIG. 1B" are three-dimensional schematic diagrams of an embodiment of the present invention. "FIG. 2" is a schematic front view of "FIG. 1B". "FIG. 3" is a schematic top view of "FIG. 1A". "FIG. 4" is a schematic top view of another embodiment of the present invention. "FIG. 5" is a schematic three-dimensional cross-sectional view along A-A of "FIG. 1A". "FIG. 6A" to "FIG. 6C" are schematic perspective cross-sectional views of "FIG. 1A" along B-B. "FIG. 7" is a schematic three-dimensional cross-sectional view along C-C of "FIG. 1A". "FIG. 8A" to "FIG. 8H" are schematic diagrams of a manufacturing process according to an embodiment of the present invention.

10: The first silicon carbide semiconductor layer

11: Buffer layer

12: Metal drain layer

20: The second silicon carbide semiconductor layer

20a:n-drift layer

20b: n-type current spreading layer

21: Upper surface

30: The third silicon carbide semiconductor layer

40: The first semiconductor region

51a: Pickup area

51b: fragment area

52: Part Two

A2: Second area

T1: First trench

T2: Second trench

Claims (3)

A silicon carbide semiconductor element, comprising: a semiconductor substrate; a trench metal oxide semiconductor field effect transistor formed on the semiconductor substrate; and a trenched Schottky diode formed on the semiconductor substrate, the trenched Schottky diode has a trench disposed vertically and passing through a first horizontal direction, a trench filled in the The metal electrodes of the trenches and a plurality of interspaces are arranged in sections and extend along a second horizontal direction to surround the doped regions of the trenches, the first horizontal direction being substantially orthogonal to the second horizontal direction, the metal electrodes A side wall and a bottom wall in the trench form a Schottky junction, and the current flowing from the metal electrode is confined between the adjacent doped regions. The element of claim 1, wherein the spacing between the doped regions is between 0.5 um and 3 um. The device of claim 1, wherein the doped region has a width between 0.5 um and 1.5 um.

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