TW202215435A - Semiconductor device with communication interface and interface managing method thereof - Google Patents

Abstract

A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Description

Semiconductor device with communication interface and interface management method of semiconductor device

The present invention relates to the fabrication of semiconductor devices, and more particularly, to a semiconductor device in a three-dimensional (3D) stack with a communication interface and a method for managing the semiconductor devices.

Digital electronic devices based on semiconductor integrated circuits, such as mobile phones, digital cameras, personal digital assistants (PDAs), etc., are designed to have more powerful functions to adapt to various applications in the modern digital world. However, digital electronic devices as a trend in semiconductor fabrication aim to be smaller and lighter, with improved functionality and higher performance. Semiconductor devices can be packaged into three-dimensional (3D) semiconductor devices, where several circuit chips can be stacked and integrated into larger integrated circuits, where bonds and through-silicon vias (TSVs) are used for the chips the connection between.

System-on-integrated-chip (SoIC) packaging, wafer-on-wafer (WoW) packaging, and chip-on-wafer-on packaging have been proposed. -substrate, CoWoS) packaging technology to package multiple wafers stacked in height.

However, the communication between the master wafer and multiple slave wafers as a 3D stack is still under development for better performance, compact structure. In addition, the bond pattern between the two wafers needs to be patterned for easy connection to accommodate 3D stacking of multiple wafers. Furthermore, since multiple slave dies are stacked on top of the master, it is possible to develop in a more efficient manner how to address the slaves during the initialization phase and how to manage the slaves to identify the addresses requested by the master.

The present invention provides a semiconductor device in a three-dimensional (3D) stack with a communication interface and a management method of the semiconductor device. The slave wafers can be easily addressed and the target address requested by the master wafer can be identified slave wafer by slave wafer. The total number of slave wafers to be driven may also increase.

In an embodiment, the present invention provides a semiconductor device having an interface, the semiconductor device including a master device and a plurality of slave devices. The host device includes a host interface. Slave devices are stacked one after the other in a three-dimensional stack on the master device. Each of the slave devices includes a slave interface and management circuitry, the master interface and the slave interface forming the interface for communicating communication signals between the master device and the slave device. The management circuit of the current one of the slave devices drives the next one of the slave devices. Operation commands received at the current one of the slave devices are passed to the next one of the slave devices only through the interface. A response from the current one of the slave devices is communicated back to the master device through the interface.

In an embodiment, the present invention provides a management method of a semiconductor device having an interface. The semiconductor device includes a master device and a plurality of slave devices stacked one after another in a three-dimensional stack on the master device. The management method includes: configuring the master device to have a master interface; and configuring each of the slave devices to have a slave interface and a management circuit. The master interface and the slave interface form the interface for communicating communication signals between the master device and the slave device. The management circuit of the current one of the slave devices drives the next one of the slave devices. Operation commands received at the current one of the slave devices are passed to the next one of the slave devices only through the interface. A response from the current one of the slave devices is communicated back to the master device through the interface.

The present invention relates to an interface of a 3D semiconductor device, wherein the interface is also fabricated based on 3D packaging technology. The interface may link a single master chip (eg, a processor) with multiple slave chips (eg, static random access memory (SRAM).

Additionally, the slave wafers may include management circuitry to address slave wafers slave wafer by slave wafer during the initialization phase. In addition, the response can be passed back to the master device. It may not be necessary to send address signals to all slave dies simultaneously. Instead, address signals from the master wafer may be passed from wafer to wafer. The number of slave wafers may be larger without limiting the drive capability of the master wafer to the limited number of slave wafers stacked.

In order to communicate between the master wafer and the plurality of slave wafers in the 3D stack, an interface is first proposed. The management mechanism for the slave chips can be based on the set interface. In the embodiments, the interface for transmitting communication signals of the present invention is first explained.

In the present invention, the interface allows communication between the master die and the plurality of slave die. Communication signals may include commands from the master chip and response information from one of the selected slave chips. The interface provides reliable communication. Additionally, the signal latency between each of the master and slave wafers can be stabilized to be approximately constant and predictable. Due to the control of the latency, the trigger edge of the valid clock can be appropriately set corresponding to the data packet (which may also be referred to as a data eye).

A number of examples are provided below to illustrate the present invention, but the present invention is not limited to the examples.

FIG. 1 is a diagram schematically illustrating a structure of a 3D semiconductor device in a cross-sectional view according to an embodiment of the present invention. Referring to FIG. 1 , the 3D semiconductor device 10 includes a plurality of circuit die 24 , 34 that are vertically stacked in addition to the horizontal distribution of the die. Thus, a 3D semiconductor device including a wafer is formed.

In one example, circuit die 24 may be considered a master die, which generally includes substrate 20 and circuit layer 22 . Several other die 34 (eg serving as slave die) will be stacked on top of die 24 with through-hole structures (eg TSVs with bonds) formed between die 24 and die 34 based on the packaging process structure 26). Circuit die 34 includes substrate 30 and circuit layer 32 and may also include TSV structures 36 at corresponding locations for electrical connection to circuit die 24 . Additionally, bonding members 38 may also be formed at the outermost surfaces corresponding to the TSV structures 36 .

3D packaging techniques have been proposed in various stack structures such as: System-on-Chip (SoIC) packaging, Wafer-to-wafer (WoW) packaging, and Die-to-wafer-to-substrate (CoWoS). The present invention is based on 3D packaging, but is not limited to the type of 3D packaging.

2 is a diagram schematically illustrating a cross-sectional stack structure of a 3D semiconductor device with an interface according to an embodiment of the present invention. Referring to FIG. 2 , based on the 3D package structure, in an embodiment, the 3D semiconductor device 10 may further include an interface region 40 , wherein the interface in each of the circuit chips 24 , 34 is formed at the interface region 40 . The interface may link the owner of the die 24 serving as the master to the owner in the die 34 serving as the slave. Communication between die 24 and die 34 may be through the interface at interface region 40 .

The circuitry of the interface implemented within the interface region 40 will be explained in detail later. It should also be noted that, in the embodiment, a plurality of interface regions 40 may be formed in the circuit chip according to actual needs, and are not limited to a single interface region.

3 is a diagram schematically illustrating a perspective stack structure of a 3D semiconductor device with a communication mechanism of an interface, according to an embodiment of the present invention.

Referring to FIG. 3 , in view of the 3D stack structure in the operation of the interface, a main wafer 100 , such as a processor wafer, is included in the semiconductor device as a base wafer. On top of the master wafer 100 are stacked a plurality of slave wafers 102, such as SRAM wafers. The master chip 100 includes a master interface and each slave chip includes a slave interface. The master interface and the slave interface form an interface 200, which may also be referred to as Glink-3D. The master chip 100 and the slave chip 102 are connected through the interface 200 to communicate using information/data/signals.

In operation as an example, the master die 100 of the processor has commands for accessing data stored in the slave die 102 of the SRAM die. Due to the interface implemented, the read latency can be controlled to be approximately constant and small, eg, 2 ns or 5 ns, in one example. Using a single clock in the interface to distribute to all slave wafers, the path length from master wafer 100 to each slave wafer 102 is approximately the same and reliable. The wait time can be adjusted to a predictable constant value.

4 is a diagram schematically illustrating a communication mechanism of an interface between a master die and a slave die, according to an embodiment of the present invention. Referring to FIG. 4 , the communication mechanism between the master chip 100 having the master interface 200M and the slave chip 102 having the slave interface 200S connected by the bonding structure 104 in the 3D package is described. As shown in FIG. 3 , the master interface 200M and the slave interface 200S form the interface 200 . Inside the master chip 100, a central processing unit (CPU) block 110, which in one example has a cache block 112, forms the processor. The processor is connected to the master interface 200M to transmit or receive signals at the master interface 200M intended to communicate with the slave die 102 .

Inside the slave chip 102, it also includes the SRAM block 120 and the slave interface 200S. The SRAM block 120 is connected to the slave interface 200S for communication with the master die 100 . During communication, the master interface 200M and the slave interface 200S are connected through the combining structure 104 . Depending on the packaging process, the bond structures 104 may include TSVs with mixed bond patterns. The connection is bidirectional. The bond pattern may generally correspond to a data bus. All signals are transmitted or received in parallel. In one example, the clock rate may be 2.5 GHz. The signal latency between the master die 100 and the slave die 102 through the interface of the master interface 200M and the slave interface 200S is reliable, and may be about 2 ns by way of example.

5 is a diagram schematically illustrating a 3D communication mechanism of an interface between a master die and a slave die, according to an embodiment of the present invention. Referring to FIG. 5 , the master wafer 100 and the slave wafer 102 in a 3D structure are shown in more detail as an example based on the operating mechanism as previously described. The host chip 100 (eg, a processor) includes a host interface 200M, and the host interface 200M includes a bonding structure 104M. The bond structure 104M of the example includes a bond pattern, which in one example consists of a plurality of bonds. Thus, depending on the data size of the bus, the bonds are formed in an array, where one bond pad 150 corresponds to a set of binary data (eg, 16-bit data with voltage bonds, clock bonds, and other specified bonds) ). The plurality of bonding sheets 150 form the entire bonding pattern of the main interface 200M. As mentioned above, data from the processor is in two-way communication with the main interface 200M.

Likewise, slave chip 102 may include SRAM and slave interface 200S. The SRAM communicates with the slave interface 200S, and the slave interface 200S communicates with the master interface 200M through the connection of the bonding structure 104S. The bonding structure 104S is also composed of a plurality of bonding elements arranged in an array into a bonding element pattern. The joints are each represented by a square element. Likewise, the bond pattern is also divided into a plurality of bond pieces 150 . In the 3D packaging technology, the master interface 200M and the slave interface 200S are connected by the bonding structure 104M and the bonding structure 104S having matching bonding member patterns. Therefore, based on the 3D packaging technology, the master interface 200M and the slave interface 200S are connected as a complete interface to have communication between the master chip 100 and the slave chip 102 . As described above, a plurality of slave wafers 102 are stacked on top of the master wafer 100, wherein the master interface 200M and the slave interface 200S are connected together in a vertical direction.

The circuits of the master interface 200M and the slave interface 200S are described as follows. 6 is a diagram schematically illustrating a circuit structure of an interface between a master wafer and a slave wafer according to an embodiment of the present invention.

6, the master interface 200M of the master chip 100 and the slave interface 200S of the slave chip 102 are described using the implemented circuit. For the main interface 200M, it includes a flip-flop (FF) block 202 to receive commands intended by the core circuitry of the main die 100 . Commands as input in the example may include data clusters tx_data and/or command, without specific limitations. The number of flip-flop blocks 202 may be one unit (FF) or more units (FFs) according to actual needs, and there is no limitation here. Commands from master chip 100 in the example may include command and data clusters to be transmitted. The command may also include a select slave identification for selecting the slave wafer 102 to execute the command from the master wafer 100 .

Multiplexer 206 receives the output of flip-flop block 202 . According to the input data at the flip-flop block 202, the multiplexer 206 in the example is a double data rate (DDR) type. The output of the multiplexer 206 is passed to the corresponding bond of the bond pattern 208 in the main interface 200M.

As described above, a single clock clk is provided into the slave chip 102 through the master interface 200M and the slave interface 200S. The flip-flop block 202 and the multiplexer 206 are timing controlled by the clock clk_in. In the master interface 200M, the flip-flop block 202 and the master multiplexer 206 form a transfer path to transfer commands to the slave die 102 .

The master interface 200M also includes receive paths to receive responses from the slave chip 102 through the slave interface 200S and the master interface 200M having corresponding bond portions of the bond pattern 208 . A first-in-first-out (FIFO) block 204A receives responses from slave interface 200S. The FIFO block 204A in the example includes a plurality of flip-flop cells 204 . The output of the FIFO block 204A is provided to another flip-flop block 210 and then passed inward to the core of the host die 100 . The flip-flop block 210 is timing controlled by the clock clk_in. The FIFO block 204A is controlled by the feedback clock from the slave die 102, which has an enable control corresponding to the response data from the slave die 102.

In the example of a read operation, the command of the master wafer 100 is received by the flip-flop block 202 of the master interface 200M. The selected slave chip 102 responds with the requested data to the FIFO block 204A of the master interface 200M.

In the slave interface 200S of the wafer 102 , the bond pattern 220 corresponds to the bond pattern 208 . The command from the master die 100 is then received by the flip-flop block 222, which also controls the clock clk. The flip-flop block 222 in the slave interface 200S then further transmits commands, such as rx_data and/or command, to the SRAM interior of the slave die 102 . In one example, the master chip 100 sends commands to read data from the SRAM of the slave chip 102 .

Slave die 102 then provides the data cluster requested from master die 100 into circuit block 230, which is also indicated by tx_data arriving at slave die 102 in one example. Circuit block 230 is also controlled by clock clk and enable signal tx_en. Circuit block 230 includes flip-flop block 224, enable flip-flop block 224a, slave multiplexer 226, and output control blocks 228a, 228b.

The clock signal clk for control in each slave interface 200S is also provided to the third flip-flop block 222, the fourth flip-flop block 224, the slave multiplexer 226, the enable flip-flop block 224a, and the output control block 228a.

The flip-flop block 224 outputs the data to the slave multiplexer 226 and then to the output control block 228b. The enable flip-flop block 224a receives the enable signal tx_en and the clock signal clk and provides control signals to control the output control block 228a. Then, the material provided by the slave wafer 102 is transferred to the master wafer 100 through the bond portion of the bond pattern 220 .

In order to properly sequence the clock signal clk in response to the master die 100, another output control block 228b also receives the raw clock clk and is controlled by the enable signal from the enable flip-flop block 224a.

The data output from the slave interface 200S is then received by the FIFO block 204A in the master interface 200M. For the main interface 200M, the data rx_data is the response from the chip 102 to a command, such as command.

In an embodiment, there are multiple slave wafers 102 stacked on top of the master wafer 100 . Commands from master wafer 100 are sent to the owner in slave wafer 102 . In this case, the command from the master wafer 100 also includes a select slave flag for selecting the slave wafer 102 to execute the command from the master wafer 100 . The slave interface 200S also includes the ability to identify the selected slave identification code. Each of the slave interfaces 200S has its own identification code. One of the slave interfaces 200S matching the selected slave identification code will be activated to respond to the command from the master die 100 at the time slot allocated by the master command. Interference from wafers can be effectively avoided.

7 is a diagram schematically illustrating a circuit structure of an interface between a master wafer and a slave wafer, further in accordance with an embodiment of the present invention. 7, the connection between the slave interface 200S and the SRAM 120 in the example is further explained.

In one example, command 300 may include command, address, write data, and select slave identification. The data rx_data from the flip-flop block 222 of the interface 200S is output to the SRAM 120 . However, the slave interface 200S may further include the logic circuit 130 and the fifth flip-flop block 132 . The logic circuit 130 also receives the command output from the third flip-flop block 222, such as data rx_data, to determine the type signal of command/read_data/write_data (CS/RD/WR) and An initial enable signal is also generated to the fifth flip-flop block 132, which in turn outputs the enable signal to the enable flip-flop block 224a. The SRAM 120 receives the CS/RD/WR type signals in response to commands from the host chip 100 . Once the command is completed from the chip 102 (eg, SRAM 120 ), the result of the read command (eg, data rd_data) is responded to the slave interface 200S as the input data tx_data of the slave interface 200S.

As further shown, in structures of the present invention that include interfaces connected to multiple slave wafers 102 (eg, 16 slave wafers), write commands and read commands may overlap and then execute concurrently. Except for some reserved bits, the size of the data bus can have 256 bits. The master bond pattern 208 and the slave bond pattern 220 have the master interface 200M and the many bonds required to transmit data signals in the slave interface 200S, which are grouped into a plurality of bond sheets 150S, 150M, as described next in shown in Figure 8. In addition, the bonding sheet 170 shown in FIG. 8 may also be included to transmit other control signals for actual operation.

Since 3D packaging technology allows multiple wafers to be stacked, the bonds are located at the face surfaces of the wafers. However, the TSV structure is included to extend the bond at the face surface to the back surface of the wafer. To form stacked wafers, the two wafers may alternatively be electrically connected at the bond pattern by face-to-face or face-to-back.

FIG. 8 is a diagram schematically illustrating a communication mechanism of an interface having a bond pattern, according to an embodiment of the present invention. Referring to FIG. 8 and also referring to FIG. 5 , the main bond pattern 208 of the main interface 200M includes a plurality of bonds 152 . The bonding pieces 152 may be grouped into a plurality of bonding pieces 150 as seen in FIG. 5 in the embodiment, wherein the bonding pieces 150 belonging to the master interface 200M may also be referred to as bonding pieces 150M and the bonding pieces 150 belonging to the slave interface 200S may also be referred to as bonding pieces 150M. It is called the bonding sheet 150S. Taking the bonding chip 150M as an example, one bonding chip 150M includes a set of bonding elements, and in one example, the group of bonding elements is used to transmit a set of data signals, voltage signals, data parity signals and control signals. The data signal in the example includes, but is not limited to, 16-bit data. The voltage bonds 154M, 156M may include a system high voltage (eg, VDD) and a ground voltage (eg, VSS). A bond having constant function to transmit voltage signals, data parity signals, and control signals may be referred to as functional bond 158M, which includes voltage bonds 154M, 156M and is located in a central row in one bond pad 150M place. In other words, one bond pad 150S may include a central row of bonds with functional bonds 158S including voltage bonds 154S, 156S. The data bond 152 for transmitting the data signal can be divided into two parts of the data row that are geometrically symmetrical with respect to the central row. Details will be explained later.

In an embodiment, depending on the operation of the interface, a bonding pad 170 may also be included for transmitting or receiving various control signals as needed in the operation between the master wafer 100 and the slave wafer 102 , wherein the bonding pad 170 may A clock signal, indicated by a thin arrow, is included for transmission or reception. Arrow 160 represents the vertical connection at the bond pattern 208 of the master interface 200M and the bond pattern 220 of the slave interface 200S for passing through the bond pattern 208 in the master interface 200M and the bond pattern in the slave interface 200S 220 communicates between the master die 100 and the slave die 102 . For the master interface 200M, the thick inward arrows represent commands issued from the master device (eg, the processor). The command is transmitted vertically down to the slave device through the bond pattern 208 of the master interface 200M and the bond pattern 220 of the slave interface 200S. The bold arrows on the output indicate the transfer of commands to a slave device, such as SRAM. The slave interface 200S then receives data from the slave device according to the command, and then transmits the data to the master interface 200M, which provides the data to the master device as indicated by the thick arrow with the output direction.

The bonding sheets 150M, 150S are configured to have a central row and a data row divided into two parts located at opposite sides of the central row in symmetrical positions. This configuration of bonds may allow for easy encapsulation of the master wafer with the plurality of slave wafers in a face-to-face, face-to-back, and back-to-back manner, with or without flipping the bonds of the bond patterns 208, 220 to Adapt to a face-to-face, face-to-back or back-to-back approach.

In the preceding description, the interface is well set up. The slave wafer 102 may also include management circuitry to manage the address of the slave wafer. The addresses of the slave wafers can be set slave wafer by slave wafer. The total number of slave wafers can also be detected. Since the operation commands from the master wafer are transferred from one slave wafer to another, the master wafer does not need to have a high drive capability. In one example, the master wafer may be designed to only pass operational commands of the zeroth order of the slave wafer. However, currently it is sufficient for the slave wafer to only drive the next slave wafer. Thus, slave wafer after slave wafer can be activated until a target slave wafer is identified. Additionally, management commands will stop being passed to the remaining slave wafers. The number of slave wafers can be increased more flexibly.

9A is a diagram schematically illustrating a management mechanism for addressing slave wafers through an interface in an initialization phase, according to an embodiment of the present invention. Referring to Figure 9A, slave wafers SO, S1 may be stacked in a face-to-face, face-to-back, or back-to-back configuration, as the front side is indicated by F and the back side is indicated by B. Bond 400 with TSV 402 involves a master/slave interface to stack the chips as previously described. For example, the number of slave wafers S0, S1 is two, but the present invention is not limited to the number of slave wafers. Take the master wafer M as an example to communicate with the slave wafers S0, S1.

In an embodiment, each of the slave wafers SO, S1 includes a management circuit 500 . The management circuit 500 also includes a comparison circuit 500a. In an embodiment, the master chip M may issue an operation command 404, in an embodiment, the operation command 404 includes a slave set address in an initialization phase or a slave target address in an actual operation. Operation command 404 is communicated through bond 400 of the interface to slave wafer SO, which also acts as the zeroth order slave wafer.

In operation, in the initialization phase, all slave wafers SO, S1 may be counted and assigned addresses set for all slave wafers SO, S1. Then, in actual operation, the slave wafers S0 and S1 can respond to the data requested by the master wafer M according to the actual operation command, or only transmit the command to the next slave wafer until the target slave wafer is reached. Additionally, the command will stop passing the command to the next slave wafer.

First, the management mechanism in the initialization phase is described. During the initialization phase, the master die M may issue operation commands 404 by issuing a sequence of slave set addresses 406 by the master die M in the initialization phase, wherein the sequence of slave set addresses 406 is incremented by one at a time. The slave set address 406 of the operation command 404 is received by the management circuit 500 of the slave wafer SO, which is in the zeroth stage in one example. If the address of the slave wafer S0 has not been set, the slave wafer S0 takes the slave set address 406 of the operation command 404 as its set address. From the set address 406 it can start from 0 up to a certain digit by incrementing by one at a time. The total number of slave wafers can also be found at the end of the initialization phase. In an embodiment, from set address 406 to "0" the first time and "1" the next time, the increment is 1, and then "2", "3", . . . , and so on. If the set address of slave wafer SO has been set, slave wafer SO may pass the address from set address 407 to the next slave wafer in slave wafer SO according to enable signal 408, which indicates that the address of S0 has been set .

FIG. 9B is a diagram schematically illustrating a management mechanism responding to a master device through an interface in an initialization phase, according to an embodiment of the present invention. Referring to FIG. 9B , in the initialization phase, the master wafer M may need to count the slave wafers actually stacked on the master wafer M. FIG. The management circuit 500 also includes a multiplexing circuit 500b to pass signals back to the main die M. In the initialization phase, the management circuit 500 may respond with the response data 410 to the master chip M to at least ensure that a current one of the slave chips exists at the master chip M. According to the enable signal 408, the response 414 after the multiplexing circuit 500b is transmitted to the main chip M as the response data 416 through the bonding element 400 of the interface.

Two scenarios are expected to follow. In the first case, the next slave wafer S1 may still need to be addressed. The second case is that the current slave wafer is the last slave wafer in the stack of slave wafers, and the total number of slave wafers will be determined.

For the first case, in the embodiment, the master wafer M knows that the slave wafer S1 is still stacked on top of the slave wafer SO, and then issues the next slave set address "1", which is incremented by one from "0" . Using the mechanism described earlier, the slave set address 407 that is "1" is greater than or equal to the address of the slave wafer SO that has been set to "0", and then the comparison circuit 500a will only be the slave set address of "1" 407 is passed to the next slave wafer S1 as the slave set address 406 for slave wafer S1. Since the address is already set, the address of the slave wafer S0 is not set. The comparison and response mechanism is the same for each slave wafer SO, S1.

Therefore, the master chip M receives the response from the slave chip S1. In one example, the master chip M issues the slave set address 406 with the content "2". Since the slave set address 406 whose content is "2" is greater than or not equal to the slave set address 406 of slave wafer S0 which is "0" and the slave set address 406 of slave wafer S1 which is "1", the slave set address 406 of slave wafer S1 is "1". The slave set address 406 with "2" in it does not set the address of the slave wafer S1, but attempts to pass to the bond 400 at the top. In an embodiment, no further slave wafers are stacked on top of slave wafer S1. Master chip M will not receive a response. Then, as the second case, the master wafer M knows that the slave wafer S1 in the embodiment is the last slave wafer S1. Then, the number of slave wafers S0, S1 is determined. In addition, the addresses of the slave wafer S0 and the slave wafer S1 are set by incrementing by one. Here, the increment is not necessarily one, and may be 2, 3, or other increment values depending on the actual design.

It should also be noted that the incremental addresses assigned to the slave wafers are examples only. Depending on the detection mechanism employed, other mechanisms may be employed to assign the addresses of the slave wafers. However, address commands are passed from die to die without the need to transmit address commands to all of the slave dies at the same time. In other words, the master wafer does not need to issue address commands with high drive capability to reach all slave wafers or the maximum number of slave wafers simultaneously. In the present invention, it is sufficient that the current slave wafer only drives the next slave wafer. Then, the number of slave wafers is more flexible without limiting the driving capability of the master wafer.

Once the initialization phase is complete, all slave wafers have been assigned identification (ID) addresses and the total number of slave wafers is also known to the master wafer M. The master wafer can also reach the target slave wafer based on the management circuit 500 . 10A is a diagram schematically illustrating a management mechanism for addressing slave wafers through an interface in an operational phase, according to an embodiment of the present invention. 10B is a diagram schematically illustrating a management mechanism responding to a master device through an interface in an operational phase, according to an embodiment of the present invention.

10A, when the master wafer M issues an operation command 404' having a slave target address to access the target slave wafer SO, the operation command 404' is transmitted to the slave wafer SO through the bond 400. The comparison circuit 500a of the management circuit 500 again compares the slave set address 406' of the operation command 404' with the wafer address, such as 0, to which the slave wafer SO is assigned. In one example, the slave set address 406' may be 0 or 1. If the slave set address 406' is 0, the comparison circuit 500a of the management circuit 500 recognizes that the slave chip S0 will be accessed by the master chip M, and stops the transfer from the set address 406' to the next according to the state of the enable signal 408'. one from wafer S1.

Referring to FIG. 10B , in an embodiment, the management circuit 500 will activate the slave chip SO to respond to the response data 410' requested by the master chip M. The multiplexing circuit 500b transmits the response data 410' as the response 414', and the response 414' is transmitted back to the main chip M through the bonding member 400 as the actual response data 416' of the main chip M. Here, the enable signal 408' as a result from the compare circuit 500a will control the multiplexer circuit 500b to pass the response data 410', but not the previous response 412', since the slave set address 406' stops being passed to the slave chip S1 And the slave set address 407' is not generated to drive or start the slave chip S1, so the previous response 412' does not actually exist. In this case, the slave wafer S1 is blocked.

In yet another case where the slave set address 406' is 1, the management circuit 500 determines that the slave set address 406' which is a 1 is greater than or not equal to the slave wafer address of the slave wafer S0, which is a 0, and the slave wafer SO is regarded as a 0. The current one of the slave wafers. The management circuit 500 then simply passes the slave set address 407' to the next slave wafer S1 considered to be the next slave wafer among the slave wafers. At this stage, the multiplexing circuit 500b of the management circuit 500 in FIG. 10B is set up to be ready to pass the response data 412' according to the enable signal 408'.

In this case, slave wafer S1 will recognize that slave wafer S1 is the target slave wafer for operation command 404'. The multiplexing circuit 500b of the management circuit 500 selects the response data 410' to the slave chip S0 by the enable signal 408' in the multiplexing circuit 500b according to the state of the enable signal 408' in the slave chip S1, and through multiplexing Circuit 500b is passed back to slave wafer SO. The state of the enable signal 408' in the slave chip S0 controls the multiplexer circuit 500b in the slave chip S0 to select the response data 412' as the master chip M's response data 414'. In other words, the multiplexer circuit 500b will select the response data 412' previously transmitted from the slave wafer S1 or select the response data 410' currently prepared in the slave wafer SO according to the enable signal 408' to continue to transmit back to the master wafer M.

In this mechanism, the slave wafers are driven one after the other, where all the slave wafers are not always enabled. In this case of an embodiment, the slave wafer behind the target slave wafer would not need to be activated.

According to the foregoing description, in one access operation, all of the slave wafers may not be activated. Boot from wafer until target is from wafer. Signals can be delivered on a wafer-by-wafer basis. The signal bus may not pass through the entire slave wafer globally, but may pass wafer by wafer.

It will be apparent to those skilled in the art that various modifications and variations of the disclosed embodiments can be made without departing from the scope or spirit of the present disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations provided that fall within the scope of the above claims and their equivalents.

10: 3D Semiconductor Devices 20, 30: Substrate 22, 32: circuit layer 24, 34: circuit chip 26, 36, 402: TSV structure 38, 400: Combined parts 40: Interface area 100, M: main chip 102, S0, S1: slave wafer 104, 104M, 104S: binding structures 110: Central processing unit block 112: Cache memory block 120: SRAM block 130: Logic Circuits 132: Fifth flip-flop block 150, 150S, 150M, 170: Combined sheet 152: Bonding pieces 154M, 154S, 156M, 156S: Voltage combination 158M, 158S: functional combination 160: Arrow 200. Glink-3D: Interface 200M: main interface 200S: From the interface 202, 210: Flip Flop (FF) Block 204: Trigger Unit 204A: First in, first out (FIFO) block 206: Multiplexer 208: Bonding pattern 220: Bonding pattern 222: Trigger Block 224: Trigger Block 224a: Enable flip-flop block 226: slave multiplexer 228a, 228b: output control block 230: Circuit Blocks 300: command 404, 404': Operation command 406, 406', 407, 407': from the set address 408, 408': enable signal 410, 410', 416, 416': response data 412', 414': Response 414: Response 500: Management Circuit 500a: Comparison Circuit 500b: Multiplexing Circuits clk: clock clk_in: clock command: command CS/RD/WR: command/read_data/write_data rd_data: data rx_data: data tx_data: data tx_en: enable signal

FIG. 1 is a diagram schematically illustrating a cross-sectional stack structure of a 3D semiconductor device according to an embodiment of the present invention. 2 is a diagram schematically illustrating a cross-sectional stack structure of a 3D semiconductor device with an interface according to an embodiment of the present invention. 3 is a diagram schematically illustrating a see-through stack structure of a 3D semiconductor device with a communication mechanism of an interface, according to an embodiment of the present invention. 4 is a diagram schematically illustrating a communication mechanism of an interface between a master die and a slave die, according to an embodiment of the present invention. 5 is a diagram schematically illustrating a 3D communication mechanism of an interface between a master die and a slave die, according to an embodiment of the present invention. 6 is a diagram schematically illustrating a circuit structure of an interface between a master wafer and a slave wafer according to an embodiment of the present invention. 7 is a diagram schematically illustrating a circuit system structure of an interface between a master die and a slave die, according to an embodiment of the present invention. FIG. 8 is a diagram schematically illustrating a communication mechanism of an interface having a bond pattern, according to an embodiment of the present invention. 9A is a diagram schematically illustrating a management mechanism for addressing slave wafers through an interface in an initialization phase, according to an embodiment of the present invention. FIG. 9B is a diagram schematically illustrating a management mechanism responding to a master device through an interface in an initialization phase, according to an embodiment of the present invention. Figure 10A is a diagram schematically illustrating a management mechanism for addressing slave wafers through an interface in an operational phase, according to an embodiment of the present invention. 10B is a diagram schematically illustrating a management mechanism responding to a master device through an interface in an operational phase, according to an embodiment of the present invention.

400: Combined piece 400

402:TSV

404: Operation command

406: from the set address

407: from set address

408: enable signal

500: Management Circuit

500a: Comparison Circuit

M: main wafer

S0, S1: slave wafer

Claims (16)

A semiconductor device having an interface, comprising: the main device, including the main interface; and a plurality of slave devices, stacked one after the other in a three-dimensional (3D) stack on the master device, wherein each of the slave devices includes a slave interface and a management circuit, the master interface and the slave interface forming the interface for communicating communication signals between the master device and the slave device, wherein the management circuit of the current one of the slave devices drives the next one of the slave devices, wherein an operation command received at the current one of the slave devices is passed to the next one of the slave devices only through the interface, wherein the response from the current one of the slave devices is communicated back to the master device through the interface. The semiconductor device of claim 1, wherein during an initialization phase, the operation command including a slave set address in an incremental sequence is issued by the master device to set each of the slave devices from address. The semiconductor device as claimed in claim 2, Wherein, when the address of the previous slave device in the slave devices has not been set, the management circuit sets the slave setting address of the current slave device in the slave devices and passes the interface. sending the response to the master, wherein when the address of the previous one of the slave devices has been set, the management circuit of the previous one of the slave devices transmits the slave set address to the the next slave in the slave device. The semiconductor device of claim 3, wherein when the master device does not receive a response to the command from the slave device to increment the slave set address, the master device determines that the stack is on the master device. The number of said slaves on the device. The semiconductor device as claimed in claim 3, wherein the management circuit includes a comparison circuit to compare the slave set address with the slave address set to the current one of the slave devices, Wherein, when the slave setting address is not equal to the slave address of the previous slave device in the slave device, the management circuit transfers the slave setting address to the slave device in the slave device. the next slave, Wherein the management circuit sets the slave setting address as the slave address of the current one of the slave devices. The semiconductor device of claim 1, wherein during an operation phase, the operation command including a slave target address is issued by the master to a target slave device of the slave devices, and the management circuit converts all The slave target address is compared with the current slave address of the slave device. The semiconductor device as claimed in claim 6, wherein when the slave target address is not equal to the slave address of the previous slave device in the slave device, the management circuit transfers the slave target address to all slave devices in the slave device. the next slave device; Wherein, when the slave target address is equal to the slave address of the previous slave device in the slave devices, the management circuit stops transmitting the slave target address. The semiconductor device of claim 7, wherein each of the management circuits includes multiplexing circuits under control to communicate response data from the current one of the slave devices, or only Passes the response data from the previous one of the slaves. A management method of a semiconductor device having an interface, wherein the semiconductor device includes a master device and a plurality of slave devices stacked one after another in a three-dimensional (3D) stack on the master device, the management method comprising: configuring the host device to have a host interface; and configuring each of the slave devices to have a slave interface and a management circuit, the master interface and the slave interface forming the interface for communicating communication signals between the master device and the slave device , wherein the management circuit of the current one of the slave devices drives the next one of the slave devices, wherein an operation command received at the current one of the slave devices is passed to the next one of the slave devices only through the interface, wherein the response from the current one of the slave devices is communicated back to the master device through the interface. The management method of a semiconductor device with an interface as claimed in claim 9, wherein during an initialization phase, the operation command including a slave set address in an incremental sequence is issued by the master device to send the slave device Each of these sets the slave address. The management method of a semiconductor device with an interface as claimed in claim 10, further When the address of the previous one of the slave devices has not been set, the management circuit is configured to set the slave set address of the previous one of the slave devices and through all the interface sends the response to the master device, When the address of the previous one of the slave devices has been set, the management circuit of the previous one of the slave devices is configured to pass the slave set address to the the next one of the slave devices. The management method of a semiconductor device with an interface according to claim 11, wherein when the master device does not receive a response to the command from the slave device to increment the slave set address, the master device The number of the slave devices stacked on the master device is determined. The management method of a semiconductor device with an interface according to claim 11, further configuring the management circuit to have a comparison circuit to compare the slave setting address with the current one of the slave devices set as the slave device The slave address of the device is compared, Wherein, when the slave setting address is not equal to the slave address of the previous slave device in the slave device, the management circuit transfers the slave setting address to the slave device in the slave device. next slave; Wherein, when the slave address has not been set, the management circuit sets the slave setting address as the slave address of the current one of the slave devices. The management method of a semiconductor device with an interface as claimed in claim 9, wherein during an operation phase, the operation command including a slave target address is issued by the master to a target slave device of the slave devices, and The management circuit compares the slave target address with the slave address of the slave device. The management method of a semiconductor device with an interface as claimed in claim 14, further comprising: configuring the management circuit to pass the slave target address into the slave device when the slave target address is not equal to the slave address of the previous one of the slave devices the next slave device of ; and The management circuit is configured to stop communicating the slave target address when the slave target address is equal to the slave address of the previous one of the slave devices. A method of managing a semiconductor device with an interface as recited in claim 15, wherein each of the management circuits is configured to include a multiplexing circuit under control to communicate the current from the slave devices Response data from one slave device, or just pass the response data from the previous one of the slave devices.

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