TW202215119A - Display - Google Patents

Abstract

A display includes a plurality of scan lines, a plurality of data lines, a pixel array, a plurality of first fan-out traces, a plurality of first signal lines and a plurality of pads. The scan lines extend in a first direction, and the data lines extend in a second direction, where the first direction is not parallel with the second direction. The pixel array is connected to the scan lines and the data lines. Each first fan-out trace is electrically connected to a data line. The extension direction of each first fan-out trace is not parallel with the first direction. Each first signal line includes a first segment, a second segment, and a first linking structure. The first segment is connected to one end of the first fan-out trace, and the first linking structure is connected to the first segment and the second segment. The first segment and the second segment both extend in the second direction. The second segment of each first signal line is electrically connected to a pad.

Description

monitor

The present invention relates to a display, and more particularly, to a display having fan-out traces.

At present, some displays, such as liquid crystal displays, use conductive adhesive to adhere the driving element on the pixel array substrate, and electrically connect the driving element to the plurality of pads of the pixel array substrate, so that the driving element can control the pixel array substrate . In the actual manufacturing process of the display, the driving elements are sometimes not adhered to the correct positions, so that the driving elements are not electrically connected to the corresponding pads. At this point, the staff will separate the combined driving elements from the pixel array substrate. Then, the driving element is re-adhered to the pixel array substrate by using the conductive adhesive, so that the driving element is adhered to the correct position, so as to electrically connect the corresponding pads.

During the process of re-adhering the driving element on the pixel array substrate, the conductive adhesive previously remaining on the pixel array substrate needs to be removed, so that the surface of the pixel array substrate is clean and flat. Otherwise, the residual conductive adhesive will make the surface of the pixel array substrate uneven, thereby hindering the electrical connection between the driving element and the pixel array substrate. In detail, the residual conductive adhesive will hinder the connection between the driving element and the pad, so that the driving element cannot be electrically connected to the corresponding pad, resulting in an open circuit.

The above-mentioned residual conductive glue is usually removed by the staff with a sharp tool, such as a toothpick. However, the residual conductive adhesive usually covers the circuit structure of the pixel array substrate, and the above-mentioned sharp tools are prone to inadvertently damage the fragile part of the circuit structure, and even damage the circuit structure in severe cases, resulting in the entire pixel array substrate being damaged forced to scrap.

At least one embodiment of the present invention provides a display to reduce or prevent the vulnerable parts of the circuit structure from being covered with conductive glue.

A display proposed in at least one embodiment of the present invention includes a substrate, a plurality of parallel scan lines, a plurality of parallel data lines, a pixel array, a plurality of first fan-out lines, a plurality of parallel first signal lines, and a plurality of a pad. The substrate has a display area and a non-display area other than the display area. The scan lines are arranged on the substrate and extend along the first direction. The data lines are disposed on the substrate and extend along the second direction, wherein the first direction is not parallel to the second direction. The pixel array is disposed on the substrate and located in the display area, wherein the pixel array connects the scan lines and the data lines. The first fan-out traces are disposed on the substrate and located in the non-display area, wherein each of the first fan-out traces is electrically connected to one of the data lines, and the extension direction of each of the first fan-out traces not parallel to the first direction. The first signal lines are disposed on the substrate and located in the non-display area. Each of the first signal lines includes a first line segment, a second line segment and a first switching structure. The first line segment connects one end of one of the first fan-out traces, and the first transition structure connects the first line segment and the second line segment, wherein the first line segment and the second line segment both extend along the second direction . The pads are disposed on the substrate and are located in the non-display area, wherein the second line segments of each of the first signal lines are electrically connected to one of the pads.

In at least one embodiment of the present invention, a shortest distance between the pads and the first transfer structures is greater than or equal to 300 μm, and an average distance between the pads and the first transfer structures is greater than 500 μm microns.

In at least one embodiment of the present invention, there is a shortest distance between at least one of the two outermost first transition structures and the pads.

In at least one embodiment of the present invention, the first transition structures are not arranged along the first direction and the second direction.

In at least one embodiment of the present invention, there is a shortest distance between at least one of the two outermost first transfer structures and the pads, and a distance between any one of the first transfer structures and the pads The distance is greater than or equal to the shortest distance.

In at least one embodiment of the present invention, the non-display area includes a first area and a second area. The first area is adjacent to the second area, and both the first area and the second area are arranged along the first direction. The first signal lines are located in the first area and the second area. The first transition structures located in the first area are arranged along a first straight line, and the first transition structures located in the second area are arranged along a second straight line. The first straight line and the second straight line are not parallel, and neither the first straight line nor the second straight line is parallel to the first direction and the second direction.

In at least one embodiment of the present invention, the non-display area includes a first area, a second area, and a central area. The central area is located between the first area and the second area, and the first area, the central area and the second area are all arranged along the first direction. The first signal lines are located in the first area, the second area and the central area, wherein the first switching structures located in the first area are arranged along a first straight line, and the first switching structures located in the second area The connecting structures are arranged along a second straight line, wherein the first straight line and the second straight line are not parallel, and neither the first straight line nor the second straight line is parallel to the first direction and the second direction. In addition, the first transition structures located in the central area are arranged along the first direction.

In at least one embodiment of the present invention, the above-mentioned display further includes a plurality of second fan-out traces and a plurality of parallel second signal lines. The second fan-out wires are disposed on the substrate and located in the non-display area, wherein each of the second fan-out wires is electrically connected to one of the data wires. The second signal lines are disposed on the substrate and located in the non-display area, wherein the second signal lines are respectively connected to one end of the second fan-out lines, and each second signal line is electrically connected to one of the pads.

In at least one embodiment of the present invention, the non-display area includes a first area, a second area, and a central area. The central area is located between the first area and the second area, and the first area, the central area and the second area are all arranged along the first direction. The first signal lines are located in the first area, the second area and the central area, wherein at least one of the first line segments located in the central area has a first impedance regulating arch.

In at least one embodiment of the present invention, the second signal lines are located in the first area, the second area and the central area, wherein at least one second signal line located in the central area has a second impedance regulating arch.

In at least one embodiment of the present invention, the above-mentioned display further includes a plurality of second switching structures and a plurality of third signal lines. The second switching structures are respectively connected to the second line segments and the second signal lines. The third signal lines are respectively connected between the second transfer structures and the pads.

In at least one embodiment of the present invention, the above-mentioned display further includes a driving element, wherein the driving element is mounted on the pads.

In at least one embodiment of the present invention, the above-mentioned display further includes conductive adhesive, wherein the conductive adhesive is distributed in an area between the first transfer structures and the pads, and covers at least a part of each of the second line segments and the connection pads. pad.

Using the above-mentioned display design of at least one embodiment of the present invention can help reduce or avoid the fragile part of the circuit structure (such as the first transition structure) being covered with conductive adhesive, so that the staff can use sharp tools to remove the residual conductive adhesive during the process of removing the conductive adhesive. In order to reduce or avoid the fragile part of the above-mentioned circuit structure being damaged by sharp tools.

In the following text, the dimensions (such as length, width, thickness and depth) of elements (such as layers, films, substrates and regions, etc.) in the drawings are exaggerated in unequal proportions in order to clearly present the technical features of the present application. . Therefore, the descriptions and explanations of the following embodiments are not limited to the dimensions and shapes of the elements in the drawings, but should cover the dimensions, shapes and deviations caused by actual manufacturing processes and/or tolerances. For example, the flat surfaces shown in the figures may have rough and/or non-linear features, while the acute angles shown in the figures may be rounded. Therefore, the elements shown in the drawings in this application are mainly for illustration, and are not intended to accurately depict the actual shapes of the elements, nor are they intended to limit the scope of the patent application of this application.

Secondly, words such as "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated numerical value and numerical value range, but also cover the understanding of those with ordinary knowledge in the technical field to which the invention belongs. The allowable deviation range of , wherein the deviation range can be determined by the error generated during measurement, for example, the error is caused by the limitations of both the measurement system or the process conditions. For example, two objects (such as planes or traces of a substrate) are "substantially parallel" or "substantially perpendicular", where "substantially parallel" and "substantially perpendicular" represent the parallel and perpendicular relationship between the two objects, respectively It can include non-parallel and non-perpendicular caused by the tolerance range.

Further, "about" can mean within one or more standard deviations of the above-mentioned numerical value, eg, within ±30%, ±20%, ±10%, or ±5%. Words such as "about", "approximately" or "substantially" appearing in this text may be used to select acceptable ranges or standard deviations based on optical properties, etching properties, mechanical properties or other properties, not a single Standard deviation to apply all of the above optical, etch, mechanical and other properties.

FIG. 1A is a schematic top view of a display according to at least one embodiment of the present invention. Referring to FIG. 1A , the display 100 includes a substrate 110 , a plurality of parallel scan lines 120 , a plurality of parallel data lines 130 and a pixel array 140 . The scan lines 120 , the data lines 130 and the pixel array 140 are all disposed on the substrate 110 , wherein the substrate 110 may be a transparent plate, such as a glass plate or a transparent plastic plate.

The scan lines 120 extend along the first direction D1, and the data lines 130 extend along the second direction D2. In other words, the main body of each scan line 120 is substantially parallel to the first direction D1 , and the main body of each data line 130 is substantially parallel to the second direction D2 . In addition, the first direction D1 is not parallel to the second direction D2. Taking FIG. 1A as an example, the first direction D1 is a horizontal direction, and the second direction D2 is a vertical direction, so the first direction D1 and the second direction D2 may be substantially perpendicular to each other. Therefore, the scan lines 120 and the data lines 130 are interlaced with each other and arranged in a mesh shape, as shown in FIG. 1A .

The substrate 110 has a display area 111 and a non-display area 112 outside the display area 111 . The pixel array 140 is located in the display area 111 and connects the scan lines 120 and the data lines 130 . The pixel array 140 includes a plurality of control elements 141 and a plurality of pixel elements 142 , wherein the control elements 141 are electrically connected to the pixel elements 142 respectively. In the embodiment shown in FIG. 1A , the control element 141 may be a transistor, such as a thin film transistor (Thin-Film Transistor, TFT, TFT). In addition, the control element 141 in FIG. 1A is represented by the circuit symbol of a transistor.

Display 100 may be one of several types of displays. For example, the display 100 may be a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode Display (OLED Display), or a Micro LED Display (μLED Display). Depending on the type of the display 100 , the pixel element 142 may have various implementations.

When the display 100 is a liquid crystal display, the display 100 may further include a liquid crystal layer (not shown) and an opposite substrate (not shown), and the pixel element 142 may be a pixel electrode, which is formed of, for example, a transparent conductive film , wherein the main material of the transparent conductive film can be a metal oxide, such as indium tin oxide (Indium Tin Oxide, ITO) or indium zinc oxide (Indium Zinc Oxide, IZO). The opposite substrate is disposed relative to the substrate 110, and the liquid crystal layer is sandwiched between the substrate 110 and the opposite substrate, wherein the opposite substrate may be a color filter substrate. When the display 100 is an organic light emitting diode display or a micro light emitting diode display, the pixel element 142 may be an organic light emitting diode or a micro light emitting diode.

In the embodiment shown in FIG. 1A , the control element 141 is a transistor (such as a thin film transistor), and each control element 141 has a gate, a source and a drain (the gate, source and drain are not indicated in FIG. 1A ) ). The scan lines 120 are electrically connected to the gates of the control elements 141 , the data lines 130 are electrically connected to the sources of the control elements 141 , and the drains of the control elements 141 are electrically connected to the pixel elements 142 respectively.

It can be seen that the voltages transmitted by the scan lines 120 can turn on and off the control elements 141 to control the data lines 130 to input pixel signals from the control elements 141 to the pixel elements 142 . In this way, according to the pixel signal, the pixel elements 142 can enable the display 100 to generate a plurality of pixels with various gray scales, so that the display 100 can display an image. In addition, since the pixel array 140 is located in the display area 111 , the image is displayed in the display area 111 but not in the non-display area 112 .

The display 100 further includes a plurality of first fan-out lines 151 , a plurality of second fan-out lines 152 , a plurality of parallel first signal lines 161 and a plurality of parallel second signal lines 162 . The first fan-out wiring 151 , the second fan-out wiring 152 , the first signal line 161 and the second signal line 162 are all disposed on the substrate 110 and are also located in the non-display area 112 . The first fan-out traces 151 and the second fan-out traces 152 are respectively electrically connected to the data lines 130 . That is, each of the first fan-out wires 151 is electrically connected to one of the data wires 130 , and each of the second fan-out wires 152 is electrically connected to the other data wire 130 .

The extending directions of each of the first fan-out traces 151 and each of the second fan-out traces 152 are obviously not parallel to the first direction D1 . Taking FIG. 1A as an example, each of the first fan-out traces 151 and each of the second fan-out traces 152 are not parallel to the first direction D1 , that is, not parallel to the horizontal direction. Therefore, the first fan-out traces 151 and the second fan-out traces 152 do not extend completely along the first direction D1 (eg, the horizontal direction).

The first signal lines 161 are respectively connected to one end of the first fan-out lines 151 , and the second signal lines 162 are respectively connected to one end of the second fan-out lines 152 , wherein each of the first signal lines 161 and each of the second Both the extending directions of the signal lines 162 may be substantially parallel to the second direction D2 (eg, the vertical direction). Therefore, the extending direction of the first signal line 161 and the second signal line 162 may be the same as the extending direction of the data line 130 . In addition, each of the first signal lines 161 includes the first switching structure V1, but the second signal lines 162 do not include the first switching structure V1.

The display 100 may further include a plurality of second transfer structures V2, a plurality of third signal lines 163 and a plurality of pads 170, wherein the second transfer structures V2, the third signal lines 163 and the pads 170 are all disposed on the substrate 110 , and both are located in the non-display area 112 . The second switching structures V2 are respectively connected to the first signal lines 161 and the second signal lines 162 , wherein each of the second switching structures V2 is connected to a first signal line 161 or a second signal line 162 . The third signal lines 163 are respectively connected between the second transfer structures V2 and the pads 170 .

Each of the second switching structures V2 is connected between the adjacent first signal lines 161 and the third signal lines 163 , or between the adjacent second signal lines 162 and the third signal lines 163 . Using the second switching structures V2 and the third signal lines 163 , each of the first signal lines 161 or each of the second signal lines 162 can be electrically connected to one of the pads 170 . In this way, the pads 170 can be electrically connected to the data lines 130 via the first signal lines 161 , the second signal lines 162 , the first fan-out lines 151 and the second fan-out lines 152 .

The display 100 may further include a driving element 180 and a conductive adhesive 190 (areas with dot distribution in FIG. 1A ), wherein the conductive adhesive 190 may be anisotropic conductive film (ACF). The driving element 180 can be a chip or a circuit substrate on which the chip is mounted, wherein the aforementioned circuit substrate can be a flexible circuit board. The conductive glue 190 is distributed in the area Z1 between the first transfer structures V1 and the pads 170 , and covers the pads 170 beyond the range of the area Z1 .

The conductive adhesive 190 can adhere and fix the driving element 180 on the substrate 110 , so that the driving element 180 can be installed on the pads 170 in the non-display area 112 and can be electrically connected to the pads 170 . In this way, the driving element 180 can transmit pixel signals from the pads 170 to the data lines 130 , so that the data lines 130 can input the pixel signals to the pixel elements 142 , so that the display 100 can display images.

FIG. 1B is a partial top schematic view of the display in FIG. 1A at a non-display area, and FIG. 1C is a schematic cross-sectional view along the line 1C-1C in FIG. 1B . It should be noted in advance that the aforementioned FIG. 1A roughly illustrates the first signal line 161 , the second signal line 162 , the first fan-out line 151 and the second fan-out line 152 , so as to simply show the overall extension direction and position of these lines. FIG. 1A is a simplified diagram of the above-mentioned circuits in the form of a circuit diagram, and these circuits are not shown in detail.

However, FIG. 1B specifically illustrates the first signal line 161 , the second signal line 162 , the first fan-out line 151 and the second fan-out line 152 , and discloses the layout of these lines. Therefore, there is a difference between FIG. 1A and FIG. 1B. However, these differences do not affect the understanding of the technical features and means of the present embodiment by those with ordinary knowledge in the technical field to which the invention belongs, that is, those with ordinary knowledge in the technical field to which the invention belongs can still use the content of the description of the present application and FIGS. 1A to 1C to make Accordingly, the display 100 is realized.

Referring to FIG. 1B and FIG. 1C , the first fan-out trace 151 and the second fan-out trace 152 are obviously not on the same plane, wherein the first fan-out trace 151 is located above the second fan-out trace 152 . That is to say, the height of the first fan-out traces 151 relative to the substrate 110 is significantly greater than the height of the second fan-out traces 152 relative to the substrate 110 . In addition, the first fan-out traces 151 may respectively overlap with the second fan-out traces 152, wherein at least a part of the second fan-out traces 152 extends along the first fan-out traces 151, so in FIG. The two fan-out traces 152 , especially the second fan-out trace 152 located on the left half, are covered by the first fan-out trace 151 .

In the embodiment shown in FIG. 1C , the display 100 may further include a plurality of insulating layers 101 , 102 , 103 and 104 stacked on each other, wherein the insulating layer 101 is formed on the substrate 110 , and the insulating layers 102 and 103 are both located on the insulating layer 101 and 104, wherein the insulating layer 102 is stacked on the insulating layer 101, and the insulating layer 103 is stacked on the insulating layer 102, so the insulating layer 102 is located between the insulating layers 101 and 103, and the insulating layer 103 is located between the insulating layers 102 and 104 between.

The first fan-out wiring 151 is formed on the insulating layer 103 and covered by the insulating layer 104 , so the first fan-out wiring 151 is sandwiched between the insulating layers 103 and 104 . The second fan-out wiring 152 is formed on the insulating layer 102 and covered by the insulating layer 103 , so the second fan-out wiring 152 is sandwiched between the insulating layers 102 and 103 . Therefore, the first fan-out trace 151 is located above the second fan-out trace 152 , that is, the distance between the first fan-out trace 151 and the substrate 110 is greater than the distance between the second fan-out trace 152 and the substrate 110 , such as shown in Figure 1C.

In particular, the first fan-out trace 151 and the second fan-out trace 152 shown in FIG. 1A are represented by a single solid line, wherein FIG. 1A shows the first fan-out trace 151 and the second fan-out trace which are separated from each other. Lines 152 to clearly show the overall extension direction of the first fan-out traces 151 and the second fan-out traces 152 . Therefore, although the first fan-out trace 151 and the second fan-out trace 152 are not shown in FIG. 1A , FIG. 1A is only used to clearly show the overall extension direction of the first fan-out trace 151 and the second fan-out trace 152 , it is not intended to restrict the first fan-out trace 151 and the second fan-out trace 152 from overlapping each other.

Each of the first signal lines 161 further includes a first line segment S1 and a second line segment S2. The first line segment S1 is connected to one end of one of the first fan-out traces 151, and the first transition structure V1 connects the first line segment S1 and the second line segment S2, so that the first line segment S1 can pass through the first transition structure V1 is electrically connected to the second line segment S2. In addition, the first line segments S1 and the second line segments S2 both extend along the second direction D2, and the first signal lines 161 and the second signal lines 162 may be staggered, as shown in FIG. 1B .

The first line segment S1 and the second line segment S2 are obviously not on the same plane. Taking FIG. 1C as an example, the first line segment S1 is formed on the insulating layer 103 and covered by the insulating layer 104, so the first line segment S1 is sandwiched between the insulating layers 103 and 104, wherein the first line segment S1 and the The first fan-out traces 151 may be substantially on the same plane. The second line segment S2 is formed on the insulating layer 102 and covered by the insulating layer 103, so the second line segment S2 is sandwiched between the insulating layers 102 and 103, wherein the second line segment S2 and the second fan-out trace 152 can be substantially on the same plane. It can be seen that the first line segment S1 is located above the second line segment S2, that is, the height of the first line segment S1 relative to the substrate 110 is significantly greater than the height of the second line segment S2 relative to the substrate 110, as shown in FIG. 1C .

The first line segments S1 and the first fan-out lines 151 may be formed by photolithography from a single conductive layer, and the second line segments S2 and the second fan-out lines 152 may be formed by photolithography of another conductive layer formed by etching, wherein the conductive layer may be a metal layer or the aforementioned transparent conductive film. Therefore, the first line segment S1 connected to each other and the first fan-out wiring 151 may be integrally formed. In addition, the data lines 130 (refer to FIG. 1A ), the second line segments S2 and the second fan-out traces 152 may also be formed by photolithography from the same conductive layer, and the data lines 130 , the second line segments S2 and the The second fan-out traces 152 may be substantially on the same plane.

Since the first line segment S1 is located above the second line segment S2, the first signal line 161 includes two layers of lines (ie, the first line segment S1 and the second line segment S2) that are not on the same plane, and is obviously not conducted by a single layer. The layers are formed by photolithography. The first transition structure V1 can connect the first line segment S1 and the second line segment S2 that are not on the same plane, so that the first line segment S1 is electrically connected to the second line segment S2.

Taking FIG. 1C as an example, each first transfer structure V1 includes two conductive pillars V11 , V12 and a bridge line V13 , wherein the bridge line V13 is formed on the insulating layer 104 and connects the conductive pillars V11 and V12 . Therefore, the conductive pillars V11 and V12 can be electrically connected to each other through the bridge wire V13. The conductive column V11 penetrates through the insulating layer 104 and is connected to the first line segment S1 of the first signal line 161 , while the conductive column V12 penetrates through the insulating layers 104 and 103 and is connected to the second line segment S2 of the first signal line 161 . In this way, through the first transition structure V1, the first line segment S1 is electrically connected to the second line segment S2. In addition, the conductive pillars V11 , V12 and the bridge line V13 can be formed by photolithography of transparent conductive materials or metal materials, wherein the transparent conductive materials can be the aforementioned metal oxides, such as indium tin oxide (ITO) or indium zinc oxide (IZO) ).

The second signal line 162 and the second line segment S2 may be substantially on the same plane. That is, the second signal line 162 is also formed on the insulating layer 102 and covered by the insulating layer 103 , so that the second signal line 162 is sandwiched between the insulating layers 102 and 103 . Therefore, the data lines 130 (refer to FIG. 1A ), the second line segments S2 , the second fan-out lines 152 and the second signal lines 162 can be formed by photolithography from the same conductive layer, wherein the second The signal line 162 and the second fan-out trace 152 may be integrally formed, and the conductive layer may be the above-mentioned transparent conductive film or metal layer.

The third signal lines 163 are formed on the insulating layer 101 and covered by the insulating layer 102 , so the third signal lines 163 are sandwiched between the insulating layers 101 and 102 . The third signal line 163 is located below the second line segment S2 , and the second line segment S2 is located between the third signal line 163 and the first line segment S1 , as shown in FIG. 1C . Of course, since the second signal line 162 and the second line segment S2 can be substantially on the same plane, the second signal line 162 is also located between the third signal line 163 and the first line segment S1.

In the embodiment shown in FIG. 1C , each of the second via structures V2 can be conductive pillars and penetrate through the insulating layer 102 . The second transfer structures V2 are respectively connected to the second line segments S2 and the second signal lines 162, wherein each of the second transfer structures V2 is connected between the adjacent second line segments S2 and the third signal lines 163, or It is connected between the adjacent second signal lines 162 and the third signal lines 163 , so that the first signal lines 161 and the second signal lines 162 are electrically connected to the third signal lines 163 respectively.

Since the third signal lines 163 are electrically connected to the pads 170, respectively, the second line segments S2 of the first signal lines 161 can be electrically connected to the third signal lines 163 using the second transition structures V2. One pad 170 and each of the second signal lines 162 can be electrically connected to the other pad 170 . In this way, the driving elements 180 can transmit pixel signals from the pads 170 to the data lines 130 , so that the pixel elements 142 receive the pixel signals, so that the display 100 can display images.

It is particularly mentioned that, in this embodiment, each of the first transition structures V1 includes two conductive pillars V11 , V12 and a bridge line V13 . However, in other embodiments, the first transfer structure V1 may also be a conductive column penetrating the insulating layer 103 and electrically connected between the first line segment S1 and the second line segment S2. Therefore, FIG. 1C is for illustration only, and does not limit the first transition structure V1 to include two conductive pillars V11 , V12 and a bridge line V13 .

The shortest distance G1 between the pads 170 and the first via structures V1 may be greater than or equal to 300 microns, for example, may be between 300 microns and 1760 microns, wherein the shortest distance G1 may be along the second direction D2. In other words, the distance (along the second direction D2 ) between any of the first via structures V1 and the pads 170 may be greater than or equal to the shortest distance G1 , eg, 300 μm. In addition, the average distance between the pads 170 and the first transfer structures V1 may be greater than 500 microns, and the average distance may also be along the second direction D2.

Please refer to FIG. 1A and FIG. 1B , the conductive adhesive 190 mainly adheres and electrically connects the driving element 180 to the pads 170 . During the process of adhering the driving element 180 to the pads 170 by the conductive adhesive 190, the conductive adhesive 190 will be squeezed by the driving element 180 and the substrate 110 to overflow, so that the conductive adhesive 190 not only covers the pads 170, but also leaks from the pads 170. The pads 170 overflow to the third signal lines 163 , the second transfer structures V2 and the second line segments S2 , so as to cover the third signal lines 163 , the second transfer structures V2 and the second line segments S2 Line segment S2.

Generally speaking, the farthest distance that the conductive paste 190 overflows from the pad 170 toward the display area 111 along the direction parallel to the second direction D2 is about 500 microns. Since the shortest distance G1 between the pads 170 and the first via structures V1 is greater than or equal to 300 microns, for example, between 300 microns and 1760 microns, the distance between the pads 170 and the first via structures V1 The average distance is greater than 500 microns, so most of the first transfer structures V1 are outside the overflow range of the conductive adhesive 190 . That is to say, the conductive adhesive 190 covers at least a part of each of the second line segments S2 and a small number of the first transition structures V1, but most of the first transition structures V1 are not covered by the conductive adhesive 190, even these first transition structures V1 Either one may not be covered by conductive glue 190 .

Referring to FIG. 1C , the first transfer structure V1 is located at the outermost side of the display 100 , and the insulating layers 103 and 104 are disposed above the second transfer structure V2 . Therefore, compared with the second transition structure V2, the first transition structure V1 is easily damaged or even damaged by foreign objects (eg, toothpicks), so that the display 100 may be forced to be scrapped. In other words, the first switching structure V1 is a fragile part of the wiring structure of the display 100 .

However, in the display 100 of this embodiment, most or even all of the first transition structures V1 are not covered by the conductive adhesive 190 . Therefore, in the production process of the display 100 , most of the remaining conductive adhesive 190 will not cover the first transfer structure V1 to reduce or avoid the damage of the first transfer structure V1 by sharp tools, thereby improving the display 100 . Yield.

Referring to FIG. 1B , there is a shortest distance G1 between at least one of the two outermost first transfer structures V1 and the pads 170 , and in this embodiment, the two outermost first transfer structures V1 , that is, the distances between the two first transition structures V1 on the far left and the far right in FIG. 1B and the pads 170 are both the shortest distances G1 . In addition, the conductive glue 190 may completely cover the outermost second line segment S2.

The non-display area 112 has a first area 112a and a second area 112b, wherein the first area 112a is adjacent to the second area 112b, and both the first area 112a and the second area 112b are arranged along the first direction D1. The first signal lines 161 and the second signal lines 162 are both located in the first area 112a and the second area 112b, and the first transition structures V1 are not arranged along the first direction D1 and the second direction D2.

Taking FIG. 1B as an example, the first transition structures V1 in the first area 112a are arranged along the first straight line L1, and the first transition structures V1 in the second area 112b are arranged along the second straight line L2, The first straight line L1 and the second straight line L2 are both virtual reference straight lines. The first straight line L1 and the second straight line L2 are not parallel, and neither the first straight line L1 nor the second straight line L2 is parallel to the first direction D1 and the second direction D2. In addition, the first straight line L1 and the second straight line L2 intersect to form an inverted V-shape as shown in FIG. 1B .

Since the shortest distance G1 between the first transition structure V1 and the pad 170 is between the outermost first transition structure V1 and the pad 170 , the intersection of the first straight line L1 and the second straight line L2 is the same as these The distance between the pads 170 will be greater than the shortest distance G1, and the intersection point may be located at or near the first transition structure V1 in the middle. In addition, the change in the distance between the first transition structure V1 and the pad 170 may decrease from the first transition structure V1 in the middle to the first transition structures V1 on the outermost sides, so the first transition structures located in the middle and near the middle A transfer structure V1 is difficult to be covered by the conductive adhesive 190 . In this way, the damage of the first transition structure V1 by sharp tools can be reduced or avoided, so as to improve the yield of the display 100 .

In particular, in this embodiment, the display 100 includes a first signal line 161 , a second signal line 162 , a first fan-out line 151 and a second fan-out line 152 . However, in other embodiments, the display 100 may include the first signal line 161 and the first fan-out line 151 , but not include any second signal line 162 and the second fan-out line 152 . That is to say, the second signal line 162 and the second fan-out trace 152 shown in FIGS. 1A to 1C can be omitted. Therefore, the display 100 is not limited to include the second signal line 162 and the second fan-out line 152 .

FIG. 2 is a partial top plan view of a display according to another embodiment of the present invention. Referring to FIG. 2 , the display 200 of this embodiment is similar to the display 100 of the previous embodiment. For example, the overall circuit structure of the display 200 is substantially the same as that of the display 100 shown in FIG. 1A , and the display 200 also includes a plurality of scan lines 120 , a plurality of data lines 130 and a pixel array 140 . The only difference between displays 100 and 200 is that they have different wiring in the non-display area. The above differences are mainly described below, wherein FIG. 2 only shows the wiring of the display 200 in the non-display area 212 thereof. In principle, the same features of the displays 100 and 200 are not repeated in description and illustration.

The substrate (for example, the substrate 110 ) included in the display 200 has a display area 111 (refer to FIG. 1A ) and a non-display area 212 , wherein the non-display area 212 has a first area 212 a , a second area 212 b and a central area 212 c . A fan-out trace 151 , the second fan-out traces 152 , the first signal lines 161 , the second signal lines 162 and the third signal lines 163 are located in the first area 212 a , the second area 212 b and the central area 212c.

The central area 212c is located between the first area 212a and the second area 212b, and the first area 212a, the central area 212c and the second area 212b are all arranged along the first direction D1. Similar to the display 100 in FIG. 1B , the first transition structures V1 in the first area 212a are arranged along a first straight line L1, and the first transition structures V1 in the second area 212b are arranged along a second straight line L2 arrangement. Secondly, the shortest distance G1 (which may be greater than or equal to 300 μm) between the first via structure V1 and the pad 170 is between the outermost first via structure V1 and the pad 170 . That is, the shortest distance G1 is within at least one of the first area 212a and the second area 212b.

Different from the display 100 in FIG. 1B , the first transition structures V1 located in the central area 212c are arranged along a third straight line L3, wherein the third straight line L3 is a virtual reference straight line and is parallel to the first direction D1, Therefore, the first transition structures V1 located in the central region 212c are arranged along the first direction D1.

Since the shortest distance G1 is in at least one of the first area 212a and the second area 212b, the distance between the first via structures V1 and the pads 170 in the central area 212c exceeds the shortest distance G1. Therefore, during the production process of the display 200, the residual conductive adhesive 190 will not substantially cover the first via structure V1 located in the central area 212c, so as to reduce or avoid the damage of the first via structure V1 by sharp tools , thereby improving the yield of the display 200 .

FIG. 3 is a partial top plan view of a display according to another embodiment of the present invention. Referring to FIG. 3 , the display 300 of this embodiment is similar to the display 200 of the previous embodiment. For example, the display 300 also includes a substrate (eg, the substrate 110 ), a plurality of first fan-out traces 151 , a plurality of second fan-out traces 152 , a plurality of first signal lines 361 , a plurality of second signal lines 362 , and a plurality of first fan-out traces 152 . Three signal lines 163 and a plurality of second switching structures V2.

The non-display area of the substrate also has a first area, a second area and a central area, such as the first area 212a, the second area 212b and the central area 212c shown in FIG. 2 . The first signal lines 361 , the second signal lines 362 and the third signal lines 163 are all located in the first area, the second area and the central area. Each first signal line 361 includes a first line segment S31, a second line segment S2 and a first switching structure V1, wherein each first switching structure V1 is electrically connected to the adjacent first line segment S31 and the second line segment S2 , so that the first line segments S31 are electrically connected to the second line segments S2 respectively. In addition, the first transition structures V1 are also arranged along the first straight line L1 , the second straight line L2 and the third straight line L3 , as shown in FIG. 2 .

The main difference between the display 300 and the display 200 is shown in FIG. 3 , wherein the display 300 shown in FIG. 3 is a top view in its central area. Specifically, different from the display 200 of the foregoing embodiment, in the central area of the display 300, at least one first line segment S31 has a first impedance regulating arch S31a, and at least one second signal line 362 has a second impedance Regulate archwire 362a.

Taking FIG. 3 as an example, the plurality of first line segments S31 respectively have a plurality of first impedance control archwires S31a, and the plurality of second signal lines 362 respectively have a plurality of second impedance control archwires 362a. In addition, in other embodiments, only one first line segment S31 may have the first impedance control arch S31a, and only one second signal line 362 may have the second impedance control arch 362a, so FIG. 3 does not limit the first impedance control The archwire S31a and the second impedance control the number of archwires 362a.

The first impedance control archwire S31a and the second impedance control archwire 362a can respectively increase the path lengths of the first signal line 361 and the second signal line 362, thereby increasing both the first signal line 361 and the second signal line 362 impedance. Specifically, the first fan-out traces and the second fan-out traces near the outer side of the non-display area have longer lengths, but the first fan-out traces and the second fan-out traces located at and near the center of the non-display area The wire however has a shorter length (as shown in Figure 1A).

Therefore, the first signal line 361 and the second signal line 362 near the outer side of the non-display area usually have a larger impedance, while the first signal line 361 and the second signal line 362 located at and near the center of the non-display area are Usually has a smaller impedance. Therefore, not only the impedance difference between the first signal lines 361 is very large, but also the impedance difference between the second signal lines 362 is also very large. In this way, the data lines 130 will receive distorted pixel signals, resulting in the degradation of image quality.

However, the first impedance control archwire S31a and the second impedance control archwire 362a located in the central area can increase the impedances of the first signal line 361 and the second signal line 362, respectively, so that the first signal lines 361 and these The impedance gap between the second signal lines is reduced. In this way, the pixel signals transmitted by the first signal line 361 and the second signal line 362 will not be too different, thereby helping to maintain or improve the image quality of the display 300 .

It is particularly mentioned that both the first impedance control arch S31a and the second impedance control arch 362a shown in FIG. 3 can be applied to the display 100 shown in FIG. 1B . In detail, at least one first signal line 161 and at least one second signal line 162 located in the center in FIG. 1B can be replaced with a first signal line 361 having a first impedance regulation arch S31a and a second impedance regulation arch The second signal line 362 of the line 362a.

In other words, in the display 200 shown in FIG. 2 , the first transition structures V1 in the central area 212c may be arranged in an inverted V-shape as shown in FIG. Both the first impedance adjustment arch S31a and the second impedance adjustment arch 362a shown in 3 may be formed on at least one first signal line 161 and at least one second signal line 162 in the central region 212c. Therefore, the first impedance-adjusting archwire S31a and the second impedance-adjusting archwire 362a are also applicable to the foregoing embodiments, and are not limited to be used in the display 300 of this embodiment.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the appended patent application.

100, 200, 300: Display 101, 102, 103, 104: insulating layer 110: Substrate 111: Display area 112, 212: non-display area 112a, 212a: first area 112b, 212b: the second area 120: scan line 130: Data line 140: pixel array 141: Control elements 142: Pixel element 151: The first fan-out trace 152: Second fan-out trace 161, 361: The first signal line 162, 362: The second signal line 163: The third signal line 170: Pad 180: Drive Components 190: Conductive glue 212c: Central Area 362a: Second Impedance Regulated Archwire L1: The first straight line L2: Second straight line L3: The third straight line D1: first direction D2: Second direction G1: shortest distance S1, S31: the first line segment S2: Second line segment S31a: First Impedance Regulated Archwire V1: The first transfer structure V2: Second transfer structure V11, V12: Conductive pillars V13: Bridge Wire Z1: Zone

FIG. 1A is a schematic top view of a display according to at least one embodiment of the present invention. FIG. 1B is a partial top schematic view of the display in FIG. 1A at a non-display area. FIG. 1C is a schematic cross-sectional view taken along the line 1C-1C in FIG. 1B . FIG. 2 is a partial top plan view of a display according to another embodiment of the present invention. FIG. 3 is a partial top plan view of a display according to another embodiment of the present invention.

100: Monitor

112: Non-display area

112a: First Region

112b: Second area

151: The first fan-out trace

152: Second fan-out trace

161: The first signal line

162: The second signal line

163: The third signal line

170: Pad

L1: The first straight line

L2: Second straight line

D1: first direction

D2: Second direction

G1: shortest distance

S1: first line segment

S2: Second line segment

V1: The first transfer structure

V2: Second transfer structure

Claims (13)

A display comprising: a substrate having a display area and a non-display area other than the display area; A plurality of parallel scan lines are arranged on the substrate and extend along a first direction; a plurality of juxtaposed data lines disposed on the substrate and extending along a second direction, wherein the first direction is not parallel to the second direction; a pixel array disposed on the substrate and located in the display area, wherein the pixel array connects the scan lines and the data lines; A plurality of first fan-out traces are disposed on the substrate and located in the non-display area, wherein each of the first fan-out traces is electrically connected to one of the data traces, and the extension direction of each of the first fan-out traces not parallel to the first direction; A plurality of parallel first signal lines are disposed on the substrate and located in the non-display area, wherein each of the first signal lines includes: a first line segment connected to one end of the first fan-out trace; a second line segment; a first transition structure connecting the first line segment and the second line segment, wherein the first line segments and the second line segments both extend along the second direction; A plurality of pads are disposed on the substrate and located in the non-display area, wherein the second line segment of each of the first signal lines is electrically connected to one of the pads. The display of claim 1, wherein a shortest distance between the pads and the first transfer structures is greater than or equal to 300 microns, and a distance between the pads and the first transfer structures An average distance greater than 500 microns. The display of claim 2, wherein the shortest distance exists between at least one of the two outermost first transition structures and the pads. The display of claim 1, wherein the first transition structures are not arranged along the first direction and the second direction. The display of claim 1, wherein there is a shortest distance between at least one of the two outermost first transfer structures and the pads, and any one of the first transfer structures is connected to the pads. The distance between the pads is greater than or equal to this shortest distance. The display of claim 5, wherein the non-display area has a first area and a second area, the first area is adjacent to the second area, and both the first area and the second area are along the first area arranged in a direction, the first signal lines are located in the first area and the second area, wherein the first switching structures located in the first area are arranged along a first straight line and located in the second area The first transfer structures inside are arranged along a second straight line, wherein the first straight line and the second straight line are not parallel, and the first straight line and the second straight line are not parallel to the first direction and the second straight line direction. The display of claim 5, wherein the non-display area has a first area, a second area and a central area, the central area is located between the first area and the second area, and the first area, Both the central area and the second area are arranged along the first direction, the first signal lines are located in the first area, the second area and the central area, wherein the first signal lines in the first area The first transfer structures are arranged along a first line, the first transfer structures in the second region are arranged along a second line, and the first transfer structures in the central region are arranged along a line The first direction is arranged, wherein the first straight line and the second straight line are not parallel, and neither the first straight line nor the second straight line is parallel to the first direction and the second direction. The display of claim 1, further comprising: a plurality of second fan-out wires disposed on the substrate and located in the non-display area, wherein each of the second fan-out wires is electrically connected to one of the data wires; and A plurality of parallel second signal lines are disposed on the substrate and located in the non-display area, wherein the second signal lines are respectively connected to one end of the second fan-out lines, and each of the second signal lines is electrically Connect one of the pads. The display of claim 8, wherein the non-display area has a first area, a second area and a central area, the central area is located between the first area and the second area, and the first area, Both the central area and the second area are arranged along the first direction, the first signal lines are located in the first area, the second area and the central area, and at least one of them located in the central area The first line segment has a first impedance regulating archwire. The display of claim 9, wherein the second signal lines are located in the first area, the second area and the central area, wherein at least one second signal line located in the central area has a first Two impedance-regulating archwires. The display of claim 8, further comprising: a plurality of second switching structures respectively connecting the second line segments and the second signal lines; and A plurality of third signal lines are respectively connected between the second transfer structures and the pads. The display according to any one of claims 1 to 11, further comprising a driving element, wherein the driving element is mounted on the pads. The display according to any one of claims 1 to 11, further comprising a conductive adhesive, wherein the conductive adhesive is distributed in an area between the first transfer structures and the pads, and covers each of the second At least a part of the line segment is connected to the pads.

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