TW202213355A - Non-volatile memroy device - Google Patents

Abstract

A non-volatile memory device includes a non-volatile memory cell array, a sense amplifier, a random access memory (RAM) and a buffer circuit. The sense amplifier is configured to generate a readout data. The RAM is used to store a write-in data. The buffer circuit generates a detection result according to a target data and the readout data, and writes the detection result to the RAM.

Description

non-volatile memory device

The present invention relates to a non-volatile memory device, and more particularly, to a non-volatile memory device that can save circuit area.

In the structure of the conventional non-volatile memory device, for the writing mechanism of the non-volatile memory device, a static memory, a comparison circuit and a data register need to be provided. The writing mechanism of the non-volatile memory device includes a programming action, an erasing action, and a soft programming action. In the implementation of the above writing mechanism, the data of the memory cell to be written needs to be read, and then the read data and the target data to be written are compared through the comparison circuit, and the comparison result is set in the data in the scratchpad. The comparison circuit and the data register required to be arranged in such a structure consume a certain circuit area and increase the circuit cost.

The present invention provides a non-volatile memory device, which can effectively reduce the area of the hardware circuit for executing the writing mechanism.

The non-volatile memory device of the present invention includes a non-volatile memory cell array, a sense amplifier, a random access memory and a buffer circuit. The sense amplifier is coupled to the non-volatile memory cell array for generating readout data. The random access memory is used to store the written data. The buffer circuit is coupled to the random access memory and the sense amplifier, and generates a detection result according to the target data and the read data, and the buffer circuit causes the detection result to be written into the random access memory.

Based on the above, the buffer circuit of the present invention can not only provide the function of writing to the random access memory, but also perform the detection function for the target data and the read data, thereby generating the detection result. In this way, in the mechanism for the non-volatile memory device to perform the writing operation, it is not necessary to additionally set the comparison circuit and the data register, which effectively reduces the hardware requirement and circuit cost.

Please refer to FIG. 1 , which is a schematic diagram of a non-volatile memory device according to an embodiment of the present invention. The non-volatile memory device 100 includes a non-volatile memory cell array 110 , a sense amplifier 120 , a random access memory 130 and a buffer circuit 140 . The sense amplifier 120 is coupled to the non-volatile memory cell array 110 . The sense amplifier 120 is used for sensing data provided by one or more memory cells corresponding to the selected address in the non-volatile memory cell array 110, and thereby generating a read data SAOUT.

The random access memory 130 is coupled to the buffer circuit 140 . The random access memory 130 can be used to store written data. The random access memory 130 can receive the input data WDIN through the buffer circuit 140 and store the input data WDIN as the write data SMOUT. The input data WDIN may be sent by an electronic device external to the non-volatile memory device 100 and written into the non-volatile memory cell array 110 .

It should be noted that when the non-volatile memory device 100 executes a write mechanism, the buffer circuit 140 can generate a detection result CR according to a target data and read data SAOUT, and write the detection result CR into the random access memory 130. The above-mentioned writing mechanism includes a program verify phase, an erase verify phase, and a soft-program verify phase. The buffer circuit 140 can set different target data according to different stages of the writing mechanism, and can generate the detection result CR.

In detail, in the programming verification stage, the buffer circuit 140 can set the write data SMOUT in the random access memory 130 as the target data. The buffer circuit 140 can read the write data SMOUT from the random access memory 130 , and receive the read data SAOUT read from the non-volatile memory cell array 110 by the sense amplifier 120 . The buffer circuit 140 generates the detection result CR according to the write data SMOUT and the read data SAOUT. Wherein, in the programming verification stage, the detection result CR can be used to indicate whether the non-volatile memory cell array 110 needs to perform further programming actions.

In the erasing verification stage, the buffer circuit 140 may set the target data to a first logic level, wherein the first logic level may be the logic level after the non-volatile memory cells are erased, for example, the logic level bit 1. The buffer circuit 140 compares the read data SAOUT with the first logic level to generate a detection result CR. In the erasing verification stage, the detection result CR is used to indicate whether the non-volatile memory cell array 110 needs to perform further erasing operations.

In the soft programming verification stage, the buffer circuit 140 may set the target data to a second logic level, wherein the second logic level may be the logic level after the soft programming of the non-volatile memory cells, such as The logic level is 0 (complementary to the first logic level). The buffer circuit 140 compares the read data SAOUT with the second logic level to generate a detection result CR. In the soft programming verification stage, the detection result CR is used to indicate whether the non-volatile memory cell array 110 needs to perform further soft programming.

On the other hand, the buffer circuit 140 can cause the input data WDIN to be written into the random access memory 130 to become the write data SMOUT in a data loading stage.

It can be known from the above description that the buffer circuit 140 is used in the embodiment of the present invention to provide detection operations between the read data SAOUT and the target data in multiple stages of the writing mechanism, and the buffer circuit 140 provides the detection result CR. Write to the buffer interface of the random access memory 130 . In this way, the area required for the circuit can be effectively reduced, and the circuit cost can be reduced.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram illustrating an implementation of a buffer circuit of a non-volatile memory device according to an embodiment of the present invention. The buffer circuit 200 includes a boost circuit 210 , pull-down circuits 220 - 240 and an output buffer 250 . The rising circuit 210 is coupled to the output terminal OE, wherein the output terminal OE is used for providing the detection result CR. The raising circuit 210 is used for providing a first driving capability to raise the detection result CR to a preset logic level, and the preset logic level may be a logic level 1 .

In this embodiment, the rising circuit 210 receives the write operation enable signal WREN_P1 and the verification operation signal VER, and generates the detection result CR according to the write operation enable signal WREN_P1 and the verification operation signal VER. The write action enable signal WREN_P1 is used to indicate that the write mechanism of the non-volatile memory device is activated. The verification action signal VER is used to indicate whether the write mechanism enters the erasure verification stage or the soft programming verification stage.

The pull-down circuit 220 is coupled to the output terminal OE. The pull-down circuit 220 is used to pull down the detection result CR according to the target data and the read data to provide the second driving capability in the programming verification stage, wherein the second driving capability may be greater than the first driving capability. The pull-down circuit 220 receives the program verification signal PVER, the input data WDIN, the reverse read data SAOUTb, the write data SMOUT, the erase verification signal EVER, and the soft program verification signal PSTVER. The program verification signal PVER, the erase verification signal EVER and the soft program verification signal PSTVER are respectively used to instruct the writing mechanism of the non-volatile memory device to enter the program verification stage, the erase verification stage and the soft program verification stage. In addition, the reverse read data SAOUTb is the reverse of the read data SAOUT.

In the data loading stage, the pull-down circuit 220 can select the input data WDIN according to the disabled programmed verification signal PVER, and determine whether to pull down the detection result CR according to the logic level of the input data WDIN. Wherein, in the data loading stage, the logic level of the detection result CR can be the same as the logic level of the input data WDIN, and can be written into the non-volatile memory. Next, in the program verification stage, the pull-down circuit 220 can select the write data SMOUT as the target data according to the enabled program verification signal PVER, and determine whether to pull down the detection according to the read data SAOUT and the target data Result CR. In this embodiment, when the write data SMOUT is at the logic level 0 and the read data SAOUT is at the logic level 1, the pull-down circuit 220 can pull down the detection result CR to be the logic level 0; and when the write data SMOUT is at the logic level 1 When the logic state of the read data SAOUT is other combinations, the pull-down circuit 220 can maintain the detection result CR as the logic level 1.

In this embodiment, the detection result CR of the logic level 0 can be used to indicate that the non-volatile memory cell array needs to perform further programming operations. On the other hand, the detection result CR, which is a logic level 1, can be used to indicate that the non-volatile memory cell array does not need to perform further programming operations.

The pull-down circuit 230 is coupled to the output terminal OE. In the soft programming verification stage, the detection result CR is pulled down according to the comparison target data (which is logic level 0) and the reverse read data SAOUTb to provide the third driving capability. The third driving capability is greater than the above-mentioned first driving capability. In this embodiment, the pull-down circuit 230 receives the soft programming verification signal PSTVER and the read data SAOUT. Based on the soft programming verification signal PSTVER, the pull-down circuit 230 in the soft programming verification stage, when the read data SAOUT is a logic level 1 (not equal to the target data), the pull-down detection result CR is a logic level 0. On the contrary, when the read data SAOUT is at the logic level 0 (equal to the target data), the detection result CR is maintained at the logic level 1. In this embodiment, the detection result CR of the logic level 0 can be used to indicate that the non-volatile memory cell array needs to perform further soft programming operations. In contrast, the detection result CR, which is a logic level 1, can be used to indicate that the non-volatile memory cell array does not need to perform further soft programming.

The pull-down circuit 240 is coupled to the output terminal OE. In the erasing verification stage, the detection result CR is pulled down according to the comparison target data (which is a logic level 1) and the read data SAOUT to provide the fourth driving capability. The fourth driving capability is greater than the above-mentioned first driving capability. In this embodiment, the pull-down circuit 240 receives the erase verification signal EVER and the read data SAOUT. Based on the erase verify signal EVER, the pull-down circuit 240 in the erase verify phase, when the read data SAOUT is logic level 0 (not equal to the target data), the pull-down detection result CR is logic level 0. On the contrary, when the read data SAOUT is at the logic level 1 (equal to the target data), the detection result CR is maintained at the logic level 1. In this embodiment, the detection result CR of the logic level 0 can be used to indicate that the non-volatile memory cell array needs to perform a further erase operation. On the contrary, the detection result CR, which is a logic level 1, can be used to indicate that the non-volatile memory cell array does not need to perform further erasing operations.

The output buffer 250 is also coupled to the output terminal OE, and receives the detection signal CR and the write enable signal WREN_P2. The output buffer 250 generates the first data DB and the second data DBb according to the detection result CR when the write operation enable signal WREN_P2 is enabled (eg, logic level 1), wherein the first data DB and The second data DBb is complementary. The output buffer 250 enables the first data DB and the second data DBb to have sufficient driving capability to be written into the random access memory.

Please refer to FIG. 3 below. FIG. 3 is a circuit diagram illustrating an implementation manner of a buffer circuit of a non-volatile memory device according to an embodiment of the present invention. The buffer circuit 300 includes a boost circuit 310 , pull-down circuits 320 - 340 and an output buffer 350 . The rising circuit 310 includes a transistor T1 and two logic circuits respectively composed of a NOR gate (NOR gate) NO1 and a gate (AND gate) AN1. The inverse OR gate NO1 is used to receive the write enable signal WREN_P1 and the verify operation signal VER, and perform an inverse OR logic operation on the write enable signal WREN_P1 and the verify operation signal VER to generate the signal CT1. The first terminal of the transistor T1 receives the reference voltage VDD, the control terminal of the transistor T1 receives the signal CT1, and determines whether to pull up the detection result CR on the output terminal OE coupled to the second terminal of the transistor T1 according to the signal CT1. In addition, the AND gate AN1 receives the detection result CR and the write operation enable signal WREN_P1, and determines whether to output the detection result CR to the output buffer 350 according to the write operation enable signal WREN_P1. Among them, the AND gate AN1 is used to perform an AND logic operation.

The pull-down circuit 320 includes a selector 321, logic circuits 322, 323, and transistors T22, T23. The selector 321 selects the input data WDIN or the write data SMOUT to generate the selected data according to the programmed verification signal PVER. The logic circuit 322 includes an inverse OR gate NO2 and an OR gate OR1. The inverse OR gate NO2 receives the above-mentioned selected data and the output of the OR gate OR1 (verification signal VER) to perform an inverse OR logic operation, thereby generating the control signal CT2. The OR gate OR1 receives the erase verification signal EVER and the soft-programmed verification signal PSTVER to perform an OR logic operation to generate the verification signal VER.

The first end of the transistor T22 is coupled to the output end OE, the control end thereof receives the control signal CT2, and the second end of the transistor T22 is coupled to the first end of the transistor T23. The second terminal of the transistor T23 is coupled to the reference ground terminal GND, and the control terminal thereof receives the control signal CT3. The control signal CT3 is generated by the logic circuit 323, wherein the logic circuit 323 includes an inversion gate NA1. The inversion gate NA1 receives the programmed verification signal PVER and the inversion readout data SAOUTb to perform inversion logic operation, thereby generating the control signal CT3.

The pull-down circuit 330 includes a transistor T32 and a logic circuit composed of an AND gate AN2. The AND gate AN2 receives the soft programming verification signal PSTVER and the reverse read data SAOUTb to generate the control signal CT4. Among them, the input terminal of the AND gate AN2 for receiving the reverse read data SAOUTb is a reverse input terminal. Therefore, the AND gate AN2 performs the AND logic operation for the reverse of the soft programming verification signal PSTVER and the reverse read data SAOUTb, and Thereby, the control signal CT4 is generated. The transistor T32 is coupled between the output terminal OE and the reference ground terminal GND, and is controlled by the control signal CT4. When the transistor T32 is turned on, the detection result CR on the output terminal OE can be pulled down to the logic level 0.

The pull-down circuit 340 includes a transistor T42 and a logic circuit composed of an AND gate AN3. The AND gate AN3 receives the erase verification signal EVER and the reverse read data SAOUTb to generate the control signal CT5. The AND gate AN3 performs AND logic operation for the erase verification signal EVER and the reverse read data SAOUTb, and thereby generates the control signal CT5. The transistor T42 is coupled between the output terminal OE and the reference ground terminal GND, and is controlled by the control signal CT5. When the transistor T42 is turned on, the detection result CR on the output terminal OE can be pulled down to the logic level 0.

The output buffer 350 includes an output stage circuit composed of transistors T51, T52, inverting and gate NA2, and inverting-OR gate NO3; another output composed of transistors T53, T54, inverting-sum gate NA3 and inverting-OR gate NO4 stage circuit; and inverter IV1. The transistors T51 and T52 are serially connected between the reference voltage VDD and the reference ground terminal GND in sequence, and are respectively controlled by the inverting-OR gate NA2 and the inverting-OR gate NO3 to output. The inversion gate NA2 and the inversion gate NO3 have input terminals for receiving the detection result CR in common, and have input terminals for respectively receiving the write operation enable signal WREN_P2 and the reverse write operation enable signal WREN_P2b. The transistors T51 and T52 jointly generate the first data DB.

In addition, the transistors T53 and T54 are serially connected between the reference voltage VDD and the reference ground terminal GND in sequence, and are controlled by the inversion gate NA3 and the inversion gate NO4 respectively. The reverse-OR gate NA3 and the reverse-OR gate NO4 have input terminals for receiving the reverse detection result CRb in common, and have input terminals for respectively receiving the write operation enable signal WREN_P2 and the reverse write operation enable signal WREN_P2b. The transistors T53 and T54 jointly generate the second data DBb, wherein the first data DB and the second data DBb are complementary.

In terms of action details, the pull-down circuit 320 selects the input data WDIN through the selector 321 to generate the selected data in the data loading stage. At this time, the verification signal VER is at logic level 0. When the input data WDIN is at the logic level 1, the inverse OR gate NO2 generates the control signal CT2 with the logic level 0 so that the transistor T22 is turned off. Therefore, the detection result CR maintains the logic level 1 (same as the input data WDIN). On the other hand, in the data loading stage, when the input data WDIN is at logic level 0, the inverse OR gate NO2 generates a control signal CT2 at logic level 1 so that transistor T22 is turned on, and transistor T23 is also turned on. Under the condition of , the detection result CR is pulled down to the logic level 0 (same as the input data WDIN).

The above detection result CR is reflected in the first data DB and the second data DBb when the write operation enable signal WREN_P2 is at the logic level 1. And write into the random access memory through the output buffer 350 .

On the other hand, in the program verification stage, the selector 321 in the pull-down circuit 320 selects the write data SMOUT to generate the selected data, and provides the selected data to the inverse OR gate NO2, at the same time, the verification signal VER is logic Level 0. At this time, the conduction of the transistors T22 and T23 depends on the logic level of the write data SMOUT and the reverse read signal SAOUTb. When both the transistors T22 and T23 are turned on, the detection result CR can be pulled down to a logic level of 0. On the contrary, when at least one of the transistors T22 and T23 is not turned on, the detection result CR is maintained at logic level Level 1. Therefore, the relationship between the write data SMOUT, the readout signal SAOUT and the detection result CR is shown in Table 1 below:

Table 1: SMOUT SAOUT CR 1 1 1 1 0 1 0 0 1 0 1 0

Here, in Table 1 above, when the detection result CR is the logic level 0, it means that the non-volatile memory cell array needs to perform further programming actions. On the contrary, when the detection result CR is the logic level 1, it means that the non-volatile memory cell array needs to perform further programming actions. The volatile memory cell array does not need to perform further programming.

In addition, in the soft programming verification stage, the AND gate AN2 in the pull-down circuit 330 can output the reverse read data SAOUTb to become the control signal CT4 according to the soft programming verification signal PSTVER which is a logic level 1. Therefore, when the reverse read data SAOUTb is at the logic level 0 (the read data SAOUT is at the logic level 1), the transistor T32 is turned on, and the detection result CR is pulled down to the logic level 0. On the contrary, when the reverse read data SAOUTb is at the logic level 1 (the read data SAOUT is at the logic level 0), the transistor T32 is turned off, and the detection result CR is maintained at the logic level 1.

Here, in the soft programming verification stage, when the detection result CR is the logic level 0, it means that the non-volatile memory cell array needs to perform further soft programming actions. On the contrary, when the detection result CR is the logic level 1 , indicating that the non-volatile memory cell array does not need to perform further soft programming actions.

In the erasing verification stage, the AND gate AN3 in the pull-down circuit 340 can output the reverse read data SAOUTb to become the control signal CT5 according to the erasing verification signal EVER having a logic level of 1. Therefore, when the reverse read data SAOUTb is at the logic level 1 (the read data SAOUT is at the logic level 0), the transistor T42 is turned on, and the detection result CR is pulled down to the logic level 0. On the contrary, when the reverse read data SAOUTb is at the logic level 0 (the read data SAOUT is at the logic level 1), the transistor T42 is turned off, and the detection result CR is maintained at the logic level 1.

Here, in the erasing verification stage, when the detection result CR is the logic level 0, it means that the non-volatile memory cell array needs to perform further erasing operations. On the contrary, when the detection result CR is the logic level 1, Indicates that the non-volatile memory cell array does not need to perform further erase operations.

It is worth mentioning that in the programming verification stage, the erasing verification stage and the soft programming verification stage, the test result CR can represent the verification result. Wherein, in this embodiment, when the detection result CR is the logic level 0, it means that the verification result is not passed, and when the detection result CR is the logic level 1, it means that the verification result is passed. The verification result can be sent to a logic circuit in the non-random access memory. The logic circuit can control the programming action, the erasing action and the soft programming action of the non-volatile memory cell array according to the detection result CR.

Incidentally, in this embodiment, the write enable signal WREN_P1 can be pulled to logic level 1 during the data loading stage, the programming verification stage, the soft programming verification stage, and the erase verification stage. The write enable signal WREN_P2 can be pulled high to the logic level 1 when the first data DB and the second data DBb are to be generated according to the detection result CR for output.

Please note that the circuit diagram shown in FIG. 3 is a circuit for processing a single bit. However, in the embodiment of the present invention, the number of bits of the write data SMOUT and the read data SAOUT is not limited to one. The illustration in FIG. 3 is only for the convenience of description. When processing the write data SMOUT and the read data SAOUT with a plurality of bits, it can be implemented by duplicating a plurality of circuits in FIG. 3 .

Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of a non-volatile memory device according to another embodiment of the present invention. The non-volatile memory device 400 includes a non-volatile memory cell array 410 , a sense amplifier 420 , a random access memory 430 , a buffer circuit 440 and a logic circuit 450 . Different from the embodiment of FIG. 1 , the buffer circuit 440 is coupled to the input terminal PAD to receive the input data WDIN, wherein the input terminal PAD can be a pad on the chip, instead of the non-volatile memory cell array 410 and the sense amplifier 420 , the random access memory 430 , the buffer circuit 440 and the logic circuit 450 are arranged on the same chip. In addition, the buffer circuit 440 is further coupled to the logic circuit 450 , and transmits the detection results CR in the multiple verification stages to the logic circuit 450 . The logic circuit 450 can determine whether to make the non-volatile memory cell array perform another programming operation, soft programming operation or erasing operation according to the detection result CR.

In this embodiment, the random access memory 430 may be a static random access memory, and the non-volatile memory cell array may be a flash memory cell array.

To sum up, the non-volatile memory device of the present invention can perform detection operations of various verification operations by providing a buffer circuit with detection capability, and can provide a buffer for writing random access memory. In this way, the circuit structure of the non-volatile memory device of the present invention can be simplified, the cost required for the circuit can be effectively reduced, and the price competitiveness of the product can be improved.

100, 400: Non-volatile memory device 110, 410: Non-volatile memory cell arrays 120, 420: sense amplifier 130, 430: random access memory 140, 200, 300, 440: Buffer circuit 210, 310: rising circuit 220~240, 320~340: pull-down circuit 250, 350: output buffer 321: selector 322, 323: Logic circuits 450: Logic Circuits AN1~AN3: and gate CR: test results CRb: reverse detection result CT2, CT3, CT4, CT5: Control signal EVER: Erase Verification Signal GND: Reference ground terminal NA1~NA3: Reverse and gate NO1~NO4: Reverse OR gate OE: output terminal OR1: OR gate PAD: input endpoint PSTVER: Soft Stylized Verification Signal PVER: Programmatic Verification Signal QB, QBb: Information SAOUT: read data SAOUTb: read data in reverse SMOUT: write data T1, T22, T23, T32, T42, T51~T54: Transistor VDD: reference voltage VER: verify action signal WDIN: input data WREN_P1, WREN_P2: Write action enable signal

FIG. 1 is a schematic diagram of a non-volatile memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram illustrating an implementation of a buffer circuit of a non-volatile memory device according to an embodiment of the present invention. 3 is a circuit diagram illustrating an implementation of a buffer circuit of a non-volatile memory device according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a non-volatile memory device according to another embodiment of the present invention.

100: Non-volatile memory device

110: Non-volatile memory cell array

120: Sense Amplifier

130: Random Access Memory

140: Buffer circuit

WDIN: input data

SMOUT: write data

SAOUT: read data

CR: test results

Claims (15)

A non-volatile memory device comprising: a non-volatile memory cell array; a sense amplifier coupled to the non-volatile memory cell array for generating a readout data; a random access memory for storing a write data; and a buffer circuit, coupled to the random access memory and the sense amplifier, generates a detection result according to a target data and the read data, the buffer circuit causes the detection result to be written into the random access Memory. The non-volatile memory device of claim 1, wherein the buffer circuit further enables an input data to be written into the random access memory to become the written data in a data loading stage. The non-volatile memory device of claim 1, wherein in a program verification stage, the buffer circuit reads the written data from the random access memory as the target data. The non-volatile memory device of claim 1, wherein in an erase verification stage, the buffer circuit sets the target data to a first logic level, and in a soft programming verification stage, the buffer circuit sets the target The data is a second logic level, wherein the first logic level and the second logic level are complementary. The non-volatile memory device of claim 1, wherein the buffer circuit comprises: a pull-up circuit, providing a first driving capability to pull up the detection result to a preset logic level; a first pull-down circuit for providing a second driving capability to pull down the detection result according to the target data and the readout data in a program verification stage; a second pull-down circuit that compares the target data and the readout data to provide a third drive capability to pull down the detection result in a soft programming verification stage; a third pull-down circuit for comparing the target data and the readout data to provide a fourth drive capability to pull down the detection result in an erase verification stage; and an output buffer, receiving the detection result, outputting the detection result to the random access memory, The second driving capability, the third driving capability and the fourth driving capability are all greater than the first driving capability. The non-volatile memory device of claim 5, wherein the pull-up circuit comprises: A first transistor with a first terminal receiving a reference voltage, a control terminal of the first transistor receiving a first signal to turn on or off, a second terminal of the transistor coupled to an output terminal, the output terminal terminal for providing the test result; and A first logic circuit receives a first write operation enable signal and a verification operation signal, and generates the first signal according to the first write operation enable signal and the verification operation signal. The non-volatile memory device of claim 6, wherein the pull-up circuit further comprises: a second logic circuit, coupled to the output terminal to receive the detection result, and to receive the write-action enable signal, and to determine whether to output the detection result to the output buffer according to the first write-action enable signal . The non-volatile memory device of claim 7, wherein the first logic circuit performs an inverse-OR logic operation, and the second logic circuit performs an AND logic operation. The non-volatile memory device of claim 6, wherein the first pull-down circuit comprises: a selector for selecting an input data or the write data to generate a selected data according to a programmed verification signal; a second logic circuit, receiving the selected data and the verification signal, and generating a first control signal according to the selected data and the verification signal; a second transistor having a first end coupled to the output end, and a control end of the second transistor receiving the first control signal; a third transistor, coupled in series between the second terminal of the second transistor and a reference ground terminal, the third transistor is controlled by a second control signal; and A third logic circuit generates the second control signal according to the programmed verification signal and the read data. The non-volatile memory device of claim 9, wherein the second logic circuit performs an inverse OR logic operation, and the third logic circuit performs a logic inversion and a logic operation. The non-volatile memory device of claim 6, wherein the second pull-down circuit comprises: a second transistor having a first end coupled to the output end, and a control end of the second transistor receiving a first control signal; A second logic circuit generates the first control signal according to a soft-programmed verification signal and the read data. The non-volatile memory device of claim 11, wherein the two logic circuits perform inverse and logical operations. The non-volatile memory device of claim 6, wherein the third pull-down circuit comprises: a second transistor having a first end coupled to the output end, and a control end of the second transistor receiving a first control signal; A second logic circuit generates the first control signal according to an erase verification signal and the read data. The non-volatile memory device of claim 13, wherein the second logic circuit performs an inverse logical operation for the erase verification signal and the reverse of the read data. The non-volatile memory device of claim 6, wherein the output buffer comprises: a first output stage circuit, based on a second write action enable signal, to generate a first data according to the detection result; and a second output stage circuit generates a second data according to the detection result based on the second write action enable signal, Wherein the first data is complementary to the second data.

Images