TW202209485A - Method of expanding 3d device architectural designs for enhanced performance - Google Patents

Abstract

Aspects of the present disclosure provide a vertical channel 3D semiconductor devices and a method for fabricating the same. The 3D semiconductor devices may have vertical channels of the same or different epitaxially grown doped materials. Sidewall structures are formed around each vertical channel by masking and etching material between the vertical channels. A dielectric layer in each of the sidewalls is etched down to the vertical channel and a gate electrode structure is formed in the opening. The gate electrode structure may include an interfacial oxide, a high-K layer and alternating metal layers. Local interconnects connect to the metal of the gate structure.

Description

Methods for extending 3D device structural design to enhance performance

The present invention relates to microelectronic devices including vertical channel semiconductor devices, transistors and integrated circuits, including microfabrication methods. [Cross-reference to related applications]

This application claims US Provisional Application No. 63/019,015, filed on May 1, 2020, US Non-Provisional Application No. 17/189,674, filed on March 2, 2021, and US Provisional Application No. 17/189,674, filed on May 22, 2020 Application No. 63/028,620, US Non-Provisional Application No. 17/113,736, filed on December 7, 2020, US Provisional Application No. 63/028,618, filed on May 22, 2020, and December 8, 2020 Priority to US Non-Provisional Application Serial No. 17/115,122, filed in Japan, the entire disclosure of which is hereby incorporated by reference.

In the fabrication of semiconductor devices, especially at the microscale, many fabrication processes, such as film deposition, etch mask formation, patterning, material etching and removal, and doping processes, can be performed. These processes can be repeated to form desired semiconductor device elements on the substrate.

Historically, with microfabrication, transistors have been formed in a plane with wiring/metallization formed above the plane of the active device, and thus have been characterized as two-dimensional (2D) circuits or 2D fabrication. Efforts in scaling have dramatically increased the number of transistors per unit area in 2D circuits, but are facing greater challenges as scaling moves into the single-digit nanoscale semiconductor device fabrication node. Semiconductor device manufacturers have expressed a need for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of one another.

3D integration (ie, vertical stacking of multiple devices) aims to overcome the scaling limitations encountered in planar devices by increasing the density of transistors in volume rather than area. While the flash memory industry has successfully demonstrated and implemented device stacking with the adoption of 3D NAND, application to random logic designs is substantially more difficult. 3D integration of logic chips (CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array, SoC (System On Chip)) is required.

Accordingly, it is an object of the present invention to provide methods and apparatus for vertical transistors that can be stacked on top of one another.

The techniques herein include methods of microfabrication of 3D devices that extend the design of 3D device structures to enhance calibration and enable higher density circuits to be produced at lower cost. Vertical 3D epitaxial growth of vertical transistors allows current flow in the vertical dimension or perpendicular to the wafer surface. The methods and designs herein include fabricating CMOS devices with vertical current flow. The vertical 3D devices herein enable another degree of freedom in the z-direction that will enhance the routing options of existing 3D devices. Since the channel length is defined by the deposited or epitaxially grown layers, relatively short transistor lengths are achieved. Precise alignment with the gate electrode is achieved by selectively removing the intermediate dielectric layer. The techniques herein obviate the need for oxide isolation for 3D nanostacks.

A first embodiment describes a method of microfabrication comprising: forming a dielectric layer stack on a first layer of semiconductor material, the dielectric layer stack having at least three layers, wherein the first dielectric material is located below the second dielectric material and Above, the first dielectric material differs from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material; openings are formed in the dielectric layer stack such that the first layer of semiconductor material is exposed ; epitaxially growing channel material in the exposed opening to form vertical channels; removing a portion of the dielectric layer stack so that the sidewall structures remain on the vertical channels; removing the second dielectric material from the sidewall structures to expose the sidewall surfaces of the vertical channels ; and forming gate structures on exposed sidewall surfaces of the vertical channels.

A second embodiment describes a semiconductor device comprising: a substrate layer; a first layer of a first dielectric material; a first layer of semiconductor material; a dielectric layer stack having at least three layers, wherein the first dielectric material is positioned over the second dielectric material Below and above, the first dielectric material is different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material; a first opening in the dielectric layer stack in which the first dielectric material is exposed A layer of semiconductor material; vertical channels with epitaxially grown dopant material in the first openings; sidewall structures formed by second openings in the stack of dielectric layers between the vertical channels; first of the sidewall structures Three openings formed by removing the second dielectric material up to the vertical channels; gate structures in the third openings; and local interconnects connected to the gate structures of each vertical channel configured to conduct Current perpendicular to the working surface of the substrate layer.

3D integration (ie, vertical stacking of multiple devices) aims to overcome the scaling limitations encountered in planar devices by increasing the density of transistors in volume rather than area. While the flash memory industry has successfully demonstrated and implemented device stacking with the adoption of 3D NAND, application to random logic designs is substantially more difficult. 3D integration of logic chips (eg, central processing unit (CPU), graphics processing unit (GPU), field programmable gate array (FPGA), and system-on-chip (SoC)) is being pursued.

Aspects of the present invention provide methods for fabricating 3D semiconductor devices. In one embodiment, the 3D semiconductor apparatus may include a first semiconductor device and a second semiconductor device. For example, the method can include forming a multi-layer stack on a substrate, the multi-layer stack including a plurality of layers of at least three different dielectric materials capable of being selectively etched relative to each other. The method may also include forming at least one opening down through the multilayer stack to the substrate such that the substrate is exposed. The method may also include vertically forming a first channel of a first semiconductor device of the semiconductor device from the exposed substrate and vertically forming a second channel of a second semiconductor device of the semiconductor device from the first channel. The method may also include removing the transition dielectric layer of the multilayer stack such that a portion of the first channel and the second channel that interface at the transition dielectric layer are exposed. The method may also include forming a silicide at the exposed portion to couple the first channel to the second channel. In one embodiment, the method may also include etching the multilayer stack to define sidewall structures of the multilayer stack surrounding the first and second vias, wherein removing the transition dielectric layer in the layers of the multilayer stack includes removing a layer of the multilayer stack. The transition dielectric layer of the sidewall structure of the layers.

For example, the first and second semiconductor devices are of different types. In one embodiment, the silicide may be formed by depositing silicide metal on the exposed portions of the first channel and the second channel, and silicidizing the silicide metal and the exposed portions of the first channel and the second channel. . For example, the silicide metal can be selected from the group consisting of ruthenium (Ru), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), platinum (Pt), and nickel (Ni). In an embodiment, the opening may have a rectangular or circular cross-section.

In one embodiment, the method may further include removing the gate dielectric layers of the layers of the multilayer stack and replacing with gate material to form a first gate region of the first semiconductor device and a second gate of the second semiconductor device extreme region. In another embodiment, the first and second gate regions may be formed by removing the gate dielectric layer to expose the first and second channels; forming gate dielectric material on the exposed first and second channels ; forming a first metal material on the gate dielectric material; forming a second metal material surrounded by the first metal material adjacent to the first channel; and forming a third metal material surrounded by the first metal material adjacent the second channel surrounded by a metallic material. For example, at least one of the first and second metallic materials may include at least two different metallic materials. As another example, the second and third metallic materials may comprise the same metallic material. In one embodiment, forming the gate dielectric material may include forming the gate dielectric material on the first and second channels and the multilayer stack.

In one embodiment, the method may further include forming an implant layer on the substrate, wherein the multi-layer stack is formed on the implant layer. In another embodiment, vertically forming a first channel of a first semiconductor device of the semiconductor device from the exposed substrate and vertically forming a second channel of a second semiconductor device of the semiconductor device from the first channel may include: within the opening, from The implant layer epitaxially grows a first channel material into the transition dielectric layer to form a first channel, and epitaxially grows a second channel material from the transition dielectric layer within the opening to the top of the multilayer stack to form a second channel. For example, the first channel material and the implant layer may be doped with the same type of dopant.

In one embodiment, the method may further include forming a fourth metal material on the silicide. In another embodiment, the method may further include forming a silicide on the multi-layer stack, and forming a fifth metal material on the silicide. In yet another embodiment, the method may further include removing a second source/drain (S/D) dielectric layer of the layers of the multilayer stack and replacing with a second S/D material to form a second semiconductor device the second S/D region, and the first S/D dielectric layer in the layers of the multilayer stack is removed and replaced with the first S/D material to form the first S/D region of the first semiconductor device. For example, the second S/D dielectric layer can be selectively etched relative to the first S/D dielectric layer.

Aspects of the present invention also provide semiconductor devices. For example, a semiconductor apparatus may include a first semiconductor device and a second semiconductor device stacked on the first semiconductor device. In one embodiment, the first semiconductor device may include a first S/D region, a first gate region sandwiched between the first S/D regions, and a first S/D region and a first gate The first channel surrounded by the area. In another embodiment, the second semiconductor device may include a second S/D region, a second gate region sandwiched between the second S/D regions, and a second S/D region and the second gate The pole region surrounds a second channel formed in situ perpendicular to the first channel. As another example, the semiconductor device may further include a silicide. In one embodiment, a silicide may be formed between the first semiconductor device and the second semiconductor device, where the first channel and the second channel interface, and the silicide is coupled to the first S// of the first semiconductor device The upper one of the D region and the lower one of the second S/D region of the second semiconductor device.

For example, the first semiconductor device and the second semiconductor device may be of different types. In one embodiment, the first gate region may include a first metal material and a second metal material surrounded by the first metal material, and the second gate region may include a first metal material and a second metal material surrounded by the first metal material. Three metal materials. For example, the second metal material and the third metal material may include the same metal material.

According to a first aspect, a semiconductor device is provided. The semiconductor device may include a pad layer including at least one pad structure having a core region and a peripheral region surrounding the core region. The semiconductor device may also include a transistor over the core region of the pad structure. The transistor includes a channel structure extending in a vertical direction and a gate structure around sidewall portions of the channel structure. The channel structure has a vertical channel region and source and drain regions on opposite ends of the vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. The semiconductor device may further include a first vertical interconnect structure contacting the top surface of the channel structure, a second vertical interconnect structure contacting the peripheral region and configured to couple to the bottom surface of the channel structure through the pad structure, disposed away from the channel structure and contact the third vertical interconnect structure of the gate structure of the transistor.

In some embodiments, the semiconductor device may further include a fourth vertical interconnect structure that contacts the peripheral region of the pad structure or the gate structure of the transistor.

In some embodiments, the channel structure may be centered or offset from the center of the pad structure.

In some embodiments, the second vertical interconnect structure and the third vertical interconnect structure may be located at the same radial position or at different radial positions from the channel structure, and the second vertical interconnect structure and the third vertical interconnect structure Can be located at the same distance or at different distances from the channel structure.

In some embodiments, a particular transistor over a particular pad structure can be the same or different from an adjacent transistor over an adjacent pad structure.

In some embodiments, one or more of the at least one pad structure can be separated from each other by a dielectric material.

In some embodiments, the at least one pad structure may include a first pad structure and a second pad structure adjacent to and in contact with the first pad structure. The third vertical interconnect structure over the first pad structure and the third vertical interconnect structure over the second pad structure are chemically identical and contact each other to integrally form the first common vertical interconnect structure, and the first pad structure The second vertical interconnect structure above and the second vertical interconnect structure above the second pad structure are chemically identical and contact each other to integrally form a second common vertical interconnect structure. The first common vertical interconnect structure can contact the first gate structure of the first transistor disposed above the first pad structure and the second gate structure of the second transistor disposed above the second pad structure, and the second The common vertical interconnect structure may contact the first pad structure and the second pad structure. Further, the semiconductor device may include a horizontal contact structure contacting the first pad structure and the second pad structure. The horizontal contact structure is disposed under the first common vertical interconnect structure. The semiconductor device may also include a dielectric material separating the horizontal contact structure from the first common vertical interconnect structure.

According to a second aspect of the present invention, a method of microfabrication is provided. The method can include forming a pad over the substrate. The pad layer includes at least one pad structure, the core area of which is surrounded by the peripheral area. A transistor can be formed over the core region of the pad structure. The transistor includes a channel structure extending in a vertical direction and a gate structure around sidewall portions of the channel structure. The channel structure has a vertical channel region and source and drain regions on opposite ends of the vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. A first vertical interconnect structure can be formed that contacts the top surface of the channel structure. A second vertical interconnect structure can be formed that contacts the peripheral region of the pad structure and is configured to couple to the bottom surface of the channel structure through the pad structure. A third vertical interconnect structure can be formed that is positioned away from the channel structure and contacts the gate structure of the transistor.

In some embodiments, after forming the transistor over the core region of the pad structure, the method may further include depositing an insulating material over the pad layer to fill the space and cover the transistor. In some embodiments, forming the first vertical interconnect structure may include forming an opening in an insulating material. The opening exposes the top surface of the channel structure. Fill the opening with conductive material. In some embodiments, forming the second vertical interconnect structure may include forming an opening in the insulating material. The opening exposes the peripheral region of the pad structure. Fill the opening with conductive material. In some embodiments, forming the third vertical interconnect structure may include forming an opening in the insulating material. The opening exposes the gate structure. Fill the opening with conductive material.

In some embodiments, prior to depositing the insulating material over the pad layer, the method may further include depositing a first conductive material that surrounds the transistor and contacts the gate structure. The first conductive material is etched based on the mask so that the first conductive material covers the sidewall portion of the transistor and contacts the sidewall portion of the gate structure. Forming the third vertical interconnect structure may further include forming an opening in the insulating material. The opening exposes the first conductive material. The opening is filled with a second conductive material. The second conductive material is disposed above the first conductive material.

In some embodiments, a fourth vertical interconnect structure may be formed that contacts the peripheral region of the pad structure or the gate structure of the transistor.

According to a third aspect of the present invention, a method of microfabrication is provided. The method can include forming a pad over the substrate. The pad layer includes a first pad structure and a second pad structure adjacent to and in contact with the first pad structure. Transistors may be formed over the first and second pad structures. The transistor includes a channel structure extending in a vertical direction and a gate structure around sidewall portions of the channel structure. The channel structure has a vertical channel region and source and drain regions on opposite ends of the vertical channel region. The channel structures are configured to be electrically coupled to corresponding pad structures disposed below the channel structures and extending horizontally beyond the perimeter of the channel structures. A first vertical interconnect structure can be formed that contacts the first top surface of the first channel structure of the first transistor disposed above the first pad structure. A second vertical interconnect structure can be formed that contacts the second top surface of the second channel structure of the second transistor disposed above the second pad structure. A first common vertical interconnect structure can be formed that is configured to couple to the first gate structure of the first transistor and the second gate structure of the second transistor. A second common vertical interconnect structure can be formed that contacts the first pad structure and the second pad structure.

In some embodiments, after forming the transistor over the first and second pad structures, the method may further include forming a first horizontal contact structure and a second horizontal contact structure. Both the first horizontal contact structure and the second horizontal contact structure contact the first pad structure and the second pad structure. A dielectric material is deposited over the first horizontal contact structure. A first conductive material is deposited over the dielectric layer to connect the first gate structure and the second gate structure. An insulating material is deposited over the pad layer to fill the spaces and cover the transistors.

In some embodiments, forming the first vertical interconnect structure may be accomplished by forming a first opening in an insulating material and filling the first opening with a second conductive material. The first opening exposes the first top surface of the first channel structure. Forming the second vertical interconnect structure is accomplished by forming a second opening in the insulating material and filling the second opening with a third conductive material. The second opening exposes the second top surface of the second channel structure. Forming the first common vertical interconnect structure is accomplished by forming a third opening in the insulating material and filling the third opening with a fourth conductive material. The third opening exposes the first conductive material. Forming the second common vertical interconnect structure is accomplished by forming a fourth opening in the insulating material and filling the fourth opening with a fifth conductive material. The fourth opening exposes the second horizontal contact structure.

Of course, the order of discussion of the various steps described herein has been presented for clarity. In general, such steps may be performed in any suitable order. Additionally, although each of the various features, techniques, configurations, etc. herein may be discussed in various places of the present disclosure, it is intended that each concept may be implemented independently of each other or in any suitable combination with each other. Accordingly, the present invention may be embodied and outlined in many different ways.

Note that this Summary section does not specify each embodiment and/or added novel aspect of the invention or claimed invention. Rather, this summary provides only a preliminary discussion of the various embodiments and corresponding points of novelty over the prior art. For additional details and/or possible perspectives of the invention and examples, the reader is referred to the Embodiments of the Invention section and corresponding drawings discussed further below.

Reference is now made to the drawings, wherein like reference numerals refer to like or corresponding parts throughout the several views.

The techniques herein include methods of microfabrication of 3D devices that extend the design of 3D device structures to enhance performance and enable higher density circuits to be produced at lower cost. Vertical 3D epitaxial growth of vertical transistors allows current flow in the vertical dimension or perpendicular to the wafer surface. The methods and designs herein include fabricating CMOS devices with vertical current flow. The vertical 3D devices herein enable another degree of freedom in the z-direction that will enhance the routing options of existing 3D devices. Since the channel length is defined by the deposited or epitaxially grown layers, relatively short transistor lengths are achieved. Precise alignment with the gate electrode is achieved by selectively removing the intermediate dielectric layer. The techniques herein obviate the need for oxide isolation for 3D nanostacks. For GAA devices with specific substrate conditions, vertical transistors can have infinite W.

Because the gate and source regions have a 360 degree connection, contacts can be placed on either side of the source or either side of the gate. The source and drain are interchangeable because each channel can be isolated from the others. The 360 degree connection is a significant advantage of the device construction for maximum wiring connection and routing. A given channel area can be concentrated in the S/D epitaxial area or offset for maximum routing efficiency depending on circuit requirements. The vertical 3D structure provides accessibility (360-degree contacts and routing to channels, sources and drains), thereby increasing circuit density.

Exemplary embodiments herein will describe several flows with reference to the drawings. 1A-1L illustrate a single vertical monocrystalline (or large grain boundary) NMOS gate-all-around (GAA) device using a substrate containing a silicon/oxide/silicon stack for NFET devices. 2A-2L illustrate a single vertical monocrystalline (or large grain boundary) PMOS gate full ring (GAA) device using a substrate comprising a silicon/oxide/silicon stack for a PFET device. 3A-3V illustrate CMOS formation using side-by-side single crystal GAA devices (NMOS and PMOS) for double epitaxial growth.

Referring now to FIG. 1A, a substrate 102 is prepared with a layer stack. This may include alternating layers of first dielectric material 104 and second dielectric material 108 . The dielectric materials are selected to be etch selective with respect to each other. The dielectric material may be SiN, silicon oxide, silicon dioxide, silicon carbide or the like. For example, a given isotropic or vapor phase etch can etch one dielectric material without etching (substantially etching) another dielectric material. In an exemplary embodiment, the first dielectric material 104 is silicon dioxide and the second dielectric material 108 is a high-K dielectric material. The high-K dielectric material can be Al ₂ O ₃ , AlN, ZrO ₂ , HfO ₂ , HfSiO _x , ZrSiOx, HfOxNy, ZrOxNy, HfxZryOz, Ta2O5, La2O3, _Y2O3 , Nb2O5, _TiO2 , Pr2O3, Gd2O3, SiBN, BCN, hydrogenated boron carbide, or the like.

In this stack, an oxide is deposited over the bulk substrate 102 material, followed by a layer of semiconductor material 106 over the oxide. This can be silicon or germanium or other N+ semiconductor materials. It can be deposited amorphous and then crystallized by baking or laser annealing. This layer may be formed of N+ dopant or implanted with N+ dopant. The N+ dopant may in particular be, for example, arsenic or phosphorous or the like. Above this semiconductor layer, a dielectric layer stack is formed of alternating layers. The dielectric layer stack includes at least the first dielectric material 104 separating the second dielectric material 108 . This will then be able to reveal the channel and maintain the spacing from the source/drain regions.

In Figure IB, photoresist 110 is used to form an etch mask on the layer stack. Photoresists are light-sensitive materials that are used in yellow light lithography to form a patterned coating on a surface. The etch mask defines openings formed in the layer stack. This opening can be circular, square/rectangular, or other channel cross-sectional shape. A directional/anisotropic etch is performed using this etch mask to remove the exposed portion 140 of the layer stack until the layer of semiconductor material 106 is reached and exposed. The mask layer 110 may then be removed.

Using the N+ material exposed in the opening, the N+ channel material 112 can be grown by epitaxial growth, as shown in FIG. 1C . Since the channel length of deposition is defined by physical deposition, the channel length herein can be as short as 10 Angstroms. For channel lengths that are considered relatively short, such lengths may be about 20A to 100A. It is known that channel lengths of tens or hundreds of nanometers are also considered. Longer lengths provide relaxed miniature sizes.

In FIG. 1D , a second etch mask of photoresist 110 is formed to define sidewall structures around epitaxially grown vertical channels 112 . Etching is performed, leaving sidewall structures on the vertical channels. The sidewall structures have a specific thickness and maintain a stack of alternating dielectric layers that substantially surround the vertical channels. This etch defines the future gate electrode region.

In FIG. 1E , the existing photoresist 110 from FIG. 1D is removed and a new pattern of photoresist 110 is applied to etch through the N+ silicon layer to isolate each device with openings 131 . This isolates each device for maximum circuit application. This step is optional. In other embodiments, the photoresist mask 110 used to define the sidewall structure of FIG. 1D can also be used to isolate the N+ silicon.

FIG. 1F, the photoresist 110 has been removed and a third dielectric material 114 has been grown or deposited on the open substrate regions and N+ regions. The third dielectric material 114 should have etch selectivity with respect to the second dielectric material 108 . Non-limiting examples of dielectric materials that are selective with respect to each other are _SixOy , _SixNy , and _SiOxNy , high- _K and ₍ high- _{K ) OxNy} .

In FIG. 1G, the second dielectric material 108 is removed without removing the first dielectric material or the third dielectric material. This reveals the future gate electrode region.

In FIG. 1H, any sacrificial oxide or interfacial oxide growth can be removed or cleared, followed by deposition of a selective high-K layer 116.

In Figure II, a selective high-K annealing step may be performed. An interfacial oxide growth 118 may be formed between the high-K layer and the vertical channel.

In Figure 1J, a metal gate electrode stack 120 may be formed/deposited on the substrate. This can be one or more layers to adjust the voltage threshold (Vt) of the transistor device. This can be conformal deposition.

In Figure 1K, a directional etch is performed to remove the gate stack material 120 from the substrate, leaving the gate stack material around the vertical channels, thus forming a GAA device. Processing may then continue, such as by forming local interconnects or other connections (not shown). Additional vertical channel GAA devices can be formed on the layers of the device to repeat the fabrication process (not shown).

1L is a perspective view of the device formed through the process of FIGS. 1A-1K. FIG. 1L shows a first layer of semiconductor material 106 , a layer of dielectric material 104 , a metal gate electrode stack 120 , a layer of dielectric material 104 , and an N+ epitaxial vertical channel 112 . Metal connections 132, 134, and 136 are attached to the first layer 106, the N+ epitaxial vertical channel 112, and the metal gate electrode stack 120, respectively.

2A-2K illustrate a similar flow for forming a PFET device. The process flow is similar except that a P-doped silicon or germanium layer 122 can be formed instead of the N-doped layer. Other than that, the mask, sidewall structure formation and gate electrode formation are similar.

In Figure 2A, a dielectric oxide 204 is deposited over the bulk substrate 202 material, followed by a layer of semiconductor material 222 over the oxide. It can be deposited amorphous and then crystallized by baking or laser annealing. This layer may be formed of P+ dopant or implanted with P+ dopant. The P+ dopant may be boron, gallium, indium, or other P+ semiconductor materials. Above the semiconductor layer, a dielectric layer stack is formed of alternating layers. The dielectric layer stack includes at least a top and bottom dielectric oxide 204 isolating the second dielectric material 208 .

In FIG. 2B , photoresist 210 is patterned on top layer 204 to define openings for etch channel regions 242 . Such openings may be rectangular or cylindrical.

In FIG. 2C, a P+ channel material 224 may be epitaxially grown using the P+ material exposed within the opening.

2D, photoresist 210 is patterned over the P+ material and sidewall structures are defined around epitaxially grown vertical channels 224. Etching is performed, leaving sidewall structures on the vertical channels. The sidewall structures have a specific thickness and maintain a stack of alternating dielectric layers that substantially surround the vertical channels. This etch defines the future gate electrode region.

In FIG. 2E , the existing photoresist 210 from FIG. 2D is removed and a new pattern of photoresist 210 is applied to etch through the P+ silicon layer to isolate each device at openings 231 . This isolates each device for maximum circuit application. This step is optional. In other embodiments, the photoresist mask 210 used to define the sidewall structure of FIG. 2D can also be used to isolate the P+ silicon.

In Figure 2F, the photoresist 210 of Figure 2E has been removed and a third dielectric 214 has been grown or selectively deposited on the open substrate regions and P+ regions. The third dielectric material 214 should have etch selectivity with respect to the second dielectric material 208 .

In FIG. 2G , the second dielectric material 208 is removed without removing the top and bottom dielectric oxides 204 or the third dielectric material 214 . This reveals the future gate electrode region.

In FIG. 2H, any sacrificial oxide or interfacial oxide growth may be removed or cleared from future electrode regions, followed by deposition of a selective high-K layer 216 on the vertical channel material 224 between the layers of the first dielectric 204 in the gate region.

In Figure 2I, a selective high-K annealing step may be performed. An interfacial oxide growth 218 can be formed between the high-K layer and the vertical channel.

In Figure 2J, a metal gate electrode stack 220 may be formed/deposited on the substrate. This can be one or more layers to adjust the voltage threshold (Vt) of the transistor device. This can be conformal deposition.

In Figure 2K, a directional etch is performed to remove the metal gate stack 220 from the substrate, top and sides, leaving only the gate stack material in and around the vertical channel, thus forming a GAA device. Processing may then continue, eg, by forming local interconnects, LI(MO), metal 1, or other connections (not shown). Additional vertical channel GAA devices can be formed on the layers of the device to repeat the fabrication process (not shown).

2L is a perspective view of the device formed by the process of FIGS. 2A-2K. FIG. 2L shows a first layer of semiconductor material 222 , a layer of dielectric material 204 , a metal gate electrode stack 220 , a layer of dielectric material 204 , and a P+ epitaxial vertical channel 224 . Metal connections 232, 234, and 236 are attached to the first layer 222, the N+ epitaxial vertical channel 224, and the metal gate electrode stack 220, respectively.

3A-3T illustrate a process flow for forming side-by-side vertical channel PFET and NFET devices.

In FIG. 3A , the process flow begins with a substrate with monocrystalline silicon 305 on a dielectric layer 304 on silicon 302 . A photomask of photoresist 310 can be formed to define regions for N+ implant doping (phosphorus, arsenic...) or plasma doping to form N+ layer 306 .

In FIG. 3B, the photomask 310 of FIG. 3A is removed and a second mask of photoresist 310 covers the N+ layer 306 to define areas for P+ dopants (eg, BF2, B, . . . ) to form the P+ layer 322. Although the N+ layer is shown on the left side of FIG. 3A and the P+ layer is shown on the right side of FIG. 3B , in other aspects, the dopant regions may be reversed so that P+ is on the right and N+ is on the left.

Figure 3C illustrates optionally separating and isolating doped semiconductor regions at this point in the process flow. In this alternative, a photoresist pattern with openings can be formed over the structure and then etched down to the dielectric layer 304.

In Figure 3D, alternating layers 304, 308, 304 may be deposited after the implant is annealed, similar to the previous process. In a non-limiting example, dielectric layer 304 may be an oxide and dielectric material 108 may be a high-K dielectric material.

In Figure 3E, photoresist 310 may be patterned to provide regions in the dielectric layer stack that are etched down to the doped layers (N+ or P+) to define openings 342 for vertical channels. Such openings may be circular, square or rectangular. In a non-limiting example, the openings may be 10 nm in diameter and have a height of 5-50 angstroms.

In FIG. 3F , a third dielectric material 314 may be grown or selectively deposited in the regions of the substrate defined by openings 342 . This prevents epitaxial growth in the selective regions during subsequent process steps. The third dielectric material 314 should have etch selectivity with respect to the second dielectric material 308 .

In FIG. 3G, the PMOS region (right stack) is blocked, and the dielectric material 314 is removed from the NMOS region (left stack).

In FIG. 3H, the N+ channel region 312 is epitaxially grown, and the PMOS region is protected by the third dielectric material 314 without epitaxial growth.

In Figure 3I, the photoresist 310 is removed and a protective film 326, such as a conformal nitride, is deposited on the substrate to cover the N+ epitaxial regions.

In Figure 3J, the protective film 326 in the PMOS region is removed.

In Figure 3K, P+ vertical channel material 324 is epitaxially grown. The P+ dopant may be boron, gallium, indium, or other P+ semiconductor materials. Remove the remaining nitride. So far, the N+ and P+ vertical channels are completed.

In Figure 3L, photoresist 310 is patterned over the NMOS and PMOS regions, and the dielectric stack is etched to form sidewall structures around the vertical channels.

FIG. 3M shows the growth or selective deposition of a third dielectric material 314 over the open substrate regions and the N+ and P+ regions. The dielectric material 314 should have etch selectivity with respect to the second dielectric material 308 .

In FIG. 3N , dielectric material 308 is removed without removing dielectric material 304 or dielectric material 314 . This reveals the future gate electrode region.

In FIG. 30 , the sacrificial oxide or interfacial oxide growth (not shown) may be removed, followed by pre-cleaning, followed by selective high-K deposition 316 . An annealing step may be performed. Interface oxide growth 318 may be formed between the high-K deposit 316 and the vertical channel.

In Figure 3P, a metal gate electrode stack may be formed/deposited on the substrate. This can be one or more layers to adjust the drive current of the transistor device. This can be conformal deposition. The metal gate stack may be a titanium nitride (TiN) and tantalum nitride (TaN) gate metal layer 328 followed by a titanium aluminide (TiAl) gate metal layer 330 .

In Figure 3Q, a directional etch is performed to remove the gate stack material from the substrate, leaving the gate stack material (316, 318, 328, 330) around the vertical channels, thus forming a GAA device.

Figure 3R shows that the PMOS region can be masked with photoresist 310 and TiAL (or other gate stack material) removed to customize the gate stack. For example, this allows NMOS and PMOS to have threshold voltages Vt of similar absolute values.

FIG. 3S shows a cross-section of the substrate with different gate stacks after removal of the metal gate material 328 . The completed NMOS stack gate electrode region is shown as 334 .

In FIG. 3T, a photoresist mask 310 may be formed on the substrate to etch separations 331 in the doped silicon layer to isolate the lower source/drain regions.

FIG. 3U shows a device with the photoresist mask 310 of FIG. 3T removed. Dielectric material 326 is deposited and chemical/mechanical polishing/cross-sectional polishing is performed. NMOS gate stack 340 and PMOS gate stack 342 are shown.

Figure 3V shows a perspective view of a side-by-side NMOS (left) and PMOS (right) stack with metal connections. The NMOS stack has gate electrode 336N connected to the gate electrode region of the NMOS stack and electrodes 332N and 334N for source/drain connections. The PMOS stack has gate electrode 336P connected to gate stack material 330 and electrodes 332P and 334P for source/drain connections.

The dielectric layers may be dielectric oxides or may be low-K dielectrics with K values less than _SiO2 (K=3.9), since metal routing will be performed in these layers. Some non-limiting examples of low-K dielectrics are shown in Table 1:

oxide derivatives F-doped oxide (CVD) K = 3.3 – 3.9 C-Doped Oxides (SOG, CVD) K = 2.8 – 3.5 H-Doped Oxide (SOG) K = 2.5 – 3.3 organic matter Polyimide (spin coating) K = 3.0 – 4.0 Aromatic polymers (spin coating) K = 2.6 – 3.2 Vapor-deposited Parylene; Parylene-F K ~ 2.7; K ~ 2.3 F-doped amorphous carbon K = 2.3 – 2.8 Teflon/PTFE (spin coating) K = 1.9 – 2.1 Highly porous oxide Xerogel/Aerogel K=1.8 – 2.5 Table 1. Dielectric Constant (K) of Low-K Dielectric Materials

Processing may then continue, such as by forming local interconnects or other connections (not shown).

Additional vertical channel GAA devices (not shown) can be formed on the layers of the device to repeat the fabrication process. In addition, the source, drain and gate regions can be connected with conductive connections, such as local interconnects and interconnects to metal layers. In one example, buried power rails (power rails below the channel) can be incorporated, where metal hookups can be obtained from the top surfaces of PMOS and NMOS transistors, or by using local interconnects.

Embodiments of the present invention may also be set forth in parentheses below.

(1) A method of microfabrication, comprising: forming a dielectric layer stack on a first layer of semiconductor material, the dielectric layer stack having at least three layers, wherein the first dielectric material is located below and above the second dielectric material, the first dielectric material is different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material; an opening is formed in the dielectric layer stack so that the first layer of semiconductor material is exposed; in exposing the epitaxially grown channel material within the opening to form the vertical channel; removing a portion of the dielectric layer stack so that the sidewall structure remains on the vertical channel; removing the second dielectric material from the sidewall structure to expose the sidewall surfaces of the vertical channel; and A gate structure is formed on the exposed sidewall surfaces of the vertical channel.

(2) The method according to (1), wherein the first layer of semiconductor material is N-doped silicon or N-doped germanium.

(3) The method according to (1), wherein the first layer of semiconductor material is P-doped silicon or P-doped germanium.

(4) The method of (1), wherein the first layer of semiconductor material includes a P-doped region adjacent to the N-doped region, wherein the N-doped vertical channel is grown in the first exposed opening above the N-doped region, and wherein the P-doped vertical channel is grown in the second exposed opening above the P-doped region.

(5) The method according to (4), further comprising: depositing a third dielectric material on the first layer of the first and second exposed openings; shielding the P doping of the first layer with a first photoresist mask region; removing the third dielectric material from the N-doped region of the first layer; epitaxially growing N+ doped material over the N-doped region; removing the first photoresist mask; stacking, N+ doping on the dielectric layer depositing a protective film over the material and the third dielectric material; removing the protective film from the third dielectric material; and epitaxially growing a P+ doped material in the second exposed opening over the third dielectric material.

(6) The method of any one of (1) to (5), further comprising forming a local interconnect to the gate structure of each vertical channel configured to conduct perpendicular to the first layer of semiconductor material current on the working surface.

(7) The method of any one of (1) to (6), further comprising removing a portion of the first layer of semiconductor material between the vertical channels.

(8) The method of any one of (1) to (7), wherein the opening formed in the dielectric layer stack has a circular or rectangular cross-section.

(9) The method of any one of (1) to (8), wherein the first layer of semiconductor material is formed on the underlying dielectric layer.

(10) The method of any one of (1) to (9), wherein removing a portion of the dielectric layer stack comprises: shielding the vertical channels and tops of sidewall regions around each vertical channel; The stack is etched down to the first layer of semiconductor material.

(11) The method of any one of (1) to (10), further comprising: forming a first layer of semiconductor material on the underlying dielectric layer; blocking the dielectric layer stack; and before forming the opening in the stack, The first layer of semiconductor material is exposed by etching a portion of the stack down to the underlying dielectric layer to separate the stack.

(12) The method of any one of (1) to (11), further comprising forming a gate structure by: depositing a selective high-K material in exposed sidewall surfaces of the vertical channel, annealing; Forming an interface oxide between the high-K material and the vertical channel; depositing a metal gate stack over the vertical channel, sidewall surfaces, and selective high-K material; and removing the metal gate stack from the vertical channel and sidewall surfaces.

(13) The method of any one of (1) to (12), wherein depositing the metal gate electrode stack comprises: depositing a first metal material on the selective high-K material; depositing a second metal material on the first metal material a metallic material; and depositing a third metallic material on the second metallic material.

(14) The method of (13), wherein the first, second and third metal materials are different metals.

(15) The method of any one of (13) to (14), wherein the first metal material is titanium nitride, the second metal material is tantalum nitride, and the third metal material is titanium aluminide.

(16) The method of any one of (13) to (15), wherein depositing the metal gate electrode stack comprises: depositing a first layer of the first metal material on the high-K material; depositing on the first layer of the metal material a second layer of the second metal material; depositing a third layer of the first metal material on the second layer of the second metal material; depositing a fourth layer of the second metal material on the third layer of the first metal material; and depositing a fourth layer of the second metal material on the fourth layer of the first metal material A third metal material is deposited on the second metal material.

(17) A semiconductor device, comprising: a substrate layer; a layer of a first dielectric material; a layer of semiconductor material; a dielectric layer stack having at least three layers, wherein the first dielectric material is located below and above the second dielectric material, and the first dielectric material is located below and above the second dielectric material. a dielectric material different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material; a first opening in the dielectric layer stack where the layer of semiconductor material is exposed; vertical channels , which has an epitaxially grown dopant material in the first opening; a sidewall structure, which is formed by a second opening in the stack of dielectric layers between the vertical channels; and a third opening in the sidewall structure, which is removed by A second dielectric material is formed up to the vertical channels; gate structures in the third openings; local interconnects connected to the gate structures of each vertical channel configured to conduct current perpendicular to the working surface of the substrate layer .

(18) The semiconductor device according to (17), wherein the first layer of semiconductor material is N-doped silicon or N-doped germanium.

(19) The semiconductor device according to (17), wherein the first layer of semiconductor material is P-doped silicon or P-doped germanium.

(20) The semiconductor device of (17), wherein the first layer of semiconductor material includes a P-doped region adjacent to the N-doped region, wherein the N-doped vertical channel is disposed in the first exposed opening above the N-doped region , and wherein the P-doped vertical channel is disposed in the second exposed opening above the P-doped region.

The technology of this paper is used to achieve precise alignment with the gate electrode. Vertical 3D epitaxial growth of vertical transistors realizes current flow in the vertical dimension, thereby realizing the expansion of 3D device structure design. The vertical 3D structure provides easy-to-make contacts (360-degree contacts and routing to channels, sources, and drains), thereby increasing circuit density. The embodiments and transistors herein may be vertical stacks of 3D devices. Embodiments enable source and drain to be interchanged, as each channel can be isolated from the other channels.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and not for limitation. For example, forming a first feature over or over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments that may be formed between the first and second features. Embodiments in which additional features are formed therebetween so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and/or configurations discussed. Further, for ease of description, spatially relative terms such as "top," "bottom," "below," "below," "lower," "above," "upper," and the like may be used herein to describe The relationship of an element or feature as shown to another element or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation, except where depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are likewise construed accordingly.

The order of discussion of the various steps as described herein has been presented for clarity. In general, such steps may be performed in any suitable order. Additionally, although each of the various features, techniques, configurations, etc. herein may be discussed in various places in the present disclosure, it is intended that each concept can be implemented independently of each other or in combination with each other. Accordingly, the present invention may be embodied and outlined in many different ways.

The techniques herein can enable 3D stacking of NMOS devices on PMOS devices and vice versa. Provides 360-degree turn-on of transistors for optimal routing of gate and source/drain (S/D) regions. Techniques may include self-aligned 3D 360-degree silicide regions. An example of an inverter application of two different transistors will be described. The techniques herein can reduce wiring because the entire vertical gate full loop (GAA) inverter can be formed in one vertical stack. The methods herein can be used for any channel material where two CMOS 3D transistors or devices have N+ regions connected to P+ regions through a common silicide region. Since the 3D channels and 3D S/D regions are grown vertically, the embodiments herein can achieve significant device scaling.

Exemplary embodiments will now be described with reference to the drawings. A process flow may describe a method for fabricating vertical 3D GAA in situ epitaxial nanodevices with two transistors. This exemplary flow may use a stack of a first dielectric material layer, a second dielectric material layer, and a third dielectric material layer that are selective with respect to each other. That is, there are one or more etchants and/or etching conditions such that a given one of the dielectrics can be etched while the other two dielectrics are not etched (or substantially etched). Exemplary dielectric material schemes may include oxide-based SiOx, SiOxNy-based, high-k-based, and high-k OxNy. For high-k materials, changing the elements used with high-k to oxides can also yield selectivity within different types of high-k. Wet etching or dry etching can be used. To further increase the selection options, full wet, full dry or a combination of wet and dry also offers more options for the three material selection schemes. A future dielectric region (a third layer of dielectric material) can be present, and the silicide connection for the channel region of the CMOS inverter will be between two future transistor regions (eg, PMOS and NMOS). The second dielectric material layer will be the future gate electrode region for the two GAA vertical growth devices. Embodiments herein may use N+ (N-doped) epitaxial growth material for the source, drain and channel of NMOS, followed by P+ (P-doped) epitaxial growth material for the source of PMOS pole, drain, and channel, as examples. However, any compatible material may also be selected for the channel or S/D region, as the embodiments herein may provide apparatus and methods for fabricating 3D vertically stacked CMOS devices.

4-12A and 13-20 show cross-sectional views illustrating exemplary methods for fabricating 3D semiconductor devices in accordance with some embodiments of the present invention. FIG. 12B shows a schematic diagram of the 3D semiconductor device of FIG. 12A. In one embodiment, the 3D semiconductor apparatus may include a first semiconductor device and a second semiconductor device. In one embodiment, the method may include forming a multi-layer stack on a substrate, the multi-layer stack comprising a plurality of layers of at least three different dielectric materials capable of being selectively etched relative to each other, forming down through the multi-layer stack to the substrate at least one opening in which the substrate is exposed in which a first channel of a first semiconductor device of the semiconductor device is formed vertically from the exposed substrate and a second channel of a second semiconductor device of the semiconductor device is formed vertically from the first channel channel, removing the transition dielectric layer in the layers of the multi-layer stack, exposing a portion of the first channel and the second channel at the interface of the transition dielectric layer, and forming a silicide at the exposed portion to couple the first channel connected to the second channel.

As shown in FIG. 4 , a substrate 130 may be provided, a dielectric layer 160 may be formed (eg, deposited) on the substrate 130 , and an implant layer 170 may be formed (eg, deposited) on the dielectric layer 160 . In one embodiment, the implant layer 170 may be doped with a first type (eg, N-type) dopant. In another embodiment, the implant layer 170 may be doped with a second type (eg, P-type) dopant.

As also shown in FIG. 4 , the first dielectric layer stack 110 may be formed on the substrate 130 . In one embodiment, the first dielectric layer stack 110 may include a lower source/drain (S/D) dielectric layer 111 , a gate formed (eg, deposited) on the lower S/D dielectric layer 111 A dielectric layer 112 , and an upper S/D dielectric layer 113 formed (eg, deposited) on the gate dielectric layer 112 . In one embodiment, the dielectric layers 111-113 may be nanosheets. For example, the dielectric layers 111-113 may include oxide-based SiOx, SiOxNy-based, high-k, and high-k OxNy-based dielectric materials. In one embodiment, the lower S/D dielectric layer 111 and the upper S/D dielectric layer 113 may include the same dielectric material, eg, the first dielectric material. In another embodiment, the gate dielectric layer 112 may include a second dielectric material capable of being selectively etched relative to the first dielectric material.

As also shown in FIG. 4 , a transition dielectric layer 140 may be formed (eg, deposited) on the first dielectric layer stack 110 . In one embodiment, the transition dielectric layer 140 can include a third dielectric material and can be opposite to the lower S/D dielectric layer 111 and the upper S/D dielectric layer 113 including the first dielectric material and the second S/D dielectric layer 113 . The gate dielectric layer 112 of dielectric material is selectively etched.

As also shown in FIG. 4 , the second dielectric layer stack 120 may be formed on the transition dielectric layer 140 . In one embodiment, the second dielectric layer stack 120 may include a lower S/D dielectric layer 121 , a gate dielectric layer 122 formed (eg, deposited) on the lower S/D dielectric layer 121 , and forming The upper S/D dielectric layer 123 is (eg, deposited) on the gate dielectric layer 122 . In one embodiment, the dielectric layers 121-123 may be nanosheets. For example, the dielectric layers 121-123 may include oxide-based SiOx, SiOxNy-based, high-k, and high-k OxNy-based dielectric materials. In one embodiment, the lower S/D dielectric layer 121 and the upper S/D dielectric layer 123 may include the same dielectric material, eg, a first dielectric material. In another embodiment, the gate dielectric layer 122 can be selectively etched relative to the lower S/D dielectric layer 121 and the upper S/D dielectric layer 123 . For example, the gate dielectric layer 122 may include a second dielectric material. In one embodiment, the first dielectric layer stack 110, the transition dielectric layer 140, and the second dielectric layer stack 120 may be included in a multi-layer stack. As also shown in FIG. 4 , a hard mask 150 may be formed on the second dielectric layer stack 120 .

As shown in FIG. 5, a mask 210 may be patterned and formed on the hard mask 150, and the second dielectric layer stack 120, the transition dielectric layer 140, and the first dielectric layer stack 110 may be etched down to the implantation into the layer 170 to form at least one opening. For example, the mask 210 may be a photoresist mask patterned through yellow lithography. In an embodiment, the opening may have a rectangular cross-section. In another embodiment, the opening may have a circular cross-section. In yet another embodiment, two openings 220 and 230 may be formed. For example, the two openings 220 and 230 may have the same size. As another example, the two openings 220 and 230 may have different sizes.

As shown in FIG. 6, the photoresist mask 210 can be removed to reveal the second dielectric layer stack 120, the transition dielectric layer 140, and the first dielectric layer stack 110 with openings 220 and 230 formed therethrough.

As shown in FIG. 7, openings 220 and 230 may be filled with channel material. In one embodiment, the implant layer 170 may be doped with a first type dopant, a first channel material of the first type may be epitaxially grown from the implant layer 170 to a specific height to form the first channel 410, and then A second channel material of the second type can be epitaxially grown to the top of the second dielectric layer stack 120 from a specific height. For example, the first type may be an N-type, and the second type may be a P-type. As another example, the first type may be P-type and the second type may be N-type. In one embodiment, at least one of the first and second channel materials may be silicon, germanium, or other semiconductor materials. In another embodiment, the specific height may be from the implant layer 170 to the transition dielectric layer 140 where the first channel 410 and the second channel 420 interface.

As shown in FIG. 8, another mask 530 (eg, a photoresist mask) may be patterned and formed on the second dielectric layer stack 120, and the second dielectric layer stack 120, the transition dielectric layer 140 and the The first dielectric layer stack 110 is etched down to the implant layer 170 to expose a portion of the implant layer 170 to form a future first semiconductor device 510 and a future second semiconductor device 510 vertically stacked in situ on the first semiconductor device 510 Semiconductor device 520 . For example, the first semiconductor device 510 may be an NMOS, the second semiconductor device 520 may be a PMOS, and the NMOS 510 and the PMOS 520 may be coupled to each other to form a CMOS inverter. As another example, the first semiconductor device 510 may be a PMOS, the second semiconductor device 520 may be an NMOS, and the PMOS 510 and the NMOS 520 may be coupled to each other to form another CMOS inverter. In one embodiment, the second dielectric layer stack 120, the transition dielectric layer 140, and the first dielectric layer stack 110 may be etched by a distance d extending beyond the epitaxial region, such that the first dielectric layer stack 110 and the first Two dielectric layer stacks 120 can form sidewall structures around each epitaxial growth material.

As shown in FIG. 9, the other photoresist mask 530 can be removed to expose the top of the second dielectric layer stack 120, and the gate dielectric layer 112 and the second dielectric layer of the first dielectric layer stack 110 can be removed The gate dielectric layer 122 of the layer stack 120 exposes the sides of the first channel 410 and the second channel 420, respectively. For example, gate dielectric layers 112 and 122 may be removed by isotropic etching, such as vapor phase etching. Since the gate dielectric layer 112 of the first dielectric layer stack 110 and the gate dielectric layer 122 of the second dielectric layer stack 120 (which may include the second dielectric material) may be relative to the first dielectric layer stack 110 S/D dielectric layers 111 and 113 and S/D dielectric layers 121 and 123 of the second dielectric layer stack 120 (which may include a first dielectric material) and transition dielectric layer 140 (which may include a third dielectric material) dielectric material) is selectively etched so that when the gate dielectric layer 112 of the first dielectric layer stack 110 and the gate dielectric layer 122 of the second dielectric layer stack 120 are etched, the first dielectric layer stack The S/D dielectric layers 111 and 113 of 110, the S/D dielectric layers 121 and 123 of the second dielectric layer stack 120, and the transition dielectric layer 140 will not be etched or substantially etched. As also shown in FIG. 9 , high-k dielectric material 610 may be deposited on the exposed tops of the second dielectric layer stack 120 and the exposed portions of the implant layer 170 , and on the exposed portions of the first channel 410 and the second channel 420 on the sides to form gate dielectric materials 612 and 622, respectively.

As shown in FIG. 10, the metal gate electrodes of the first and second semiconductor devices 510 and 520 may be formed. In one embodiment, the metal gate electrode of the first semiconductor device 510 may include an outer metal material 715 (which is blanket deposited over the gate dielectric material 612 , the lower S/D dielectric layer 111 and the upper S/D dielectric layer) 113) and an inner metallic material 714 surrounded by an outer metallic material 715. For example, the outer metal material 715 and the inner metal material 714 of the first semiconductor device 510 may include two different metal materials, eg, first and second metal materials. In another embodiment, the metal gate electrode of the first semiconductor device 520 may include an outer metal material 725 (which is blanket deposited over the gate dielectric material 622 , the lower S/D dielectric layer 121 and the upper S/D dielectric layer 123) and an inner metallic material 724 surrounded by an outer metallic material 725. For example, the outer metal material 725 and the inner metal material 724 of the second semiconductor device 520 may include two different metal materials, such as a first metal material and a second metal material. In one embodiment, each of the outer metallic material and the inner metallic material may include one or more metallic materials depending on the desired work function required for a particular circuit or transistor.

As shown in FIG. 11 , the transition dielectric layer 140 may be removed to reveal a portion of the first channel 410 and the second channel 420 that interface at the transition dielectric layer 140, and the high-k dielectric material 610 may also be removed to reveal the second channel Dielectric layer stack 120 and top of implant layer 170 . As also shown in FIG. 11 , a silicide metal may then be deposited on the exposed portions of the first channel 410 and the second channel 420 and the exposed tops of the second dielectric layer stack 120 and the implant layer 170 . In one embodiment, the silicide metal may be ruthenium (Ru), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), platinum (Pt), or nickel (Ni). The silicide metal can then react with the exposed portions of the first channel 410 and the second channel 410 and the exposed tops of the second dielectric stack 120 and the implant layer 170 and annealed to form the surface between the first channel 410 and the second channel 420 A silicide 810 is formed on the exposed portion (ie, surrounding the exposed portion of the first channel 410 and the second channel 420 to form a gate full ring (GAA) structure) and between the second dielectric layer stack 120 and the implant layer 170 A silicide 820 is formed on the exposed top. In one embodiment, unreacted silicide metal may be removed using wet chemistry in the non-silicon regions. In one embodiment, the silicide 810 may couple the first semiconductor device 510 to the second semiconductor device 520 .

As shown in FIG. 12A, a transition dielectric material 910 may be deposited over the silicide 810 to protect/isolate the silicide 810, the first channel 410 and the second channel 420 from the gate electrodes for future electrical connections. In one embodiment, the transition dielectric material 910 may be selectively etched relative to the first and second dielectric materials. For example, transition dielectric material 910 may include a third dielectric material. As another example, the transition dielectric material 910 may include a different dielectric material than the first to third dielectric materials. FIG. 12B shows a schematic diagram of the 3D semiconductor device of FIG. 12A. In one embodiment, the silicide 820 and the 3D semiconductor device may have a circular cross-section, as shown in Figure 12B. In another embodiment, at least one of the silicide 820 and the 3D semiconductor device may have a rectangular cross-section.

As shown in FIG. 13 , a dielectric material 1010 may be deposited to cover the sidewall structures of the first and second semiconductor devices 510 and 520 and the implant layer 170 . In one embodiment, the dielectric material 1010 may be selectively etched with respect to the S/D dielectric layers 121 and 123 including the first dielectric material and the transition dielectric layer 910 including the third dielectric material. For example, dielectric material 1010 may include the same dielectric material as gate dielectric layers 112 and 122, which include the second dielectric material. In one embodiment, the capping layer may be planarized using chemical mechanical polishing (CMP). As also shown in FIG. 13, the dielectric material 1010 may then be etched to a depth sufficient to reveal the second semiconductor device 420, leaving the first semiconductor device 410 and the implant layer 170 covered. As also shown in FIG. 13 , the inner metal material 724 of the second semiconductor device 520 may be removed.

As shown in FIG. 14, the dielectric material 1010 may be further etched to reveal the first semiconductor device 510, leaving the implant layer 170 still covered. As also shown in FIG. 14 , a third metal material 1110 may be deposited and planarized to form an inner metal material 1124 . For example, the third metal material 1010 may include a different metal material than the inner metal material 714 of the first semiconductor device 510 . In such cases, inner metallic material 1124 and inner metallic material 714 may comprise different metallic materials. In another embodiment, the removal of the inner metal material 724 of the second semiconductor device 520 may be omitted, and the third metal material 724 (which may then be referred to as the inner metal material 1124 of the second semiconductor device 520 ) may be completely deposited under the inner metal material 724 . metal material 1110 and planarize it. In these cases, the inner metal material 1124 of the second semiconductor device 520 and the inner metal material 714 of the first semiconductor device 510 may have the same metal material. In one embodiment, a substrate (not shown) may optionally be coated prior to depositing the third metal material 1110 .

As shown in FIG. 15, an etch mask (eg, a photoresist mask) 1210 can be patterned and formed, and a third metal material 1110 can be etched to define metal lines that couple the first semiconductor device 510 and the second semiconductor device. In one embodiment, Vin may be formed to couple the first gate region of the first semiconductor device 510 (eg, including the inner metal material 714 and the outer metal material 715 ) and the second gate region of the second semiconductor device 520 (eg, including inner metal material 1124 and outer metal material 725).

As shown in FIG. 16 , the photoresist mask 1210 can be stripped, and then oxide 1310 can be deposited to fill the space formed after etching the third metal material 1110 in FIG. 15 . In one embodiment, oxide 1310 may be deposited to be flush with the top of silicide 820 formed on second semiconductor device 520 . In another embodiment, oxide 1310 may include the same dielectric material as transition dielectric layer 910, eg, a third dielectric material. As also shown in FIG. 16 , the oxide 1310 may be ground, and then a hard mask 1320 may be deposited over the oxide 1310 and the silicide 820 formed on the second semiconductor device 520 .

As shown in FIG. 17 , an etch mask (eg, a photoresist mask) 1410 can be patterned and formed, and can be sequentially etched to and transition from the hard mask 1320 and oxide 1310 not covered by the etch mask 1410 The tops of dielectric layer 910 and silicide 810 are approximately flush with depths to form openings 1420 .

As shown in FIG. 18, the photoresist mask 1410 may be removed, a spacer film 1510 may be deposited on the sides of the opening 1420, and the oxide 1310 sandwiched between the first semiconductor device 510 and the second semiconductor device 520 may be etched to expose the silicide 810 .

As shown in FIG. 19, a fourth metal material 1610 may be deposited in the opening 1420 to form the Vout of a CMOS inverter (ie, the first semiconductor device 510, which may be PMOS, and the semiconductor device 520, which may be NMOS, and vice versa) . For example, the fourth metal material 1610 and the third metal material 1110 may include the same metal material. As another example, the fourth metal material 1610 and the third metal material 1110 may include different metal materials. As also shown in FIG. 19, the hard mask 1320 may be removed.

As shown in Figure 20, Vdd and GND of the CMOS inverter can be formed. In one embodiment, a dielectric material 1710 may be deposited over the second semiconductor device 520, a mask (not shown) may be formed over the dielectric material 1710, and a mask (not shown) may be formed in the dielectric material 1710 for forming Vdd and GND Then, metal material can be deposited to fill the openings to form Vdd and GND, and chemical mechanical polishing (CMP) can be used to remove the capping layer. In one embodiment, GND may be formed next to Vin. In another embodiment, GND may have 360 degree rotational symmetry.

In summary, a 3D semiconductor device (eg, a 3D CMOS inverter) fabricated by the exemplary methods shown in FIGS. 4-20 may include: a first semiconductor device 510 including a first S/D region (eg, a first S /D layers 111 and 113), the first gate region (eg, including the inner metal material 714 and the outer metal material 715) sandwiched between the first S/D regions 111 and 113, and the first S/D The regions 111 and 113 and the first channel 410 surrounded by the first gate region; the second semiconductor device 520 stacked on the first semiconductor device 510 including the second S/D region (eg, the second S/D layer 121 and 123), the second gate region sandwiched between the second S/D regions 121 and 123 (for example, including the inner metal material 1124 and the outer metal material 725), and the second S/D regions 121 and 123 and A second channel 420 surrounding the second gate region and formed vertically on the first channel 410 in situ; and a silicide 820 formed between the first semiconductor device 510 and the second semiconductor device 520 , wherein the first channel 410 and The second channel 420 borders and is coupled to the upper of the first S/D regions 111 and 113 of the first semiconductor device 510 and the upper of the second S/D regions 121 and 123 of the second semiconductor device 520 next. In one embodiment, the first semiconductor device 510 and the second semiconductor device 520 may be of different types. In another embodiment, the first gate region may include a first metallic material (eg, outer metallic material 715 ) and a second metallic material (eg, inner metallic material 714 ) surrounded by the first metallic material, the second metallic material The gate region may include a first metallic material (eg, outer metallic material 725) and a third metallic material (eg, inner metallic material 1124) surrounded by the first metallic material. For example, the second and third metallic materials may comprise the same metallic material. As another example, the second and third metallic materials may comprise different metallic materials.

21 illustrates a top view of a 3D semiconductor device 1800 (eg, a 3D CMOS inverter) fabricated by the methods shown in FIGS. 4-20 in accordance with some embodiments of the present invention. The CMOS inverter 1800 may have openings 220/230 with circular cross-sections, Vdd at the center of the openings 220/230, and Vin, GND, and Vout and other contacts with 360 degree rotational symmetry. For example, Vin can be next to GND. The CMOS inverter 1800 shown in FIG. 21 may have 14 contacts. In one embodiment, the CMOS inverter 1800 may have a different number of contacts, eg, depending on the contact size. Accordingly, many options are available for the placement and routing of metal connections.

22 illustrates a top view of a 3D semiconductor device 1900 (eg, a 3D CMOS inverter) fabricated by the methods shown in FIGS. 4-20 in accordance with some embodiments of the present invention. The CMOS inverter 1900 may be different from the CMOS 1800 at least in that Vin and GND of the CMOS inverter 1900 are separated from each other.

23 illustrates a top view of a 3D semiconductor device 2000 (eg, a 3D CMOS inverter) fabricated by the methods shown in FIGS. 4-20 in accordance with some embodiments of the present invention. CMOS inverter 2000 may differ from CMOS inverters 1800 and 1900 at least in that Vdd of CMOS inverter 2000 surrounds openings 220/230.

24 illustrates a top view of a 3D semiconductor device 2100 (eg, a 3D CMOS inverter) fabricated by the methods shown in FIGS. 4-20 in accordance with some embodiments of the present invention. CMOS inverter 2100 may differ from CMOS inverters 1800, 1900, and 2000 at least in that CMOS inverter 2100 has openings 220/230 with rectangular cross-sections.

25 shows a flow diagram of an exemplary method 2200 of fabricating a 3D semiconductor device according to some embodiments of the present invention. For example, a 3D semiconductor apparatus may include a first semiconductor device and a second semiconductor device. In one embodiment, some of the steps of the illustrated method 2200 may be performed concurrently or in a different order than shown, may be replaced by other method steps, or may be omitted. Additional method steps may also be performed as desired. In another embodiment, method 2200 may correspond to the methods shown in FIGS. 4-20.

At step 2205, an implant layer and a first dielectric layer stack may be sequentially formed on the substrate. In one embodiment, the implant layer may be the implant layer 170 , the first dielectric layer stack may be the first dielectric layer stack 110 , and the substrate may be the substrate 130 , as shown in FIG. 4 .

At step 2210, a transition dielectric layer may be formed on the first dielectric layer stack. In one embodiment, the transition dielectric layer may be the transition dielectric layer 140 , as shown in FIG. 4 .

At step 2215, a second dielectric layer stack may be formed over the transition dielectric layer. In one embodiment, the second dielectric layer stack may be the second dielectric layer stack 120 , as shown in FIG. 4 .

At step 2220 , at least one opening may be formed down through the second dielectric layer stack, the transition dielectric layer, and the first dielectric layer stack to the substrate 130 . In one embodiment, the at least one opening may include openings 220 and 230, as shown in FIG. 5 .

At step 2225, the openings may be filled with channel material. In one embodiment, the channel material may include a first channel material and a second channel material. For example, the implant layer 170 may be doped with the first type dopant, and the first channel material may be epitaxially grown from the implant layer 170 to the transition dielectric layer 140 and doped with the first type dopant to form the first channel material. A channel 410 is shown in FIG. 7 . As another example, a second channel material may be epitaxially grown from the transition dielectric layer 140 to the top of the second dielectric layer stack 120, and a second type of dopant may be doped into the second channel material to form a second channel material. The second channel 420 is shown in FIG. 7 .

At step 2230 , the second dielectric layer stack 120 , the transition dielectric layer 140 , and the first dielectric layer stack 110 may be etched, as shown in FIG. 8 .

At step 2235, the gate dielectric layer of the first and second dielectric layer stacks may be removed. In one embodiment, the gate dielectric layer 112 of the first dielectric layer stack 110 and the gate dielectric layer 122 of the second dielectric layer stack 120 may be removed to expose the first channel 410 and the second channel 420, respectively side, as shown in Figure 9.

At step 2240, a high-k dielectric material can be deposited. In one embodiment, the high-k dielectric material may be high-k dielectric material 610 , also shown in FIG. 9 .

At step 2245, metal gate electrodes of the first and second semiconductor devices may be formed. In one embodiment, the metal gate electrode of the first semiconductor device 510 may include an outer metal material 715 blanket deposited on the dielectric material 612 , the lower S/D dielectric layer 111 and the upper S/D dielectric layer 113 , and an inner metallic material 714 surrounded by an outer metallic material 715 as shown in FIG. 10 . In another embodiment, the metal gate electrode of the second semiconductor device 520 may comprise an outer metal material 725 blanket deposited on the dielectric material 622 , the lower S/D dielectric layer 121 and the upper S/D dielectric layer 123 , and an inner metallic material 724 surrounded by an outer metallic material 725 , also shown in FIG. 10 .

At step 2250, a silicide coupling the first semiconductor device to the second semiconductor device may be formed. In one embodiment, the silicide may be the silicide 820 that couples the first semiconductor device 510 to the second semiconductor device 520, as shown in FIG. 11 .

In step 2255, a transition dielectric material may be deposited over the silicide. In one embodiment, the transition dielectric material may be transition dielectric material 910, which may be deposited on the silicide 820 and protect/use the silicide 810, the first channel 410 and the second channel 420 with The gate electrode of the electrical connection line is isolated, as shown in Figure 12.

At step 2260, a dielectric material may be deposited to cover the sidewall structures of the first and second semiconductor devices. In one embodiment, the dielectric material may be a dielectric material 1010 covering the sidewall structures of the first and second semiconductor devices 510 and 520 and the implant layer 170, as shown in FIG. 13 .

At step 2265, a portion of the dielectric material may be removed. In one embodiment, the dielectric material 1010 may be etched to a depth sufficient to reveal the second semiconductor device 420 while keeping the first semiconductor device 410 and the implant layer 170 covered, as also shown in FIG. 13 .

In step 2270, the inner metal material of the second semiconductor device not covered by the dielectric material may be removed. In one embodiment, the inner metal material may be inner metal material 724, which is not covered by the etched dielectric material 1010 and can be removed, as also shown in FIG. 13 .

At step 2275, a third metallic material may be deposited to form an inner metallic material. In one embodiment, the third metal material may be a third metal material 1110, which may be deposited and planarized to form an inner metal material 1124, as shown in FIG. 14 .

At step 2280, a third metal material may be etched to form metal lines that couple the first semiconductor device to the second semiconductor device. In one embodiment, the third metal material 1110 may be etched to form the first gate region (eg, including the inner metal material 714 and the outer metal material 715 ) of the first semiconductor device 510 that couples to the second semiconductor device 520 . Vin of the second gate region (eg, including inner metal material 1124 and outer metal material 725 ), as shown in FIG. 15 .

At step 2285, the Vout of the 3D semiconductor device (eg, a 3D CMOS inverter) may be formed. In one embodiment, oxide 1310 may be deposited to fill the space formed after etching the third metal material 1110, as shown in FIG. 16; then oxide 1310 and silicide 820 may be formed on the second semiconductor device 520 A hard mask 1320 is deposited on top, also as shown in FIG. 16 ; a photoresist mask 141 can be patterned and formed and can be etched to and the transition dielectric by etching the hard mask 1320 and oxide 1310 not covered by the etch mask 1410 The tops of layer 910 and silicide 810 are approximately flush to a depth to form openings 1420, as shown in FIG. 17; photoresist mask 1410 may be removed, spacer films 1510 may be deposited on the sides of openings 1420, and the sandwich may be etched The oxide 1310 between the first semiconductor device 510 and the second semiconductor device 520 to expose the silicide 810, as shown in FIG. 18; and a fourth metal material 1610 can be deposited in the opening 1420 to form the Vout of the CMOS inverter , as shown in Figure 19.

At step 2290, GND and Vdd may be formed. In one embodiment, a dielectric material 1710 may be deposited over the second semiconductor device 520, openings may be formed in the dielectric material 1710 to form Vdd and GND, and then a metal material may be deposited to fill the openings to form Vdd and GND , and the capping layer can be removed by chemical mechanical polishing (CMP), as shown in FIG. 20 .

As described in the prior art, 3D integration (ie, vertical stacking of multiple devices) aims to overcome the scaling limitations encountered in planar devices by increasing the density of transistors in volume rather than area. While the flash memory industry has successfully demonstrated and implemented device stacking with the adoption of 3D NAND, application to random logic designs is substantially more difficult. 3D integration of logic chips (CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array, SoC (System On Chip)) is being pursued.

The techniques herein include methods of microfabrication of 3D devices that extend the design of 3D device structures to enhance performance and enable higher density circuits to be produced at lower cost. Technologies include vertically oriented and epitaxially grown channels and other metal routing methods and designs for vertical transistors.

Methods and designs for these vertical transistors are described in USSN 63/019,015, filed May 1, 2020, and entitled "METHOD OF FORMING 3D DEVICES WITH VERTICAL CHANNELS," the entire contents of which are incorporated herein by reference. Vertical 3D epitaxial growth of vertical transistors allows current flow in the vertical dimension or perpendicular to the wafer surface. The methods and designs herein include fabricating CMOS devices with vertical current flow. The vertical 3D devices herein enable another degree of freedom in the z-direction that will enhance the routing options of existing 3D devices. Since the channel length is defined by the deposited or epitaxially grown layers, relatively short transistor lengths are achieved. Precise alignment with the gate electrode is achieved by selectively removing the intermediate dielectric layer. The techniques herein obviate the need for oxide isolation for 3D nanostacks. A 360 degree contact connection and routing will be presented for the gate connection and the source and drain connections. Since the design here has 360 degree symmetry for the vertical device structure, the source, drain and gate electrodes can be placed along either side of the vertical structure for optimal routing efficiency.

Since the gate and source regions herein have a 360 degree turn-on, a given contact can be placed on either side of the source or either side of the gate. Relatively short transistor channel lengths can be achieved by depositing layers compared to the channel lengths defined by yellow lithography. Features include providing multiple selectable contact positions for vertical channel devices. Advantages include more options to reduce routing congestion and more options for routing scaling for 3D routing and 3D contacts. Multiple channel lengths within a vertically unified stack are also achieved.

34 is a cross-sectional view of a semiconductor device 900 according to an exemplary embodiment of the present invention. Figure 34 can show a conventional 3D nanochip with current flow only in the X direction (parallel to the working surface of the substrate/wafer) in multiple horizontal planes (ie, without the 360 degree rotational symmetry of the vertical transistors herein). Semiconductor device 900 may include source and drain regions 803 over substrate 801 . The semiconductor device 900 may also include a gate structure 815 and a nanochip 805 over the substrate 801 . The transistors herein (with vertical channels where current flows in a vertical direction) have many turn-on points leading to source, drain and gate regions.

26A is a perspective view of a semiconductor device 100 according to an exemplary embodiment of the present invention. The semiconductor device 100 may include a substrate 101 and a pad layer 130 over the substrate 101 . In some embodiments, the substrate 101 and the pad layer 130 may be separated by the first dielectric layer 103 . The pad layer 130 may include at least one pad structure, such as the first pad structure 131 and the second pad structure 132 in this example. In some embodiments, one or more of the pad structures may be connected to corresponding adjacent pad structures. In other embodiments, one or more of the pad structures may be separated from corresponding adjacent pad structures. In this example, the first pad structure 131 and the second pad structure 132 are separated from each other through the second dielectric material 105 . The second dielectric material 105 may also be disposed on a portion of the first pad structure 131 and the second pad structure 132 . In some embodiments, the second dielectric material 105 may be disposed to completely cover the exposed portions of the first pad structure 131 and the second pad structure 132 . Further, semiconductor device 100 may include transistors (eg, 110 and 120) and vertical interconnect structures (eg, 150a, 150b, 160a, 160b, 170a, and 170b) disposed over pad structures (eg, 131 and 132) . Although shown as cylindrical in this example, the transistors (eg, 110 and 120) and vertical interconnect structures (eg, 150a, 150b, 160a, 160b, 170a, and 170b) can also have other shapes.

Figure 26B is a cross-sectional view taken along line AA' in Figure 26A, according to an exemplary embodiment of the present invention. As shown, the pad structure may have a core region surrounded by a peripheral region. In this example, the first pad structure 131 includes a first core region 131a surrounded by a first peripheral region 131b, and the second pad structure 132 includes a second core region 132a surrounded by a second peripheral region 132b. In some embodiments, specific core regions may be disposed on the edges of the corresponding pad structures.

Further, the semiconductor device 100 may include a transistor disposed over the core region of the pad structure. Therefore, the pad structure can extend horizontally beyond the perimeter of the corresponding transistor. As shown, the first transistor 110 and the second transistor 120 are disposed over the first core region 131a and the second core region 132a, respectively. In this example, the first transistor 110 and the second transistor 120 are NMOS and PMOS, respectively. Accordingly, the first pad structure 131 and the second pad structure 132 may include n-type silicon and p-type germanium, respectively. As shown, the first transistor 110 may include a first channel structure 111 (eg, n-type silicon) extending in the vertical direction (or in the Z direction) and a first gate around the sidewall portion of the first channel structure 111 Structure 115 (eg, TiN and TaN). The first high-k dielectric material 113 (eg, HfO 2 , ZrO 2 , TiO 2 , La 2 O 3 , and Y 2 O 3 ) may be sandwiched between the first channel structure 111 and the first gate structure 115 . The first transistor 110 may further include a first spacer material 117 isolating the first gate structure 115 .

Likewise, the second transistor 120 may include a second channel structure 121 (eg, p-type germanium), a second gate structure 125, a second high-k dielectric 123 (eg, HfO2, ZrO2, TiO2, La2O3, and Y2O3) ) and the second spacer material 127. The second gate structure 125 may have a first portion 125a (eg, TiN and TaN) and a second portion (eg, TiAl). The first spacer material 117 and the second spacer material 127 may comprise any electrical insulator, and in this example comprise the same material, such as silicon nitride. Likewise, the first high-k dielectric material 113 and the second high-k dielectric material 123 may be made of the same high-k dielectric material.

Further, although not shown, the channel structures (eg, 111 and 121 ) may include vertical channel regions and source and drain regions on opposite ends (eg, top and bottom) of the vertical channel regions. The vertical channel regions, source regions, and drain regions may comprise the same semiconductor material, but may have different dopants and/or different dopant concentrations. Since the positions of the source and drain regions are interchangeable, the source or drain regions will be labeled as S/D regions. Accordingly, the top S/D region and the bottom S/D region are disposed above and below the vertical channel region, respectively. During operation, current may flow in the Z direction, eg, from the top S/D region to the bottom S/D region via the vertical channel region.

Still referring to FIG. 26B, an insulating material 102 (eg, silicon oxide) disposed over the pad layer 130 may fill the space and cover the transistors (eg, 110 and 120). The semiconductor device 100 may include first vertical interconnect structures (eg, 150a and 150b) that extend through the insulating material 102 and contact the top surfaces of the channel structures (eg, 111 and 121). Accordingly, the first vertical interconnect structures 150a and 150b are configured to be coupled to the top S/D region of the first transistor 110 and the top S/D region of the second transistor 120, respectively. The semiconductor device 100 may also include second vertical interconnect structures (eg, 160a and 160b) that extend through the insulating material 102, contact peripheral regions (eg, 131b and 132b), and are configured to pass through the pad structures (eg, 131 and 132b) 132) is coupled to the bottom surface of the channel structures (eg, 111 and 121). Accordingly, the second vertical interconnect structures 160a and 160b are configured to be coupled to the bottom S/D region of the first transistor 110 and the bottom S/D region of the second transistor 120, respectively. The semiconductor device 100 may further include third vertical interconnect structures (eg, 170a and 170b) disposed away from the channel structures (eg, 111 and 121) and contacting the gate structures (eg, 115 and 125). Therefore, the third vertical interconnection structures 170a and 170b may function as the first gate electrode and the second gate electrode, respectively.

As shown in FIG. 26B, the first and second vertical interconnect structures may include metal portions (eg, 151a, 151b, 161a, and 161b) over bottom portions (eg, 153a, 153b, 163a, and 163b). In this example, the metal portions 151a, 151b, 161a and 161b and the third vertical interconnect structures 170a and 170b are made of the same metal material, such as tungsten, and may be formed by chemical vapor deposition (CVD). Bottom portions 153a and 163a are made of the same silicide, such as nickel silicide. Bottom portions 153b and 163b are made of the same material, such as nickel germanium. In some embodiments, metal portions 151a, 151b, 161a, and 161b may include other conductive materials. In some embodiments, bottom portions 153a, 153b, 163a, and 163b may include other metal-silicon compounds or other metal-germanium compounds, while typical metals may include Ru, Ti, Co, W, Pt, Pd, and the like. In some embodiments, the metal portions 151a, 151b, 161a, and 161b and the third vertical interconnect structures 170a and 170b may include mutually different conductive materials. In some embodiments, the bottom portions 153a, 153b, 163a, and 163b may comprise mutually different materials. In some embodiments, the third vertical interconnect structures 170a and 170b may include a bottom portion and a top portion (not shown). Further, although the third vertical interconnect structures 170a and 170b are separated from the pad structures 131 and 132 through the second dielectric material 105 in this example, in other embodiments, the third vertical interconnect structures 170a and 170b may be It is further separated from the second dielectric material 105 through the insulating material 102 (not shown).

Note that although the first transistor 110 and the second transistor 120 are NMOS and PMOS, respectively, in this example, the first transistor 110 and the second transistor 120 may include any kind of transistors to meet specific design requirements. In one embodiment, the first transistor 110 and the second transistor 120 are PMOS and NMOS, respectively. In another embodiment, the first transistor 110 and the second transistor 120 are both PMOS. In another embodiment, the first transistor 110 and the second transistor 120 are both NMOS.

26C is a schematic top view of the semiconductor device of FIG. 26A according to an exemplary embodiment of the present invention. In this embodiment, the second vertical interconnection structure 160a and the third vertical interconnection structure 170a are disposed on different sides of the first channel structure 111 and are spaced apart from the first channel structure 111 by the same distance. The second vertical interconnection structure 160b and the third vertical interconnection structure 170b are disposed on the same side of the second channel structure 121 and separated from the second channel structure 121 by different distances. It will be appreciated that the position (including radial position and distance) of the vertical interconnect structures (eg, 150a, 150b, 160a, 160b, 170a, and 170c) relative to the corresponding channel structures (eg, 111 and 121) (eg, 150a, 150b) , 160a, 160b, 170a, and 170c) may vary based on the wiring routing design.

27A-27E illustrate examples of wiring designs (wiring 200A, wiring 200B, wiring 200C, wiring 200D, and wiring 200E) in accordance with some embodiments. In particular, Figures 27A and 27B are top views showing the position of the channel structure relative to the pad structure. Note that a given channel structure can be centered on the corresponding pad structure or offset in any direction. For example, in wiring 200A, channel structure 211 is located at the center of pad structure 213 , while in wiring 200B, channel structure 211 is offset from the center of pad structure 213 .

27C-27E are top views illustrating exemplary vertical interconnect structure arrangements. In the wiring 200C, the channel structure 211 is located at the center of the pad structure 231 . The first vertical interconnect structure 250 is disposed over the pad structure 213 and can be used as a top S/D contact. A second vertical interconnect structure 260 , which can be used as a bottom S/D contact, and a third vertical interconnect structure 270 , which can be used as a gate electrode, are located on different sides of the channel structure 211 . Further, the first, second and third vertical interconnect structures 250, 260 and 270 are in line with each other. Note that the first transistor 110 in FIGS. 26A-26C may correspond to the wiring 200C.

In the routing 200D, the channel structure 211 is offset from the center of the pad structure 231 (or the pad structure 231 extends more to the right of the channel structure 211 in the X direction). The second vertical interconnection structure 260 and the third vertical interconnection structure 270 are located on the same side of the channel structure 211 . Further, the second vertical interconnect structure 260 and the third vertical interconnect structure 270 may be disposed at the same radial position with respect to the channel structure 211, but at different distances. In this example, the third vertical interconnection structure 270 is disposed at a peripheral position of the channel structure 211 , and the second vertical interconnection structure 260 is disposed at a position farther from the channel structure 211 . Note that the second transistor 120 in FIGS. 26A-26C may correspond to the wiring 200D.

The wiring 200E is similar to the wiring 200D, except that a fourth vertical interconnect structure 240 may be provided on the backside of the channel structure 211 . The fourth vertical interconnect structure 240 may contact a gate structure (not shown) and function as a gate electrode, similar to the third vertical interconnect structure 270 . Alternatively, the fourth vertical interconnect structure 240 may contact the peripheral region of the pad structure 231 and serve as a bottom S/D contact, similar to the second vertical interconnect structure 260 .

Note that the channel structure 211, the pad structure 231 and the first, second and third vertical interconnect structures 250, 260 and 270 may correspond to the channel structures 111 and 121, the pad structures 131 and 132 and the vertical interconnect structures 150a-150b, respectively , 160a-160b and 170a-170b. The description has been provided above and will be omitted here for brevity. Further, although the first, second and third vertical interconnect structures 250, 260 and 270 are shown in line with each other in FIGS. 27C-27E, it is possible to vary the second and third vertical interconnect structures 260 and 270 relative to each other. In the radial position of the channel structure 211, it will be explained in detail in Figures 28A-28D.

28A-28D illustrate examples of wiring designs (wiring 300A, wiring 300B, wiring 300C, and wiring 300D) in accordance with some embodiments. Displays circular and rectangular 3D vertical installations. A vertical channel of any shape can be considered to have a perimeter or perimeter around which contacts can be placed at any radial position and at any distance. Of course, the 3D vertical device can also have other shapes.

In the wiring 300A, the first vertical interconnect structure 350 may be formed over the channel structure 311 in the Z direction. The second vertical interconnection structure 360 and the third vertical interconnection structure 370 can be separated from the channel structure 311 in the XY plane through the isolation layer 304 and are arranged along the periphery of the isolation layer 304 . In this example, the second vertical interconnection structure 360 and the third vertical interconnection structure 370 are in line with the first vertical interconnection structure 350 . Thus, wiring 300A may correspond to first transistor 110 in Figures 26A-26C and wiring 200C in Figure 27C. In other embodiments, the second vertical interconnection structure 360 and the third vertical interconnection structure 370 may be located anywhere away from the channel structure 311 . Accordingly, the vertical interconnect structures 350, 360 and 370 may not need to be in line with each other. Note that the channel structure 311, the vertical interconnect structures 350, 360 and 370 may correspond to the channel structures 111 and 121 and the vertical interconnect structures 150a-150b, 160a-160b and 170a-170b, respectively. In some embodiments, isolation layer 304 may correspond to insulating material 102 . In other embodiments, isolation layer 304 may further include first spacer material 117 or second spacer material 127 .

Figure 28B shows a top view of an example of a 360 degree connection option for vertical transistors. The vertical connection size controls several optional positions. In this example, there are twelve (different potential) contact locations 306a-306k relative to the channel structure 311 of the 3D vertical device. During fabrication, two of the contact locations 306a-306k can be selectively used to form second and third vertical interconnect structures 360 and 370, which can serve as bottom S/D contacts and gate electrodes, respectively. Note that wiring 300B is similar to wiring 300A, except that there are ten unused contact locations 306a-306f, 306h, and 306j-306k. In other words, during fabrication, only contact locations 306g and 306i are subjected to corresponding etching and deposition processes to form contacts or interconnects. Also note that because this vertical device structure is 360 degree symmetrical, the second and third vertical interconnect structures 360 and 370 can be placed on either side of the vertical structure for optimal routing efficiency.

In some embodiments, two adjacent contact positions of the photomask may be used. For example, in wiring 300C of Figure 28C, second and third vertical interconnect structures 360 and 370 are formed in contact locations 306a and 306b. It should be understood that the contact locations 306a and 306b are separated from each other by one or more electrical insulators. In some embodiments, the channel structures 311 may have different shapes. For example, wiring 300D shown in Figure 28D is similar to wirings 300B and 300C, except that channel structure 311 is rectangular and has thirteen contact locations 306a-306l. Contact locations 306i and 306l are used in this example. Further, the size, shape, radial position relative to the channel structure 311, distance from the channel structure 311, and number of contact locations can be varied in other embodiments.

29 illustrates a flow diagram of an exemplary process 400 for fabricating an exemplary semiconductor device in accordance with an embodiment of the present invention. Process 400 begins at step S401 in which a pad layer is formed over a substrate. The pad layer may include at least one pad structure having a core region surrounded by a peripheral region. For example, the pad layer may include a first pad structure and a second pad structure. In some embodiments, the first pad structure and the second pad structure can be separated from each other by a dielectric material. In an alternative embodiment, the first pad structure and the second pad structure may be interconnected.

In step S402, a transistor may be formed over the core region of the pad structure. The transistor may include a channel structure extending in a vertical direction and a gate structure around sidewall portions of the channel structure. The channel structure may have a vertical channel region and source and drain regions on opposite ends of the vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. In some embodiments, PMOS devices and NMOS devices may be formed on two adjacent pad structures. In some embodiments, two PMOS devices or two NMOS devices may be formed on two adjacent pad structures.

In step S403, a first vertical interconnect structure may be formed that contacts the top surface of the channel structure. In some embodiments, the first vertical interconnect structure is configured to be electrically coupled to a top source region or a top drain region of the transistor.

In step S404, a second vertical interconnect structure may be formed, which contacts the peripheral region of the pad structure and is configured to be coupled to the bottom surface of the channel structure via the pad structure. In some embodiments, the second vertical interconnect structure is configured to be electrically coupled to a bottom source region or a bottom drain region of the transistor.

In step S405, a third vertical interconnect structure may be formed, which is disposed away from the channel structure and contacts the gate structure of the transistor. In some embodiments, the third vertical interconnect structure serves as the gate electrode of the transistor.

It should be noted that additional steps may be provided before, during, and after process 400, and that additional embodiments of process 400 may replace, delete, or perform some of the steps described in a different order. For example, before step S403, an insulating material may be deposited over the pad layer to fill the space and cover the transistor. In some embodiments, step S403 may be performed before or after step S404. In other embodiments, step S403 and step S404 may be performed together. That is, the first and second vertical interconnect structures can be formed in the same process. Further, in some embodiments, step S405 may be performed during an intermediate step between step S403 and step S404.

30A-30H are cross-sectional views of a semiconductor device 500 at various intermediate steps in the fabrication process in accordance with exemplary embodiments of the present invention. In particular, Figures 30A-30H may illustrate the formation of a 360 degree VIA (vertical interconnect on) on a CMOS GAA vertical transistor by first forming a through-hole gate contact (or bottom portion of the gate electrode), followed by Source and drain contacts, which are silicided after contact opening. This example uses a CMOS flow, but in other embodiments an NMOS-only or PMOS-only flow can be substituted.

As shown in FIG. 30A , the semiconductor device 500 includes a substrate 501 and a pad layer 530 above the substrate 501 . The substrate 501 and the pad layer 530 may be separated by the first dielectric layer 503 . The pad layer 530 may include at least one pad structure, such as a first pad structure 531 and a second pad structure 532 . In this example, the first pad structure 531 and the second pad structure 532 are separated by the second dielectric material 505 .

The first pad structure 531 may have a first core region 531a surrounded by a first peripheral region 531b, and the second pad structure 532 may have a second core region 532a surrounded by a second peripheral region 532b. The first transistor 510 and the second transistor 520 may be disposed above the first core region 531a and the second core region 532a, respectively. The first transistor 510 may have a first channel structure 511 and a first gate structure 515 around a sidewall portion of the first channel structure 511 . The first transistor 510 may also include a first high-k dielectric material 513 sandwiched between the first channel structure 511 and the first gate structure 515 , and a first spacer material 517 isolating the first channel structure 511 . Likewise, the second transistor 520 may have a second channel structure 521 , a second gate structure 525 , a second high-k dielectric material 523 and a second spacer material 527 . In this example, the first transistor 510 and the second transistor 520 are NMOS and PMOS, respectively. Accordingly, the second gate structure 525 may include a first portion 525a and a second portion 525b. In addition, a portion of the first and second peripheral regions 531b and 532b and the first and second channel structures 511 and 521 may be covered by the second dielectric material 505 .

Note that the substrate 501, the first dielectric layer 503, the pad layer 530 (including the first pad structure 531 and the second pad structure 532), and the second dielectric layer 505 may correspond to the substrate 101, the first dielectric layer 103, The pad layer 130 (including the first pad structure 131 and the second pad structure 132 ) and the second dielectric material 105 . The first transistor 510 and the second transistor 520 may correspond to the first transistor 110 and the second transistor 120, respectively. Accordingly, the channel structures 511 and 521, the gate structures 515 and 525, the high-k dielectric materials 513 and 525, and the spacer materials 517 and 527 may correspond to the channel structures 111 and 121, the gate structures 115 and 125, the high-k dielectric materials, respectively Dielectric materials 113 and 125, and spacer materials 117 and 127.

Further, in Figure 30A, each of the channel structures 511 and 521 may have a length defined by a deposition process (eg, epitaxial growth). A conventional technique for defining channel lengths is performed by depositing a film and then using yellow light lithography to cut the film or fins into channels or fin segments. Using the techniques herein, the channel locations are defined, and then the length or distance of the current transport path can be defined by epitaxial growth, atomic layer deposition, or other precisely controlled deposition techniques. Note that the channel structures 511 and 521 may be on silicon or germanium material, which may have P or N implanted dopants. In this example, the NMOS and the PMOS are spaced apart and arranged side by side. In other examples, pad structures (eg, 531 and 532) may be connected. Such pad structures may serve as S/D connection landing spots and thus extend beyond the footprint or perimeter of the channel structures (eg, 511 and 521).

In FIG. 30B , a conductive material 573 may be deposited over the pad layer 530 to fill the spaces, and a second dielectric material 505 may be deposited over the conductive material 573 . For example, the conductive material 573 may include a metal such as tungsten (W). Accordingly, deposition of tungsten may be performed by CVD, followed by a planarization step (eg, CMP) to remove the W capping layer, followed by deposition of a second dielectric material 505 thereon. Note that the second dielectric material 505 and the first dielectric material 503 can be the same material or different dielectric materials that can be selectively etched relative to each other.

In Figure 30C, a first etch mask 509a is used to etch and define future metal gate connections. Accordingly, bottom portions of the third vertical interconnect structures 573a and 573b can be formed, which are connected to the sidewall portions of the first and second channel structures 511 and 521, respectively. The first etch mask 509a may be made of photoresist or hard mask material. In Figure 30D, the first etch mask 509a is removed, followed by dielectric deposition and planarization. Accordingly, insulating material 502 is formed over pad layer 530 to fill space and cover transistors 510 and 520 .

In Figure 30E, a second etch mask 509b is used to define the S/D regions or to form contact openings to the S/D regions. As shown, first openings 555a and 555b extend through insulating material 502 and second dielectric material 505 and land on top surfaces of first and second channel structures 511 and 521, respectively. The second openings 565a and 565b extend through the insulating material 502 and the second dielectric material 505 and then fall on the top surfaces of the first and second peripheral regions 531b and 532b, respectively. Note that the pad structures 531 and 532 are in contact with the channel structures 511 and 521 and extend beyond the perimeter or periphery of the channel structures 511 and 521, respectively. Pad structures 531 and 532 may extend beyond channel structures 511 and 521 in all directions (or some directions), respectively, to provide usable connection points at any radial location and any distance from the center point of channel structures 511 and 521 . In addition, although the first openings 555a and 555b and the second openings 565a and 565b are formed in the same step in this example, in other embodiments the first openings 555a and 555b and the second openings 565a and 565b may be separated formed in the step.

30F, the second mask 509b is removed, followed by the bottoms of the first openings 555a and 555b on the exposed portions of the first and second channel structures 511 and 521 and between the first and second peripheral regions 531b and 532b A metal material (not shown) is deposited at the bottom of the second openings 565a and 565b on the exposed portions, followed by silicidation to form bottom portions 553a, 553b, 563a and 563b. The silicide can be accomplished, for example, by annealing the metal material to react with the pad structures 531 and 532 to form a silicide layer, and can remove any unreacted metal material. In this example, the metal material is Ni. The bottom portions 553a, 553b, 563a and 563b may include nickel silicide and/or nickel germanium, depending on the chemical composition of the first and second pad structures 531 and 532. Other metals (eg, Ru, Ti, Co, W, Pt, Pd, etc.) may also be used to form bottom portions 553a, 553b, 563a, and 563b. The bottom portions 553a, 553b, 563a and 563b can be made of the same material or different materials, depending on the chemical composition of the first and second pad structures 531 and 532. Further, the thickness of the bottom portions 553a, 553b, 563a and 563b can be controlled by metal deposition and silicidation.

In some embodiments, the fabrication process then proceeds to FIG. 30G, where metal portions 551a, 551b, 561a, and 561b are formed, thereby completing the first vertical interconnect structures 550a and 550b and the second vertical interconnect structures 560a and 560b. For example, deposition of W (eg, by CVD) may be performed, followed by removal of the capping layer. Note that the first vertical interconnect structures 550a and 550b and the second vertical interconnect structures 560a and 560b may correspond to the first vertical interconnect structures 150a and 150b and the second vertical interconnect structures 160a and 160b, respectively.

Subsequently, in FIG. 30H, third vertical interconnect structures 570a and 570b are completed, so that the semiconductor device 500 may correspond to the semiconductor device 100 in FIGS. 26A-26C. To complete the third vertical interconnect structures 570a and 570b, a third etch mask (not shown) is formed to form a third opening (not shown) that exposes bottom portions of the third vertical interconnect structures 573a and 537b, and then The third opening may be filled by depositing conductive material 573 to form a top portion (not shown) of the third vertical interconnect structure thereon. In other embodiments, the top portion of the third vertical interconnect structure may be chemically different from the bottom portion of the third vertical interconnect structures 573a and 573b. Furthermore, the third vertical interconnect structures 573a and 537b can be located at any radial position around the perimeter of the channel structures 511 and 521 .

In an alternative embodiment, after the silicidation in FIG. 30F, the fabrication process proceeds to FIG. 30G', in which the third opening 575a and 575b. First, insulating material 502 may be deposited to fill first openings 555a and 555b and second openings 565a and 565b (not shown). Next, a fourth etch mask 509c is formed which redefines the first and second openings 555a, 555b, 565a and 565b and defines third openings 575a and 575b that expose bottom portions of the third vertical interconnect structures 573a and 573b. In some embodiments, the first openings 555a and 555b and the second openings 565a and 565b do not need to be filled and redefined, and the third openings 575a and 575b can be directly formed with different fourth etch masks 509c.

Subsequently, in FIG. 30H, metal deposition is performed to fill the first, second, and third openings 555a, 555b, 565a, 565b, 575a, and 575b, followed by CMP planarization to remove the capping layer. Thus, the semiconductor device 500 may correspond to the semiconductor device 100 in FIGS. 26A-26C.

31A-31C are cross-sectional views of a semiconductor device 600 at various intermediate steps in an alternate fabrication process according to an exemplary embodiment of the present invention. In particular, Figures 31A-31C may illustrate an alternative embodiment providing 360 degree via formation on a CMOS GAA vertical transistor that fabricates source and drain contacts (silicided after S/D contact openings) , followed by through-hole contacts for the gate electrode area. The illustration shows a CMOS device, but the techniques herein can also be applied to side-by-side PMOS devices and side-by-side NMOS devices.

Since the exemplary embodiment of the semiconductor device 600 in FIG. 31A is similar to the exemplary embodiment of the semiconductor device 500 in FIG. 31A , explanation of the differences will be emphasized. Semiconductor device 600 may include insulating material 602 over pad layer 630 . The insulating material 602 may fill the space and cover the first transistor 610 and the second transistor 620 .

In FIG. 31B, first vertical interconnect structures 650a and 650b and second vertical interconnect structures 660a and 660b may be formed, which correspond to the first vertical interconnect structures 550a and 550b and the second vertical interconnect in FIG. 30H, respectively Structures 560a and 560b. The formation of the first vertical interconnect structures 650a and 650b and the second vertical interconnect structures 660a and 660b can be accomplished in a process similar to that shown in Figures 30E-30G. Specifically, a mask (not shown) can be formed that defines first and second openings (not shown) for the vertical interconnect structures 650a, 650b, 660a, and 660b. Next, bottom portions 653a, 653b, 663a, and 663b may be formed by metal deposition and silicidation. Next, metal portions 651a, 651b, 661a, and 661b may be formed. Further, an etch stop layer 608 (eg, silicon nitride) is optionally deposited over insulating material 602 and vertical interconnect structures 650a, 650b, 660a, and 660b.

In FIG. 31C, third vertical interconnect structures 670a and 670b are formed. Thus, the semiconductor device 600 may correspond to the semiconductor device 500 in FIG. 30H. In this embodiment, the gate electrode opening is formed with a separate mask (not shown), with which a directional etch is performed, followed by mask removal and metal filling. A subsequent CMP process may be performed, which stops on insulating material 602 using etch stop layer 608 to determine the endpoint of the CMP process. Note that the directional etch may include etching a portion of the insulating material 602 adjacent the first gate 615 to expose the first gate 615 . Further, the third vertical interconnect structures 670a and 670b may correspond to the third vertical interconnect structures 570a and 570b in FIG. 30H, respectively, except that the third vertical interconnect structures 670a and 670b may be formed in a single etching and deposition process and the third Three vertical interconnect structures 570a and 570b may be formed in addition to the two etch and deposition processes. In addition, the third vertical interconnect structures 670a and 670b can be separated from the second dielectric material 605 through the insulating material 602 .

Although not shown, in some embodiments, the first and second openings may be formed in insulating material 602 in FIG. 31A, followed by silicidation to form bottom portions 653a, 653b, 663a, and 663b. Next, a third opening can be formed, followed by metal deposition to fill the first, second, and third openings, thereby forming the semiconductor device 600 of FIG. 31C.

32A is a schematic top view of a semiconductor device 700A according to an exemplary embodiment of the present invention. As shown, the semiconductor device 700A may include first vertical interconnect structures 750a and 750b disposed over the first channel structure 711 and the second channel structure 721, respectively. The semiconductor device 700A may also include a first common vertical interconnect structure 780 and a second common vertical interconnect structure 790 . The insulating material 702 may fill the space and separate the first common vertical interconnect structure 780 from the second common vertical interconnect structure 790 . Although not shown, the plurality of semiconductor devices 700A may be formed in an array.

Fig. 32B shows a cross-sectional view taken along the line BB' in the Z direction in Fig. 32A. Since the exemplary embodiment of the semiconductor device 700A in FIG. 32B is similar to the exemplary embodiment of the semiconductor device 600 in FIG. 31C , explanation of the differences will be emphasized. In this present example, the second vertical interconnect structure (shown and explained in FIG. 31C ) and the third vertical interconnect structures 770a and 770b are arranged at different radial positions. In particular, the third vertical interconnect structures 770a and 770b are adjacent to and in contact with each other. Further, the third vertical interconnect structures 770a and 770b may be chemically identical and thus integrally form the first common vertical interconnect structure 780 . In this example, the third vertical interconnect structures 770a and 770b may include top portions 771a and 771b and bottom portions 773a and 773b. The top portions 771a and 771b may be chemically identical and integrally formed to form the top portion of the first common vertical interconnect structure 781 . The bottom portions 773a and 773b may be chemically identical and integrally formed to form the bottom portion of the first common vertical interconnect structure 783 connected to the first gate structure 715 and the second gate structure 725 . Therefore, the first common vertical interconnect structure 780 can be used as a common gate electrode of the first transistor 710 and the second transistor 720 . In this example, the top and bottom portions of the first common vertical interconnect structures 781 and 783 are made of different materials. Alternatively, the top and bottom portions of the first common vertical interconnect structures 781 and 783 may be made of the same material, such as tungsten.

Further, in FIG. 32B , the first pad structure 731 and the second pad structure 732 are in contact with each other. A first horizontal contact structure 741 may be provided that contacts both the first pad structure 731 and the second pad structure 732 . The first horizontal contact structure 741 can reduce the resistance between the first pad structure 731 and the second pad structure 732 . The first horizontal contact structure 741 can be arranged in the recesses of the first pad structure 731 and the second pad structure 732 as shown in this example, or in other embodiments, in the first pad structure 731 and the second pad structure 732 above. The second dielectric material 705 may be disposed over the first horizontal contact structure 741 to separate the first horizontal contact structure 741 from the first common vertical interconnect structure 780 . In this example, the first horizontal contact structure 741 is a silicide, such as nickel silicide, and a horizontal structure 741' made of the same silicide can be disposed over the peripheral regions 731b and 732b.

FIG. 32C is a cross-sectional view taken along the line CC' in the Z direction in FIG. 32A. The second vertical interconnect structures 760a and 760b are adjacent to and in contact with each other. Further, the second vertical interconnect structures 760a and 760b may be chemically identical and thus integrally form the second common vertical interconnect structure 790 . That is, the second vertical interconnect structures 760a and 760b may include metal portions 761a and 761b and bottom portions 763a and 763b. The metal portions 761a and 761b may be chemically identical and integrally formed to form the metal portion of the second common vertical interconnect structure 791 . Bottom portions 763a and 763b may be chemically identical and integrally formed to form the bottom portion (also referred to as the second horizontal contact structure) of the first common vertical interconnect structure 793, which is connected to the first pad structure 731 and the second pad structure 732. Therefore, the second common vertical interconnect structure 790 can be used as a common bottom S/D contact, which is connected to the bottom S/D regions (not shown) of the transistors 710 and 720 via the pad structures 731 and 732 .

32D is an equivalent circuit diagram 700B of the semiconductor device 700A of FIGS. 32A-32C (in an embodiment in which transistors 710 and 720 form a CMOS device). The circuit diagram 700B shows that the semiconductor device 700A can be used as a CMOS inverter including a ground voltage Vss, a supply voltage Vdd, an input voltage Vin, and an output voltage Vout. The ground voltage Vss and the supply voltage Vdd may correspond to the first vertical interconnect structures 750a and 750b. The input voltage Vin and the output voltage Vout may correspond to the first common vertical interconnection structure 780 and the second common vertical interconnection structure 790, respectively.

33A-33H are cross-sectional views of a semiconductor device 800 at various intermediate steps of fabrication in accordance with an exemplary embodiment of the present invention. In particular, Figures 33A-33H may illustrate exemplary processes for fabricating CMOS GAA inverters. It is understood that other logic device types may also be created using the techniques herein.

The semiconductor device 800 in FIG. 33A is similar to the semiconductor device 500 in FIG. 30A except that the first pad structure 831 and the second pad structure 832 are in contact with each other. The first horizontal contact structure 841 and the second horizontal contact structure (not shown) may be arranged to contact both the first pad structure 831 and the second pad structure 832 . Bottom portions of the first vertical interconnect structures 853a and 853b may be disposed over the first channel structure 811 and the second channel structure 812 . The first horizontal contact structure 841 can reduce the resistance between the first pad structure 831 and the second pad structure 832 . The first horizontal contact structure 841 can be arranged in the recesses of the first pad structure 831 and the second pad structure 832 as shown in this example, or in other embodiments in the first pad structure 831 and the second pad structure 832 above. In this example, the bottom portions of the first vertical interconnect structures 853a and 853b and the first horizontal contact structure 841 are made of one or more silicides, such as nickel silicide and nickel germanium, also made of silicides The horizontal structure 841' may be disposed above the peripheral regions 831b and 832b.

In FIG. 33B, the second dielectric material 805 may be disposed above the first horizontal contact structure 841 and the horizontal structure 841'. In Figure 33C, the second dielectric material 805 may be etched to a predetermined thickness. In FIG. 33D, a first conductive material 883' (eg, tungsten) may be deposited over the second dielectric material 805, followed by planarization and deposition of the second dielectric material 805.

In Figure 33E, a mask 809 is formed, which defines the future gate metal connection. A portion of the second dielectric material 805 and a portion of the first conductive material 883' are removed. The remaining first conductive material 883 ′ may form the bottom portion of the third vertical interconnect structure 883 , which contacts the first gate structure 815 of the first transistor 810 and the second gate structure of the second transistor 820 . In this example, the first transistor 810 and the second transistor 820 are NMOS and PMOS, respectively. Therefore, the bottom portion of the third vertical interconnection structure 883 is connected between the NMOS and the PMOS.

In FIG. 33F, the exposed portions of the mask 809 and the second dielectric material 805 are removed, so that the bottom portions of the first vertical interconnect structures 853a and 853b are exposed.

In FIG. 33G, an insulating material 802 (eg, silicon oxide) is deposited to fill the space and cover the first transistor 810 and the second transistor 820. Subsequently, openings (eg, 855a, 855b, and 885) may be defined and etched for contacts of the inverter connection lines. Note that at least four contacts are required, whereas Figure 33G shows three openings 855a, 855b, and 885. A fourth opening may be behind this cross-sectional view of Figure 33G.

In Figure 33H, a second conductive material can be deposited and any capping layers can be removed by planarization. Thus, the first vertical interconnect structures 850a and 850b and the first common vertical interconnect structure 880 are completed. Semiconductor device 800 may correspond to semiconductor device 700A in FIGS. 32A-32C. Accordingly, a second common vertical interconnect structure may be disposed behind the cross-sectional view of Figure 33H.

The various embodiments described herein provide several advantages. For example, vertical 3D epitaxial growth of vertical transistors allows current flow in the vertical dimension or perpendicular to the wafer surface. The methods and designs herein include fabricating CMOS devices with vertical current flow, ie, current flow in one direction. The vertical 3 device herein enables another degree of freedom in the Z-direction that will enhance the routing options of existing 3D devices. Since the channel length is defined by the deposited or epitaxially grown layers, relatively short transistor lengths are achieved. Precise alignment with the gate electrode is achieved by selectively removing the intermediate dielectric layer. The techniques herein obviate the need for oxide isolation for 3D nanostacks. For gate full loop (GAA) devices with specific substrate conditions, vertical transistors can have infinite widths.

Because the gate and source regions have a 360 degree connection, contacts can be placed on either side of the source or either side of the gate. The source and drain are interchangeable because each channel can be isolated from the others. The 360 degree connection is a significant advantage of the device structure for maximum wiring connection and wiring. A given channel area can be focused on pad structure or offset depending on circuit requirements for maximum routing efficiency. The vertical 3D structure provides turn-on (360-degree contacts and routing to channel, source, and drain), thereby increasing circuit density. Several exemplary embodiments of contact routing with metal routing will be described and illustrated, including inverter flows with GAA channels with 3D connections.

In the foregoing description, specific details have been set forth, such as a description of the particular geometry of the processing system and the various components and processes used therein. It should be understood, however, that the techniques herein may be practiced in other embodiments that depart from these specific details, which are presented for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Likewise, for purposes of explanation, specific numbers, materials and configurations have been given to provide a thorough understanding. However, embodiments may be practiced without these specific details. Components having substantially the same functional configuration are denoted by the same reference numerals, and thus any redundant descriptions may be omitted.

Various techniques have been described as discrete operations to facilitate understanding of the various embodiments. The order of description should not be construed to imply that such operations are necessarily order dependent. In fact, such operations need not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Numerous additional operations may be performed in additional embodiments and/or such operations may be omitted.

As used herein, "substrate" or "target substrate" generally means an object to be processed in accordance with the present invention. The substrate may comprise any material portion or structure of a device, especially a semiconductor or other electronic device, and may, for example, be a base substrate structure such as a semiconductor wafer, a photomask, or on or overlying a base substrate structure a layer (eg a film). Thus, the substrate is not limited to any particular base structure, underlying or overlying layer, patterned or unpatterned, but rather is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may refer to a particular type of substrate, but this is for illustration purposes only.

Those skilled in the art will also appreciate that many variations can be made in the operation of the above-described techniques while still achieving the same objectives of the present invention. Such variations are intended to be encompassed by the scope of the present invention. As such, the foregoing description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.

In the foregoing description, specific details have been set forth, such as a description of the particular geometry of the processing system and the various components and processes used therein. It should be understood, however, that the techniques herein may be practiced in other embodiments that depart from these specific details, which are presented for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Likewise, for purposes of explanation, specific numbers, materials and configurations have been given to provide a thorough understanding. However, embodiments may be practiced without these specific details. Components having substantially the same functional configuration are denoted by the same reference numerals, and thus any redundant descriptions may be omitted.

Various techniques have been described as discrete operations to facilitate understanding of the various embodiments. The order of description should not be construed to imply that such operations are necessarily order dependent. In fact, such operations need not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Numerous additional operations may be performed in additional embodiments and/or such operations may be omitted.

As used herein, "substrate" or "target substrate" generally means an object to be processed in accordance with the present invention. The substrate may comprise any material portion or structure of a device, especially a semiconductor or other electronic device, and may, for example, be a base substrate structure such as a semiconductor wafer, a photomask, or on or overlying a base substrate structure a layer (eg a film). Thus, the substrate is not limited to any particular base structure, underlying or overlying layer, patterned or unpatterned, but rather is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may refer to a particular type of substrate, but this is for illustration purposes only.

Those skilled in the art will also appreciate that many variations can be made in the operation of the above-described techniques while still achieving the same objectives of the present invention. Such variations are intended to be encompassed by the scope of the present invention. As such, the foregoing description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described herein.

100: Semiconductor Devices 101: Substrate 102: Substrate, insulating material 103: first dielectric layer 104: The first dielectric material 105: The second dielectric material 106: The first layer of semiconductor materials 108: The second dielectric material 110: photoresist, mask layer, first dielectric layer stack, first transistor 111: Lower source/drain dielectric layer 112: N+ channel material, vertical channel, gate dielectric layer 113: Upper source/drain dielectric layer 114: The third dielectric material 115: The first gate structure 116: Deposition of Selective High-K Layers 117: First Spacer Material 118: Interfacial oxide growth 120: metal gate electrode stack, gate stack material, second dielectric layer stack, second transistor 121: Lower source/drain dielectric layer 122: P-doped silicon or germanium layer, gate dielectric layer 123: Upper source/drain dielectric layer, second high-k dielectric material 125: Second gate structure, high-k dielectric material 125a: Part 1 125b: Part II 127: Second Spacer Material 130: substrate, cushion 131: Opening, first pad structure 131a: First Core Area 131b: First Peripheral Area 132: Metal connection, second pad structure 132a: Second core area 132b: Second peripheral area 134: Metal connection 136: Metal connection 140: exposed part, transition dielectric layer 150: hard mask 150a: Vertical Interconnect Structure 150b: Vertical Interconnect Structure 151a: Metal parts 151b: Metal parts 153a: Bottom part 153b: Bottom part 160: Dielectric layer 160a: Vertical Interconnect Architecture 160b: Vertical Interconnect Structure 161a: Metal parts 161b: Metal parts 163a: Bottom part 163b: Bottom part 170: Implant Layer 170a: Vertical Interconnect Structure 170b: Vertical Interconnect Structure 200A: Wiring 200B: Wiring 200C: Wiring 200D: Wiring 200E: Wiring 202: Substrate 204: Dielectric oxide, first dielectric material 208: Second Dielectric Material 210: photoresist, mask 211: Channel Structure 214: The third dielectric material 216: Selective High-K Layer 218: Interfacial oxide growth 220: Metal gate electrode stack, opening 222: First Layer Semiconductor Materials 224: Vertical channel, P+ channel material 230: Opening 231: Opening, pad structure 232: Metal connection 234: Metal connection 236: Metal connection 240: Fourth Vertical Interconnect Structure 242: Channel area 250: First Vertical Interconnect Structure 260: Second Vertical Interconnect Structure 270: Third Vertical Interconnect Structure 300A: Wiring 300B: Wiring 300C: Wiring 300D: Wiring 302: Silicon 304: Dielectric layer, dielectric material, isolation layer 305: Monocrystalline silicon 306: N+ Layer 306a: Contact position 306b: Contact position 306c: Contact position 306d: Contact position 306e: Contact position 306f: Contact position 306g: Contact position 306h: Contact position 306i: Contact position 306j: Contact position 306k: Contact position 306l: Contact position 308: Dielectric Layer/Dielectric Material 310: Photomask, photoresist, photoresist mask 311: Channel Structure 312: N+ channel area 314: The third dielectric material 316: High-K Deposition, Gate Stacking Materials 318: Interface Oxide Growth, Gate Stack Materials 322:P+layer 324:P+ vertical channel material 326: protective film, dielectric material 328: Gate metal layer, gate stack material 330: Gate metal layer, gate stack material 331: Separation 332N: Electrode 332P: Electrode 334: NMOS stack gate electrode area 334N: Electrode 334P: Electrode 336N: Gate electrode 336P: Gate electrode 340:NMOS gate stack 342: Open, PMOS gate stack 350: First Vertical Interconnect Structure 360: Second Vertical Interconnect Structure 370: Third Vertical Interconnect Structure 400: Semiconductor devices and processes 410: first channel, first semiconductor device 420: Second channel 500: Semiconductor Devices 501: Substrate 502: Insulation material 503: first dielectric layer, first dielectric material 505: the second dielectric layer, the second dielectric material 509a: First etch mask 509b: Second etch mask 509c: Fourth etch mask 510: First semiconductor device, NMOS, PMOS 511: First channel structure 513: The first high-k dielectric material 515: The first gate structure 517: First Spacer Material 520: Second semiconductor device, PMOS, NMOS 521: Second channel structure 523: Second High-k Dielectric Material 525: Second gate structure 525a: Part 1 525b: Part II 527: Second Spacer Material 530: mask, photoresist mask, cushion 531: Pad Structure 531a: First Core Area 531b: First Peripheral Area 532: Second Pad Structure 532a: Second core area 532b: Second Peripheral Area 550a: First Vertical Interconnect Structure 550b: First Vertical Interconnect Structure 551a: Metal parts 551b: Metal parts 553a: Bottom part 553b: Bottom part 555a: first opening 555b: First opening 560a: Second Vertical Interconnect Structure 560b: Second Vertical Interconnect Structure 561a: Metal parts 561b: Metal parts 563a: Bottom part 563b: Bottom part 565a: Second opening 565b: Second opening 570a: Third Vertical Interconnect Structure 570b: Third Vertical Interconnect Structure 573: Conductive Materials 573a: Third Vertical Interconnect Structure 573b: Third Vertical Interconnect Structure 575a: Third Opening 575b: Third opening 600: Semiconductor Devices 601: Substrate 602: Insulation material 603: The first dielectric material 605: Second Dielectric Material 608: Etch stop layer 610: High-k Dielectric Materials 611: First channel structure 612: Gate Dielectric Material 613: The first high-k dielectric material 615: first gate 617: First Spacer Material 620: Second transistor 621: Second channel structure 622: Gate Dielectric Material 623: Second High-k Dielectric 625: second gate 625a: Part 1 625b: Part II 627: Second Spacer Material 630: Cushion 631: First Pad Structure 631a: First Core Area 631b: First Peripheral Area 632: Second Pad Structure 632a: Second Core Area 632b: Second Peripheral Area 650a: First Vertical Interconnect Structure 650b: First Vertical Interconnect Structure 651a: Metal parts 651b: Metal parts 653a: Bottom part 653b: Bottom part 660a: Second Vertical Interconnect Structure 660b: Second Vertical Interconnect Structure 661a: Metal parts 661b: Metal parts 663a: Bottom part 663b: Bottom part 670a: Third Vertical Interconnect Structure 670b: Third vertical interconnect structure 700A: Semiconductor Devices 700B: Circuit Diagram 701: Substrate 702: Insulation material 703: The first dielectric material 705: Second Dielectric Material 711: First channel structure 713: The first high-k dielectric material 714: Internal Metal Materials 715: External metal material, first gate structure 717: First Spacer Material 720: Second transistor 721: Second channel structure 723: Second High-k Dielectric 724: Internal Metal Materials 725: External metal material, second gate structure 725a: Part 1 725b: Part II 727: Second Spacer Material 730: Cushion 731: First Pad Structure 731a: First Core Area 731b: First Peripheral Area 732: Second Pad Structure 732a: Second Core Area 732b: Second Peripheral Area 741: First Horizontal Contact Structure 741’: Horizontal Structure 750a: First Vertical Interconnect Structure 750b: First Vertical Interconnect Structure 751a: Metal parts 751b: Metal Parts 753a: Bottom section 753b: Bottom section 760a: Second Vertical Interconnect Structure 760b: Second Vertical Interconnect Structure 761a: Metal parts 761b: Metal Parts 763a: Bottom section 763b: Bottom section 770a: Third Vertical Interconnect Structure 770b: Third Vertical Interconnect Structure 771a: Top section 771b: Top section 773a: Bottom section 773b: Bottom section 780: First Common Vertical Interconnect Structure 781: First Common Vertical Interconnect Structure 783: First Common Vertical Interconnect Structure 790: Second Common Vertical Interconnect Structure 791: Second Common Vertical Interconnect Structure 793: First Common Vertical Interconnect Structure 800: Semiconductor Devices 801: Substrate 802: Deposition of insulating material 803: source and drain regions 805: Nanosheet, Second Dielectric Material 809:Mask 810: silicide, first transistor 811: First channel structure 813: The first high-k dielectric material 815: First gate structure 817: First Spacer Material 820: silicide, second transistor 821: Second channel structure 823: Second High-k Dielectric 825: Second gate structure 825a: Part 1 825b: Part II 827: Second Spacer Material 830: Cushion 831: First Pad Structure 831a: First Core Area 831b: First Peripheral Area 832: Second Pad Structure 832a: Second Core Area 832b: Second Peripheral Area 841: First Horizontal Contact Structure 841’: Horizontal Structure 850a: First Vertical Interconnect Structure 850b: First Vertical Interconnect Structure 851a: Metal parts 851b: Metal parts 853a: First Vertical Interconnect Structure 853b: First Vertical Interconnect Structure 855a: Opening 855b: Opening 870a: Third Vertical Interconnect Structure 870b: Third Vertical Interconnect Structure 871a: Metal parts 871b: Metal parts 873a: Third Vertical Interconnect Structure 873b: Third Vertical Interconnect Structure 880: Vertical Interconnect Structure 881: First Common Vertical Interconnect Structure 883: Third Vertical Interconnect Structure 883': first conductive material 885: Opening 900: Semiconductor Devices 910: Transition Dielectric Materials 1010: Dielectric Materials 1110: The third metal material 1124: Metal Materials 1310: Oxide 1320:Hard Mask 1410: etching mask, photoresist mask 1420: Opening 1510: Spacer Film 1520: Opening 1710: Dielectric Materials 1800: 3D semiconductor devices, CMOS inverters 1900: 3D semiconductor devices, CMOS inverters 2000: 3D semiconductor devices, CMOS inverters 2100: 3D Semiconductor Devices, CMOS Inverters 2200: Methods 2205: Steps 2210: Steps 2215: Steps 2220: Steps 2225: Steps 2230: Steps 2235: Steps 2240: Steps 2245: Steps 2250: Steps 2255: Steps 2260: Steps 2265: Steps 2270: Steps 2275: Steps 2280: Steps 2285: Steps 2290: Steps A: Section line A': section line B: Section line B': section line C: section line C': section line S401: Steps S402: Step S403: Step S404: Step S405: Step Vdd: Supply voltage Vin: input voltage Vout: output voltage Vss: ground voltage X: direction Y: direction Z: direction

A more complete understanding of the present invention and its many attendant advantages will become more readily obtained by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

1A is a cross-sectional substrate portion showing deposited layers of different dielectric types in accordance with an embodiment of the present invention.

1B is a cross-sectional substrate portion illustrating the formation of an etch mask to define openings in a layer stack, in accordance with an embodiment of the present invention.

1C is a cross-sectional substrate portion showing epitaxial growth of N+ channel material in an opening, in accordance with an embodiment of the present invention.

1D is a cross-sectional substrate portion illustrating formation of a second etch mask to define sidewall structures around vertical channels for epitaxial growth, in accordance with an embodiment of the present invention.

1E is a cross-sectional substrate portion showing an optional etch through an N+ silicon layer to isolate a device, in accordance with an embodiment of the present invention.

1F is a cross-sectional substrate portion showing growth or selective deposition of a third dielectric material on open substrate regions and N+ regions, in accordance with an embodiment of the present invention.

1G is a cross-sectional substrate portion showing removal of the second dielectric material according to an embodiment of the present invention.

1H is a cross-sectional substrate portion illustrating deposition of a selective high-K layer in the gate region in accordance with an embodiment of the present invention.

1I is a cross-sectional substrate portion showing a selective high-K annealing step to form interfacial oxide growth in the gate region in accordance with an embodiment of the present invention.

FIG. 1J is a cross-sectional substrate portion illustrating forming a metal gate electrode stack in accordance with an embodiment of the present invention.

1K is a cross-sectional substrate portion illustrating the directionally etched removal of gate stack material from the substrate, leaving gate stack material surrounding vertical channels to form a GAA device, in accordance with an embodiment of the present invention.

1L is a perspective view of an NMOS GAA device with gate, source and drain connected to metal contacts according to an embodiment of the present invention.

2A is a cross-sectional substrate portion showing deposited layers of different dielectric types in accordance with an embodiment of the present invention.

2B is a cross-sectional substrate portion illustrating the formation of an etch mask to define openings in a layer stack, in accordance with an embodiment of the present invention.

2C is a cross-sectional substrate portion showing epitaxial growth of P+ channel material in an opening, in accordance with an embodiment of the present invention.

2D is a cross-sectional substrate portion illustrating formation of a second etch mask to define sidewall structures surrounding vertical channels for epitaxial growth, in accordance with an embodiment of the present invention.

2E is a cross-sectional substrate portion showing an optional etch through the P+ silicon layer to isolate the device, in accordance with an embodiment of the present invention.

2F is a cross-sectional substrate portion showing growth or selective deposition of a third dielectric material on open substrate regions and P+ regions in accordance with an embodiment of the present invention.

2G is a cross-sectional substrate portion showing removal of the second dielectric material according to an embodiment of the present invention.

2H is a cross-sectional substrate portion illustrating deposition of a selective high-K layer in the gate region in accordance with an embodiment of the present invention.

2I is a cross-sectional substrate portion illustrating a selective high-K annealing step to form interfacial oxide growth in the gate region in accordance with an embodiment of the present invention.

2J is a cross-sectional substrate portion illustrating forming a metal gate electrode stack in accordance with an embodiment of the present invention.

2K is a cross-sectional substrate portion illustrating the directionally etched removal of gate stack material from the substrate, leaving gate stack material surrounding vertical channels to form a GAA device, in accordance with an embodiment of the present invention.

2L is a perspective view of a PMOS GAA device with gate, source, and drain connected to metal contacts according to an embodiment of the present invention.

3A is a cross-sectional substrate portion showing monocrystalline silicon on oxide-on-silicon substrate patterned on one side with a photomask and implanted with N+ doping on the other side, in accordance with an embodiment of the present invention.

3B is a cross-sectional substrate portion showing shading and P+ implant doping on the other side of the substrate layer in accordance with an embodiment of the present invention.

3C is a cross-sectional substrate portion showing an optional step of isolating doped semiconductor regions by masking and etching down to a dielectric oxide layer in accordance with an embodiment of the present invention.

3D is a cross-sectional substrate portion showing annealing of the implanted region followed by deposition of a first dielectric layer, a second dielectric layer, and a layer of a first dielectric material, in accordance with an embodiment of the present invention.

3E is a cross-sectional substrate portion showing patterning of a photoresist to define openings etched down to a doped layer in accordance with an embodiment of the present invention.

3F is a cross-sectional view of a portion of a substrate showing the formation of a third dielectric material in an opening, in accordance with an embodiment of the present invention.

3G is a cross-sectional substrate portion showing removal of a third dielectric material from an NMOS region in accordance with an embodiment of the present invention.

3H is a cross-sectional substrate portion showing epitaxial growth of N+ channel regions and protection of PMOS regions in accordance with an embodiment of the present invention.

3I is a cross-sectional substrate portion illustrating deposition of a protective film on the substrate in accordance with an embodiment of the present invention.

3J is a cross-sectional substrate portion showing removal of the protective film from the PMOS region in accordance with an embodiment of the present invention.

3K is a cross-sectional substrate portion illustrating epitaxial growth of P+ vertical channel material in accordance with an embodiment of the present invention.

3L is a cross-sectional substrate portion showing masking the PMOS and NMOS regions and etching the dielectric stack to form sidewall structures around vertical channels in accordance with an embodiment of the present invention.

3M is a cross-sectional substrate portion showing growth or selective deposition of a third dielectric material on open substrate regions and N+ and P+ regions, according to an embodiment of the present invention.

3N is a cross-sectional substrate portion showing removal of the second dielectric material without removing the first dielectric material or the third dielectric material to reveal a future gate electrode region, in accordance with an embodiment of the present invention.

3O is a cross-sectional substrate portion illustrating deposition of a high-K dielectric, annealing, and formation of interfacial oxide growth between the high-K deposit and vertical channels, in accordance with an embodiment of the present invention.

3P is a cross-sectional substrate portion showing forming a metal gate electrode stack in accordance with an embodiment of the present invention.

3Q is a cross-sectional substrate portion illustrating performing a directional etch to remove gate stack material from the substrate, leaving gate stack material surrounding vertical channels, in accordance with an embodiment of the present invention.

3R is a cross-sectional substrate portion according to an embodiment of the present invention.

3S is a cross-sectional substrate portion showing removal of a TiAl layer from a PMOS region in accordance with an embodiment of the present invention.

FIG. 3T is a cross-sectional substrate portion showing separations etched in the doped silicon layer to isolate lower source/drain regions in accordance with an embodiment of the present invention.

3U is a cross-sectional substrate portion showing deposition of a dielectric capping layer in accordance with an embodiment of the present invention.

3V is a perspective view of an NMOS device next to a PMOS device with gate, source, and drain connected to metal contacts in accordance with an embodiment of the present invention.

4-12A and 13-20 show cross-sectional views illustrating exemplary methods of fabricating 3D semiconductor devices in accordance with some embodiments of the present invention;

FIG. 12B shows a schematic diagram of the 3D semiconductor device of FIG. 9A;

Figure 21 shows a top view of a 3D semiconductor device according to some embodiments of the present invention;

22-24 illustrate top views of three different 3D semiconductor devices fabricated by methods according to various embodiments of the present invention; and

25 shows a flowchart of an exemplary method of fabricating a 3D semiconductor device in accordance with some embodiments of the present invention.

26A is a perspective view of a semiconductor device according to an exemplary embodiment of the present invention.

Figure 26B is a cross-sectional view taken along line AA' in Figure 26A, according to an exemplary embodiment of the present invention.

26C is a schematic top view of the semiconductor device of FIG. 26A according to an exemplary embodiment of the present invention.

27A, 27B, 27C, 27D, and 27E illustrate examples of routing designs according to some embodiments.

28A, 28B, 28C, and 28D illustrate examples of routing designs according to some embodiments.

29 shows a flowchart of an exemplary process for fabricating an exemplary semiconductor device in accordance with an embodiment of the present invention.

30A, 30B, 30C, 30D, 30E, 30F, 30G, 30G', and 30H are cross-sectional views of semiconductor devices at various intermediate steps of fabrication in accordance with exemplary embodiments of the present invention.

31A, 31B, and 31C are cross-sectional views of a semiconductor device at various intermediate steps of fabrication in accordance with exemplary embodiments of the present invention.

32A is a schematic top view of a semiconductor device according to an exemplary embodiment of the present invention.

32B and 32C are cross-sectional views taken along line BB' and CC' in FIG. 32A, respectively, according to an exemplary embodiment of the present invention.

32D is an equivalent circuit diagram of the semiconductor device of FIGS. 32A, 32B, and 32C according to an exemplary embodiment of the present invention.

33A, 33B, 33C, 33D, 33E, 33F, 33G, and 33H are cross-sectional views of semiconductor devices at various intermediate steps of fabrication in accordance with exemplary embodiments of the present invention.

34 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

302: Silicon

304: Dielectric layer, dielectric material, isolation layer

306: N+ Layer

322:P+layer

331: Separation

332N: Electrode

332P: Electrode

334N: Electrode

334P: Electrode

336N: Gate electrode

336P: Gate electrode

340:NMOS gate stack

342: Open, PMOS gate stack

Claims (62)

A method of microfabrication comprising: A dielectric layer stack is formed on a first layer of semiconductor material, the dielectric layer stack has at least three layers, wherein a first dielectric material is located below and above a second dielectric material, the first dielectric a material different from the second dielectric material such that the second dielectric material can be removed without removing the first dielectric material; forming openings in the dielectric layer stack such that the semiconductor material of the first layer is exposed; epitaxially growing channel material within the exposed openings to form vertical channels; removing a portion of the dielectric layer stack, leaving sidewall structures on the vertical channels; removing the second dielectric material from the sidewall structures to expose the sidewall surfaces of the vertical channels; and A gate structure is formed on the exposed sidewall surfaces of the vertical channels. The microfabrication method as claimed in claim 1, wherein the semiconductor material of the first layer is N-doped silicon or N-doped germanium. The microfabrication method as claimed in claim 1, wherein the semiconductor material of the first layer is P-doped silicon or P-doped germanium. The method of microfabrication of claim 1, wherein the semiconductor material of the first layer comprises a P-doped region adjacent to an N-doped region, wherein the N-doped vertical channel is above the N-doped region with a first exposed opening grown in the P-doped region, and wherein a P-doped vertical channel is grown in the second exposed opening over the P-doped region. The method for microfabrication as claimed in claim 4, further comprising: depositing a third dielectric material on the first layer of the first and second exposed openings; shielding the P-doped region of the first layer with a first photoresist mask; removing the third dielectric material from the N-doped region of the first layer; epitaxially growing N+ doped material over the N-doped region; removing the first photoresist mask; depositing a protective film over the dielectric layer stack, the N+ doped material and the third dielectric material; removing the protective film from the third dielectric material; and P+ doped material is epitaxially grown in the second exposed opening over the third dielectric material. The method of microfabrication of claim 1, further comprising forming a local interconnect to the gate structure of each vertical channel configured to conduct operation perpendicular to one of the semiconductor materials of the first layer surface current. The method of microfabrication of claim 1, further comprising removing a portion of the semiconductor material of the first layer between the vertical channels. The method of microfabrication of claim 1, wherein the openings formed in the dielectric layer stack have circular or rectangular cross-sections. The method of microfabrication of claim 1, wherein the semiconductor material of the first layer is formed on an underlying dielectric layer. The method of microfabrication of claim 1, wherein removing a portion of the dielectric layer stack comprises: shielding the vertical channels and a top of a sidewall area around each vertical channel; and The dielectric layer stack is etched down to the semiconductor material of the first layer. The method for microfabrication as claimed in claim 1, further comprising: forming the first layer on an underlying dielectric layer; shielding the dielectric layer stack; and The stack is separated by etching a portion of the stack down to the underlying dielectric layer before forming openings in the stack to expose the semiconductor material of the first layer. The method of microfabrication as claimed in claim 1, further comprising forming the gate structure in the following manner: depositing a selective high-K material within the exposed sidewall surfaces of the vertical channels; annealing; forming an interface oxide between the selective high-K material and the vertical channels; depositing a metal gate electrode stack on the vertical channels, sidewall surfaces and selective high-K material; and The metal gate electrode stack is removed from the vertical channels and sidewall surfaces. The method of microfabrication of claim 12, wherein depositing a metal gate electrode stack comprises: depositing a first metal material on the selective high-K material; depositing a second metal material on the first metal material; and A third metal material is deposited on the second metal material. The method of microfabrication of claim 13, wherein the first, second and third metal materials are different metals. The microfabrication method of claim 14, wherein the first metal material is titanium nitride, the second metal material is tantalum nitride, and the third metal material is titanium aluminide. The method of microfabrication of claim 12, wherein depositing a metal gate electrode stack comprises: depositing a first layer of a first metal material on the high-K material; depositing a second layer of second metal material on the first layer of metal material; depositing a third layer of first metal material on the second layer of second metal material; depositing a fourth layer of second metal material on the third layer of first metal material; and A third metal material is deposited on the fourth layer of the second metal material. A semiconductor device comprising: a substrate layer; a layer of first dielectric material; a layer of semiconductor material; A dielectric layer stack having at least three layers, wherein the first dielectric material is located below and above a second dielectric material, the first dielectric material is different from the second dielectric material and can be removed without removing the second dielectric material in the presence of the first dielectric material; a first opening in the dielectric layer stack in which the layer of semiconductor material is exposed; vertical channels having epitaxially grown dopant material in the first openings; sidewall structures formed by second openings in the dielectric layer stack between the vertical channels; a third opening in the sidewall structures formed by removing the second dielectric material up to the vertical channel; gate structures in the third openings; and Local interconnects connected to the gate structure of each vertical channel configured to conduct current perpendicular to a working surface of the substrate layer. The semiconductor device of claim 17, wherein the layer of semiconductor material is N-doped silicon or N-doped germanium. The semiconductor device of claim 17, wherein the layer of semiconductor material is P-doped silicon or P-doped germanium. The semiconductor device of claim 17, wherein the layer of semiconductor material includes a P-doped region adjacent to an N-doped region, wherein an N-doped vertical channel is disposed in the first exposed opening over the N-doped region, and wherein A P-doped vertical channel is disposed in the second exposed opening above the P-doped region. A method of manufacturing a semiconductor device, comprising: forming a multi-layer stack on a substrate, the multi-layer stack including a plurality of layers of at least three different dielectric materials capable of being selectively etched relative to each other; forming at least one opening down through the multi-layer stack to the substrate such that the substrate is exposed; forming a first channel of a first semiconductor device of the semiconductor device vertically from the exposed substrate and a second channel of a second semiconductor device of the semiconductor device vertically formed from the first channel in the opening; removing a transition dielectric layer of the multilayer stack such that a portion of the first channel and the second channel that interface at the transition dielectric layer is exposed; and A silicide is formed at the exposed portion to couple the first channel to the second channel. The method of manufacturing a semiconductor device of claim 21, wherein the first and second semiconductor devices are of different types. The method of manufacturing a semiconductor device of claim 21, wherein the silicide is formed by: depositing silicide metal on the exposed portions of the first channel and the second channel; and The exposed portion of the first channel and the second channel is silicided with the silicide metal. The method of manufacturing a semiconductor device as claimed in claim 23, wherein the silicide metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), platinum (Pt) and nickel The group formed by (Ni). The method of manufacturing a semiconductor device of claim 21, wherein the opening has a rectangular or circular cross-section. The method for manufacturing a semiconductor device as claimed in claim 21, further comprising: The gate dielectric layers of the layers of the multilayer stack are removed and replaced with a gate material to form a first gate region of the first semiconductor device and a second gate region of the second semiconductor device. The method of manufacturing a semiconductor device of claim 26, wherein the first and second gate regions are formed by: removing the gate dielectric layers to reveal the first and second channels; forming a gate dielectric material on the exposed first and second channels; forming a first metal material on the gate dielectric material; forming a second metal material surrounded by the first metal material adjacent to the first channel; and A third metal material is formed surrounded by the first metal material adjacent to the second channel. The method of manufacturing a semiconductor device of claim 27, wherein at least one of the first and second metal materials comprises at least two different metal materials. The method of manufacturing a semiconductor device of claim 27, wherein the second and third metal materials comprise the same metal material. The method of fabricating a semiconductor device of claim 27, wherein forming a gate dielectric material includes forming a gate dielectric material over the first and second channels and the multilayer stack. The method for manufacturing a semiconductor device as claimed in claim 21, further comprising: forming an implant layer on the substrate, wherein the multi-layer stack is formed on the implant layer. The method of manufacturing a semiconductor device of claim 31, wherein a first channel of a first semiconductor device of the semiconductor device is vertically formed from the exposed substrate and a second channel of the semiconductor device is vertically formed from the first channel A second channel of the semiconductor device includes: epitaxially growing a first channel material from the implant layer to the transition dielectric layer within the opening to form the first channel; and A second channel material is epitaxially grown from the transition dielectric layer within the opening to the top of the multilayer stack to form the second channel. The method of manufacturing a semiconductor device of claim 32, wherein the first channel material and the implant layer are doped with the same type of dopant. The method for manufacturing a semiconductor device as claimed in claim 21, further comprising: A fourth metal material is formed on the silicide. The method for manufacturing a semiconductor device as claimed in claim 21, further comprising: forming a silicide on the multilayer stack; and A fifth metal material is formed on the silicide. The method for manufacturing a semiconductor device as claimed in claim 21, further comprising: removing the second source/drain (S/D) dielectric layer of the layers of the multi-layer stack and replacing it with a second S/D material to form a second S/D region of the second semiconductor device; and The first source/drain (S/D) dielectric layer of the layers of the multi-layer stack is removed and replaced with a first S/D material to form a first S/D region of the first semiconductor device. The method of fabricating a semiconductor device of claim 36, wherein the second S/D dielectric layers are selectively etchable relative to the first S/D dielectric layer. The method for manufacturing a semiconductor device as claimed in claim 21, further comprising: etching the multi-layer stack to define sidewall structures of the multi-layer stack surrounding the first and second channels, wherein removing one of the transition dielectric layers of the layers of the multi-layer stack includes removing one of the transition dielectric layers of the sidewall structures of the layers of the multi-layer stack. A semiconductor device comprising: A first semiconductor device including first S/D regions, a first gate region sandwiched between the first S/D regions, and a first S/D region and the first the gate region surrounds a first channel; a second semiconductor device stacked on the first semiconductor device, comprising a second S/D region, a second gate region sandwiched between the second S/D regions, and Two S/D regions and the second gate region surround and in-situ form a second channel vertically on the first channel; and A silicide formed between the first semiconductor device and the second semiconductor device, where the first channel and the second channel interface, and the silicide is coupled to the first S of the first semiconductor device The upper of the /D region and the lower of the second S/D regions of the second semiconductor device. The semiconductor apparatus of claim 39, wherein the first semiconductor device and the second semiconductor device are of different types. The semiconductor device of claim 39, wherein the first gate region includes a first metal material and a second metal material surrounded by the first metal material, and the second gate region includes the first metal material and a third metal material surrounded by the first metal material. The semiconductor device of claim 41, wherein the second and third metal materials comprise the same metal material. A method of microfabrication comprising: forming a pad layer over a substrate, the pad layer including at least one pad structure having a core region surrounded by a peripheral region; A transistor is formed over the core region of the pad structure, the transistor including a channel structure extending in a vertical direction and a gate structure around a sidewall portion of the channel structure, the channel structure having a vertical channel region and a source region and a drain region on opposite ends of the vertical channel region, the channel structure configured to be electrically coupled to the pad structure; forming a first vertical interconnect structure that contacts a top surface of the channel structure; forming a second vertical interconnect structure that contacts the peripheral region of the pad structure and is configured to couple to a bottom surface of the channel structure through the pad structure; and A third vertical interconnect structure is formed, which is disposed away from the channel structure and contacts the gate structure of the transistor. The method for microfabrication as claimed in claim 43, wherein after forming the transistor above the core region of the pad structure, the method further comprises: An insulating material is deposited over the pad to fill the space and cover the transistor. The method of microfabrication of claim 44, wherein forming the first vertical interconnect structure comprises: forming an opening in the insulating material, the opening exposing the top surface of the channel structure; and The opening is filled with a conductive material. The method of microfabrication of claim 44, wherein forming the second vertical interconnect structure comprises: forming an opening in the insulating material, the opening exposing the peripheral region of the pad structure; and The opening is filled with a conductive material. The method of microfabrication of claim 44, wherein forming the third vertical interconnect structure comprises: forming an opening in the insulating material, the opening exposing the gate structure; and The opening is filled with a conductive material. The method of microfabrication as claimed in claim 44, wherein before depositing the insulating material above the underlayer, the method further comprises: depositing a first conductive material surrounding the transistor and contacting the gate structure; and Based on a mask, the first conductive material is etched so that the first conductive material covers a sidewall portion of the transistor and contacts a sidewall portion of the gate structure. The method of microfabrication of claim 48, wherein forming the third vertical interconnect structure further comprises: forming an opening in the insulating material, the opening exposing the first conductive material; and The opening is filled with a second conductive material disposed above the first conductive material. The method of microfabrication of claim 43, further comprising forming a fourth vertical interconnect structure contacting the peripheral region of the pad structure or the gate structure of the transistor. A method of microfabrication comprising: forming a pad layer over a substrate, the pad layer comprising a first pad structure and a second pad structure adjacent to and in contact with the first pad structure; A transistor is formed over the first and second pad structures, the transistor including a channel structure extending in a vertical direction and a gate structure around a sidewall portion of the channel structure, the channel structure having a vertical a channel region and a source region and a drain region on opposite ends of the vertical channel region, the channel structure configured to be electrically coupled to a corresponding pad structure disposed below the channel structure and extending horizontally beyond the channel the periphery of one of the structures; forming a first vertical interconnect structure contacting a first top surface of a first channel structure of a first transistor disposed above the first pad structure; forming a second vertical interconnect structure contacting a second top surface of a second channel structure of a second transistor disposed above the second pad structure; forming a first common vertical interconnect structure configured to couple to a first gate structure of the first transistor and a second gate structure of the second transistor; and A second common vertical interconnect structure is formed in contact with the first pad structure and the second pad structure. The method of microfabrication of claim 51, wherein after forming the transistors over the first and second pad structures, the method further comprises: forming a first horizontal contact structure and a second horizontal contact structure, the first horizontal contact structure and the second horizontal contact structure both contact the first pad structure and the second pad structure; depositing a dielectric material over the first horizontal contact structure; depositing a first conductive material over the dielectric material to connect the first gate structure and the second gate structure; and An insulating material is deposited over the pad to fill the spaces and cover the transistors. The method of microfabrication of claim 52, wherein: Forming the first vertical interconnect structure is accomplished by forming a first opening in the insulating material and filling the first opening with a second conductive material, the first opening exposing the first top surface of the first channel structure , Forming the second vertical interconnect structure is accomplished by forming a second opening in the insulating material and filling the second opening with a third conductive material, the second opening exposing the second top surface of the second channel structure , forming the first common vertical interconnect structure is accomplished by forming a third opening in the insulating material and filling the third opening with a fourth conductive material, the third opening exposing the first conductive material, and Forming the second common vertical interconnect structure is accomplished by forming a fourth opening in the insulating material and filling the fourth opening with a fifth conductive material, the fourth opening exposing the second horizontal contact structure. A semiconductor device comprising: a cushion layer including at least one cushion structure having a core region and a peripheral region surrounding the core region; a transistor, above the core region of the pad structure, the transistor including a channel structure extending in a vertical direction and a gate structure around a sidewall portion of the channel structure, the channel structure having a vertical channel region and a source region and a drain region on opposite ends of the vertical channel region, the channel structure configured to be electrically coupled to the pad structure; a first vertical interconnect structure contacting a top surface of the channel structure; a second vertical interconnect structure contacting the peripheral region and configured to couple to a bottom surface of the channel structure through the pad structure; and A third vertical interconnect structure is disposed away from the channel structure and contacts the gate structure of the transistor. The semiconductor device of claim 54, further comprising a fourth vertical interconnect structure contacting the peripheral region of the pad structure or the gate structure of the transistor. The semiconductor device of claim 54, wherein the channel structure is located at a center of the pad structure or is offset from the center of the pad structure. The semiconductor device of claim 54, wherein: The second vertical interconnect structure and the third vertical interconnect structure are located at the same radial position or at different radial positions from the channel structure, and The second vertical interconnect structure and the third vertical interconnect structure are located at the same distance or different distances from the channel structure. The semiconductor device of claim 54, wherein a particular transistor over a particular pad structure is the same or different from an adjacent transistor over an adjacent pad structure. The semiconductor device of claim 54, wherein one or more of the at least one pad structures are separated from each other by a dielectric material. The semiconductor device of claim 54, wherein: The at least one pad structure includes a first pad structure and a second pad structure adjacent to and in contact with the first pad structure, The third vertical interconnect structure over the first pad structure and the third vertical interconnect structure over the second pad structure are chemically identical and contact each other to integrally form a first common vertical interconnect structure, and The second vertical interconnect structure over the first pad structure and the second vertical interconnect structure over the second pad structure are chemically identical and contact each other to integrally form a second common vertical interconnect structure. The semiconductor device of claim 60, wherein: The first common vertical interconnect structure contacts a first gate structure of a first transistor disposed above the first pad structure and a second gate structure of a second transistor disposed above the second pad structure pole structure, and The second common vertical interconnect structure contacts the first pad structure and the second pad structure. The semiconductor device of claim 61, further comprising: a horizontal contact structure contacting the first pad structure and the second pad structure, the horizontal contact structure disposed below the first common vertical interconnect structure; and A dielectric material separating the horizontal contact structure from the first common vertical interconnect structure.

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