TW202207381A - Copper base substrate - Google Patents
Copper base substrate Download PDFInfo
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- TW202207381A TW202207381A TW110111517A TW110111517A TW202207381A TW 202207381 A TW202207381 A TW 202207381A TW 110111517 A TW110111517 A TW 110111517A TW 110111517 A TW110111517 A TW 110111517A TW 202207381 A TW202207381 A TW 202207381A
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- insulating layer
- copper
- base substrate
- substrate
- copper base
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- 239000000758 substrate Substances 0.000 title claims abstract description 113
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 97
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 89
- 239000010949 copper Substances 0.000 title claims abstract description 89
- 239000011256 inorganic filler Substances 0.000 claims description 33
- 229910003475 inorganic filler Inorganic materials 0.000 claims description 33
- 239000002245 particle Substances 0.000 claims description 33
- 239000011347 resin Substances 0.000 claims description 29
- 229920005989 resin Polymers 0.000 claims description 29
- 239000011888 foil Substances 0.000 claims description 16
- 229920001721 polyimide Polymers 0.000 claims description 12
- 239000009719 polyimide resin Substances 0.000 claims description 9
- 239000011889 copper foil Substances 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 8
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910000838 Al alloy Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 136
- 238000010438 heat treatment Methods 0.000 description 32
- 238000001816 cooling Methods 0.000 description 24
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 21
- 229910000679 solder Inorganic materials 0.000 description 17
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 13
- 238000000576 coating method Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 12
- 239000011248 coating agent Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 239000011247 coating layer Substances 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000004070 electrodeposition Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000002788 crimping Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000011342 resin composition Substances 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 238000007611 bar coating method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- -1 copper Chemical class 0.000 description 1
- 238000007607 die coating method Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002659 electrodeposit Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007756 gravure coating Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000011164 primary particle Substances 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000010345 tape casting Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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Abstract
Description
本發明係有關銅基底基板。 本發明係根據於2020年3月13日,日本申請之日本特願2020-065163號主張優先權,將此內容援用於此。The present invention relates to a copper base substrate. The present invention claims priority based on Japanese Patent Application No. 2020-065163 filed on March 13, 2020, the content of which is incorporated herein by reference.
做為用以安裝半導體元件或LED等之電子零件之基板之一種,已知有金屬基材基板。金屬基材基板係將金屬基板、和絕緣層、和電路層以此順序層積之層積體。絕緣層係一般而言,由包含絕緣性或耐電壓性優異之樹脂、和熱傳導性優異之無機物填料之絕緣性組成物所形成。電子零件係於電路層之上,藉由銲錫加以安裝。如此構成之金屬基材基板中,於電子零件所產生之熱係隔著絕緣層,傳達至金屬基板,從金屬基板散熱至外部。A metal base substrate is known as one of the substrates for mounting electronic components such as semiconductor elements and LEDs. The metal base substrate is a laminate in which a metal substrate, an insulating layer, and a circuit layer are laminated in this order. The insulating layer is generally formed of an insulating composition containing a resin having excellent insulating properties or withstand voltage and an inorganic filler having excellent thermal conductivity. Electronic components are mounted on the circuit layer by soldering. In the metal base substrate thus constituted, the heat generated by the electronic components is transmitted to the metal substrate through the insulating layer, and is dissipated from the metal substrate to the outside.
金屬基材基板中,金屬基材基板、和於該金屬基材基板藉由銲錫接合之電子零件之熱膨脹率之差異大時,經由電子零件之開/關或外部環境所造成冷熱周期,在於接合電子零件與金屬基材基板之電路層之銲錫,賦予之應力會變大,因而有產生銲錫龜裂之情形。為此,有使金屬基材基板之絕緣層之彈性率變低,將經由金屬基材基板之金屬基板與電子零件之熱膨脹率之差,以絕緣層加以緩和之檢討方案(專利文獻1、2)。 [先前技術文獻] [專利文獻]Among the metal substrate substrates, when the thermal expansion rate of the metal substrate substrate and the electronic components joined by soldering on the metal substrate substrate is greatly different, the cooling and heating cycles caused by the opening/closing of the electronic components or the external environment are used in the bonding. The stress imparted by the soldering of the circuit layer of electronic components and metal substrate substrates will increase, so that solder cracks may occur. For this reason, there is a review plan to reduce the elastic modulus of the insulating layer of the metal base substrate, and to reduce the difference in thermal expansion coefficient between the metal substrate and the electronic component via the metal base substrate with the insulating layer (Patent Documents 1 and 2). ). [Prior Art Literature] [Patent Literature]
[專利文獻1]日本特開平11-87866號公報 [專利文獻2]日本特開2016-111171號公報[Patent Document 1] Japanese Patent Application Laid-Open No. 11-87866 [Patent Document 2] Japanese Patent Laid-Open No. 2016-111171
[發明欲解決之課題][The problem to be solved by the invention]
抑制安裝電子零件時之冷熱周期所造成銲錫龜裂之產生,為提升對於冷熱周期之可靠性,經由降低金屬基材基板之絕緣層之彈性率,易於變形絕緣層,有效緩和金屬基材之膨脹所造成之熱應力。但是,存在電路層之膨脹所造成對銲錫之應力之故,僅降低金屬基材基板之絕緣層之彈性率,提升對於冷熱周期之可靠性上有其極限。Suppresses the generation of solder cracks caused by the cooling and heating cycle when installing electronic components. In order to improve the reliability of the cooling and heating cycle, by reducing the elastic modulus of the insulating layer of the metal substrate substrate, it is easy to deform the insulating layer and effectively alleviate the expansion of the metal substrate. caused by thermal stress. However, due to the stress on the solder caused by the expansion of the circuit layer, only the elastic modulus of the insulating layer of the metal base substrate is reduced, and there is a limit to improving the reliability of the cooling and heating cycle.
本發明係有鑑於上述情事而成,提供安裝電子零件時之對於冷熱周期之可靠性優異之金屬基材基板為目的。 [為解決課題之手段]The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a metal base substrate excellent in reliability with respect to a cooling and heating cycle when mounting electronic components. [Means for solving problems]
為解決上述課題,本發明之金屬基材基板係銅基板、和絕緣膜、和電路層以此順序層積之銅基底基板中,前述絕緣層係對於100℃之彈性率(單位:GPa)之厚度(單位:μm)之比為50以上,前記電路層係100℃之彈性率為100GPa以下為特徵。In order to solve the above-mentioned problems, the metal base substrate of the present invention is a copper base substrate in which a copper substrate, an insulating film, and a circuit layer are laminated in this order, wherein the insulating layer is a ratio of the elastic modulus (unit: GPa) to 100°C. The ratio of the thickness (unit: μm) is 50 or more, and the elastic modulus of the circuit layer at 100° C. mentioned above is 100 GPa or less.
根據本發明之銅基底基板時,絕緣層係對於100℃之彈性率(單位:GPa)之厚度(單位:μm)之比為大到50以上之故,絕緣層則易於變形,可將冷熱周期所造成金屬基板與電子零件之熱膨脹率之差,以絕緣層加以緩和。又,電路層係100℃之彈性率低至100GPa以下故,可使冷熱周期所造成電路層與電子零件之熱膨脹率之差變小。因此,經由冷熱周期,可使賦予接合電子零件與銅基底基板之電路層之銲錫之應力變小。因此,本發明之銅基底基板係提升安裝電子零件時之對於冷熱周期之可靠性。According to the copper base substrate of the present invention, since the ratio of the thickness (unit: μm) of the insulating layer to the modulus of elasticity (unit: GPa) at 100° C. is greater than 50, the insulating layer is easily deformed, and the cycle of cooling and heating can be changed. The resulting difference in thermal expansion between the metal substrate and the electronic components is mitigated by an insulating layer. In addition, since the elastic modulus of the circuit layer at 100°C is as low as 100GPa or less, the difference between the thermal expansion coefficients of the circuit layer and the electronic components caused by the cycle of cooling and heating can be reduced. Therefore, through the cycle of cooling and heating, the stress applied to the solder of the circuit layer that joins the electronic component and the copper base substrate can be reduced. Therefore, the copper base substrate of the present invention improves the reliability of the cooling and heating cycles when mounting electronic components.
在此,於本發明之銅基底基板中,前述絕緣層係可包含聚醯亞胺樹脂、聚醯胺醯亞胺樹脂、或此等之混合物之樹脂。 此時,絕緣層包含此等之樹脂之故,提升銅基底基板之絕緣性、耐電壓性、化學承受性及機械特性。Here, in the copper base substrate of the present invention, the insulating layer may include polyimide resin, polyimide resin, or a mixture of these resins. At this time, since the insulating layer contains these resins, the insulating properties, voltage resistance, chemical resistance and mechanical properties of the copper base substrate are improved.
又,本發明之銅基底基板中,前述絕緣層係包含無機物填料,前述無機物填料之平均粒子徑可為0.1μm以上20μm以下之範圍內, 此時,絕緣層包含上述之無機物填料之故,提升銅基底基板之熱傳導性和耐電壓性。In addition, in the copper base substrate of the present invention, the insulating layer contains an inorganic filler, and the average particle size of the inorganic filler can be in the range of 0.1 μm or more and 20 μm or less. At this time, since the insulating layer contains the above-mentioned inorganic filler, the thermal conductivity and withstand voltage of the copper base substrate are improved.
又,本發明之銅基底基板中,前述電路層可由銅箔、銅合金箔、鋁箔或鋁合金箔所成者。 此時,電路層由銅箔、銅合金箔、鋁箔或鋁合金箔所成之故,由於導電度高,可使電路層變薄。 [發明效果]Furthermore, in the copper base substrate of the present invention, the circuit layer may be made of copper foil, copper alloy foil, aluminum foil, or aluminum alloy foil. At this time, since the circuit layer is made of copper foil, copper alloy foil, aluminum foil or aluminum alloy foil, the circuit layer can be thinned due to high conductivity. [Inventive effect]
根據本發明時,可提供安裝電子零件時之對於冷熱周期之可靠性優異之銅基底基板。According to the present invention, it is possible to provide a copper base substrate excellent in reliability with respect to cooling and heating cycles when mounting electronic components.
以下,對於本發明之一實施形態,參照附件圖面加以說明。
圖1係關於本發明之一實施形態之銅基底基板之概略剖面圖。
圖1中,銅基底基板10係將銅基板20、和絕緣層30、和電路層40以此順序層積之層積體。於銅基底基板10之電路層40之上,藉由銲錫50,安裝電子零件60之端子61。Hereinafter, an embodiment of the present invention will be described with reference to the attached drawings.
FIG. 1 is a schematic cross-sectional view of a copper base substrate according to an embodiment of the present invention.
In FIG. 1, the
銅基板20係成為銅基底基板10之基礎之構件。銅基板20係由銅或銅合金所成。The
絕緣層30係為絕緣銅基板20與和電路層40之層。絕緣層30係由包含絕緣性樹脂31與無機物填料32之絕緣性樹脂組成物組成物所形成。令絕緣層30由包含絕緣性高之絕緣性樹脂31、和熱傳導度高之無機物填料32之絕緣性樹脂組成物組成物所形成,可維持絕緣性下,更為減低由電路層40至銅基板20之銅基底基板10整體之熱阻抗。The
絕緣性樹脂31係包含聚醯亞胺樹脂、聚醯胺醯亞胺樹脂、或此等之混合物為佳。此等之樹脂係絕緣性、耐電壓性、化學承受性及機械特性等之特性優異之故,提升銅基底基板10之此等特性。The
無機物填料32係平均粒子徑為0.1μm以上20μm以下之範圍內為佳。藉由無機物填料32之平均粒子徑係0.1μm以上時,提升絕緣層30之熱傳導性。藉由無機物填料32之平均粒子徑係20μm以下時,提升絕緣層30之耐電壓性。又,無機物填料32之平均粒子徑為上述之範圍內時,無機物填料32難以形成凝聚粒子,於絕緣性樹脂31中易於均勻分散無機物填料32。無機物填料32不形成凝聚粒子,做為一次粒子或接近於此之微細之粒子,分散於絕緣性樹脂31時,絕緣層30之耐電壓性則提升。從提升絕緣層30之熱傳導性之觀點視之,無機物填料32之平均粒子徑係0.3μm以上20μm以下之範圍內為佳。The
絕緣層30之無機物填料32之含有量係50體積%以上85體積%以下之範圍內為佳。藉由無機物填料32之含有量為50體積%μm以上時,提升絕緣層30之熱傳導性。另一方面,藉由無機物填料32之含有量為85體積%μm以下時,提升絕緣層30之耐電壓性。又,無機物填料32之含有量在上述之範圍內時,易於絕緣性樹脂31中均勻分散無機物填料32。無機物填料32均勻分散於絕緣性樹脂31時,絕緣層30之機械性強度則提升。從提升絕緣層30之熱傳導性之觀點視之,無機物填料32之含有量係50體積%以上80體積%以下之範圍內為更佳。The content of the
做為無機物填料32,可使用氧化鋁(Al2
O3
)粒子、氧化鋁水合物粒子、氮化鋁(AlN)粒子、矽石(SiO2
)粒子、碳化矽(SiC)粒子、氧化鈦(TiO2
)粒子、氮化硼(BN)粒子等。此等之填料中,以氧化鋁粒子為佳。氧化鋁粒子係以α-氧化鋁粒子為更佳,α-氧化鋁粒子係對於真密度而言之敲緊密度之比(敲緊密度/真密度)為0.1以上為佳。敲緊密度/真密度係與絕緣層30中之α-氧化鋁粒子之填充密度相關,敲緊密度/真密度高時,可使絕緣層30中之α-氧化鋁粒子之填充密度變高。絕緣層30中之α-氧化鋁粒子之填充密度高時,絕緣層30中之α-氧化鋁粒子之間隔則變窄,於絕緣層30難以產生空洞(氣孔)。敲緊密度/真密度係在0.2以上0.9以下之範圍內為佳。又,α-氧化鋁係可為多結晶粒子,以單結晶粒子為更佳。As the
絕緣層30係對於100℃之彈性率(單位:GPa)之厚度(單位:μm)之比(厚度/彈性率)為50以上。絕緣層30之厚度/彈性率為高達50以上之故,絕緣層30易於變形,厚度方向之緩衝性變高。為此,絕緣層30係緩和冷熱周期所造成銅基板20與電路層40之熱膨脹率之差的作用則變高。絕緣層30之厚度/彈性率係50以上20000以下之範圍內為佳,50以上2000以下之範圍內為較佳,更佳為50以上200以下之範圍內。絕緣層30之100℃之彈性率係0.01GPa以上1GPa以下之範圍內為佳,更佳為0.01GPa以上0.1GPa以下之範圍內。又,絕緣層30之厚度係10μm以上200μm以下之範圍內為佳,更佳為50μm以上200μm以下之範圍內。The ratio (thickness/elastic modulus) of the insulating
電路層40係形成為電路圖案狀。於形成為該電路圖案狀之電路層40上,電子零件60之端子61藉由銲錫50等加以接合。做為電路層40之材料,可使用銅、銅合金、鋁、鋁合金、金等之金屬。電路層40係由銅箔、銅合金箔、鋁箔或鋁合金箔所成為佳。The
電路層40係100℃之彈性率成為100GPa以下故,可使冷熱周期所造成電路層40與電子零件60之熱膨脹率之差所造成附加於銲鍚之應力變小。電路層40之100℃之彈性率係50GPa以上100GPa以下之範圍內為佳。電路層40之厚度係20μm以上200μm以下之範圍內為佳。The elastic modulus of the
銅基底基板10之銅基板20、絕緣層30及電路層40之厚度之可例如如下加以測定。將銅基底基板10埋入樹脂,經由機械研磨,露出剖面。接著,將露出之銅基底基板之剖面,使用光學顯微鏡觀察,測定銅基板20、絕緣層30及電路層40之厚度。The thicknesses of the
銅基底基板10之銅基板20、絕緣層30及電路層40之彈性率係在100℃下測定之值。
銅基底基板10之銅基板20及電路層40之彈性率(拉伸彈性率)係可例如如下加以測定。將銅基底基板10之絕緣層30經由溶劑加以除去,分離銅基板20與電路層40。對於所得之銅基板20與電路層40,經由動態黏彈性測定,測定彈性率。銅基底基板10之絕緣層30之彈性率係可例如如下加以測定。將銅基底基板10之銅基板20與電路層40經由蝕刻加以除去,離析絕緣層30。對於所得之絕緣層30,經由動態黏彈性測定,測定彈性率。The elastic modulus of the
做為安裝於本實施形態之銅基底基板10之電子零件60之例,沒有特別之限制,可列舉半導體元件、電阻、電容器、石英振盪器等。做為半導體元件之例,可列舉MOSFET(Metal-oxide-semiconductor field effect transistor)、IGBT(Insulated Gate Bipolar Transistor)、LSI (Large Scale Integration)、LED(發光二極體)、LED晶片、LED-CSP(LED-Chip Size Package)。Examples of the
以下,對於關於本實施形態之銅基底基板10之製造方法加以說明。
關於本實施形態之銅基底基板10係例如可經由包含絕緣層形成工程、和電路層壓接工程之方法加以製造。Hereinafter, the manufacturing method of the copper base board|
絕緣層形成工程中,於銅基板20之上,形成絕緣層30,得附有絕緣層之銅基板。絕緣層30之厚度(單位:μm)係將彈性率測定用之絕緣層30,形成於銅基板20,測定所得絕緣層30之彈性率,設定厚度/彈性率為50以上之厚度。做為絕緣層30之形成方法,可使用塗佈法或電沉積法。In the insulating layer forming process, an insulating
塗佈法係將包含溶媒與絕緣性樹脂與無機物填料的塗佈液,塗佈於銅基板20之上,形成塗佈層,接著加熱塗佈層,得絕緣層30之方法。做為塗佈液,可使用包含溶解絕緣性樹脂之樹脂材料溶液、和分散於此樹脂材料溶液之無機物填料之無機物填料分散樹脂材料溶液。做為將塗佈液塗佈於基板之表面之方法,可使用旋塗法、棒塗法、刀塗法、輥塗法、刮刀塗佈法、模塗法、凹版塗佈法、浸泡式塗佈法等。The coating method is a method of coating a coating liquid containing a solvent, an insulating resin and an inorganic filler on the
電沉積法係於包含絕緣性樹脂粒子與無機物填料之電沉積液浸漬銅基板20,於基板之表面電沉積絕緣性樹脂粒子與無機物填料,形成電沉積膜,接著加熱所得電沉積膜,形成絕緣層30之方法。做為電沉積液,可使用於包含絕緣性樹脂材料溶液、和分散於該絕緣性樹脂溶液之無機物填料之無機物填料分散樹脂材料溶液,添加絕緣性樹脂材料之弱溶媒,將絕緣性樹脂做為粒子加以析出而調製者。The electrodeposition method is to immerse the
電路層壓接工程中,於附有絕緣層之銅基板之絕緣層30之上,層積金屬箔,邊加熱所得層積體,邊進行加壓,形成電路層40,得銅基底基板10。層積體之加熱溫度係例如200℃以上,更佳為250℃以上。加熱溫度之上限係不足絕緣性樹脂之熱分解溫度,較佳為較熱分解溫度低30℃之溫度以下。壓接時施加之壓力係係1MPa以上30MPa以下之範圍內,更佳為3MPa以上25MPa以下之範圍內。壓接時間係會因為加熱溫度或壓力而有所不同,一般而言為10分鐘以上180分鐘以下。In the circuit lamination process, metal foil is laminated on the insulating
根據如以上構成之本實施形態之銅基底基板10時,絕緣層30係對於100℃之彈性率(單位:GPa)之厚度(單位:μm)之比為大到50以上之故,絕緣層30則易於變形,可將冷熱周期所造成銅基板20與電路層40之熱膨脹率之差,以絕緣層30加以緩和。又,電路層40係100℃之彈性率低至100GPa以下故,可使冷熱周期所造成電路層40與電子零件60之熱膨脹率之差變小。因此,經由冷熱周期,可使賦予接合電子零件60與銅基底基板10之電路層40之銲錫50之應力變小。因此,本實施形態之銅基底基板10係提升安裝電子零件60時之對於冷熱周期之可靠性。According to the
又,本實施形態之銅基底基板10中,絕緣層30包含聚醯亞胺樹脂、聚醯胺醯亞胺樹脂、或此等混合物之時,提升銅基底基板10之絕緣性、耐電壓性、化學承受性及機械特性。更且,絕緣層30係包含無機物填料32,無機物填料32之平均粒子徑在0.1μm以上20μm以下之範圍內時,銅基底基板10之熱傳導性與耐電壓性則提升。又,更且,電路層40由銅箔、銅合金箔、鋁箔或鋁合金箔所成之時,由於導電度高,可使電路層40的厚度變薄。In addition, in the
以上,雖對於本發明的實施形態做了說明,但本發明非限定於此,在不脫離該發明之技術思想之範圍下,可適切加以變更。 [實施例]The embodiments of the present invention have been described above, but the present invention is not limited thereto, and changes can be appropriately made without departing from the technical idea of the invention. [Example]
[本發明例1] 令溶媒可溶性聚醯亞胺溶液與α-氧化鋁粉末(結晶構造:單結晶,平均粒子徑:0.7μm),使經由加熱生成之固形物(絕緣層)中之聚醯亞胺與α-氧化鋁粉末之含有比率成為65體積%加以混合。於所得混合物,添加溶媒,使聚醯亞胺之濃度成為5質量%加以稀釋。接著將所得稀釋混合物,使用速技能機械股份有限公司製Star Burst,經由10次重覆壓力50MPa之高壓噴射處理,進行分散處理,調製絕緣層形成用之塗佈液。[Example 1 of the present invention] Solvent-soluble polyimide solution and α-alumina powder (crystal structure: single crystal, average particle diameter: 0.7 μm), polyimide and α-oxidation in the solid (insulating layer) generated by heating The content ratio of the aluminum powder was 65% by volume and mixed. A solvent was added to the obtained mixture so that the concentration of polyimide was 5% by mass and diluted. Next, the obtained diluted mixture was subjected to a dispersion treatment by repeating 10 times of high-pressure spray treatment at a pressure of 50 MPa using a Star Burst manufactured by Sugino Machinery Co., Ltd. to prepare a coating liquid for forming an insulating layer.
準備厚度1000μm縱30mm×橫20mm之銅基板(組成:C1100、韌煉銅)。於此銅基板之表面,將絕緣層形成用之塗佈液,經由棒塗法加以塗佈,形成塗佈層。接著,將形成塗佈層之銅基板,配置於加熱板上,從室溫,以3℃/分,昇溫至60℃,在60℃下加熱100分鐘後,更以1℃/分,昇溫至120℃,在120℃下加熱100分鐘,乾燥塗佈層。接著,將銅基板在250℃下加熱1分鐘後,在400℃下加熱1分鐘。如此,於表面,製作形成由分散α-氧化鋁單結晶粒子之聚醯亞胺樹脂所成絕緣層的附有絕緣膜之銅基板。然而,絕緣層之厚度為30μm,100℃之彈性率係0.27GPa,令厚度/彈性率成為110。A copper substrate (composition: C1100, tough copper) having a thickness of 1000 μm and a length of 30 mm x a width of 20 mm was prepared. On the surface of the copper substrate, a coating liquid for forming an insulating layer is applied by a bar coating method to form a coating layer. Next, the copper substrate on which the coating layer was formed was placed on a hot plate, and the temperature was raised from room temperature to 60°C at 3°C/min. After heating at 60°C for 100 minutes, the temperature was further increased to 1°C/min. The coating layer was dried by heating at 120°C for 100 minutes. Next, after heating the copper substrate at 250° C. for 1 minute, it was heated at 400° C. for 1 minute. In this way, on the surface, an insulating film-attached copper substrate in which an insulating layer made of a polyimide resin in which α-alumina single crystal particles are dispersed was formed was produced. However, the thickness of the insulating layer is 30 μm, the elastic modulus at 100° C. is 0.27 GPa, and the thickness/elastic modulus is 110.
於所得附有絕緣層之銅基板之絕緣膜之上,重疊層積厚70μm之銅箔(100℃之彈性率:75GPa,JX金屬股份有限公司製GHY5-HA-V2)。接著,將所得層積體,使用碳治具,邊賦予5MPa之壓力下,在真空中、以300℃之壓接溫度加熱120分鐘,壓接絕緣層與銅箔。如此,製作銅基板和絕緣層和銅箔以此順序層積之銅基底基板。On the insulating film of the obtained copper substrate with an insulating layer, a copper foil with a thickness of 70 μm (elastic modulus at 100° C.: 75 GPa, GHY5-HA-V2 manufactured by JX Metals Co., Ltd.) was laminated. Next, using a carbon jig, the obtained laminate was heated in a vacuum at a pressure-bonding temperature of 300° C. for 120 minutes while applying a pressure of 5 MPa, and the insulating layer and the copper foil were pressure-bonded. In this way, a copper base substrate in which a copper substrate and an insulating layer and a copper foil are laminated in this order is produced.
[本發明例2~4、比較例1~2] 將絕緣層之厚度與彈性率、電路層之彈性率,各別改變成下述表1記載之值以外,與本發明例1相同,製作銅基底基板。[Examples 2 to 4 of the present invention, Comparative Examples 1 to 2] A copper base substrate was produced in the same manner as in Example 1 of the present invention, except that the thickness and elastic modulus of the insulating layer and the elastic modulus of the circuit layer were changed to the values described in Table 1 below.
[評估] 對於本發明例1~4及比較例1~2所得銅基底基板,將對於冷熱周期可靠性,經由下述方法加以評估。將其結果示於表1。[evaluate] With respect to the copper base substrates obtained in Examples 1 to 4 of the present invention and Comparative Examples 1 to 2, the reliability of the cooling and heating cycle was evaluated by the following method. The results are shown in Table 1.
(對於銅基底基板之冷熱周期可靠性) 於銅基底基板之電路層上,塗佈Sn-Ag-Cu銲錫,形成縱2.5cm×橫2.5cm×厚度100μm之銲錫層,於該銲錫層之上,搭載2.5cm平方之Si晶片,製作試驗體。於製作之試驗體,將1周期為-40℃×30分鐘~150℃×30分鐘之冷熱周期,賦予3000周期。將賦予冷熱周期後之試驗體,埋入樹脂,使用經由研磨露出剖面之試料加以觀察,於銲錫層,令不產生長5mm以上之龜裂者為「〇」,產生長5mm以上之龜裂者為「×」。(Cold/hot cycle reliability for copper base substrates) On the circuit layer of the copper base substrate, apply Sn-Ag-Cu solder to form a solder layer with a length of 2.5cm × a width of 2.5cm × a thickness of 100μm. On the solder layer, a 2.5cm square Si wafer is mounted to make a test. body. For the produced test body, 3000 cycles were assigned to one cycle of cooling and heating cycles of -40°C x 30 minutes to 150°C x 30 minutes. The test body after applying the cooling and heating cycle is embedded in the resin, and the sample whose cross section is exposed by grinding is used to observe it. In the solder layer, those with a length of 5 mm or more are designated as "0", and those with a length of 5 mm or more are generated. "X".
對於絕緣層之彈性率(單位:GPa)之厚度(單位:μm)之比(厚度/彈性率)、和電路層之彈性率在本發明之範圍內之本發明例1~4之銅基底基板係確認到對於冷熱周期之可靠性優異。此係,經由絕緣層之厚度/彈性率在本發明之範圍內,冷熱周期所造成銅基板與電子零件之熱膨脹率之差,可經由絕緣層加以緩和之緣故。又,經由電路層之彈性率在本發明之範圍內,可使電路層與電子零件之熱膨脹率之差賦予銲錫之熱應力變小。The ratio (thickness/elasticity) of the elastic modulus (unit: GPa) of the insulating layer to the thickness (unit: μm) and the elastic modulus of the circuit layer are within the scope of the present invention for the copper base substrates of Examples 1 to 4 of the present invention It was confirmed that the reliability with respect to the cooling and heating cycle was excellent. This is because the thickness/elastic modulus of the insulating layer is within the scope of the present invention, and the difference in thermal expansion rate between the copper substrate and the electronic components caused by the cooling and heating cycle can be alleviated by the insulating layer. In addition, the thermal stress imparted to the solder due to the difference in thermal expansion coefficient between the circuit layer and the electronic component can be reduced through the elastic modulus of the circuit layer within the scope of the present invention.
相較於此,絕緣層之彈性率厚度/彈性率雖在本發明之範圍內,但電路層之彈性率超過本發明之範圍之比較例1之銅基底基板係對於冷熱周期之可靠性則下降。此係,經由電路層之彈性率超過本發明之範圍,使得電路層與電子零件之熱膨脹率之差賦予銲錫之熱應力變大之緣故。Compared with this, although the elastic modulus thickness/elastic modulus of the insulating layer is within the scope of the present invention, the copper base substrate of Comparative Example 1 in which the elastic modulus of the circuit layer exceeds the scope of the present invention is less reliable for cooling and heating cycles . This is because the thermal stress imparted to the solder due to the difference in thermal expansion coefficients between the circuit layer and the electronic component increases due to the fact that the elastic modulus of the circuit layer exceeds the scope of the present invention.
又,電路層之彈性率雖在本發明之範圍內,但絕緣層之厚度/彈性率不足本發明之範圍之比較例2之銅基底基板係對於冷熱周期之可靠性則下降。此係,經由絕緣層之厚度/彈性率不足於本發明之範圍,不能充分緩和經由冷熱周期所造成銅基板與電路層之熱膨脹率之差賦予銲錫之熱應力。In addition, although the elastic modulus of the circuit layer is within the scope of the present invention, the copper base substrate of Comparative Example 2 in which the thickness/elastic modulus of the insulating layer is not within the scope of the present invention is less reliable for cooling and heating cycles. This is because the thickness/elastic modulus of the insulating layer is not within the scope of the present invention, and the thermal stress imparted to the solder by the difference in thermal expansion rate between the copper substrate and the circuit layer caused by the cooling and heating cycle cannot be sufficiently relieved.
10:銅基底基板 20:銅基板 30:絕緣層 31:絕緣性樹脂 32:無機物填料 40:電路層 50:銲錫 60:電子零件 61:端子10: Copper base substrate 20: Copper substrate 30: Insulation layer 31: Insulating resin 32: inorganic filler 40: circuit layer 50: Solder 60: Electronic Parts 61: Terminal
[圖1]關於本發明之一實施形態之銅基底基板之概略剖面圖。1 is a schematic cross-sectional view of a copper base substrate according to an embodiment of the present invention.
10:銅基底基板 10: Copper base substrate
20:銅基板 20: Copper substrate
30:絕緣層 30: Insulation layer
31:絕緣性樹脂 31: Insulating resin
32:無機物填料 32: inorganic filler
40:電路層 40: circuit layer
50:銲錫 50: Solder
60:電子零件 60: Electronic Parts
61:端子 61: Terminal
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