TW202205580A - Masking apparatus - Google Patents

Abstract

A method for bonding semiconductor substrates includes placing a die on a substrate and performing a heating process on the die and the substrate to bond the respective first connectors with the respective second connectors. Respective first connectors of a plurality of first connectors on the die contact respective second connectors of a plurality of second connectors on the substrate. The heating process includes placing a mask between a laser generator and the substrate and performing a laser shot. The mask includes a masking layer and a transparent layer. Portions of the masking layer are opaque. The laser passes through a first gap in the masking layer and through the transparent layer to heat a first portion of a top side of the die opposite the substrate.

Description

masking device

Embodiments of the present invention relate to a semiconductor device, and more particularly, to a masking device.

The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). To a large extent, the improvement in integration density comes from the continuous reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices increases, there is a great need for smaller and more inventive packaging techniques for semiconductor dies. An example of such a packaging system is Package-on-Package (PoP) technology. In a PoP device, the top semiconductor package is stacked on top of the bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB).

A masking device for performing a laser heating process according to an embodiment of the present invention includes a masking layer and a mounting layer. The masking layer includes a plurality of masking portions that are opaque to the reflow laser. The masking layer is located on the mounting layer, and the mounting layer is transparent to the reflow laser.

A method for bonding a semiconductor substrate according to an embodiment of the present invention includes the following steps: placing a die on the substrate, and a corresponding first connector among a plurality of first connectors on the die contacts the substrate a corresponding second connector among the plurality of second connectors; and performing a heating process on the die and the substrate to connect the corresponding first connector with the corresponding second connector combine. The heating process includes the following steps: placing a masking device between the laser generator and the substrate, the masking device including a masking layer and a transparent layer, a portion of the masking layer is opaque; and performing a first laser The laser is fired through a first gap in the masking layer and through the transparent layer to heat a first portion of the top side of the die opposite the substrate.

A method of forming a semiconductor device according to an embodiment of the present invention includes the steps of: aligning a first package element with a second package element, the first package element having a first conductive connection, and the second package element having a second package element a conductive connector, wherein the alignment brings the first conductive connector into physical contact with the second conductive connector; performing a first laser shot that strikes the first conductive connection the first encapsulation element opposite the piece, the first laser emission being shaped by passing through a first opening in the masking layer and through a first partially transparent portion of the masking layer adjacent to the first opening, The first laser emission reflows the first conductive connector and the second conductive connector.

The following disclosure provides many different embodiments or examples for implementing different features of embodiments of the invention. Specific examples of elements and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which the first feature is in direct contact Embodiments in which additional features may be formed between the feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, this disclosure may reuse reference numbers and/or letters in various instances. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper" and the like may be used herein. to illustrate the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, the first packaged component is bonded to the second packaged component by a laser assisted bonding (LAB) process. The first package element and the second package element may be, for example, wafers, and each includes a plurality of package regions. In the LAB process, the encapsulation areas of the encapsulated components are sequentially heated by a laser beam. A masking device including a masking layer and a transparent mounting layer is placed between the laser beam emitter and the top surface of the top package element. Masking means are used to confine the laser beam to heating specific encapsulation areas by allowing the laser emission to pass through openings in the masking layer and hit the targeted encapsulation area. The LAB process allows the first package element to be joined with the second package element by directly heating only the top package element. Indirect heating of bottom packaged components can be reduced, which can help reduce wafer warpage. Laser heating using different types of laser beams and different types of heating profiles obtained by moving the position of the masking device provides faster heating, which can be used to increase manufacturing throughput. Although an embodiment of a LAB process utilizing a multi-layer masking device is described with respect to the combination of two packaged components, any suitable substrate may be combined with the disclosed process and device, such as, for example, two wafers, two A die or a wafer and a die.

1-10 illustrate cross-sectional views of various intermediate steps during a process for forming a first package component 100, according to some embodiments. A first package area 100A and a second package area 100B are shown, and a first package 101 is formed in each of the package areas 100A and 100B (see FIG. 18 ). The first package 101 may also be referred to as an integrated fan-out (InFO) package.

In FIG. 1 , a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102 . The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer such that multiple packages may be formed on the carrier substrate 102 simultaneously. The release layer 104 may be formed of a polymer-based material, which may be removed together with the carrier substrate 102 from an overlying structure to be formed in a subsequent step. In some embodiments, the release layer 104 is an epoxy-based heat release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultra-violet (UV) glue, which loses its adhesive properties when exposed to UV light. The release layer 104 may be dispensed and cured as a liquid, may be a laminate film laminated to the carrier substrate 102, or the like. The top surface of the release layer 104 may be leveled and may have a high degree of planarity.

In FIG. 2 , a backside wiring structure 106 is formed on the release layer 104 . In the illustrated embodiment, the backside redistribution structure 106 includes a dielectric layer 108 , a metallization pattern 110 (sometimes referred to as a redistribution layer or redistribution trace), and a dielectric layer 112 . The backside wiring structure 106 is optional, and in some embodiments, only the dielectric layer 108 is formed.

A dielectric layer 108 is formed on the release layer 104 . The bottom surface of the dielectric layer 108 may be in contact with the top surface of the release layer 104 . In some embodiments, the dielectric layer 108 is formed of polymers such as polybenzoxazole (PBO), polyimide (polyimide), benzocyclobutene (BCB), and the like. In other embodiments, the dielectric layer 108 is formed of the following materials: nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (borosilicate glass) Glass, BSG), boron-doped phosphosilicate glass (boron-doped phosphosilicate glass, BPSG), etc.; or similar materials. The dielectric layer 108 may be formed by any acceptable deposition process such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof.

A metallization pattern 110 is formed on the dielectric layer 108 . As an example of forming the metallization pattern 110 , a seed layer is formed over the dielectric layer 108 . In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer overlying the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 110 . The patterning forms openings through the photoresist to expose the seed layer. Conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. Conductive materials may include metals such as copper, titanium, tungsten, aluminum, and the like. Next, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, eg, by using an acceptable etching process (eg, by wet etching or dry etching). The remainder of the seed layer and the conductive material form a metallization pattern 110 .

A dielectric layer 112 is formed on the metallization pattern 110 and the dielectric layer 108 . In some embodiments, the dielectric layer 112 is formed of a polymer that can be patterned using a lithography mask, such as a photosensitive material such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric layer 112 is formed of a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 112 may be formed by spin coating, lamination, CVD, similar processes, or a combination thereof. The dielectric layer 112 is then patterned to form openings 114 that expose portions of the metallization pattern 110 . The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photosensitive material, or by etching using, for example, anisotropic etch to proceed.

It should be understood that the backside wiring structure 106 may include any number of dielectric layers and metallization patterns. Additional dielectric layers and metallization patterns may be formed by repeating the processes used to form metallization patterns 110 and dielectric layers 112 . The metallization pattern may include conductive lines and vias. The vias may be formed during formation of the metallization pattern by forming a seed layer and conductive material of the metallization pattern in the openings of the underlying dielectric layer. The vias can thus interconnect and electrically couple various conductive lines.

In FIG. 3 , through vias 116 are formed in openings 114 that extend away from the topmost dielectric layer (eg, dielectric layer 112 in the illustrated embodiment) of the backside wiring structure 106 . As an example of forming vias 116 , a seed layer is formed over backside wiring structures 106 (eg, over dielectric layer 112 and portions of metallization pattern 110 exposed by openings 114 ). In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In certain embodiments, the seed layer includes a titanium layer and a copper layer overlying the titanium layer. The seed layer can be formed using, for example, PVD or the like. A photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the via hole. The patterning forms openings through the photoresist to expose the seed layer. Conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. Conductive materials may include metals such as copper, titanium, tungsten, aluminum, and the like. The photoresist and the portion of the seed layer over which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, eg, by using an acceptable etching process (eg, by wet etching or dry etching). The remainder of the seed layer and conductive material form vias 116 .

In FIG. 4 , the integrated circuit die 126 is bonded to the dielectric layer 112 by an adhesive 128 . The integrated circuit die 126 may be a logic die (eg, central processing unit, microcontroller, etc.), a memory die (eg, dynamic random access memory (DRAM)) die, static random access memory (SRAM) die, etc.), power management die (eg, power management integrated circuit (PMIC) die), radio frequency (radio frequency) , RF) die, sensor die, micro-electro-mechanical-system (MEMS) die, signal processing die (eg, digital signal processing (DSP) die), A front-end die (eg, an analog front-end (AFE) die), a similar die, or a combination thereof. Furthermore, in some embodiments, the integrated circuit dies 126 may be of different sizes (eg, different heights and/or surface areas), and in other embodiments, the integrated circuit dies 126 may be of the same size (eg, the same height and/or surface area).

Before bonding to the dielectric layer 112 , the integrated circuit die 126 may be processed according to a manufacturing process suitable for forming integrated circuits in the integrated circuit die 126 . For example, the integrated circuit dies 126 each include a semiconductor substrate 130, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs , AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates such as multilayer substrates or gradient substrates can also be used. Devices such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on semiconductor substrate 130 and may be formed by metallization, for example, in one or more dielectric layers on semiconductor substrate 130 The patterned interconnect structures 132 interconnect the devices to form integrated circuits.

The integrated circuit die 126 further includes pads 134 (eg, aluminum pads) for external connection. The pads 134 are located on what may be referred to as the respective active sides of the integrated circuit die 126 . The passivation film 136 is located on the integrated circuit die 126 and on portions of the pads 134 . The openings extend through passivation film 136 to pads 134 . Die connectors 138 , such as conductive pillars (eg, including a metal such as copper), extend through openings in passivation film 136 and are mechanically and electrically coupled to corresponding pads 134 . The die connectors 138 may be formed by, for example, plating or the like. The die connectors 138 electrically couple the corresponding integrated circuits of the integrated circuit dies 126 .

Dielectric material 140 is located on the active side of integrated circuit die 126 , such as on passivation film 136 and die connector 138 . Dielectric material 140 encapsulates die connectors 138 laterally, and dielectric material 140 laterally interfaces with corresponding integrated circuit dies 126 . The dielectric material 140 may be a polymer, such as PBO, polyimide, BCB, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; similar materials or combinations thereof, and It can be formed, for example, by spin coating, lamination, CVD, or the like.

The adhesive 128 is on the backside of the integrated circuit die 126 and bonds the integrated circuit die 126 to the backside wiring structure 106 (eg, the dielectric layer 112 ). Adhesive 128 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 128 may be applied to the backside of the integrated circuit die 126 or may be applied over the surface of the carrier substrate 102 . For example, the adhesive 128 may be applied to the backside of the integrated circuit die 126 prior to singulation to separate the integrated circuit die 126 .

Although one IC die 126 is shown bonded in each of the first package area 100A and the second package area 100B, it should be understood that more IC die 126 may be bonded in each package in the area. For example, multiple integrated circuit dies 126 may be bonded in each region. Additionally, the dimensions of the integrated circuit die 126 may vary. In some embodiments, the integrated circuit die 126 may be a die with a large footprint, such as a system-on-chip (SoC) device. In embodiments in which the integrated circuit die 126 has a large footprint, the space available for the vias 116 in the package area may be limited. The use of backside-side routing structures 106 enables improved interconnect placement when the package area has limited space available for vias 116 .

In Figure 5, an encapsulant 142 is formed over the various elements. After formation, the encapsulant 142 encapsulates the via 116 and the integrated circuit die 126 laterally. The encapsulant 142 may be a molding compound, epoxy, or the like. The encapsulant 142 may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate 102 such that the vias 116 and/or the integrated circuit die 126 are buried or covered. The encapsulant 142 is then cured.

In FIG. 6 , a planarization process is performed on the encapsulant 142 to expose the vias 116 and the die connectors 138 . The planarization process may also grind the dielectric material 140 . After the planarization process, the top surfaces of the vias 116 , the die connectors 138 , the dielectric material 140 and the encapsulant 142 are coplanar. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, the planarization may be omitted, such as if vias 116 and die connectors 138 have been exposed.

In FIG. 7 , front-side wiring structures 144 are formed over the vias 116 , the encapsulation body 142 and the integrated circuit die 126 . Front side wiring structure 144 includes dielectric layers 146 , 150 , 154 and 158 ; metallization patterns 148 , 152 and 156 ; and under bump metallurgy (UBM) 160 . Metallization patterns may also be referred to as redistribution layers or redistribution traces. The front side routing structure 144 is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the front side routing structure 144 . The steps and processes discussed below may be omitted if fewer dielectric layers and metallization patterns are to be formed. The steps and processes discussed below may be repeated if more dielectric layers and metallization patterns are to be formed.

Dielectric layer 146 is deposited over encapsulation 142 , vias 116 , and die connectors 138 as an example of forming front-side wiring structures 144 . In some embodiments, the dielectric layer 146 is formed of a photosensitive material such as PBO, polyimide, BCB, etc. that can be patterned using a photoresist mask. Dielectric layer 146 may be formed by spin coating, lamination, CVD, similar processes, or a combination thereof. The dielectric layer 146 is then patterned. Openings are patterned to expose portions of vias 116 and die connectors 138 . The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 146 to light when the dielectric layer 146 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 146 is a photosensitive material, the dielectric layer 146 may be developed after exposure.

Metallization patterns 148 are then formed. Metallization pattern 148 includes conductive lines on and extending along the major surface of dielectric layer 146 . The metallization pattern 148 further includes vias extending through the dielectric layer 146 for physical and electrical connection to the vias 116 and the integrated circuit die 126 . To form metallization pattern 148 , a seed layer is formed over dielectric layer 146 and in the openings extending through dielectric layer 146 . In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer overlying the titanium layer. The seed layer can be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 148 . The patterning forms openings through the photoresist to expose the seed layer. Conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. Conductive materials may include metals such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and the underlying portion of the seed layer forms the metallization pattern 148 . The photoresist and the portion of the seed layer over which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, eg, by using an acceptable etching process (eg, by wet etching or dry etching).

A dielectric layer 150 is formed on the metallization pattern 148 and the dielectric layer 146 . Dielectric layer 150 may be formed in a similar manner to dielectric layer 146 and may be formed of the same material as dielectric layer 146 .

Metallization patterns 152 are then formed. The metallization pattern 152 includes conductive lines on and extending along the major surface of the dielectric layer 150 . The metallization pattern 152 further includes vias extending through the dielectric layer 150 for physical and electrical connection to the metallization pattern 148 . Metallization pattern 152 may be formed in a manner similar to metallization pattern 148 and may be formed of the same material as metallization pattern 148 .

A dielectric layer 154 is formed on the metallization pattern 152 and the dielectric layer 150 . Dielectric layer 154 may be formed in a similar manner to dielectric layer 146 and may be formed of the same material as dielectric layer 146 .

Metallization patterns 156 are then formed. Metallization pattern 156 includes conductive lines on and extending along the major surface of dielectric layer 154 . The metallization pattern 156 further includes vias extending through the dielectric layer 154 for physical and electrical connection to the metallization pattern 152 . Metallization pattern 156 may be formed in a manner similar to metallization pattern 148 , and may be formed of the same material as metallization pattern 148 .

A dielectric layer 158 is formed on the metallization pattern 156 and the dielectric layer 154 . Dielectric layer 158 may be formed in a similar manner to dielectric layer 146 and may be formed of the same material as dielectric layer 146 .

A UBM 160 extending through the dielectric layer 158 is optionally formed on the dielectric layer 158 . As an example of forming UBM 160 , dielectric layer 158 may be patterned to form openings that expose portions of metallization pattern 156 . The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 158 to light when the dielectric layer 158 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 158 is a photosensitive material, the dielectric layer 158 may be developed after exposure. The openings for UBM 160 may be wider than the openings for the via portions of metallization patterns 148 , 152 and 156 . A seed layer is formed over dielectric layer 158 and in the openings. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer overlying the titanium layer. The seed layer can be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to UBM 160. The patterning forms openings through the photoresist to expose the seed layer. Conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. Conductive materials may include metals such as copper, titanium, tungsten, aluminum, and the like. Next, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, eg, by using an acceptable etching process (eg, by wet etching or dry etching). The remainder of the seed layer and conductive material form UBM 160 . In embodiments in which UBM 160 is formed differently, more photoresist and patterning steps may be utilized.

In FIG. 8 , conductive connections 162 are formed on UBM 160 . The conductive connectors 162 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel palladium Bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connections 162 may comprise conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, similar materials, or combinations thereof. In some embodiments, the conductive connections 162 are formed by initially forming a solder layer using such common methods as evaporation, electroplating, printing, solder transfer, ball placement, and the like. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connections 162 include metal pillars (eg, copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, similar materials, or combinations thereof, and may be formed by a plating process.

In FIG. 9 , carrier substrate de-bonding is performed to detach (or “peel”) the carrier substrate 102 from the backside wiring structure 106 (eg, the dielectric layer 108 ). According to some embodiments, the lift-off includes projecting light, such as a laser or ultraviolet light, on the release layer 104 such that the release layer 104 decomposes under the heat of the light, and the carrier substrate 102 may be removed. The structure was then turned over and placed on tape.

In FIG. 10 , conductive connections 164 extending through dielectric layer 108 are formed to contact metallization pattern 110 . Openings are formed through dielectric layer 108 to expose portions of metallization pattern 110 . The openings may be formed, for example, using laser drilling, etching, or the like. Conductive connections 164 are formed in the openings. In some embodiments, the conductive connections 164 include flux and are formed in a flux dipping process. In some embodiments, the conductive connections 164 include a conductive paste (eg, solder paste, silver paste, etc.) and are dispensed during the printing process. In some embodiments, the conductive connections 164 are formed in a similar manner to the conductive connections 162 and may be formed of the same material as the conductive connections 162 .

11-18 illustrate cross-sectional views of various intermediate steps during a process for bonding a first package component 100 to a second package component 200 in accordance with some embodiments. A first package area 200A and a second package area 200B are shown, and a second package 201 is formed in each of the package areas 200A and 200B (see FIG. 18 ).

In Figure 11, a second package component 200 is provided or produced. In the illustrated embodiment, the same type of package is formed in package components 100 and 200 . In some embodiments, different types of packages are formed in package components 100 and 200 . In the illustrated embodiment, package components 100 and 200 are both InFO packages. The second package element 200 has conductive connections 166 that are similar to the conductive connections 162 of the first package element 100 .

In FIG. 12 , the second package component 200 is aligned with the first package component 100 . The respective package regions of each of package components 100 and 200 are aligned. For example, the first package regions 100A and 200A are aligned, and the second package regions 100B and 200B are aligned. The package components 100 and 200 are pressed together such that the conductive connections 166 of the second package component 200 contact the conductive connectors 164 of the first package component 100 .

Figures 13A-13J illustrate a masking device 400 that can be used to profile the laser emission in a subsequent reflow process. FIG. 13A shows a top view of the masking device showing masking layer 402 having openings such as annular opening 412 , circular opening 422 and rectangular opening 432 exposing mounting layer 404 . Masking layer 402 includes a material that is opaque to the laser, such as, for example, a metal such as aluminum, copper, iron, lead, ceramic, similar materials, or combinations thereof. In some embodiments, the masking device has a length L1 ranging from about 50 mm to about 400 mm in the x-direction and a width W1 ranging from about 50 mm to about 400 mm in the y-direction. The top view of masking layer 402 shows an exemplary embodiment of the arrangement of openings through masking layer 402 . It should be understood that the embodiment device shown in the top view in FIG. 13A is only an example of many possible embodiment devices. Those of ordinary skill in the art will recognize many variations, substitutions and modifications. For example, the various openings shown in FIG. 13A through masking layer 402 may be added, removed, replaced, rearranged, and repeated.

Mounting layer 404 includes a material that is 90% transparent to the laser or greater, such as, for example, glass, plexiglass, sapphire, similar materials, or combinations thereof. Masking layer 402 may be attached to mounting layer 404 by mechanical fasteners (eg, screws), however, any suitable method of securing masking layer 402 to mounting layer 404 may be used. Mounting layer 404 allows portions of masking layer 402 (eg, circular portion 414 ) to rest on mounting layer 404 and be separated from the rest of masking layer 402 without being directly connected across openings in masking layer 402 . In some embodiments, the index of refraction of the mounting layer may range from about 1.3 to about 1.8, which can be used to scatter the laser for a wider heating profile.

Figure 13B shows a cross-sectional view of the masking device 400 taken through the cross-section 13B-13B' shown in Figure 13A. As shown in FIG. 13B , an opaque masking layer 402 is placed over a transparent mounting layer 404 . In some embodiments, the thickness T1 of the masking layer 402 is in the range of about 100 nm to about 3 mm, and the thickness T2 of the mounting layer 404 is in the range of about 0.5 mm to about 3 mm.

Figure 13C shows a detailed view of zone 410 as shown in Figure 13A. An annular opening 412 extends through masking layer 402 to expose an annular region of mounting layer 404 . The annular opening 412 can be used to profile subsequent laser shots (see Figure 15 below). The circular portion 414 of the masking layer 402 is located in the center of the annular opening 412 without connecting the remainder of the masking layer 402 . The circular portion 414 may be secured to the underlying mounting layer 404 by suitable mechanical fasteners (eg, screws), however, any suitable method of securing the circular portion 414 to the mounting layer 404 may be used.

Figure 13D shows a cross-sectional view of region 410 taken through cross-section 13D-13D' as shown in Figure 13C. As shown in FIG. 13D , in some embodiments, the diameter D1 of the annular opening 412 is in the range of about 10 mm to about 60 mm, which is useful for implementing the conductive connector 164 of the first package element 100 and the second package element 200 Laser-Assisted Bonding (LAB) between the conductive connections 166 may be advantageous without causing significant warping of the first package element 100 and the second package element 200 . Diameter D1 greater than about 60 mm may be disadvantageous because a greater amount of laser energy is allowed to heat package components 100 and 200 , which may result in undesired warping of package components 100 and 200 . Diameter D1 less than about 10 mm may be disadvantageous because the smaller amount of laser energy that allows heating of package elements 100 and 200 may not result in the desired bond strength.

In some embodiments, the diameter D2 of the circular portion 414 is in the range of about 4 mm to about 30 mm, which is useful for implementing the conductive connections 164 of the first package component 100 and the conductive connections 166 of the second package component 200 . Laser-assisted bonding (LAB) therebetween may be advantageous without causing significant warpage of the first packaged component 100 and the second packaged component 200 . Diameter D2 less than about 4 mm may be disadvantageous because a greater amount of laser energy is allowed to heat package components 100 and 200 , which may result in undesired warping of package components 100 and 200 . Diameter D2 greater than about 30 mm may be disadvantageous because the smaller amount of laser energy that allows heating of package elements 100 and 200 may not result in the desired bond strength.

Figure 13E shows a detailed view of zone 420 as shown in Figure 13A. A circular opening 422 extends through the masking layer 402 to expose a circular area of the mounting layer 404 . The circular opening 422 can be used to profile subsequent laser shots (see Figure 14 below). However, in this embodiment, the circular opening 422 is present and the circular portion 414 is not present.

Figure 13F shows a cross-sectional view of region 420 taken through cross-section 13F-13F' as shown in Figure 13E. As shown in FIG. 13F , in some embodiments, the diameter D3 of the circular opening 422 is in the range of about 4 mm to about 60 mm, which is useful for implementing the conductive connector 164 of the first package element 100 and the second package element Laser assisted bonding (LAB) between the conductive connections 166 of 200 may be advantageous without causing significant warping of the first packaged component 100 and the second packaged component 200 . Diameter D3 greater than about 60 mm may be disadvantageous because a greater amount of laser energy is allowed to heat package components 100 and 200 , which may result in undesired warping of package components 100 and 200 . Diameter D3 less than about 4 mm may be disadvantageous because the smaller amount of laser energy that allows heating of package elements 100 and 200 may not result in the desired bond strength.

Figure 13G shows a detailed view of zone 430 as shown in Figure 13A. At least two rectangular openings 432 extend through masking layer 402 to expose rectangular regions of mounting layer 404 .

Figure 13H shows a cross-sectional view of region 430 taken through cross-section 13H-13H' as shown in Figure 13G. As shown in FIG. 13H, in some embodiments, rectangular opening 432 has a length L2 in the range of about 10 mm to about 40 mm in the x-direction and in the range of about 15 mm to about 40 mm in the y-direction The width W2. The length L2 is in the range of about 10 mm to about 40 mm for enabling laser-assisted bonding (LAB) between the conductive connections 164 of the first package element 100 and the conductive connections 166 of the second package element 200 This is advantageous without causing significant warping of the first package component 100 and the second package component 200 . A length L2 greater than about 40 mm may be disadvantageous because a greater amount of laser energy is allowed to heat the packaged components 100 and 200 , which may result in undesired warping of the packaged components 100 and 200 . A length L2 of less than about 10 mm may be disadvantageous because the smaller amount of laser energy that allows heating of package elements 100 and 200 may not result in the desired bond strength.

The width W2 is in the range of about 15 mm to about 40 mm for enabling laser-assisted bonding (LAB) between the conductive connections 164 of the first package element 100 and the conductive connections 166 of the second package element 200 This is advantageous without causing significant warping of the first package component 100 and the second package component 200 . A width W2 greater than about 40 mm may be disadvantageous because a greater amount of laser energy is allowed to heat the packaged components 100 and 200 , which may result in undesired warping of the packaged components 100 and 200 . A width W2 of less than about 15 mm may be disadvantageous because the smaller amount of laser energy that allows heating of package elements 100 and 200 may not result in the desired bond strength.

The rectangular openings 432 may be separated in the x-direction by a separation length L3 in the range of about 5 mm to about 40 mm. The separation length L3 is in the range of about 10 mm to about 40 mm for enabling laser-assisted bonding (LAB) between the conductive connections 164 of the first package element 100 and the conductive connections 166 of the second package element 200 It may be advantageous without causing significant warping of the first package component 100 and the second package component 200 . Separation length L3 greater than about 40 mm may be disadvantageous because it does not allow heating and reflow of a sufficient number of conductive connections 164 and 166, thereby reducing throughput. Separation length L3 less than about 5 mm may disadvantageously allow a greater amount of laser energy to heat package components 100 and 200 , which may result in undesired warping of package components 100 and 200 .

Figure 13I shows a detailed view of zone 440 as shown in Figure 13A. Region 440 includes a plurality of rectangular openings 432 having a substantially similar length L2, width W2, and separation length L3 as shown above with respect to FIG. 13G. However, in this embodiment, the plurality of rectangular openings 432 are separated by partially transparent portions 444 between the rectangular openings 432 .

Figure 13J shows a cross-sectional view of region 440 taken through cross-section 13J-13J' as shown in Figure 13I. As shown, partially transparent portions 444 are located between adjacent rectangular openings 432 having length L3 and width W2. The partially transparent portion 444 comprises polyimide (PI), silicon, thin metal films, other suitable optical films, similar materials, or combinations thereof. The rectangular opening 432 and partially transparent portion 444 can be used to shape the contours of subsequent laser emissions (see FIG. 16 below).

However, although the transparent portion 444 and the rectangular opening 432 are shown as rectangular in FIG. 13I, this is intended to be illustrative and not intended to limit the embodiments. For example, in other embodiments (not shown), the partially transparent portion 444 may have a substantially similar circular profile as the circular portion 414 shown in Figure 13C. In this embodiment, the circular, partially transparent portion may be mounted on the mounting layer 404 and surrounded by a circular opening substantially similar to the circular opening 412 without any opaque portions of the masking layer 402 in direct contact therewith. Any suitable shape can be used.

The transparency of the partially transparent portion 444 to the laser is in the range of about 10% to about 60%, which is useful for realizing the connection between the conductive connections 164 of the first package element 100 and the conductive connections 166 of the second package element 200 . Laser assisted bonding (LAB) may be advantageous without causing significant warping of the first packaged component 100 and the second packaged component 200 . The transparency of the partially transparent portion 444 to the laser of less than 10% may be disadvantageous because the smaller amount of laser energy that allows heating of the package components 100 and 200 through the partially transparent portion 444 may not produce the desired bond strength. Transparency of the partially transparent portion 444 to the laser in excess of 60% may be disadvantageous because a greater amount of laser energy is allowed to heat the packaged components 100 and 200 , which may result in undesired warping of the packaged components 100 and 200 .

14A-15B illustrate an embodiment of a first reflow process that includes multiple laser shots, and thus multiple reflow processes. Therefore, the reflow process shown in FIGS. 14A to 15B is called a multi-shot reflow process. The plurality of laser shots are performed using the laser beam 52 generated by the laser beam generator 54 . In each laser shot, the laser beam 52 is projected on an area of the top surface of the second package element 200 such that heat is absorbed by the second package element 200 and conducted through the second package element 200 to the conductive connections 164 and 166 , resulting in reflow of conductive connections 164 and 166 to form conductive connection 168 . The laser beam generator 54 is configured to generate the laser beam 52 , and the laser beam 52 is emitted from the emitter of the laser beam generator 54 . The laser beam 52 is larger than a typical laser beam. For example, the laser beam 52 may have a size ranging from about 3x3 mm2 to about 100x100 mm2. For example, the laser beam generator 54 is configured to amplify a small laser beam to a desired larger size. The power of the different portions of the laser beam 52 is substantially uniform, eg, with a variation of less than about 10% over the entire rectangular area. At each laser shot, the conductive connections 164 and 166 covered by the laser beam 52 are reflowed substantially simultaneously.

In FIG. 14A , the masking device 400 is positioned between the laser beam generator 54 and the second package element 200 to expose the first region 40A of the second package element 200 . A first laser shot 52A is then performed through the circular opening 422 in the first region 40A. FIG. 14B shows a top view of the second package component 200 showing the first region 40A. The first region 40A includes the components of the packaged components 100 and 200 that are directly in the projection path of the first laser shot 52A. When the laser beam 52 is projected on the first area 40A of the second package element 200, the first area 40A is heated, and the heat is transferred to the conductive connections 164 and 166 directly below the first area 40A. The first laser shot 52A is performed until the conductive connections 164 and 166 in the first region 40A are melted and reflowed to form the conductive connection 168 . Although the first region 40A is shown with a single conductive connection 168 for simplicity of illustration, in some embodiments, the first region 40A includes a plurality of conductive connections 168 . The conductive connections 164 and 166 outside the first area 40A (eg, not in the projection path of the laser beam 52 ) are less heated and not reflowed than the conductive connections 164 and 166 in the first area 40A.

The duration and unit power (eg, power per unit area) of the first laser shot 52A are controlled such that most of the conductive connections 164 and 166 outside the first region 40A are not melted, and thus not reflowed . Thus, the duration of the first laser shot 52A is long enough to melt the conductive connections 164 and 166 within the first region 40A, and short enough so that at least a majority ( or all) are not melted. For example, a small number of conductive connections 164 and 166 located outside and near the first region 40A may also be melted due to process variation or increased process margin. The unit power of the laser beam 52 is also selected to be high enough to melt the conductive connections 164 and 166 within the first area 40A, and low enough so that the conductive connections 164 and 166 outside the first area 40A are not melted. In some embodiments, the duration of the laser firing is in the range of about 2 seconds to about 30 seconds. The unit power may be in the range of about 0.1 watts/mm 2 to about 3 watts/mm 2 . It should be understood that the length of time and the specific power required to melt the conductive connections 164 and 166 are affected by a number of factors, which may include the specific power, the firing duration, the thickness of the second package element 200, the second package element 200 material and thermal conductivity. In some embodiments, conductive connections 164 and 166 have melting temperatures above about 200°C, and may range from about 215°C to about 230°C. The unit power emitted by the laser can be adjusted to obtain a specific heating rate and peak temperature. In embodiments, the peak temperature is in the range of about 240°C to about 300°C, and the heating rate is in the range of about 10°C/sec to about 400°C/sec. The first laser firing ends after the conductive connections 164 and 166 in the first area 40A are melted and before the conductive connections 164 and 166 outside the first area 40A are melted.

After the first laser emission 52A, the laser beam 52 is turned off and stops projecting on the second package element 200 . Between the end time of the first laser shot 52A and the start time of the second laser shot 52B (see FIG. 15A ), a delay time may be implemented. During the delay, no laser firing is performed. The delay is long enough to allow the reflowed conductive connections 168 to cool and solidify. For example, after the delay time, the temperature of the conductive connections 168 may drop to a range of about 100°C to about 150°C. The delay time can range from about 5 seconds to about 30 seconds. In some embodiments, cooling of the conductive connections 168 is performed, such as air cooling. In such an embodiment, the delay time can be adjusted to achieve a specific cooling rate. In some embodiments, the delay time is a predetermined period of time. In embodiments, the cooling rate is greater than about 5°C/sec.

In FIG. 15A , the masking device 400 is positioned between the laser beam generator 54 and the second package element 200 to expose the second region 40B of the second package element 200 through the annular opening 412 . A second laser shot 52B is then performed at the second region 40B of the second packaged component 200 . FIG. 15B shows a top view of the second package component 200 showing the second region 40B surrounding the first region 40A. Second region 40B includes components of package components 100 and 200 that are directly in the projection path of second laser emission 52B. Accordingly, the conductive connections 164 and 166 in the second region 40B are reflowed. Most or all of the conductive connections 164 and 166 outside the second region 40B do not receive sufficient heat and are not melted and reflowed. For example, a small number of conductive connections 164 and 166 located outside and close to second region 40B may also be melted due to process variation or increased process margin. Although the second region 40B is shown as having two conductive connections 168 for simplicity of illustration, in some embodiments, the second region 40B includes more than two conductive connections 168 .

By repositioning the masking device 400 between the laser beam generator 54 and the second package element 200, the movable masking device 400 enables a greater number of laser firing shapes and heating profiles. This may allow the conductive connections 168 to be reflowed with a smaller number of laser shots, resulting in higher process efficiency and higher throughput. In some embodiments, multiple first laser shots 52A and/or second laser shots 52B are performed simultaneously through multiple circular openings 422 and annular opening 412 . Transparent mounting layer 404 allows portions of masking layer 402, such as, for example, circular portion 414 (see FIG. 13C above) to rest on mounting layer 404 and be separated from the rest of masking layer 402 without crossing the masking layer The opening in 402 is directly connected. This can be used to achieve laser-assisted bonding (LAB) between the conductive connections 164 of the first package element 100 and the conductive connections 166 of the second package element 200 without causing the first package element 100 and the second package element 200's of significant warping.

In some embodiments, the order of the first laser shot 52A and the second laser shot 52B is reversed. The laser beam 52 may first pass through the annular opening 412 to reflow the conductive connections 164 and 166 in the second region 40B. Thereafter, masking device 400 is repositioned so that laser beam 52 can then pass through circular opening 422 to reflow conductive connections 164 and 166 in first region 40A. In these embodiments, the conductive connections 164 and 166 in the second area 40B are reflowed before the conductive connections 164 and 166 in the first area 40A.

16 illustrates an embodiment of a second reflow process that may be performed alternately or sequentially with the first reflow process described above with respect to FIGS. 14A-15B. The second reflow process includes multiple laser shots, and thus includes multiple reflow processes, and is therefore also referred to as a multi-shot reflow process. The plurality of laser shots 52C may be performed using a substantially similar laser beam 52 and laser beam generator 54 as described above with respect to FIG. 14A.

In FIG. 16 , the masking device 400 is located between the laser beam generator 54 and the second package element 200 to expose the third region 40C of the second package element 200 . A third laser shot 52C is then performed through the rectangular opening 432 and the partially transparent portion 444 on the third region 40C. The third region 40C includes the components of the packaged components 100 and 200 that are directly in the projection path of the third laser shot 52C. When the laser beam 52 is projected on the third area 40C of the second package element 200, the third area 40C is heated, and the heat is transferred to the conductive connections 164 and 166 directly below the third area 40C. A third laser shot 52C is performed until the conductive connections 164 and 166 in the third region 40C are melted and reflowed to form the conductive connection 168 . Although the third region 40C is shown as having three conductive connections 168 for simplicity of illustration, in some embodiments the third region 40C includes a different number of conductive connections 168, such as more than three conductive connections Piece 168. The conductive connections 164 and 166 outside the third zone 40C (eg, not in the projection path of the laser beam 52 ) are less heated and not reflowed than the conductive connections 164 and 166 within the third zone 40C.

By passing the third laser emission 52C through the partially transparent portion 444 other than the rectangular opening 432, the conductive connections 164 and 166 in the third region 40C can be heated sufficiently to be reflowed without overheating the package components 100 and 200 without undesired warpage. Using the partially transparent portion 444 to shape the third laser shot 52C may allow one third laser shot 52C to be used to heat the larger third region 40C without overheating and causing warping. The conductive connections 164 and 166 in the path of the portion of the third laser emission 52C through the partially transparent portion 444 can be heated sufficiently to reflow into the conductive connection 168 without heating directly through the rectangular opening 432 Subsequent laser firing of conductive connections 164 and 166 . In some embodiments, the plurality of third laser shots 52C are performed simultaneously through the plurality of rectangular openings 432 and the partially transparent portion 444 . In some embodiments, a plurality of third laser shots 52C are performed sequentially through the rectangular opening 432 and the partially transparent portion 444 .

FIG. 17 shows the reflow process after performing the first reflow process shown in FIGS. 14A-15B above, the second reflow process shown in FIG. 16 above, or a combination thereof to reflow all the conductive connections 164 and 166 and generate reflow. After the conductive connections 168 , the packaged components 100 and 200 are joined by the conductive connections 168 . The multiple shot reflow process results in localized heating of second packaged component 200 on each shot, rather than global heating of both packaged components 100 and 200 simultaneously. When the laser firing is performed after the previous firing has ended, the elevated temperature caused by the previous laser firing has decreased. Heating the package elements 100 and 200 causes the wafer to warp, and the magnitude of the warp is related to the heating temperature. By performing more localized heating, the overall heating temperature can be reduced, and the warpage of the package elements 100 and 200 can be reduced. Furthermore, the laser emissions 52A and 52B are projected on the second package element 200, and the first package element 100 directly receives a very small dose (if any) of the laser beam. Therefore, the first package element 100 is not heated significantly, and the corresponding warpage is reduced.

Although conductive connections 168 are shown connecting metallization pattern 110 and UBM 160 , it should be understood that conductive connections 168 may be used to connect to any conductive feature of package components 100 and 200 . For example, conductive connections 168 may also be physically connected to vias 116, such as in embodiments in which backside routing structures 106 are omitted. Likewise, conductive connections 168 may be physically connected to metallization patterns 156, such as in embodiments in which UBM 160 is omitted.

Since the multiple shot reflow process reduces or avoids wafer warpage, the overall distance Dist1 between the package components 100 and 200 may be more consistent in different package areas. For example, the distance Dist1 at the edges of the package elements 100 and 200 may be smaller than the distance Dist1 at the center of the package elements 100 and 200 . Furthermore, the distance Dist1 may vary by less than 5% over the diameter of the packaged components 100 and 200 .

After the multiple shot reflow process is completed, the packaged components 100 and 200 may be cleaned in a cleaning process. The cleaning process can be, for example, flux cleaning, which helps remove residual material. Flux cleaning can be performed by flushing, rinsing or soaking with hot water or cleaning solvent. Additionally, an underfill or encapsulant may optionally be injected between package components 100 and 200 to surround conductive connections 168 .

18 shows cross-sectional views of various intermediate steps during a process for forming a package structure 300 in accordance with some embodiments. The package structure 300 may be referred to as a package-on-package (PoP) structure.

The singulation process is performed by sawing along a scribe line area (eg, between the package areas of package components 100 and 200 ). The sawing singulates adjacent package regions 100A, 100B, 200A, and 200B from package components 100 and 200 . The resulting singulated first package 101 is from one of the first encapsulation region 100A or the second encapsulation region 100B, and the resulting singulated second package 201 is from one of the first encapsulation region 200A or the second encapsulation region 200B one.

The packages 101 and 201 are then mounted to the package substrate 302 using the conductive connectors 162 . The package substrate 302 may be made of semiconductor materials such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations of these can also be used. In addition, the package substrate 302 may be an SOI substrate. Generally, SOI substrates include layers of semiconductor materials such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the package substrate 302 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is fiberglass resin (eg, FR4). Other options for core materials include bismaleimide-triazine BT resins, or alternatively, other PCB materials or films. The package substrate 302 may use a build-up film such as Ajinomoto Build up Film (ABF) or other laminates.

Package substrate 302 may include active devices or passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to create the structural and functional requirements for the design of package structure 300 . The device may be formed using any suitable method.

Package substrate 302 may also include metallization layers and vias (not shown) and bond pads 304 over the metallization layers and vias. Metallization layers can be formed over active and passive devices and designed to connect various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (eg, low-k dielectric material) and conductive material (eg, copper) and vias interconnecting each layer of conductive material, and may be formed by any suitable process (eg, deposition, damascene, dual damascene, etc.). In some embodiments, the package substrate 302 is substantially free of active and passive devices.

In some embodiments, the conductive connections 162 are reflowed to attach the first package 101 to the bond pads 304 . The conductive connections 162 electrically and/or physically couple the package substrate 302 (including the metallization layer in the package substrate 302 ) to the first package 101 . In some embodiments, a passive device (eg, a surface mount device (SMD), not shown) may be attached to the first package 101 (eg, bonded to bond pads) prior to being mounted on the package substrate 302 304). In such an embodiment, the passive device may be bonded to the same surface of the first package 101 as the conductive connections 162 .

Before the conductive connectors 162 are reflowed, an epoxy flux (not shown) may be formed on the conductive connectors 162 , and at least some of the epoxy resin portion of the epoxy flux will seal the first package 101 It remains after being attached to the package substrate 302 . This remaining portion of epoxy may act as an underfill to reduce stress from reflowing the conductive connections 162 and protect seams from reflowing the conductive connections 162 . In some embodiments, an underfill (not shown) surrounding the conductive connections 162 may be formed between the first package 101 and the package substrate 302 . The underfill may be formed by a capillary flow process after the first package 101 is attached, or may be formed by a suitable deposition method before the first package 101 is attached.

Various advantages may be realized by various embodiments. Warpage of the packaged components 100 and 200 may be reduced by performing laser assisted bonding (LAB) with a multi-layer masking device. By selectively heating areas of package elements 100 and 200 with different types of laser beam shapes and heating profiles, greater flexibility may be provided during fabrication. Laser heating with various laser beam profiles obtained by moving the position of the masking device can provide faster heating, which can increase manufacturing throughput.

According to an embodiment, a masking apparatus for performing a laser heating process includes: a masking layer, the masking layer including a plurality of masking portions, the masking portions being opaque to a reflow laser; and a mounting layer, the masking A layer is on the mounting layer, which is transparent to the reflow laser. In an embodiment, a first masking portion of the plurality of masking portions includes a circular profile. In an embodiment, a second masking portion of the plurality of masking portions includes a circular profile, the second masking portion surrounds the first masking portion, wherein the first masking portion does not contact the masking layer any other part. In an embodiment, the second masking portion is located in an opening in the first masking portion, the diameter of the opening is in the range of 10 mm to 60 mm, and the diameter of the second masking portion is between in the range of 4 mm to 30 mm. In an embodiment, at least one gap within the masking layer has a rectangular outline. In an embodiment, the masking layer includes a partially transparent portion. In an embodiment, the mounting layer comprises glass. In an embodiment, the masking layer is attached to the mounting layer by means of screws.

According to another embodiment, a method for bonding a semiconductor substrate includes placing a die on a substrate, a corresponding first connector of a plurality of first connectors on the die contacting a plurality of first connectors on the substrate a corresponding second connector of a plurality of second connectors; and performing a heating process on the die and the substrate to bond the corresponding first connector with the corresponding second connector , the heating process includes: placing a masking device between the laser generator and the substrate, the masking device includes a masking layer and a transparent layer, and a part of the masking layer is opaque; and performing a first laser emission , the laser passes through a first gap in the masking layer and through the transparent layer to heat a first portion of the top side of the die opposite the substrate. In an embodiment, the first gap has an annular profile. In an embodiment, the method further includes performing a second laser shot, wherein during the second laser shot, the laser passes through a second gap in the masking layer to heat the die. The second portion of the top side, the second portion of the top side of the die is surrounded by the first portion of the top side of the die. In an embodiment, the method further includes moving the masking layer relative to the substrate after performing the first laser shot and before performing the second laser shot. In an embodiment, the second gap has an outer circular profile and an inner circular profile. In an embodiment, the method further includes performing a plurality of the heating processes that connect each of the plurality of first connectors with the plurality of second connectors The corresponding second connectors in the .

According to yet another embodiment, a method of forming a semiconductor device includes aligning a first package element having a first conductive connection with a second package element having a second conductive connection a connector, wherein the alignment brings the first conductive connector into physical contact with the second conductive connector; performing a first laser shot that strikes the first conductive connector Opposite to the first package element, the first laser emission is shaped by passing through a first opening in the masking layer and through a first partially transparent portion of the masking layer adjacent to the first opening, so that The first laser emission reflows the first conductive connection member and the second conductive connection member. In an embodiment, the first laser shot being shaped further comprises the first laser shot passing through a second opening in the masking layer. In an embodiment, the method further includes performing a second laser shot, the second laser shot hitting the first package element opposite a third conductive connector, the third conductive connector and the The fourth conductive connection on the second package element is in physical contact. In an embodiment, the second laser is emitted through a third opening in the masking layer, through a fourth opening in the masking layer, and through the third opening and the masking layer. The second partially transparent portion between the fourth openings is formed. In an embodiment, the first laser shot is performed concurrently with the second laser shot. In an embodiment, the transparency of the first partially transparent portion to the laser is in the range of 10% to 60%.

13B-13B', 13D-13D', 13F-13F', 13H-13H', 13J-13J': cross section 40A: District 1 40B: District 2 40C: The third district 52: Laser Beam 52A: First laser launch 52B: Second laser launch 52C: Third laser launch 54: Laser beam generator 100: The first package component 100A, 200A: the first packaging area 100B, 200B: the second packaging area 101: The first package 102: Carrier substrate 104: Release Layer 106: Back-side wiring structure 108, 112, 146, 150, 154, 158: Dielectric layer 110, 148, 152, 156: Metallization pattern 114: Opening 116: Through hole 126: integrated circuit die 128: Adhesive 130: Semiconductor substrate 132: Interconnect structure 134: Pad 136: Passivation film 138: Die connectors 140: Dielectric Materials 142: Encapsulation 144: Front-side wiring structure 160: metal layer under bump 162, 164, 166, 168: Conductive connectors 200: Second package component 201: Second package 300: Package structure 302: Package substrate 304: Bonding pads 400: Masking Device 402: masking layer 404: Install Layer 410, 420, 430, 440: District 412: Ring opening 414: Circular part 422: round opening 432: Rectangular opening 444: Partially transparent part D1, D2, D3: Diameter Dist1: Overall distance L1, L2: length L3: separation length T1, T2: Thickness W1, W2: width x, y: direction

Aspects of the embodiments of the present invention are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. 1-12 and 14A-18 are cross-sectional views of various intermediate steps during a process for forming a device package in accordance with some embodiments. 13A-13J are top and cross-sectional views of a masking device according to some embodiments.

13B-13B’: cross section

400: Masking Device

402: masking layer

404: Install Layer

410, 420, 430, 440: District

412: Ring opening

414: Circular part

422: round opening

432: Rectangular opening

444: Partially transparent part

D1, D2, D3: Diameter

Dist1: Overall distance

L1: length

L3: separation length

T1, T2: Thickness

W1: width

x, y: direction

Claims (1)

A masking device for performing a laser heating process, comprising: a masking layer, the masking layer including a plurality of masking portions, the plurality of masking portions being opaque to the reflow laser; and an installation layer, the masking layer is located on the installation layer, and the installation layer is transparent to the reflow laser.

Images