TW202203379A - Three-dimensional flash memory device - Google Patents

Abstract

Provided are various three-dimensional flash memory devices. A three-dimensional flash memory device includes a gate stack structure, separate arc-shaped channel pillars, source/drain pillars and a charge storage structure. The gate stack structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The arc-shaped channel pillar are disposed on the substrate and located in the gate stack structure. The source/drain pillars are disposed on the substrate and penetrate through the gate stack structure, wherein two source/drain pillars are disposed at two ends of each of the arc-shaped channel pillars. The charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel pillar.

Description

3D flash memory device

The present invention relates to a semiconductor device, and more particularly, to a three-dimensional flash memory device.

Non-volatile memory (such as flash memory) is widely used in personal computers and other electronic devices because of its advantage that the stored data will not disappear after a power failure.

Currently, three-dimensional flash memories commonly used in the industry include NOR flash memory and NAND flash memory. In addition, another three-dimensional flash memory is an AND flash memory, which can be applied in a multi-dimensional flash memory array with high integration and high area utilization, and has a fast operation speed. The advantages. Therefore, the development of three-dimensional flash memory devices has gradually become a current trend.

The present invention provides a three-dimensional flash memory device. The channel column of the memory cell is designed in arc shape or semicircle shape, which can provide longer channel length and better device performance.

The three-dimensional flash memory device of the present invention includes a gate stack structure, a plurality of separate arc-shaped channel pillars, a plurality of source/drain pillars, and a charge storage structure. The gate stack structure is disposed on the substrate and includes a plurality of gate layers that are electrically insulated from each other. A plurality of separate arc-shaped channel pillars are disposed on the substrate and in the gate stack structure. A plurality of source/drain poles are disposed on the substrate and pass through the gate stack structure, wherein two source/drain poles are respectively disposed at two ends of each of the plurality of arc-shaped channel poles Drain pole. A charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel column.

In an embodiment of the present invention, two adjacent ones of the arc-shaped channel columns are configured in mirror symmetry.

In an embodiment of the present invention, two adjacent ones of the arc-shaped channel columns are non-mirror symmetrical.

In an embodiment of the present invention, an insulating column is disposed between two adjacent ones of the arc-shaped channel columns.

In an embodiment of the present invention, the plurality of insulating pillars in different columns are arranged in a staggered manner.

In an embodiment of the present invention, the plurality of insulating pillars in different columns are arranged in alignment.

In an embodiment of the present invention, the source/drain pillars at the corresponding ends of the plurality of arc-shaped channel pillars are separated from each other.

In an embodiment of the present invention, a contact plug is electrically connected to the source/drain pillars at the corresponding ends of the plurality of arc-shaped channel pillars adjacent to the two.

In an embodiment of the present invention, the contact plug is electrically connected to a conductive line on the gate stack structure.

In an embodiment of the present invention, the conductive lines include source lines or bit lines.

In an embodiment of the present invention, among the plurality of arc-shaped channel pillars, the source/drain pillars at the corresponding end portions of the two adjacent ones of the plurality of arc-shaped channel pillars are connected to each other.

In an embodiment of the present invention, a contact plug is electrically connected to the connected source/drain posts.

In one embodiment of the invention, the sidewalls of each of the charge storage structures have a substantially smooth profile.

In one embodiment of the invention, the sidewalls of each of the charge storage structures have a wavy profile.

In one embodiment of the present invention, each of the arc-shaped channel columns is continuous in its extending direction.

In an embodiment of the present invention, each of the plurality of arc-shaped channel columns is discontinuous in its extending direction, and the plurality of channel portions of the arc-shaped channel column are only connected with the plurality of gates Pole layer corresponds.

In an embodiment of the present invention, both ends of each of the plurality of arc-shaped channel pillars are the same distance from the corresponding gate layer.

In an embodiment of the present invention, the distances between the two ends of each of the plurality of arc-shaped channel pillars from the corresponding gate layer are unequal.

In an embodiment of the present invention, the material of the plurality of arc-shaped channel pillars includes undoped polysilicon, and the material of the plurality of source/drain pillars includes doped polysilicon.

In an embodiment of the present invention, from a top view, the shape of each of the plurality of source/drain pillars is L-shaped, I-shaped, polygonal, circular, arc-shaped, annular or its combination.

Based on the above, in the three-dimensional flash memory device of the present invention, the memory cell has an arc-shaped channel column, which will generate a curvature effect to enhance the operation desire of programming/erasing the memory cell, and can provide a relatively high level of flexibility. Long channel lengths and better element performance. In addition, the three-dimensional flash memory device of the present invention can have high integration and high area utilization, and meet the requirement of high operating speed.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

1A to 1I illustrate a manufacturing process of a three-dimensional flash memory device according to a first embodiment of the present invention, wherein FIGS. 1A to 1F are three-dimensional schematic diagrams, and FIGS. 1G to 1I are schematic top views.

Referring to FIG. 1A , a stacked structure 102 is formed on the substrate 100 . The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. In one embodiment, doped regions may be formed in the substrate 100 according to design requirements. In one embodiment, a dielectric layer, such as a silicon oxide layer, is formed on the substrate 100 . In this embodiment, the stacked structure 102 includes a plurality of first film layers 104 and a plurality of second film layers 106 alternately stacked on the substrate 100 . In one embodiment, the first layer 104 is an insulating layer (eg, a silicon oxide layer), and the second layer 106 is a sacrificial layer (eg, a silicon nitride layer). However, the present invention is not limited thereto. In another embodiment, the first film layer 104 is an insulating layer (eg, a silicon oxide layer), and the second film layer 106 is a gate layer (eg, a doped polysilicon layer).

Next, a patterning process is performed to form a plurality of trenches T penetrating the stacked structure 102 . In one embodiment, during the patterning process, part of the substrate 100 is also removed at the same time, so that the trench T extends into the substrate 100 . In one embodiment, the sidewall of the trench T is wavy, and the shape is defined by the photomask. More specifically, the trench T includes a plurality of rectangular openings 107 and a plurality of columnar openings 108 arranged alternately. In one embodiment, the columnar openings 108 are configured to accommodate subsequently formed memory cells therein, while the rectangular openings 107 are configured to accommodate therein an insulating layer that electrically insulates adjacent memory cells from each other. In this embodiment, from the above perspective, the cylindrical opening 108 has an elliptical outline, but the present invention is not limited thereto. In other embodiments, the cylindrical openings 108 may have profiles of other shapes, such as circle-like, circular, oval-like, or polygonal.

In one embodiment, the column openings 108 of adjacent trenches T are arranged to be staggered with each other. More specifically, the column openings 108 of the trenches T of the (N)th and (N+2)th columns are aligned with each other, and the columns of the (N+1)th and (N+3)th columns of the trenches T are aligned with each other. The openings 108 are aligned with each other, and the column openings 108 of the trenches T in the (N)th and (N+1)th columns are staggered with each other, where N is a positive integer. However, the present invention is not limited thereto. In another embodiment, the column openings 108 of adjacent trenches T may be configured to be aligned with each other.

Referring to FIG. 1B , a charge storage structure 110 is formed on the stacked structure 102 and the surface of the trench T. As shown in FIG. In one embodiment, the charge storage structure 110 is an oxide-nitride-oxide (ONO) composite layer. For example, the charge storage structure 110 includes a silicon oxide layer 110a, a silicon nitride layer 110b and a silicon oxide layer 110c stacked on the surface of the trench T in sequence. In one embodiment, the charge storage structure 110 is blanket-formed on the sidewall and bottom surface of the trench T. As shown in FIG. From another perspective, a plurality of charge storage structures 110 are formed on the sidewalls and the bottom surface of the trench T, respectively, and are connected to each other. However, the present invention is not limited thereto. In another embodiment, a plurality of charge storage structures 110 are formed on opposite sidewalls of each trench T in the form of spacers.

Referring to FIG. 1C , channel pillars 112 are formed on the charge storage structure 110 in the trench T. As shown in FIG. More specifically, the channel pillars 112 are compliantly formed along the sidewalls of the trenches T and do not fill the trenches T. As shown in FIG. In one embodiment, the material of the channel pillars 112 includes undoped polysilicon. In one embodiment, two channel pillars 112 are formed on opposite sidewalls of each trench T in the form of spacers, and the charge storage structure 110 at the bottom of the trench T is exposed.

Referring to FIG. 1D , the lower portion of each trench T is filled with insulating pillars 114 . In one embodiment, the material of the insulating pillars 114 includes silicon oxide. In one embodiment, the top surface of the insulating pillar 114 is lower than the uppermost first film layer 104 and higher than the uppermost second film layer 106 .

Next, the upper portion of each trench T is filled with semiconductor plugs 116 . In one embodiment, the material of the semiconductor plug 116 includes undoped polysilicon. In one embodiment, the top surface of the semiconductor plug 116 is substantially flush with the top surface of the stacked structure 102 .

Referring to FIG. 1E , the film layer in the rectangular opening 107 of the trench T is removed, and the film layer in the columnar opening 108 of the trench T is left. In one embodiment, lithography and etching processes are performed to remove the charge storage structures 110 , the insulating pillars 114 and the semiconductor plugs 116 in each rectangular opening 107 of the trench T. FIG. In one embodiment, after the removing step of FIG. 1E , the remaining channel pillars 112 are arc-shaped or semicircular, and the facing channel pillars 112 are mirror-symmetrical.

In the present invention, the channel pillar 112 can be described as an arc-shaped channel pillar or a semi-cylindrical channel layer, and the channel pillar 112 is in its extending direction (at the pillar opening 108 ). between the top and bottom) is continuous. More specifically, each channel column 112 is integral in its extending direction and is not divided into a plurality of disconnected parts.

Referring to FIG. 1F , two source/drain pillars 118 are formed at both ends of each arc-shaped channel pillar 112 . In the present invention, the source/drain pillars are also referred to as buried diffusion regions. In one embodiment, a sidewall plasma doping process is performed to implant dopants into a portion of the channel pillars 112 exposed by the rectangular openings 107 to form the source/drain pillars 118 . In one embodiment, the sidewall plasma doping process also implants dopants into the portion of the semiconductor plug 114 exposed by the rectangular opening 107 .

For the convenience of description, the following FIGS. 1G to 1I only show schematic top views of the second film layer 106 in the uppermost layer of the stacked structure 102 , so as to clearly understand the corresponding relationship of each component.

Referring to FIG. 1G , an isolation layer 120 is formed in the rectangular opening 107 of the trench T. As shown in FIG. In one embodiment, the material of the isolation layer 120 includes silicon oxide. In one embodiment, the top surface of the isolation layer 120 is substantially flush with the top surface of the stacked structure 102 .

Referring to FIG. 1H , the second film layer 106 of the stacked structure 102 is replaced with a gate layer 126 . In one embodiment, the second film layer 106 in the stacked structure 102 is removed to form a plurality of horizontal openings between adjacent first film layers 104 . After that, a gate layer 126 is formed in the formed horizontal opening. The material of the gate layer 126 includes tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix ) or cobalt silicide ( _{CoSix )} . In addition, in other embodiments, before the gate layer 126 is formed, a buffer layer and a barrier layer may be sequentially formed in the horizontal opening. The material of the buffer layer includes high dielectric constant materials with a dielectric constant greater than 7, such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxides, lanthanum Element oxides or combinations thereof. The material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

In one embodiment, the replacement step is performed when the second film layer 106 is a sacrificial layer (eg, a silicon nitride layer). After the replacement step, the stacked structure 102 may include a plurality of first film layers 104 (eg, insulating layers) and a plurality of gate layers 126 (eg, tungsten layers) that are alternately stacked. In one embodiment, the stack structure 102 is also referred to as a gate stack structure. However, the present invention is not limited thereto. In another embodiment, when the second film layer 106 is a gate layer (eg, a doped polysilicon layer), the replacement step can be omitted. So far, the fabrication of the plurality of memory cells MC1 of the present invention is completed.

In one embodiment, each memory cell MC1 includes a gate layer 126 disposed horizontally, an arc-shaped channel column 112 disposed vertically, a charge storage structure 110 located between the gate layer 126 and the arc-shaped channel column 112 , and Two source/drain pillars 118 at both ends of the arc-shaped channel pillar 112 . In this embodiment, the source/drain pillars 118 at the corresponding ends adjacent to the two of the plurality of arc-shaped channel pillars 112 are separated from each other. In this embodiment, the face-to-face memory cells MC1 are configured in mirror symmetry, and can be operated separately or together according to design requirements. The memory cell MC1 of the present invention has an arc-shaped channel column, which produces a curvature effect to enhance the operating margin of the program/erase memory cell, and can provide a longer channel length and better device performance.

In one embodiment, the three-dimensional flash memory device of the present invention may optionally include a conductive layer 124 as a heater to heat the gate stack structure, as shown in FIG. 1H . In one embodiment, the conductive layer 124 may be formed at the same time in the above-mentioned replacement step. The conductive layer 124 is disposed on the substrate 100 and is adjacent to and extends along the sidewall of the gate stack structure. In addition, in this embodiment, the conductive layers 124 are disposed along two opposite sidewalls of the gate stack structure, but the present invention is not limited thereto. In other embodiments, the conductive layer 124 may be provided only beside one sidewall of the gate stack structure, or the conductive layers 124 may be provided all around the gate stack structure according to actual requirements. In one embodiment, the method of using the conductive layer 124 as a heater is to apply a relatively high voltage and a relatively low voltage to the electrical connection points at two opposite ends of the conductive layer 124 respectively to form a voltage difference. As a result, a current can be generated. When current passes through the conductive layer 124, the conductive layer 124 generates heat, which in turn can heat the adjacent gate stack structure.

Referring to FIG. 1I , a plurality of conductive wires W1 and W2 are formed on the stacked structure 102 to electrically connect the plurality of memory cells MC1 . More specifically, the conductive wire W1 is electrically connected to the memory cells MC1 in the (N)th column and the (N+2)th column, and the conductive wire W2 is electrically connected to the (N+1)th column and the (N+3)th column. The memory cell MC1, where N is a positive integer. In one embodiment, each of the conductive lines W1 and W2 is a source line or a bit line according to design requirements. In one embodiment, the plurality of conductive wires W1 and W2 are respectively electrically connected to the plurality of memory cells MC1 through the contact plug 122 . More specifically, the contact plugs 122 are electrically connected to the source/drain pillars 118 at corresponding ends adjacent to the two of the plurality of arc-shaped channel pillars 112 . In one embodiment, the contact plug 122 partially overlaps the adjacent source/drain pillar 118 from a top view. So far, the fabrication of the three-dimensional flash memory device 10 of the present invention is completed.

2A to 2F are schematic top views of a manufacturing process of a three-dimensional flash memory device according to a second embodiment of the present invention. For the convenience of description, the following FIGS. 2A to 2F only show schematic top views of the second film layer 106 in the uppermost layer in the stacked structure, so as to clearly understand the corresponding relationship of each component. Furthermore, in the second embodiment, similar reference numerals are used for components that are similar in material or function to those in the first embodiment.

Referring to FIG. 2A, a stacked structure is formed on the substrate. In one embodiment, the stacked structure includes a plurality of first film layers and a plurality of second film layers 106 alternately stacked on the substrate. In one embodiment, the first layer is an insulating layer (eg, a silicon oxide layer), and the second layer is a sacrificial layer (eg, a silicon nitride layer). However, the present invention is not limited thereto. In another embodiment, the first film layer is an insulating layer (eg, a silicon oxide layer), and the second film layer is a gate layer (eg, a doped polysilicon layer).

Next, a patterning process is performed to form a plurality of trenches Ta penetrating the stacked structure. In one embodiment, during the patterning process, part of the substrate is also removed at the same time, so that the trench Ta extends into the substrate. In one embodiment, the sidewalls of the trenches Ta are substantially vertical.

After that, an isolation layer 103 is formed in the trench Ta. In one embodiment, the material of the isolation layer 103 includes silicon oxide. In one embodiment, the top surface of the isolation layer 103 is substantially flush with the top surface of the stacked structure.

Referring to FIG. 2B , a patterning process is performed to form a plurality of columnar openings Ha penetrating the stacked structure and the isolation layer 103 . In the present embodiment, the columnar opening Ha has an elliptical profile from the above perspective, but the present invention is not limited thereto. In other embodiments, the cylindrical opening Ha may have contours of other shapes, such as circular, elliptical-like, or polygonal.

In one embodiment, adjacent columnar openings Ha are configured to be aligned with each other. More specifically, the columnar openings Ha of the (N)th and (N+1)th columns are aligned with each other, where N is a positive integer. However, the present invention is not limited thereto. In another embodiment, adjacent columnar openings Ha are arranged to be staggered with each other.

Then, a charge storage structure 110 is formed on the sidewall of the columnar opening Ha. In the present embodiment, each of the charge storage structures 110 has an annular profile from the above perspective. In one embodiment, the charge storage structure 110 is an oxide-nitride-oxide (ONO) composite layer. For example, the charge storage structure 110 includes a silicon oxide layer 110a, a silicon nitride layer 110b, and a silicon oxide layer 110c sequentially stacked on the sidewalls of the columnar openings Ha. In one embodiment, the charge storage structure 110 is formed on the sidewall and bottom surface of the columnar opening Ha. However, the present invention is not limited thereto. In another embodiment, the charge storage structures 110 are formed only on the sidewalls of the columnar openings Ha.

After that, channel pillars 112 are formed on the charge storage structure 110 in the pillar-shaped opening Ha. In the present embodiment, each of the channel posts 112 has an annular profile from the above perspective. In one embodiment, the material of the channel pillars 112 includes undoped polysilicon. In one embodiment, the channel pillars 112 are only formed on the sidewalls of each pillar-shaped opening Ha, and the charge storage structures 110 at the bottom of the pillar-shaped opening Ha are exposed.

Next, the insulating pillars 113 are filled in the pillar-shaped openings Ha. In one embodiment, the material of the insulating pillars 113 includes silicon oxide. In one embodiment, the top surfaces of the insulating pillars 113 are substantially flush with the top surfaces of the stacked structure.

Referring to FIG. 2C , a patterning process is performed to form a plurality of column openings Hb penetrating the charge storage structure 110 and the channel column 112 . In one embodiment, the patterning process also removes part of the insulating pillars 113 and part of the isolation layer 103 . In one embodiment, two column-shaped openings Hb are formed on opposite sides of each annular channel column 112 and the corresponding annular charge storage structure 110 . In this embodiment, from the above perspective, the columnar opening Hb has a circular outline, but the present invention is not limited thereto. In other embodiments, the columnar opening Hb may have contours of other shapes, such as an ellipse, an ellipse-like shape, or a polygon.

Next, the source/drain pillars 218 are filled in the pillar openings Hb. In one embodiment, the material of the source/drain pillars 218 includes doped polysilicon.

Referring to FIG. 2D, a tempering process is performed to diffuse the dopants in the source/drain pillars 218 to the outside. In one embodiment, the dopant in each source/drain pillar 218 is diffused to both sides along the corresponding annular channel pillar 112 to form the source/drain pillar 218 having two extension portions 219 .

Referring to FIG. 2E , the second film layer 106 of the stacked structure is replaced with a gate layer 126 . In one embodiment, the material of the gate layer 126 includes tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix ) or cobalt silicide ( _{CoSix )} . In addition, in other embodiments, a buffer layer and a barrier layer may also be formed between the gate layer 126 and the charge storage structure 110 . The material of the buffer layer is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxides, Lanthanide oxides or combinations thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

In one embodiment, the replacement step is performed when the second film layer 106 is a sacrificial layer (eg, a silicon nitride layer). However, the present invention is not limited thereto. In another embodiment, when the second film layer 106 is a gate layer (eg, a doped polysilicon layer), the replacement step can be omitted. So far, the fabrication of the plurality of memory cells MC2 of the present invention is completed.

In this embodiment, each memory cell MC2 includes a gate layer 126 arranged horizontally, an arc-shaped channel column 112 arranged vertically, a charge storage structure 110 located between the gate layer 126 and the arc-shaped channel column 112 , and Two source/drain pillars 218 at both ends of the arcuate channel pillar 112 . In this embodiment, the source/drain pillars 218 at the corresponding ends adjacent to the two of the plurality of arc-shaped channel pillars 112 are connected to each other. In this embodiment, the face-to-face memory cells MC2 are configured in mirror symmetry and share the source/drain poles 218 . Such a common and larger area source/drain pillar 218 helps to reduce resistance, and the subsequently formed contact plugs have larger landing areas. The memory cell MC2 of the present invention has an arc-shaped channel column, which can generate a curvature effect to enhance the operation flexibility of the program/erase memory cell, and can provide a longer channel length and better device performance.

In one embodiment, the three-dimensional flash memory device of the present invention may optionally include a conductive layer 124 as a heater to heat the gate stack structure, as shown in FIG. 2E . In one embodiment, the conductive layer 124 may be formed at the same time in the above-mentioned replacement step. The conductive layer 124 is disposed on the substrate, adjacent to and extending along the sidewall of the gate stack structure.

Referring to FIG. 2F, a plurality of conductive wires W are formed on the stacked structure to electrically connect the plurality of memory cells MC2. More specifically, the conductive wire W electrically connects the memory cells MC2 in the (N)th column and the (N+1)th column, where N is a positive integer. In one embodiment, each of the conductive lines W is a source line or a bit line according to design requirements. In one embodiment, the plurality of conductive wires W are electrically connected to the plurality of memory cells MC2 through the contact plugs 222 respectively. More specifically, the contact plugs 222 are electrically connected to the source/drain pillars 218 at corresponding ends adjacent to both of the plurality of arc-shaped channel pillars 112 . In one embodiment, the contact plugs 222 partially overlap the adjacent source/drain pillars 218 when viewed from above. So far, the fabrication of the three-dimensional flash memory device 20 of the present invention is completed.

3A to 3F are schematic top views of a manufacturing process of a three-dimensional flash memory device according to a third embodiment of the present invention. For the convenience of description, the following FIGS. 3A to 3F only show schematic top views of the second film layer 106 in the uppermost layer in the stacked structure, so as to clearly understand the corresponding relationship of each component. Furthermore, in the third embodiment, similar reference numerals are used for components that are similar in material or function to those of the first or second embodiment.

Referring to FIG. 3A, a stacked structure is formed on the substrate. In one embodiment, the stacked structure includes a plurality of first film layers and a plurality of second film layers 106 alternately stacked on the substrate. In one embodiment, the first layer is an insulating layer (eg, a silicon oxide layer), and the second layer is a sacrificial layer (eg, a silicon nitride layer). However, the present invention is not limited thereto. In another embodiment, the first film layer is an insulating layer (eg, a silicon oxide layer), and the second film layer is a gate layer (eg, a doped polysilicon layer).

Next, a patterning process is performed to form a plurality of columnar openings H1 penetrating the stacked structure. In this embodiment, from the above perspective, the columnar opening H1 has an elliptical outline, but the present invention is not limited thereto. In other embodiments, the cylindrical opening H1 may have contours of other shapes, such as circular, elliptical-like, or polygonal. In one embodiment, the column openings H1 of adjacent columns are configured to be aligned with each other. In another embodiment, the column openings H1 of adjacent columns are arranged to be staggered with each other.

Then, the charge storage structure 110 is formed on the sidewall of the columnar opening H1. In the present embodiment, each of the charge storage structures 110 has an annular profile from the above perspective. In one embodiment, the charge storage structure 110 is an oxide-nitride-oxide (ONO) composite layer. For example, the charge storage structure 110 includes a silicon oxide layer 110a, a silicon nitride layer 110b, and a silicon oxide layer 110c sequentially stacked on the sidewalls of the columnar openings Ha. In one embodiment, the charge storage structure 110 is formed on the sidewall and bottom surface of the column opening H1. However, the present invention is not limited thereto. In another embodiment, the charge storage structure 110 is formed only on the sidewall of the column opening H1.

After that, channel pillars 112 are formed on the charge storage structure 110 in the pillar opening H1. In the present embodiment, each of the channel posts 112 has an annular profile from the above perspective. In one embodiment, the material of the channel pillars 112 includes undoped polysilicon. In one embodiment, the channel pillars 112 are only formed on the sidewalls of each pillar-shaped opening H1, and the charge storage structure 110 at the bottom of the pillar-shaped opening H1 is exposed.

Next, the insulating pillars 105 are filled in the pillar-shaped openings H1. In one embodiment, the material of the insulating pillars 105 includes silicon oxide. In one embodiment, the top surfaces of the insulating pillars 105 are substantially flush with the top surfaces of the stacked structure.

Referring to FIG. 3B , a patterning process is performed to form trenches T1 penetrating the stack structure, the charge storage structure 110 , the channel pillars 112 and the insulating pillars 105 . In one embodiment, during the patterning process, part of the substrate is also removed at the same time, so that the trench T1 extends into the substrate. In one embodiment, the sidewalls of the trenches T1 are substantially vertical.

Referring to FIG. 3C , an etching process is performed to remove part of the channel pillars 112 exposed by the trenches T1 to form openings H2 at the ends of the remaining channel pillars 112 . In one embodiment, two openings H2 are provided at the end of each channel column 112 .

Referring to FIG. 3D, a source/drain material layer 317 is formed on the surface of the trench T1, and the source/drain material layer 317 fills the opening H2. In one embodiment, the material of the source/drain material layer 317 includes doped polysilicon.

Referring to FIG. 3E , a portion of the source/drain material layer 317 is removed to form a plurality of source/drain pillars 318 . More specifically, the source/drain material layer 317 on the surface of the trench T1 is removed, leaving the source/drain material layer 317 in the opening H2 as the source/drain pillar 318 . In one embodiment, two source/drain columns 318 are disposed at the ends of each channel column 112 .

Next, an isolation layer 107 is formed in the trench T1. In one embodiment, the material of the isolation layer 107 includes silicon oxide. In one embodiment, the top surface of the isolation layer 107 is substantially flush with the top surface of the stacked structure.

Referring to FIG. 3F , the second film layer 106 of the stacked structure is replaced with a gate layer 126 . In one embodiment, the material of the gate layer 126 includes tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix ) or cobalt silicide ( _{CoSix )} . In addition, in other embodiments, a buffer layer and a barrier layer may also be formed between the gate layer 126 and the charge storage structure 110 . The material of the buffer layer is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxides, Lanthanide oxides or combinations thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

In one embodiment, the replacement step is performed when the second film layer 106 is a sacrificial layer (eg, a silicon nitride layer). However, the present invention is not limited thereto. In another embodiment, when the second film layer 106 is a gate layer (eg, a doped polysilicon layer), the replacement step can be omitted. So far, the fabrication of the plurality of memory cells MC3 of the present invention is completed.

In this embodiment, each memory cell MC3 includes a gate layer 126 arranged horizontally, an arc-shaped channel column 112 arranged vertically, a charge storage structure 110 located between the gate layer 126 and the arc-shaped channel column 112 , and Two source/drain posts 318 at both ends of the arcuate channel post 112 . In this embodiment, the source/drain pillars 318 at the corresponding ends of the plurality of arc-shaped channel pillars 112 are separated from each other. In this embodiment, the face-to-face memory cells MC3 are configured in mirror symmetry, and can be operated separately or together according to design requirements. The memory cell MC3 of the present invention has an arc-shaped channel column, which can generate a curvature effect to enhance the operation flexibility of the program/erase memory cell, and can provide a longer channel length and better device performance.

In one embodiment, the three-dimensional flash memory device of the present invention may optionally include a conductive layer 124 as a heater to heat the gate stack structure, as shown in FIG. 3F . In one embodiment, the conductive layer 124 may be formed at the same time in the above-mentioned replacement step. The conductive layer 124 is disposed on the substrate, adjacent to and extending along the sidewall of the gate stack structure.

Please continue to refer to FIG. 3F , a plurality of conductive wires W are formed on the stack structure 102 to electrically connect the plurality of memory cells MC3 . More specifically, the conductive wire W electrically connects the memory cells MC3 in the (N)th column and the (N+1)th column, where N is a positive integer. In one embodiment, each of the conductive lines W is a source line or a bit line according to design requirements. In one embodiment, the plurality of conductive wires W are respectively electrically connected to the plurality of memory cells MC3 through the contact plugs 320 . More specifically, the contact plugs 320 are electrically connected to the source/drain posts 318 at corresponding ends adjacent to the two of the plurality of arc-shaped channel posts 112 . In one embodiment, the contact plug 320 partially overlaps the adjacent source/drain pillar 318 from a top view. So far, the fabrication of the three-dimensional flash memory device 30 of the present invention is completed.

In addition, the three-dimensional flash memory device of the present invention can also be modified according to the above-mentioned three structures. Several structures are listed below for description, but are not intended to limit the present invention. More specifically, as long as the memory cell has an arc-shaped channel column, which produces a curvature effect to provide a longer channel length and better device performance, such a memory cell is considered to fall within the spirit of the present invention with the category.

4 is a schematic top view of a three-dimensional flash memory device according to a fourth embodiment of the present invention. The three-dimensional flash memory device 40 of FIG. 4 is similar to the three-dimensional flash memory device 20 of FIG. 2 , and the differences will be described below, and the same parts will not be repeated. In the three-dimensional flash memory device 20 of FIG. 2, the source/drain pillars 218 at the ends of adjacent arc-shaped channel pillars of the same column are arranged to be spaced apart from each other. However, in the three-dimensional flash memory device 40 of FIG. 4, the source/drain pillars 218 at the ends of adjacent arc-shaped channel pillars of the same column are arranged to be connected to each other. Since the adjacent memory cells in the same row share the connected source/drain pillars 218, such a larger area of the source/drain pillars 218 helps to reduce the resistance value, and the contact plugs formed subsequently have relatively high resistance. A large landing area. This design can also allow for more pitch reductions.

5 is a schematic top view of a three-dimensional flash memory device according to a fifth embodiment of the present invention. The three-dimensional flash memory device 50 of FIG. 5 is similar to the three-dimensional flash memory device 20 of FIG. 2 , and the differences will be described below, and the same parts will not be repeated. In the three-dimensional flash memory device 20 of FIG. 2, the source/drain pillars 218 at the ends of the arc-shaped channel pillars of the same column are arranged to be aligned with each other. However, in the three-dimensional flash memory device 50 of FIG. 5, the source/drain pillars 218 at the ends of the arc-shaped channel pillars of the same column are arranged to be staggered with each other. Such a staggered configuration of the source/drain pillars 218 may provide more process margin for the overlying contact plugs 222 . Furthermore, such asymmetrical or twisted source/drain pillars 218 help to reduce gate induce drain leakage (GIDL).

6 is a schematic top view of a three-dimensional flash memory device according to a sixth embodiment of the present invention. The three-dimensional flash memory device 60 of FIG. 6 is similar to the three-dimensional flash memory device 50 of FIG. 5 , and the differences will be described below, and the same parts will not be repeated. In the three-dimensional flash memory device 50 of FIG. 5 , the extending direction of the gate layer 126 and the extending direction of the overlying conductive wires W are substantially perpendicular to each other. More specifically, as shown in FIG. 5 , the included angle between the extending direction of the gate layer 126 and the extending direction of the overlying conductive wire W is about 90 degrees. However, in the three-dimensional flash memory device 60 of FIG. 6 , the extending direction of the gate layer 126 and the extending direction of the overlying conductive wires W are not perpendicular. More specifically, as shown in FIG. 6 , the included angle between the extending direction of the gate layer 126 and the extending direction of the overlying conductive wire W is less than 90 degrees. The staggered configuration of the source/drain pillars 218 may provide more process margin for the overlying contact plugs 222 and help reduce gate induced drain leakage current (GIDL). Furthermore, such a tilted layout can provide greater process flexibility.

7A is a schematic cross-sectional view of a partial three-dimensional flash memory device according to an embodiment of the present invention. 7B is a schematic cross-sectional view of a partial three-dimensional flash memory device according to another embodiment of the present invention. The cross-sectional configuration diagrams of FIGS. 7A and 7B can be applied to any structure of the three-dimensional flash memory device 10/20/30/40/50/60 of the present invention.

Referring to FIG. 7A , the side surface of the gate stack structure is substantially vertical, and includes a plurality of first film layers 104 (eg, insulating layers) and a plurality of gate layers 126 arranged alternately, wherein the ends of the first film layers 104 are arranged alternately. are substantially aligned with the ends of the gate layer 126 . The charge storage structure 110 is continuous in its extending direction, and the sidewall of the charge storage structure 110 has a substantially vertical cross-section. In addition, the channel column 112 is continuous in its extending direction, and the side wall of the channel column 112 has a substantially vertical cross section.

Referring to FIG. 7B , the side surface of the gate stack structure is wavy, and includes a plurality of first film layers 104 (eg, insulating layers) and a plurality of gate layers 126 arranged alternately, wherein the end of the first film layer 104 is Protruding from the end of the gate layer 126 . The charge storage structure 110 is continuous in its extending direction, and the sidewall of the charge storage structure 110 has a wavy cross section. In addition, the channel pillars 112 are discontinuous in their extending directions, and the plurality of channel portions of the channel pillars only correspond to the plurality of gate layers 126 . More specifically, each channel column 112 is not integral in its extending direction, but is divided into a plurality of disconnected parts. In other words, the formed channel column 112 includes a plurality of channel portions 112a, 112b, 112c, 112d, and one channel portion is located between two adjacent first membrane layers 104 and is only connected to one gate of the adjacent stacked structure. The pole layer 126 corresponds. That is, the channel portion 112a, the channel portion 112b, the channel portion 112c, and the channel portion 112d are sequentially arranged in the extending direction of the channel column 112 without contacting each other. This configuration confines the charge storage structure 110 and the channel pillar 112 to the side of the corresponding gate layer 126 , which can greatly reduce leakage current and provide better gate control and programming efficiency.

Hereinafter, the structure of the three-dimensional flash memory device of the present invention will be described with reference to FIGS. 1A to 7B .

The three-dimensional flash memory device 10/20/30/40/50/60 of the present invention includes a gate stack structure, a plurality of spaced arc-shaped channel pillars 112, a plurality of source/drain pillars 118/218/318, and Charge storage structure 110 . The gate stack structure is disposed on the substrate 100 and includes a plurality of gate layers 126 that are electrically insulated from each other. A plurality of spaced arc-shaped channel pillars 112 are disposed on the substrate 100 and penetrate the gate stack structure. A plurality of source/drain pillars 118/218/318 are disposed on the substrate 100 and pass through the gate stack structure, wherein two ends of each of the plurality of arc-shaped channel pillars 112 are respectively Two source/drain posts 118/218/318 are configured. A charge storage structure 110 is disposed between each of the plurality of gate layers 126 and the corresponding arc-shaped channel pillar 112 .

In the three-dimensional flash memory device 10/20/30/40 of the present invention, two adjacent ones of the arc-shaped channel pillars 112 are configured in mirror symmetry.

In the three-dimensional flash memory device 50/60 of the present invention, two adjacent ones of the arc-shaped channel pillars 112 are not mirror-symmetrical.

In the three-dimensional flash memory device 10/20/30/40/50/60 of the present invention, an insulating column 114/113/105 is disposed between two adjacent ones of the arc-shaped channel columns 112 .

In the three-dimensional flash memory device 10 of the present invention, the plurality of insulating pillars 114 in different columns are arranged in a staggered manner. In the three-dimensional flash memory device 20/30 of the present invention, the plurality of insulating pillars 113/105 in different columns are arranged in alignment. However, the present invention is not limited thereto. In the three-dimensional flash memory device 10/20/30/40/50/60 of the present invention, a plurality of insulating pillars in different columns can be designed to be aligned or staggered according to layout requirements.

In the three-dimensional flash memory device 10/30 of the present invention, the source/drain pillars 118/318 at the corresponding ends of the plurality of arc-shaped channel pillars 112 adjacent to each other separate. In the three-dimensional flash memory device 10/30 of the present invention, a contact plug 122/320 is electrically connected to all of the ends of the plurality of arc-shaped channel pillars 112 adjacent to both of them. The source/drain posts 118/318 are described.

In the three-dimensional flash memory device 20/40/50/60 of the present invention, the source/drain pillars at the corresponding ends of the plurality of arc-shaped channel pillars 112 are adjacent to the two 218 are connected to each other. In the three-dimensional flash memory devices 20/40/50/60 of the present invention, a contact plug 222 is electrically connected to the connected source/drain posts 218 .

In the three-dimensional flash memory device 10/20/30/40/50/60 of the present invention, the contact plug 122/222/320 and a conductive wire W1/W2/W on the gate stack structure Electrical connection.

In the three-dimensional flash memory device 10/20/30/40/50/60 of the present invention, the conductive lines W1/W2/W include source lines or bit lines.

In the three-dimensional flash memory devices 10/20/30/40/50/60 of the present invention, the sidewalls of each of the charge storage structures 110 have a substantially smooth profile (see FIG. 7A ).

In the three-dimensional flash memory devices 10/20/30/40/50/60 of the present invention, the sidewalls of each of the charge storage structures 110 have a wavy profile (see FIG. 7B ).

In the three-dimensional flash memory devices 10/20/30/40/50/60 of the present invention, each of the arc-shaped channel pillars 112 is continuous in its extending direction (see FIG. 7A ).

In the three-dimensional flash memory device 10/20/30/40/50/60 of the present invention, each of the plurality of arc-shaped channel pillars 112 is discontinuous in its extending direction, and the arc The plurality of channel portions of the shaped channel pillars 112 correspond only to the plurality of gate layers 126 (see FIG. 7B ).

In the three-dimensional flash memory device 10/20/30/40 of the present invention, both ends of each of the plurality of arc-shaped channel pillars 112 are at the same distance from the corresponding gate layer 126 .

In the three-dimensional flash memory device 50/60 of the present invention, the distances between the two ends of each of the plurality of arc-shaped channel pillars 112 from the corresponding gate layer are unequal.

In the three-dimensional flash memory device 10/20/30/40/50/60 of the present invention, the material of the plurality of arc-shaped channel pillars 112 includes undoped polysilicon, and the plurality of source/drain electrodes The material of the pillars includes doped polysilicon.

In the three-dimensional flash memory device 10 of the present invention, each of the plurality of source/drain pillars 118 is L-shaped when viewed from above. In the three-dimensional flash memory device 20/50/60 of the present invention, from a top view, the shapes of each of the plurality of source/drain pillars 218 are circular/ring-like and arc-like The combination. In the three-dimensional flash memory device 30 of the present invention, each of the plurality of source/drain pillars 318 is arc-shaped when viewed from above. In the above-mentioned embodiments, the specific shapes of the source/drain pillars are only used for illustration, but are not intended to limit the present invention. In other embodiments, the source/drain posts may have other shapes, such as I-shaped, polygonal, irregular, or combinations thereof.

To sum up, in the three-dimensional flash memory device of the present invention, the memory cells have arc-shaped channel columns, which will generate a curvature effect to enhance the operation desire of programming/erasing the memory cells, and can Provides longer channel lengths and better element performance. In addition, the three-dimensional flash memory device of the present invention can have high integration and high area utilization, and meet the requirement of high operating speed.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 20, 30, 40, 50, 60: 3D flash memory elements MC1, MC2, MC3: memory unit 100: base 102: Stacked Structure 103, 107, 120: isolation layer 104: The first film layer 105, 113, 114: insulating column 106: Second film layer 107: Rectangular opening 108, H1, Ha, Hb: cylindrical opening 110: Charge Storage Structure 110a, 110c: silicon oxide layer 110b: Silicon nitride layer 112: Channel column 112a, 112b, 112c, 112d: channel section 118, 218, 318: source/drain posts 122, 222, 320: contact plugs 124: Conductive layer 126: gate layer 219: Extensions 317: source/drain material layer H2: Opening T, T1, T2, Ta: trenches W, W1, W2: Conductive wire

1A to 1I illustrate a manufacturing process of a three-dimensional flash memory device according to a first embodiment of the present invention, wherein FIGS. 1A to 1F are three-dimensional schematic diagrams, and FIGS. 1G to 1I are schematic top views. 2A to 2F are schematic top views of a manufacturing process of a three-dimensional flash memory device according to a second embodiment of the present invention. 3A to 3F are schematic top views of a manufacturing process of a three-dimensional flash memory device according to a third embodiment of the present invention. 4 is a schematic top view of a three-dimensional flash memory device according to a fourth embodiment of the present invention. 5 is a schematic top view of a three-dimensional flash memory device according to a fifth embodiment of the present invention. 6 is a schematic top view of a three-dimensional flash memory device according to a sixth embodiment of the present invention. 7A is a schematic cross-sectional view of a partial three-dimensional flash memory device according to an embodiment of the present invention. 7B is a schematic cross-sectional view of a partial three-dimensional flash memory device according to another embodiment of the present invention.

10: 3D Flash Memory Device

107: Rectangular opening

108: Column opening

110: Charge Storage Structure

112: Channel column

114: Insulation column

118: source/drain column A

120: isolation layer

122: Contact plug

124: Conductive layer

126: gate layer

W1, W2: Conductive wire

T: Ditch

Claims (20)

A three-dimensional flash memory device, comprising: The gate stack structure is arranged on the substrate and includes a plurality of gate layers electrically insulated from each other; a plurality of separate arc-shaped channel pillars disposed on the substrate and located in the gate stack structure; a plurality of source/drain pillars disposed on the substrate and passing through the gate stack structure, wherein two source electrodes are respectively disposed at two ends of each of the plurality of arc-shaped channel pillars /drain column; and A charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel column. The three-dimensional flash memory device of claim 1, wherein two adjacent ones of the arc-shaped channel pillars are configured in mirror symmetry. The three-dimensional flash memory device of claim 1, wherein two adjacent ones of the arc-shaped channel pillars are non-mirror-symmetrically configured. The three-dimensional flash memory device of claim 1, wherein an insulating column is disposed between two adjacent ones of the arc-shaped channel columns. The three-dimensional flash memory device of claim 4, wherein the plurality of insulating pillars in different columns are arranged in a staggered manner. The three-dimensional flash memory device of claim 4, wherein the plurality of insulating pillars in different columns are in an aligned configuration. The three-dimensional flash memory device of claim 1, wherein the source/drain pillars at the corresponding ends of adjacent two of the plurality of arc-shaped channel pillars are separated from each other. The three-dimensional flash memory device as claimed in claim 7, wherein a contact plug is electrically connected to the source/s at the corresponding ends of the plurality of arc-shaped channel pillars adjacent to the two. Drain pole. The three-dimensional flash memory device of claim 8, wherein the contact plug is electrically connected to a conductive line on the gate stack structure. The three-dimensional flash memory device of claim 9, wherein the conductive lines comprise source lines or bit lines. The three-dimensional flash memory device of claim 1, wherein the source/drain pillars at the corresponding end portions of the plurality of arc-shaped channel pillars are in a mirror-symmetric configuration adjacent to the two. connected to each other. The three-dimensional flash memory device of claim 11, wherein a contact plug is electrically connected to the connected source/drain posts. The three-dimensional flash memory device of claim 1, wherein a sidewall of each of the charge storage structures has a substantially smooth profile. The three-dimensional flash memory device of claim 1, wherein a sidewall of each of the charge storage structures has a wavy profile. The three-dimensional flash memory device of claim 1, wherein each of the arc-shaped channel pillars is continuous in its extending direction. The three-dimensional flash memory device of claim 1, wherein each of the plurality of arc-shaped channel columns is discontinuous in its extending direction, and the plurality of channel portions of the arc-shaped channel columns are only corresponding to the plurality of gate layers. The three-dimensional flash memory device of claim 1, wherein both ends of each of the plurality of arc-shaped channel pillars are the same distance from the corresponding gate layer. The three-dimensional flash memory device of claim 1, wherein the distances between the two ends of each of the plurality of arc-shaped channel pillars are unequal from the corresponding gate layer. The three-dimensional flash memory device of claim 1, wherein the material of the plurality of arc-shaped channel pillars comprises undoped polysilicon, and the material of the plurality of source/drain pillars comprises doped polysilicon. The three-dimensional flash memory device of claim 1, wherein from a top view, each of the plurality of source/drain pillars is L-shaped, I-shaped, irregular, polygonal , circular, arcuate, annular or a combination thereof.

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