TW202145530A - Three-dimensional memory device and method for forming the same - Google Patents

Abstract

A three-dimensional (3D) memory device is disclosed, which includes a substrate, a peripheral circuit disposed on the substrate, a memory stack structure comprising a plurality of alternatingly stacked conductive layers and dielectric layers disposed on the peripheral circuit, a first semiconductor layer disposed on the memory stack structure, a second semiconductor layer disposed on the first semiconductor layer and contacting the first semiconductor layer, a plurality of channel structures vertically penetrating through the memory stack structure and the first semiconductor layer, and an isolation structure vertically penetrating through the memory stack structure, the first semiconductor layer and the second semiconductor layer.

Description

Three-dimensional memory device and method of making the same

The present invention relates to a semiconductor device, in particular to a three-dimensional memory device and a manufacturing method thereof.

With advances in process technology, circuit design, programming algorithms, and manufacturing processes, the dimensions of semiconductor devices such as memory devices have been gradually shrunk to smaller dimensions to achieve higher density. However, as the feature size of the planar memory cell approaches the lower limit, the process technology becomes more and more challenging and expensive, so that the storage density of the planar memory cell is limited.

Three-dimensional (3D) memory device architectures can address the density constraints of planar memory. The 3D memory element architecture includes a memory array and peripheral elements for controlling the transmission and reception of signals from the memory array.

The present invention aims to provide a three-dimensional (3D) memory device and a manufacturing method thereof.

A 3D memory device provided according to an embodiment of the present invention includes a substrate, a peripheral circuit on the substrate, and a memory stack including a plurality of staggered conductive layers on the peripheral circuit and a plurality of dielectric layers, a first semiconductor layer on the memory stack, a second semiconductor layer on and in contact with the first semiconductor layer, a plurality of channel structures, wherein each of the channel structures extends vertically through the memory stack and the first semiconductor layer, and an insulating structure extends vertically through the memory stack, the first semiconductor layer and the second semiconductor layer.

A 3D memory device according to another embodiment of the present invention includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a memory stack including interleaved conductive and dielectric layers, a doped semiconductor layer, a plurality of channel structures, wherein each of the channel structures extends vertically through the memory stack and extending into the doped semiconductor layer and electrically connected to the peripheral circuitry, and insulating structures extending vertically through the memory stack and the doped semiconductor layer and extending laterally to separate the channel structures into multiple block.

According to yet another embodiment of the present invention, a method for forming a 3D memory device is provided, the steps comprising forming a trench in a doped region on a first side of a substrate, followed by forming a trench over the doped region and the trench A sacrificial layer in and a dielectric stack on the sacrificial layer, then a channel structure is formed extending vertically through the dielectric stack and the sacrificial layer and into the doped region, followed by forming a channel structure extending vertically through the dielectric The dielectric stack is connected to the opening of the trench, and the sacrificial layer is then replaced through the opening to form a doped semiconductor layer between the doped region and the dielectric stack. Subsequently, insulating structures are formed in the openings and trenches. Next, the substrate is thinned from a second side of the substrate relative to the first side until the end of the insulating structure is reached and the doped regions are exposed.

According to yet another embodiment of the present invention, a method for forming a 3D memory device is provided, the steps include forming a peripheral circuit on a first substrate, forming a channel structure and an insulating structure on a first side of the second substrate, each The channel structure and the insulating structure extend vertically through the memory stack and the doped semiconductor layer on the second substrate and into the doped region on the first side of the second substrate. The first substrate and the second substrate are then bonded in a face-to-face manner so that the memory is stacked over the peripheral circuits. The second substrate is thinned from a second side of the second substrate relative to the first side until the end of the insulating structure is reached and the doped regions of the second substrate are exposed.

The specific configurations and arrangements of the following embodiments are only for the purpose of facilitating the description of the present invention, and are not intended to limit the present invention. Those skilled in the relevant art will appreciate that other configurations and arrangements may be used without departing from the spirit and scope of the present invention. It will be apparent to those skilled in the relevant art that the present invention may also find application in other applications.

It should be noted that references in the specification to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc. mean that the described embodiment may include a particular feature, structure, or characteristic, Not every embodiment, however, necessarily includes the particular feature, structure or characteristic. Additionally, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in conjunction with one embodiment, whether explicitly described or not, it is within the knowledge of those skilled in the relevant art to implement such feature, structure or characteristic in conjunction with other embodiments.

Generally, terms used herein can be understood, at least in part, by their usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may also be used to describe a combination of features, structures or characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a," "an," "the," or "the" may likewise be construed to express the singular or the plural, depending at least in part on the context. Additionally, the terms "based on", "depending on" are not limited to being understood to express an exclusive set of factors, but may allow for the presence of other factors not expressly described, again depending at least in part on the context.

It should be easily understood that the meanings of "on", "on" and "over" in the present invention should be construed in the broadest manner, so that "on" is not limited to "on" Directly on something", which can also include the meaning of "on something" with intervening features or layers. By the same token, "on" or "over" is not limited to the meaning of "over something" or "over something", but may also include "direct positions without intervening features or layers". The meaning of "on top of something" or "directly above something".

Furthermore, for ease of description, spatially relative terms such as "under", "below", "under", "above", "on" and the like may be used herein to describe the one shown in the figures The relationship of an element or feature to another element or feature(s). In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations of elements in use or in the steps. The element may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term "substrate" refers to the material upon which elements are fabricated and/or subsequent layers of material are disposed. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor elements are formed. Accordingly, unless otherwise indicated herein, semiconductor elements are typically formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material disposed on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic or sapphire wafer.

As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer has a "top side" and a "bottom side", where the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a "layer" can be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located in the area between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along a tapered surface. A substrate can be a layer, one or more layers can be included in the substrate, and/or one or more layers can be thereon, over and/or under it. Layers may include multiple layers. For example, the interconnect layer may include one or more conductive and contact layers in which contacts, interconnect lines, and/or vertical interconnect plugs (VIAs) are formed, and one or more dielectric layers.

As used herein, the terms "nominal/nominal", "nominal/nominal" refer to the expected or target value of a characteristic or parameter of a component or process step set during the design time of a product or process, and a high range of values above and/or below the expected value. The range of values can be due to slight variations in manufacturing process or tolerances. As used herein, the terms "about" or "approximately" or "substantially" represent a given amount of value that may vary based on the particular technology node associated with the subject semiconductor element. Based on a particular technology node, the terms "about" or "about" or "substantially" may refer to a value of a given amount that varies, for example, within 10-30% of the value (eg, ±10% of the value, ±10% of the value, ±10% of the value) 20% or ±30%).

As used herein, the term "three-dimensional memory device" refers to a string of memory cell transistors (referred to herein as "memory strings" or "memory strings") having a vertical orientation on a horizontally oriented substrate, such as NAND memory strings) such that the memory strings extend in a vertical direction with respect to the substrate. As used herein, the terms "vertical" or "perpendicularly" mean an orientation that is nominally perpendicular to a lateral surface of a substrate.

In some 3D memory devices, such as 3D NAND memory devices, slit openings, such as gate line slits (GLS), are used to deliver etchant and etchant during the gate replacement process when forming the memory stack. Pathway for reactive gases. However, as the level of the memory stack increases, the etching of slit openings with high aspect ratios becomes more challenging. In particular, when the slit openings extend laterally over both the stepped region and the core array region of the memory stack with different layer structures, the variation of the slotting of the slit openings in the different regions becomes difficult to control. For example, the etch depth of the slit opening may be greater in the stepped region than in the core array region, causing damage to the substrate in the stepped region. For 3D NAND memory devices with semiconductor plugs that are selectively grown at the sidewalls of the channel structure (also known as "Sidewall Selective Epitaxial Growth (SEG)"), the problem of gouge variation may be more pronounced, Therefore, strict requirements are required for gouge changes.

In view of this, various embodiments of the present disclosure provide a 3D memory device capable of compensating for gouge variation and a method for fabricating the same. The present invention includes trenches with slit openings aligned laterally and filled with a sacrificial material (eg, polysilicon) that can act as an etch stop when forming the slit openings and as a buffer to balance the flow between the core array area and the stepped area. Etch loading effects, compensating for gouge variations among different regions. In some embodiments, the trenches and slit openings are filled with a dielectric material to form insulating structures. The end of the insulating structure can be used as a stop layer in the backside thinning process of the substrate, such as chemical mechanical polishing (CMP), so that the backside thinning process of the substrate can be automatically stopped, so that the substrate can have a uniform thickness after thinning. Thickness. Thereby, the 3D memory device of the present invention can have a simplified manufacturing process, which contributes to an increase in yield.

Figure 1 shows a schematic cross-sectional view of an exemplary 3D memory device in accordance with some embodiments of this disclosure. In some embodiments, the 3D memory device 100 is a bonded wafer that includes a first semiconductor structure 102 and a second semiconductor structure 104 stacked over the first semiconductor structure 102 . According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are connected by a bonding interface 106 therebetween. As shown in FIG. 1, the first semiconductor structure 102 may include a substrate 101, which may include silicon (eg, monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator ( SOI) or any other suitable material.

The first semiconductor structure 102 of the 3D memory device 100 may include peripheral circuits 108 on the substrate 101 . It should be noted that, FIG. 1 shows the coordinate axes of the x-direction, the y-direction and the z-direction to illustrate the spatial relationship of the components in the 3D memory device 100 . The substrate 101 includes two lateral surfaces extending laterally along the x-y plane, namely a top surface on the front side of the wafer and a bottom surface on the back side opposite the front side of the wafer. In some embodiments, the x-direction and the y-direction are two orthogonal directions in the wafer plane. In some embodiments, the x direction is the word line direction and the y direction is the bit line direction. The z direction is perpendicular to the x and y directions. As used herein, a feature (eg, layer or structure) is the lowest plane of a three-dimensional memory element (eg, three-dimensional memory element 100 ) when a substrate (eg, substrate 101 ) is in the Z-direction (ie, vertical direction) In the middle, the position in the Z direction relative to the substrate of the three-dimensional memory device (such as the substrate 101) determines whether it is “on” or “between” another component (such as a layer or structure) of the three-dimensional memory device. above" or "below". The same concepts described above for describing spatial relationships can be applied throughout the present disclosure.

In some embodiments, peripheral circuitry 108 is configured to control and sense 3D memory element 100 . Peripheral circuitry 108 may be any suitable digital, analog, and/or mixed-signal control and sensing circuitry for facilitating operation of 3D memory element 100, including but not limited to page buffers, decoders such as row decoders and column decoders devices), read amplifiers, drivers (such as word line drivers), charge pumps, current or voltage references, or any active or passive component of a circuit (such as transistors, diodes, resistors, or capacitors). Peripheral circuitry 108 may include transistors formed “on” substrate 101 , wherein all or part of the transistors may be located in substrate 101 (eg, under the top surface of substrate 101 ) and/or formed directly on substrate 101 . Isolation regions (eg, shallow trench isolation structures (STIs)) and doped regions (eg, source and drain regions of transistors) may also be formed in the substrate 101 . According to some embodiments, the transistors may be fabricated using advanced logic processes (eg, 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm) , 2 nm, etc.) high-speed transistors. It should be appreciated that, in some embodiments, peripheral circuits 108 may also include any other circuits compatible with advanced logic processes, including logic circuits (eg, processors and programmable logic elements (PLDs)) or memory circuits (eg, static random access memory (SRAM) and dynamic random access memory (DRAM)).

In some embodiments, the first semiconductor structure 102 of the 3D memory element 100 also includes an interconnect layer (not shown) overlying the peripheral circuit 108 to transmit electrical signals to and from the peripheral circuit 108 electric signal. The interconnect layer may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect plug (VIA) contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as mid-end of line (MEOL) interconnects and back-end of line (BEOL) interconnects. The interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers"), and interconnect lines and VIA contacts may be formed on one or more layers. in an interlayer dielectric layer. In other words, the interconnect layer may include interconnect lines and VIA contacts in multiple interlayer dielectric layers. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials, such as may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof . The interlayer dielectric layers in the interconnect layers may include dielectric materials such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof .

As shown in FIG. 1 , the first semiconductor structure 102 of the 3D memory device 100 may also include a bonding layer 110 at the bonding interface 106 and above the interconnect layer and peripheral circuitry 108 . The bonding layer 110 may include a plurality of bonding contacts 111 and a dielectric for electrically isolating the bonding contacts 111 . Bonding contacts 111 may include conductive materials, such as, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. Other regions of the bonding layer 110 may be formed of dielectrics such as including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 111 in the bonding layer 110 and the surrounding dielectric can be used for hybrid bonding.

Similarly, as shown in FIG. 1 , the second semiconductor structure 104 of the 3D memory device 100 may further include a bonding layer 112 overlying the bonding layer 110 of the first semiconductor structure 102 and the bonding interface 106 . The bonding layer 112 may include a plurality of bonding contacts 113 and a dielectric for electrically isolating the bonding contacts 113 . The bond contacts 113 may comprise conductive materials such as, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of the bonding layer 112 may be formed of dielectrics such as including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bond contacts 113 in bonding layer 112 and surrounding dielectrics can be used for hybrid bonding. According to some embodiments, the bond contacts 113 are in contact with the bond contacts 111 at the bond interface 106 .

As described in more detail below, the second semiconductor structure 104 may be bonded on top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106 . In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded together by hybrid bonding (also referred to as "metal/dielectric hybrid bonding"), including Bonding interface 106 between bonding layer 110 and bonding layer 112 . Hybrid bonding is a direct bonding technique (eg, bonds formed between surfaces without the use of interlayers such as solder or adhesives) and can result in both metal-metal bonding and dielectric-dielectric bonding . In some embodiments, the bonding interface 106 is where the bonding layers 112 and 110 meet and bond. In practice, the bonding interface 106 may be a layer having a thickness that includes the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104 .

In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) overlying the bonding layer 112 for transmitting electrical signals. The interconnect layer may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer may also include one or more interlayer dielectric layers in which interconnect lines and VIA contacts may be formed. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials such as, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The interlayer dielectric layers in the interconnect layers may include dielectric materials such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, the 3D memory device 100 is a NAND flash memory device that includes memory cells arranged in an array of NAND memory strings. As shown in FIG. 1 , the second semiconductor structure 104 of the 3D memory device 100 may comprise an array of NAND memory strings strung together by channel structures 124 . As shown in FIG. 1 , each channel structure 124 may extend vertically through a plurality of material layer pairs, each material layer pair including a conductive layer 116 and a dielectric layer 118 . The conductive layers 116 and the dielectric layers 118 are alternately arranged to form the memory stack 114 . In the memory stack 114, a set of layer pairs composed of a conductive layer 116 and a dielectric layer 118 is also referred to as a level of the memory stack 114, and the number of layer pairs included in the memory stack 114 ( For example, 32, 64, 96, 128, 160, 192, 224, 256 levels or more) determines the number of memory cells in the 3D memory device 100 . It should be appreciated that in some embodiments, the memory stack 114 may have a multi-stack architecture (not shown) that includes multiple memory stacks stacked on top of each other. The number of pairs of conductive layers 116 and dielectric layers 118 in each memory stack may be the same or different.

The memory stack 114 may include a plurality of alternating conductive layers 116 and dielectric layers 118 . Conductive layers 116 and dielectric layers 118 in memory stack 114 may alternate in a vertical direction. In other words, other than the layers at the top or bottom of the memory stack 114 , the sides of each conductive layer 116 may be adjoined by two dielectric layers 118 , and the sides of each dielectric layer 118 may be The two conductive layers 116 are contiguous. The conductive layer 116 may include a conductive material such as, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 116 may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrodes of the conductive layer 116 may serve as word lines of the 3D memory device 100, extending laterally in the memory stack 114 and terminating at one or more stepped structures. The dielectric layer 118 may include a dielectric material such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. It should be understood that the stepped structure shown in FIG. 1 is for illustrative purposes only, and is not intended to represent or limit the actual arrangement of the stepped regions in the 3D memory device 100 of the present invention.

As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 may further include a first semiconductor layer 120 over the memory stack 114 and a first semiconductor layer 120 overlying the first semiconductor layer 120 and connected to the first semiconductor layer 120 is in contact with the second semiconductor layer 122 . The first semiconductor layer 120 may be an example of "Sidewall Selective Epitaxial Growth (SEG)" as previously described. In some embodiments, the lateral dimension of the second semiconductor layer 122 may be larger than the lateral dimension of the first semiconductor layer 120 in the y-direction and/or the x-direction (also referred to as the lateral direction). In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 is a doped semiconductor layer, such as a silicon layer with an N-type dopant or a P-type dopant. Accordingly, the first semiconductor layer 120 and the second semiconductor layer 122 may be generally referred to as doped semiconductor layers overlying the memory stack 114 . It should be understood that the doping concentrations in the first semiconductor layer 120 and the second semiconductor layer 122 may be the same or different.

In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 is an N-type doped semiconductor layer, eg, doped with an N-type dopant, eg, doped with phosphorus (P), A silicon layer of arsenic (Ar) or antimony (Sb), these dopants provide free electrons to increase the conductivity of the intrinsic semiconductor. In some embodiments, the second semiconductor layer 122 may include an N-type well region. That is, the second semiconductor layer 122 may be a region of the substrate doped with an N-type dopant (eg, P, As, or Sb). According to some embodiments, the first semiconductor layer 120 may include polysilicon, such as N-type doped polysilicon. As described in detail below, the first semiconductor layer 120 may be formed over the silicon substrate through a thin film deposition process and/or an epitaxial growth process. Differently, according to some embodiments, the second semiconductor layer 122 may include single crystal silicon, such as N-type doped single crystal silicon. As described in more detail below, the second semiconductor layer 122 may be formed by implanting an N-type dopant into a silicon substrate having single crystal silicon. In some embodiments, the doped semiconductor layer may include a first N-type doped semiconductor layer 120 including polysilicon and a second N-type doped semiconductor layer 122 including monocrystalline silicon.

In some embodiments, the first semiconductor layer 120 is an N-type doped semiconductor layer, such as a silicon layer doped with an N-type dopant (eg, P, Ar, or Sb), and the second semiconductor layer 122 is a P-type Doped semiconductor layers, such as silicon layers doped with P-type dopants such as boron (B), gallium (Ga), or aluminum (Al), the intrinsic semiconductor generates valence electrons called "holes" the absence of. In some embodiments, the second semiconductor layer 122 includes a P-type well region. That is, the second semiconductor layer 122 may be a region in the substrate doped with a P-type dopant (eg, B, Ga, or Al). According to some embodiments, the first semiconductor layer 120 includes polysilicon, such as N-type doped polysilicon. As described in more detail below, the first semiconductor layer 120 may be formed over the silicon substrate through a thin film deposition process and/or an epitaxial growth process. Differently, according to some embodiments, the second semiconductor layer 122 includes single crystal silicon, such as P-type doped single crystal silicon. As described in more detail below, the second semiconductor layer 122 may be formed by implanting a P-type dopant into a silicon substrate having single crystal silicon. In some embodiments, the doped semiconductor layer includes an N-type doped semiconductor layer 120 comprising polysilicon and a P-type doped semiconductor layer 122 comprising monocrystalline silicon.

In some embodiments, each channel structure 124 includes a channel hole filled with a semiconductor layer (eg, as semiconductor channel 128 ) and a composite dielectric layer (eg, as storage film 126 ). In some embodiments, the semiconductor channel 128 includes silicon, such as amorphous silicon, polysilicon, or monocrystalline silicon. In some embodiments, the storage film 126 is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a blocking layer. The remaining space of the channel structure 124 may be partially or fully filled with a fill layer including a dielectric material such as silicon oxide and/or air gaps. The channel structure 124 may have a cylindrical shape (eg, a cylindrical shape). According to some embodiments, the filling layer, the semiconductor channel 128 , the tunneling layer of the storage film 126 , the storage layer, and the barrier layer are sequentially disposed along the radial direction from the center of the cylinder toward the outer surface of the cylinder. In some embodiments, the tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, the storage film 126 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, the channel structure 124 also includes a channel plug 129 in the bottom of the channel structure 124 (eg, at the lower end). As used herein, when the substrate 101 is in the lowermost plane of the 3D memory device 100, the "upper end" of a feature (eg, channel structure 124) is the end that is further away from the substrate 101 in the z-direction, the feature (eg, channel structure 124) The "lower end" of 124) is the end that is closer to the substrate 101 in the z-direction. The channel plug 129 may include a semiconductor material (eg, polysilicon). In some embodiments, the channel plug 129 acts as the drain of the NAND memory string.

As shown in FIG. 1, each channel structure 124 may extend vertically through the interleaved conductive layers 116 and dielectric layers 118 of the memory stack 114 and the first semiconductor layer 120 (eg, an N-type doped semiconductor layer ( For example N-type doped polysilicon layer)). In some embodiments, the first semiconductor layer 120 surrounds a portion of the channel structure 124 and is in contact with the semiconductor channel 128 comprising polysilicon. That is, according to some embodiments, the storage film 126 is separated at a portion adjacent to the channel structure 124 of the first semiconductor layer 120 to expose the semiconductor channel 128 so that the semiconductor channel 128 is in contact with the surrounding first semiconductor layer 120 . As a result, the first semiconductor layer 120 surrounding and in contact with the semiconductor channel 128 may serve as a "sidewall semiconductor plug/SEG" for the channel structure 124 instead of a "bottom semiconductor plug/SEG".

In some embodiments, each channel structure 124 may extend vertically further into the second semiconductor layer 122 (eg, an N-type doped or P-type doped semiconductor layer (eg, an N-type doped or P-type doped monocrystalline silicon layer) layer)) inside. That is, according to some embodiments, each channel structure 124 extends vertically through the memory stack 114 and into the doped semiconductor layers (including the first semiconductor layer 120 and the second semiconductor layer 122 ). As shown in FIG. 1 , according to some embodiments, the top (eg, upper end) of the channel structure 124 is in the second semiconductor layer 122 . In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 is an N-type doped semiconductor layer for gate induced drain leakage (GIDL) assisted body biasing for erase operations become possible. The GIDL bias around the source select gates of the NAND memory strings can generate hole currents into the NAND memory strings to raise the body potential for erase operations. In some embodiments, the first semiconductor layer 120 and the second semiconductor layer 122 are N-type doped semiconductor layers and P-type doped semiconductor layers, respectively, to enable mass erase operations, wherein the second semiconductor layer 122 is A P-well region that provides holes for NAND memory strings for data erasure.

As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 may further include insulating structures 130, each insulating structure 130 extending vertically through the interleaved conductive layers 116 and the dielectric of the memory stack 114 layer 118 , first semiconductor layer 120 and second semiconductor layer 122 . In some embodiments, the insulating structure 130 extends further through the doped semiconductor layer including the first semiconductor layer 120 and the second semiconductor layer 122 . As described in more detail below with respect to the fabrication process, the insulating structure 130 may be used as a stop layer to automatically stop a backside thinning process (eg, a CMP process) on the substrate on which the memory stack 114 is formed (including the second semiconductor layer 122 ). . As a result, according to some embodiments, the upper end of the insulating structure 130 is flush with the top surface of the second semiconductor layer 122, which is the remainder of the thinned substrate. In some embodiments, the upper end of the insulating structure 130 is above the upper end of each channel structure 124 . This design ensures that the backside thinning process can be stopped by the insulating structure 130 before reaching the upper end of each channel structure 124 . It should be appreciated that in some examples, the upper ends of the insulating structures 130 may be flush with the upper ends of the one or more channel structures 124 . Each insulating structure 130 may also extend vertically (eg, in the word line direction, or in the x-direction in FIG. 1 ) to divide the channel structures 124 into a plurality of blocks. That is, the memory stack 114 and the array of channel structures 124 therein may be divided into a plurality of memory blocks by the insulating structure 130 .

According to some embodiments, unlike slit structures in some 3D NAND memory elements that include front-side source contacts, insulating structure 130 does not include any contacts therein (ie, does not function as a source contact), and thus, Parasitic capacitance and leakage currents are not introduced by conductive layer 116 (including word lines). In some embodiments, each insulating structure 130 includes an opening (eg, a slit) filled with one or more dielectric materials (eg, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof). In one example, each insulating structure 130 may be filled with a high-k dielectric and silicon oxide. For example, the insulating structure 130 may include a high-k dielectric material along the sidewalls and silicon oxide filling the remaining space of the opening.

In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 includes a source contact 142 under and in contact with the first semiconductor layer 120 (eg, an N-type doped semiconductor layer). That is, the source contact 142 may be disposed vertically between the bonding interface 106 and the first semiconductor layer 120, as shown in FIG. 1 . The first semiconductor layer 120 can thus be electrically connected to the peripheral circuit 108 in the first semiconductor structure 102 through at least the source contact 142 and the bonding layer 112 and the bonding layer 110 . In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes another semiconductor layer 122 under and in contact with the second semiconductor layer 122 (eg, a P-type or N-type doped semiconductor layer) Source contact 146 . The second semiconductor layer 122 can thus be electrically connected to the peripheral circuit 108 in the first semiconductor structure 102 through at least the source contact 146 and the bonding layer 112 and the bonding layer 110 . In some embodiments, peripheral circuitry 108 in first semiconductor structure 102 passes through source contact 142 and first semiconductor layer 120 (eg, serving as sidewall SEGs) and/or through source contact 146 and second semiconductor layer 122 to control the source of the NAND memory string. Source contact 142 and source contact 146 may include one or more conductive layers, such as a metal layer (eg, W, Co, Cu, or Al) or a silicide surrounded by an adhesion layer (eg, titanium nitride (TiN)) Floor.

It should be understood that although source contact 142 and source contact 146 are shown in FIG. 1 as front-side source contacts (eg, on the same side as memory stack 114 relative to second semiconductor layer 122), In some examples, however, the 3D memory element 100 may include one or more backside source contacts on the opposite side of the memory stack 114 relative to the second semiconductor layer 122 (thinned substrate). For example, a backside source contact may be over the memory stack 114 and in contact with the second semiconductor layer 122 . The backside source contact may be electrically connected to peripheral circuitry 108 in the first semiconductor structure 102 by interconnects over and through the second semiconductor layer 122 .

As shown in FIG. 1, the 3D memory device 100 may also include a BEOL interconnect layer 133 for drawing out the pads (eg, to transmit electrical signals between the 3D memory device 100 and external circuits). In some embodiments, the interconnect layer 133 includes one or more interlayer dielectric layers 134 on the second semiconductor layer 122 . According to some embodiments, the upper end of the insulating structure 130 is flush with the bottom surface of the interlayer dielectric layer 134 . The interlayer dielectric layer 134 in the interconnect layer 133 may include a dielectric material such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, interconnect layer 133 also includes passivation layer 138 as the outermost layer for passivation and protection of 3D memory device 100 . Passivation layer 138 may include a dielectric material (eg, silicon nitride). The interconnect layer 133 of the 3D memory element 100 may also include contact pads 140 for wire bonding and/or bonding with the interposer mechanism. Contact pads 140 in interconnect layer 133 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the contact pads 140 include Al.

In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 144 through the second semiconductor layer 122 . According to some embodiments, since the second semiconductor layer 122 may be a thinned substrate, such as an N-type well region or a P-type well region of a silicon substrate, the contacts 144 are through-silicon contacts (TSCs). In some embodiments, the source contact 142 extends through the second semiconductor layer 122 and the interlayer dielectric layer 134 to make contact with the contact pad 140 . In some embodiments, the 3D memory device 100 also includes peripheral contacts 148 extending vertically to the second semiconductor layer 122 outside the memory stack 144 . The peripheral contacts 148 may have a depth greater than that of the memory stack 114 to extend vertically from the bonding layer 112 to the second semiconductor layer 122 in the peripheral region outside the memory stack 114 . In some embodiments, the peripheral contacts 148 are below and in contact with the contacts 144 such that the peripheral circuits 108 in the first semiconductor structure 102 are electrically connected to the contact pads 140 for passing through at least the contacts 144 and peripheral contacts 148 lead out to pads. Contact 144 and peripheral contact 148 may each include one or more conductive layers, such as a metal layer (eg, W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (eg, TiN). In some embodiments, the contact 144 also includes an isolation layer (eg, a dielectric layer) that electrically separates the contact 144 from the second semiconductor layer 122 .

As shown in FIG. 1 , the 3D memory device 100 also includes various local contacts (also referred to as “C1 ”) that are part of the interconnect structure, which are in direct contact with structures in the memory stack 114 . In some embodiments, the local contacts include channel local contacts 150 , each channel local contact 150 being below the corresponding channel structure 124 and in contact with the lower end of the corresponding channel structure 124 . Each channel local contact 150 may be electrically connected to a bitline contact (not shown) for bitline fanout. In some embodiments, the local contacts also include word line local contacts 152 , each word line local contact 152 is located below a corresponding conductive layer 116 in a stepped structure region of the memory stack 114 (including word line local contacts 152 ) line) and contact the corresponding conductive layer 116 for word line fan-out. Local contacts (eg, channel local contact 150 and wordline local contact 152 ) may be electrically connected to peripheral circuitry 108 of first semiconductor structure 102 through at least bonding layer 112 and bonding layer 110 . Local contacts (eg, channel local contact 150 and wordline local contact 152 ) may each include one or more conductive layers, such as metal layers (eg, W, Co, Cu, or Al) or formed by adhesion layers (eg, TiN) surrounding silicide layer.

Figure 2A shows a schematic plan view of an exemplary 3D memory element 200 in accordance with some embodiments of this disclosure. The 3D memory element 200 may be an example of the 3D memory element 100 in FIG. 1 . As shown in FIG. 2A, according to some embodiments, a 3D memory device 200 includes a central stepped region 204 that laterally divides the memory stack in the x-direction (eg, word line direction) into two parts and a first core Array area 206A and second core array area 206B, wherein first core array area 206A and second core array area 206B, respectively, include an array of channel structures 210 (corresponding to channel structures 124 in FIG. 1). According to some embodiments, the 3D memory device 200 further includes parallel insulating structures 208 (corresponding to the insulating structures 130 in FIG. 1 ) in the y-direction (eg, the bit line direction), each insulating structure 208 in the x-direction The upper laterally extends to divide the first core array area 206A and the second core array area 206B and the array of channel structures 210 therein into a plurality of blocks 202 . As shown in FIG. 2A, according to some embodiments, each insulating structure 208 extends laterally along the x-direction (eg, the word-line direction) over the central stepped region 204 and the core array regions 206A and 206B.

It should be understood that the layout of the stepped area and the core array area is not limited to the example of FIG. 2A, and may include any other suitable layout in other embodiments, for example, may include side stepped areas at the edge of the memory stack. For example, Figure 2B shows a schematic plan view of another exemplary 3D memory element 201 in accordance with some embodiments of this disclosure. The 3D memory element 201 may be another example of the 3D memory element 100 in FIG. 1 . As shown in FIG. 2B, the 3D memory device 201 includes side stepped regions 207A and 207B and a central core array region 205, wherein each side stepped region is a memory stack in the x-direction (eg, word line direction) At the corresponding edge of the layer, the central core array region 205 includes an array of channel structures 210 (corresponding to channel structures 124 in Figure 1). According to some embodiments, the 3D memory element 201 further includes parallel insulating structures 208 (corresponding to the insulating structures 130 in FIG. 1 ) in the y-direction (eg, the bit line direction), each insulating structure 208 along the x The direction extends laterally to divide the central core array region 205 and the array of channel structures 210 therein into a plurality of blocks 202 . As shown in FIG. 2B , according to some embodiments, each insulating structure 208 extends laterally along the x-direction (eg, the word line direction) over the side step regions 207A and 207B and the central core array region 205 .

Figures 3A-3M show cross-sectional schematic diagrams of steps of a method for forming an exemplary 3D memory device in accordance with some embodiments of this disclosure. Figures 4A and 4B illustrate a flow diagram of the steps of a method 400 for forming an exemplary 3D memory element in accordance with some embodiments of this disclosure. An example of the 3D memory element depicted in FIGS. 3A to 3M , 4A and 4B is, for example, the 3D memory element 100 depicted in FIG. 1 . The following description will be made with reference to FIGS. 3A to 3M, 4A, and 4B simultaneously. It should be understood that the steps shown in the method 400 are not intended to limit the present invention, and other optional steps not described herein may be included before, after or between the steps shown in the method 400 . Furthermore, in other embodiments, the steps of method 400 may be performed in a different order or concurrently.

Referring to FIG. 4A, method 400 begins by performing step 402 of forming peripheral circuits on a first substrate. As shown in FIG. 3K , the first substrate is, for example, a silicon substrate 350 . Various processes (including but not limited to lithography, etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process) may be performed to form a plurality of transistors on the silicon substrate 350 . In some embodiments, doped regions (not shown) may be formed in the silicon substrate 350 by ion implantation and/or thermal diffusion, such as may serve as source and/or drain regions of a transistor. In some embodiments, isolation regions (eg, shallow trench insulation (STI)) are also formed in the silicon substrate 350 by wet and/or dry etching and thin film deposition. The transistors may form peripheral circuits 352 on the silicon substrate 350 .

Bonding layer 348 is then formed over peripheral circuit 352 as shown in FIG. 3K. Bonding layer 348 may include bond contacts that are electrically connected to peripheral circuitry 352 . The step of forming the bonding layer 348 may include depositing an interlayer dielectric using one or more thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof layer, then using wet and/or dry etching (eg reactive ion etching (RIE)) and one or more thin film deposition processes (eg ALD, CVD, PVD, any other suitable process, or any combination thereof) to form through Bonding contacts for interlayer dielectric layers.

The method 400 proceeds to step 404 as shown in FIG. 4A by doping from the first side of the second substrate to form a doped region in a portion of the second substrate. The second substrate may be a silicon substrate. The first side of the second substrate may be the front side of the second substrate, and the semiconductor element may be formed on the front side of the second substrate. In some embodiments, the first side of the second substrate may be doped with an N-type dopant to form an N-type doped monocrystalline silicon layer (eg, an N-type well region). In some embodiments, the first side of the second substrate may be doped with a P-type dopant to form a P-type doped monocrystalline silicon layer (eg, a P-type well region).

As shown in FIG. 3A , the second substrate is, for example, a silicon substrate 302 , a part of which is doped to form a doped region 304 of the silicon substrate 302 , and the doped region 304 is also called a doped semiconductor layer. The doped region 304 may include an N-type well region or a P-type well region in the silicon substrate 302, and includes monocrystalline silicon. The silicon substrate 302 may be doped with an N-type dopant (eg, P, As, or Sb) or a P-type dopant (eg, B, Ga, or Al) by performing an ion implantation process and/or a thermal diffusion process. Doped regions 304 are formed.

The method 400 proceeds to step 406 as shown in FIG. 4A by forming trenches in the doped regions of the second substrate. In some embodiments, the depth of the trench is no greater than the thickness of the doped region of the second substrate. In some embodiments, the trenches may extend laterally over stepped regions of the dielectric structure.

As shown in FIG. 3A, trenches 303 are formed in doped regions 304 of silicon substrate 302 using wet and/or dry etching (eg, reactive ion etching (RIE)). In some embodiments, the etch rate and/or etch time can be controlled so that the depth of the trenches 303 can be nominally the same as or less than the thickness of the doped regions 304 of the silicon substrate 302 . That is, according to some embodiments, the depth of trench 303 is no greater than the thickness of doped region 304 . In some embodiments, trenches 303 extend laterally in the x-direction (eg, word-line direction) over stepped regions of the dielectric stack 308 (shown in Figure 3B) to be formed.

The method 400 proceeds to step 408 as shown in FIG. 4A by forming a sacrificial layer over the doped regions and in the trenches and a dielectric stack over the sacrificial layer. The dielectric stack may include staggered stacked sacrificial layers and stacked dielectric layers. In some embodiments, the steps of forming the sacrificial layer and the dielectric stack may, for example, first deposit polysilicon over the second doped region and in the trench to form the sacrificial layer, and then deposit the stacked dielectric layer and the stacked sacrificial layer. Layers are alternately deposited on the sacrificial layer to form a dielectric stack.

As shown in FIG. 3B , a sacrificial layer 306 is formed over the doped regions 304 of the silicon substrate 302 . According to some embodiments, sacrificial layer 306 also fills trench 303 . The sacrificial layer 306 may be formed by depositing polysilicon or any other suitable sacrificial material (eg, carbon) that may be selected later using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof Sexually removed. In some embodiments, prior to forming the sacrificial layer 306, a dielectric material (eg, silicon oxide) may be deposited by depositing a dielectric material (eg, silicon oxide) on the silicon substrate 302 (eg, on the top surface of the doped region 304 and the sidewall and bottom surfaces of the trench 303 ). or thermal oxidation) to form an oxide pad layer 305 between the sacrificial layer 306 and the doped region 304, as shown in FIG. 3A.

As shown in FIG. 3B , then a plurality of pairs of a first dielectric layer (also referred to as a stacked sacrificial layer) 302 and a second dielectric layer (also referred to as a stacked dielectric layer) are formed on the sacrificial layer 306 ) 310 of the dielectric stack 308 . Each pair of stacked sacrificial layer 302 and stacked dielectric layer 310 may be referred to as a pair of dielectric layers. According to some embodiments, dielectric stack 308 includes stacked sacrificial layers 312 and stacked dielectric layers 310 that are staggered. Stacked dielectric layers 310 and stacked sacrificial layers 312 may be alternately deposited on sacrificial layer 306 over silicon substrate 302 to form dielectric stack 308 . In some embodiments, each stacked dielectric layer 310 may include a layer of silicon oxide, and each stacked sacrificial layer 312 may include a layer of silicon nitride. Dielectric stack 308 may be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

As shown in FIG. 3B , a stepped structure may be formed on the edges of the dielectric stack 308 . The stepped structure may be formed by performing a number of so-called "trim-etch" cycles of the dielectric layer pairs of the dielectric stack 308 towards the silicon substrate 302 . Due to repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack 308, dielectric stack 308 may have one or more sloped edges and a top dielectric that is shorter than the bottom dielectric layer pair. Electric layer pair. It should be understood that the stepped structure shown in FIG. 3B is for illustration purposes only, and is not intended to represent or limit the actual arrangement of the stepped regions of the dielectric stack 308 . Figures 2A and 2B above provide examples of possible arrangements of stepped regions in a memory stack (replacing dielectric stack 308 in a later process). However, trenches 303 filled with sacrificial layer 306 may extend laterally in the x-direction (eg, word line direction) over one or more stepped regions of dielectric stack 308 .

The method 400 proceeds to step 410 as shown in FIG. 4A by forming a channel structure extending vertically through the dielectric stack and the sacrificial layer and into the doped region of the second substrate. In some embodiments, the step of forming the channel structure may include forming a channel hole extending vertically through the dielectric stack and the sacrificial layer and into the doped region, and then forming a storage film and a storage film over the sidewalls of the channel hole. semiconductor channel.

As shown in FIG. 3C , via holes are openings extending vertically through the dielectric stack 308 and the sacrificial layer 306 and into the doped regions 304 of the silicon substrate 302 . In some embodiments, a plurality of openings may be formed, wherein each opening is a location where a channel structure 314 is grown in a subsequent process. In some embodiments, the process steps of forming the channel holes of the channel structure 314 include wet etching and/or dry etching (eg, deep reactive ion etching (DRIE)). In some embodiments, the tops of the channel holes of the channel structures 314 may extend farther through the doped regions 304 , eg, so that the etch process through the dielectric stack 308 and the sacrificial layer 306 may continue to etch the doped regions Section 304. In some embodiments, after etching through dielectric stack 308 and sacrificial layer 306 , another etching process is performed separately to etch portions of doped region 304 . In some embodiments, the via hole may not extend to the epitaxy of the bottom surface of the doped region 304 . According to some embodiments, trenches 303 (shown in FIG. 3A ) extend vertically into doped regions 304 to a depth greater than the depth to which channel holes extend vertically into doped regions 304 .

As shown in FIG. 3C, after forming a channel hole extending vertically through the dielectric stack 308 and the sacrificial layer 306, a storage film 316 (including barrier layers, storage layer and tunneling layer) and semiconductor channel 318. In some embodiments, the storage film 316 is first deposited along the sidewalls and bottom surface of the via hole, and then the semiconductor channel 318 is deposited over the storage film 316 . In some embodiments, one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof) may be used sequentially to deposit the barrier, storage, and tunneling layers of storage film 316, to form the storage film 316 . Semiconductor channel 318 may then be formed by depositing a semiconductor material (eg, polysilicon) over the tunneling layer of storage film 316 using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof) . In some embodiments, the storage film 316 and the semiconductor channel 318 may be formed by depositing a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure).

As shown in Figure 3C, a fill layer may be formed in the via hole and over the semiconductor via 318 to fully or partially fill the via hole (eg, without or with air gaps). The fill layer may be formed by depositing a dielectric material (eg, silicon oxide) using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof). Subsequently, a channel plug can be formed in the top of the channel hole. In some embodiments, the step of forming the channel plug includes removing portions of the storage film 316 , the semiconductor channel 318 and the fill layer on the top surface of the dielectric stack 308 and removing by CMP, wet etching and/or dry etching Planarization, followed by wet and/or dry etching to remove portions of the semiconductor channel 318 and fill layer in the top of the via hole to form a recess in the top of the via hole, followed by one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof) deposits semiconductor material (eg, polysilicon) into the recesses to form channel plugs. As shown in FIG. 3C , channel structure 314 extends through dielectric stack 308 and sacrificial layer 306 and into doped region 304 of silicon substrate 302 .

The method 400 proceeds to step 412 as shown in FIG. 4A by forming openings extending vertically through the dielectric stack and connecting to the trenches. In some embodiments, the openings are laterally aligned with the grooves, and the lateral dimensions of the grooves are greater than the lateral dimensions of the openings.

As shown in FIG. 3C, slits 320 are openings formed in step 412 that extend vertically through dielectric stack 308 to expose portions of sacrificial layer 306 . Slits 320 may be formed in lateral alignment with trenches 303 (shown in Figure 3A, filled with sacrificial layer 306) by a lithography process. In some embodiments, the lateral dimension of the trenches 303 in the y-direction (eg, the bit line direction) is larger than the lateral dimension of the slits 320 in the y-direction. Therefore, in a plan view of the x-y plane, the pattern of slits 320 is not within the trenches 303 in neither the x-direction nor the y-direction. In some embodiments, the step of forming the slits 320 may include wet etching and/or dry etching (eg, DRIE). In some embodiments, the etch process through dielectric stack 308 may not stop at the top surface of sacrificial layer 306, but may continue to etch to remove portions of sacrificial layer 306 so that slit 320 may extend further into the sacrificial layer 306 inside the top.

FIG. 3D is a schematic cross-sectional view along the D-D tangent line passing through the middle of the slit 320 in FIG. 3C. According to some embodiments, slits 320 and trenches 303 each extend laterally in the x-direction (eg, word-line direction) over stepped regions 380 and core array regions 382 of dielectric stack 308 . It should be understood that although Figure 3D shows an example similar to 2A with a central stepped region 380 and two core array regions 382, any other suitable arrangement of stepped regions and core array regions (such as the example of Figure 2B with a central stepped region 380 and two core array regions 382) Core array area and multiple side stepped areas) may also be applicable herein. As mentioned above, the film structure of the dielectric stack 308 is different in the core array region 382 and the stepped region 380 because there are fewer stacked sacrificial layers 312 in the stepped region 380 than in the core array region 382 (eg silicon nitride layer). Therefore, the slits 320 in the stepped area 380 tend to be etched faster and deeper than the slits 320 in the core array area 382, resulting in uneven depth distribution of the slits 320 along the x-direction, as shown in the 3D as shown in the figure. By introducing the trenches 303 and aligning the slits 320 with the trenches 303 , the thickness of the sacrificial layer 306 in the areas where the slits 320 will be etched becomes thicker and has a greater buffer effect to avoid the slits in the stepped area 380 An overetch occurs at 320 extending through the sacrificial layer 306 into the silicon substrate 302 . FIG. 3D also shows the bottom surface 384 of the sacrificial layer 306 in other areas outside the trenches 303 . Without trenches 303 , slits 320 in stepped region 380 may extend below bottom surface 384 of sacrificial layer 306 . Thus, trenches 303 laterally aligned with slits 320 and filled with sacrificial layer 306 (eg, polysilicon) can serve as etch stop layers when forming slits 320 and as a buffer to balance the core array area 382 and the stepped area 380 between etch loading effects, thereby compensating for gouge variations among different regions.

The method 400 proceeds to step 414 as shown in FIG. 4B by replacing the sacrificial layer with a doped semiconductor layer located between the doped region and the dielectric stack through the opening. In some embodiments, the step of replacing the sacrificial layer with the doped semiconductor layer may include removing the sacrificial layer by etching through the opening to form a cavity between the doped region and the dielectric stack, and then passing through the opening and The cavity etch removes a portion of the storage film to expose a portion of the semiconductor channel along the sidewalls of the via hole, followed by depositing doped polysilicon into the cavity through the opening to form a doped semiconductor layer. Subsequently, part of the doped polysilicon deposited in the openings and the trenches is removed by opening etching.

As shown in FIG. 3E , step 414 may include removing sacrificial layer 306 (shown in FIG. 3D ) by wet and/or dry etching to form cavity 322 and re-expose trench 303 . In some embodiments, the material of sacrificial layer 306 includes polysilicon and can be removed by a tetramethylammonium hydroxide (TMAH) etchant etch through slit 320, where the etch can stop at sacrificial layer 306 and doping Oxide pad 305 between regions 304 . That is, removal of sacrificial layer 306 does not affect doped regions 304 according to some embodiments. In some embodiments, isolation layers 324 may be formed along sidewalls of slits 320 prior to removal of sacrificial layer 306 . Isolation layer 324 may be formed by depositing a dielectric material (eg, silicon nitride, silicon oxide, and silicon nitride) into slit 320 using one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof) .

3F, the portion of the storage film 316 of the channel structure 314 exposed in the cavity 322 is then removed to expose the portion of the semiconductor channel 318 that adjoins the channel structure 314 of the cavity 322. In some embodiments, an etchant (eg, phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide) may be provided through slit 320 and cavity 322 to etch barrier layers of storage film 316 (eg, including silicon oxide), storage layer (for example comprising silicon nitride) and tunneling layer (for example comprising silicon oxide) exposed portion. The above-described etching may stop at the semiconductor channel 318 of the channel structure 314 . The isolation layer 324 (shown in FIG. 3E ) comprising a dielectric material also protects the dielectric stack 308 from damage when the storage film 316 is etched, and can be used when the storage film 316 is partially removed. removed by the etchant in the step. Similarly, oxide pad layer 305 (shown in FIG. 3E ) on doped region 304 (also on the sidewalls and bottom surface of trench 303 ) can also be used in the same step of removing part of storage film 316 removed in .

Next, as shown in FIG. 3G , a doped semiconductor layer 326 (shown in FIG. 3F ) is formed in the cavity 322 . In some embodiments, one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof) may be performed to deposit polysilicon into cavity 322 through slit 320 to form doped semiconductor layer 326 . In some embodiments, doped semiconductor layer 326 may be formed by selectively epitaxially growing polysilicon on exposed portions of semiconductor channel 318 (including polysilicon) using an epitaxial growth process to fill cavity 322 . The epitaxial growth process may include pre-cleaning the cavity 322 and then performing, for example, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. In some embodiments, in-situ doping of an N-type dopant (eg, P, As, or Sb) may be performed during deposition of polysilicon or epitaxially grown polysilicon to form an N-type doped polysilicon layer as a doped semiconductor layer 326. The doped semiconductor layer 326 may fill the cavity 322 and be in contact with the exposed portion of the semiconductor channel 318 of the channel structure 314 .

It should be understood that doped semiconductor layer 326 may also be formed in trench 303 and/or opening 320 . As shown in Figures 3G and 3H, wet and/or dry etching may be used to etch through the slit 320 the portion of the doped semiconductor layer 326 deposited into the slit 320 and trench 303, leaving behind the silicon substrate 302. The remainder of the doped semiconductor layer 326 between the doped region 304 and the dielectric stack 308 . The etching of the doped semiconductor layer 326 in the slits 320 and trenches 303 can be controlled by controlling the etch rate and/or the etch time to avoid etching between the doped regions 304 and the dielectric stack 308 the remainder of the doped semiconductor layer 326. Through the above process, replacement of sacrificial layer 326 (shown in FIG. 3C ) with doped semiconductor layer 326 located between doped region 304 and dielectric stack 308 is achieved. Also, according to some embodiments, slits 320 and trenches 303 are thus connected to form a continuum extending vertically through dielectric stack 308 and doped semiconductor layer 326 and into doped regions 304 of silicon substrate 302 Open your mouth.

The method 400 proceeds to step 416 as shown in FIG. 4B by performing a so-called "gate replacement" process through the opening to replace the dielectric stack with the memory stack, thus allowing the channel structure to extend vertically through the memory The stacked and doped semiconductor layers extend into the doped regions of the second substrate. In some embodiments, replacing the dielectric stack with the memory stack includes replacing the stacked sacrificial layer with the stacked conductive layer through the opening. In some embodiments, the memory stack includes alternating stacked conductive layers and stacked dielectric layers.

As shown in FIG. 3H , the stacked sacrificial layer 312 (shown in FIG. 3A ) is first removed by passing through the slits 320 to form lateral grooves 327 . In some embodiments, the stacked sacrificial layer 312 may be removed by applying an etchant through the slits 320 , thereby forming a plurality of lateral grooves 327 interleaved with the stacked dielectric layers 310 . Stacked sacrificial layer 312 may be etched away using any etchant having etch selectivity for stacked sacrificial layer 312 and stacked dielectric layer 310 .

As shown in Figure 3I, a stacked conductive layer 328 (including gate electrodes and adhesion layers) is then deposited through slits 320 into each lateral groove 327 (shown in Figure 3H). In some embodiments, the gate dielectric layer 332 may be deposited into the lateral grooves 327 prior to the stacked conductive layer 328 , and then the stacked conductive layer 328 is deposited on the gate dielectric layer 332 . Stacked conductive layer 328 (eg, metal layer) may be deposited using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, a gate dielectric layer 332 (eg, a high-k dielectric layer) is also formed along the sidewalls and bottom of the slit 320 . According to some embodiments, the dielectric stack 308 (shown in FIG. 3G ) is replaced by the above-described replacement of the stacked sacrificial layer 312 with the stacked conductive layer 328 to include alternating stacked conductive layers 328 and stacked dielectric layers Memory stack 330 of 310 . According to some embodiments, the channel structure 314 thus extends vertically through the memory stack 330 and the doped semiconductor layer 326 and into the doped region 304 of the silicon substrate 302 .

Method 400 proceeds to step 418 as shown in FIG. 4B by forming insulating structures in the openings and trenches. The insulating structure may extend vertically through the memory stack and the doped semiconductor layer and into the doped region of the second substrate. In some embodiments, to form insulating structures, one or more dielectric layer materials may be deposited into and fill the openings and trenches. In some embodiments, the insulating structure extends vertically into the doped region to a greater depth than the channel structure extends vertically into the doped region.

As shown in FIG. 3I , an insulating structure 336 is formed extending vertically through the memory stack 330 and the doped semiconductor layer 326 and into the doped region 304 . One or more dielectric materials (eg, silicon oxide) may be deposited into slits 320 and trenches 303 (eg, silicon oxide) by using one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof). Insulating structure 336 is formed in fully or partially filling slits 320 and trenches 303 (with or without air gaps) within FIG. 3H . In some embodiments, insulating structure 336 may include gate dielectric layer 332 (eg, including a high-k dielectric) and a dielectric fill layer 334 (eg, including silicon oxide). In some embodiments, insulating structures 336 extend vertically into doped regions 304 to a greater depth than channel structures 314 extend vertically into doped regions 304 .

As shown in FIG. 3J, after insulating structure 336 is formed, peripheral contacts 340, source contacts 338 and 339 and local contacts, including channel local contacts 344 and word line local contacts, are then formed 342. In some embodiments, source contact 339 is formed over and in contact with doped semiconductor layer 326 and source contact 338 is formed over and in contact with doped region 304 of silicon substrate 302 Area 304 contacts. In some embodiments, a dielectric material (eg, silicon oxide or silicon nitride) may be deposited on top of memory stack 330 by using one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof) A local dielectric layer is formed on the memory stack 330 and then defined in the local dielectric layer (and any other interlayers) in the local dielectric layer by, for example, wet etching and/or dry etching (eg, RIE). dielectric layer), followed by one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof) to form conductive material to fill the contact openings, thereby forming via local contacts 344, Word line local contact 342, peripheral contact 340, and source contacts 338 and 339.

Next, as shown in FIG. 3J, a bonding layer 346 may be formed over the channel local contacts 344, word line local contacts 342, peripheral contacts 340, and source contacts 338 and 339. Bond layer 346 includes a plurality of bond contacts electrically connected to channel local contacts 344 , word line local contacts 342 , peripheral contacts 340 , and source contacts 338 and 339 . The step of forming bonding layer 346 is, for example, performing one or more thin film deposition processes (eg, CVD, PVD, ALD, or any combination thereof) to deposit an interlayer dielectric layer, and using wet and/or dry etching (eg, RIE) and one or Various thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof) form bonding contacts through the interlayer dielectric layers.

The method 400 proceeds to step 420 as shown in FIG. 4B by bonding the first substrate and the second substrate in a face-to-face manner such that the memory stack is positioned over the peripheral circuitry. The bonding of the first substrate and the second substrate may be hybrid bonding. As shown in FIG. 3K, the silicon substrate 302 and the components formed thereon (eg, the memory stack 330 and the channel structures 314 through the memory stack 330) are turned upside down. According to some embodiments, the downward facing bonding layer 346 is bonded with the upward facing bonding layer 348 in a face-to-face manner to form a bonding interface 354 between the silicon substrate 302 and the silicon substrate 350 . In some embodiments, the bonding surfaces may be subjected to a treatment process (eg, plasma treatment, wet treatment, and/or thermal treatment) prior to bonding. After bonding, the bond contacts in bond layer 346 and the bond contacts in bond layer 348 are aligned and contacted with each other such that memory stack 330 and the channels through memory stack 330 Structure 314 may be electrically connected to peripheral circuit 352 and overlying peripheral circuit 352 . In some embodiments, after bonding, doped semiconductor layer 326 is electrically connected to peripheral circuit 352 through at least source contact 339 and doped region 304 is electrically connected to peripheral circuit 352 through at least source contact 338 .

The method 400 proceeds to step 422 as shown in FIG. 4B by thinning the second substrate from a second side of the second substrate relative to the first side until the end of the insulating structure is reached to expose the dopant of the second substrate. up to the miscellaneous area. The second side of the second substrate is, for example, the backside of the second substrate.

As shown in Figure 3L, the silicon substrate 302 (shown in Figure 3K) is thinned from the backside of the second substrate to expose the doped regions 304. Because the material filling the insulating structure 336 (eg, silicon oxide and high-k dielectrics) is different from the material of the silicon substrate 302 (ie, silicon), when the thinning process is performed until the upper end of the insulating structure 336 is exposed, the thinning process Can stop automatically. Silicon substrate 302 may be thinned using CMP, grinding, dry etching, and/or wet etching. In some embodiments, the silicon substrate 302 may be thinned using a silicon wafer CMP process and may automatically stop when the silicon oxide at the upper end of the insulating structure 336 is reached. According to some embodiments, depending on the depth to which insulating structure 336 extends into doped region 304, the thickness of doped region 304 may also be reduced by a thinning process such that doped region 304 (also referred to herein as a doped semiconductor) The top surface of the remainder of the layer) is flush with the upper end of the insulating structure 336 .

The method 400 proceeds to step 424 as shown in FIG. 4B by forming contacts through the doped regions of the thinned second substrate. Next, the method 400 proceeds to step 426 as shown in FIG. 4B by forming an interconnect layer in contact with the contacts on the doped regions of the thinned second substrate.

As shown in FIG. 3M, one or more interlayer dielectric layers 356 are formed on the doped regions 304 of the thinned silicon substrate 302. As shown in FIG. The interlayer dielectric layer 356 may be formed by depositing a dielectric material on the top surface of the doped region 304 by performing one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof). Contacts 368 extend vertically through interlayer dielectric layer 356 and doped region 304 according to some embodiments. In some embodiments, an etch process may be performed to form contact openings for contacts 368 through interlayer dielectric layer 356 and doped regions 304 and aligned with peripheral contacts 340, followed by one or more thin film deposition processes (eg, ALD) , CVD, PVD, any other suitable process, or any combination thereof) to deposit one or more conductive materials (eg, an adhesion layer (eg, TiN) and a conductor layer (eg, W)) into the contact openings of the contacts 368 and fill the contacts Openings are then performed, and a planarization process (eg, CMP) is performed to remove excess conductive material such that the top surface of contacts 368 is flush with the top surface of interlayer dielectric layer 356 . In some embodiments, the contacts 368 are also over and in contact with the peripheral contacts 340 when the contact openings are aligned with the peripheral contacts 340 .

As shown in FIG. 3M , subsequently, a passivation layer 372 may be formed on the interlayer dielectric layer 356 . In some embodiments, passivation layer 372 may be formed by depositing a dielectric material (eg, silicon nitride) by performing one or more thin film deposition processes (eg, ALD, CVD, PVD, any other suitable process, or any combination thereof). Next, contact pads 374 are formed over and in contact with contacts 368 . In some embodiments, portions of passivation layer 372 covering contacts 368 may be removed by wet and dry etching to form contact pads 374 . Thus, the contact pads 374 for lead-out pads may be electrically connected to the peripheral circuit 352 through the contacts 368 , the peripheral contacts 340 , and the bonding layers 346 and 348 . Through the above process, the interconnect layer 376 including the interlayer dielectric layer 356 , the contact pads 374 and the passivation layer 372 can be obtained.

To sum up, one aspect of the present invention provides a 3D memory device, which includes a substrate, a peripheral circuit located on the substrate, a plurality of interleaved conductive layers and a plurality of dielectric layers located on the peripheral circuit. a memory stack of electrical layers, a first semiconductor layer overlying the memory stack, a second semiconductor layer overlying the first semiconductor layer and in contact with the first semiconductor layer, a plurality of channel structures, wherein each of the channel structures extends vertically through the memory stack and the first semiconductor layer, and vertically through the memory stack, the first semiconductor layer and the second semiconductor layer an insulating structure.

In some embodiments, an upper end of the insulating structure is flush with a top surface of the second semiconductor layer.

In some embodiments, the upper end of the insulating structure is located above an upper end of each of the channel structures.

In some embodiments, the insulating structure is filled with one or more dielectric materials.

In some embodiments, the insulating structure extends laterally to divide the channel structures into blocks.

In some embodiments, each of the channel structures extends vertically into the second semiconductor layer.

In some embodiments, the second semiconductor layer includes single crystal silicon. In some embodiments, the first semiconductor layer includes polysilicon.

In some embodiments, the first semiconductor layer is an N-type doped semiconductor layer, and the second semiconductor layer is an N-type doped semiconductor layer. In some embodiments, the first semiconductor layer is an N-type doped semiconductor layer, and the second semiconductor layer is a P-type doped semiconductor layer.

In some embodiments, the 3D memory device further includes a source contact located under the first semiconductor layer and in contact with the first semiconductor layer, so that the first semiconductor layer is electrically connected through at least the source contact connected to the peripheral circuit.

In some embodiments, the 3D memory device further includes a bonding interface between the peripheral circuit and the memory stack.

In some embodiments, the 3D memory device further includes a contact through the second semiconductor layer, and an interconnect layer over the second semiconductor layer and including a contact pad, wherein the contact pad passes through at least The contact is electrically connected to the peripheral circuit.

Another aspect of the present invention provides a 3D memory device including a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a memory stack including interleaved conductive and dielectric layers, a doped semiconductor layer, a plurality of channel structures, wherein each of the channel structures extends vertically through the memory stack and extending into the doped semiconductor layer and electrically connected to the peripheral circuitry, and insulating structures extending vertically through the memory stack and the doped semiconductor layer and extending laterally to separate the channel structures into multiple block.

In some embodiments, the doped semiconductor layer includes a first N-type doped semiconductor layer comprising polysilicon and a second N-type doped semiconductor layer comprising monocrystalline silicon. In some embodiments, the doped semiconductor layer includes a first N-type doped semiconductor layer comprising polysilicon and a P-type doped semiconductor layer comprising monocrystalline silicon.

In some embodiments, each of the channel structures extends vertically through the first N-type doped semiconductor layer.

In some embodiments, an upper end of the insulating structure is flush with a top surface of the doped semiconductor layer.

In some embodiments, the insulating structure is filled with one or more dielectric materials.

In some embodiments, the second semiconductor structure further includes a source contact extending vertically between the bonding interface and the doped semiconductor layer, wherein the source contact is in contact with the doped semiconductor layer such that The doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact.

Yet another aspect of the present invention provides a method for forming a 3D memory device, the steps comprising forming a trench in a doped region on a first side of a substrate, followed by forming a sacrificial sacrificial over the doped region and in the trench layer and a dielectric stack over the sacrificial layer, followed by forming a channel structure extending vertically through the dielectric stack and the sacrificial layer and into the doped regions, followed by forming vertically extending through the dielectric stack layer and connect to the opening of the trench, and then the sacrificial layer is replaced through the opening to form a doped semiconductor layer between the doped region and the dielectric stack. Subsequently, insulating structures are formed in the openings and trenches. Next, the substrate is thinned from a second side of the substrate relative to the first side until the end of the insulating structure is reached and the doped regions are exposed.

In some embodiments, the openings are laterally aligned with the grooves, and the lateral dimensions of the grooves are greater than the lateral dimensions of the openings.

In some embodiments, the depth of the trench is no greater than the thickness of the doped region of the substrate.

In some embodiments, the trenches extend laterally over stepped regions of the dielectric structure.

In some embodiments, after replacing the sacrificial layer with a doped semiconductor layer, the dielectric stack is then replaced by forming a memory stack through openings such that the channel structure extends vertically through the memory stack and the doping The semiconductor layer extends into the doped regions of the substrate.

In some embodiments, the step of forming the channel structure includes forming a channel hole extending vertically through the dielectric stack and the sacrificial layer into a doped region of the substrate, and forming a storage film and a semiconductor channel along sidewalls of the channel hole .

In some embodiments, the step of replacing the sacrificial layer with the doped semiconductor layer includes removing the sacrificial layer through an opening etch to form a cavity between the doped region and the dielectric stack, followed by etching a portion of the storage film through the opening to expose a portion of the semiconductor channel along the sidewall of the via hole, then deposit doped polysilicon into the cavity through the opening to form a doped semiconductor layer, and then etch the portion of the doped polysilicon deposited into the opening and the trench through the opening.

In some embodiments, the step of forming the insulating structure includes depositing one or more dielectric materials into the openings and trenches to fill the openings and trenches.

Yet another aspect of the present invention discloses a method for forming a 3D memory device, the steps including forming a peripheral circuit on a first substrate, forming a channel structure and an insulating structure on a first side of the second substrate, each channel structure and The insulating structure extends vertically through the memory stack and the doped semiconductor layer on the second substrate and into the doped region on the first side of the second substrate. The first substrate and the second substrate are then bonded in a face-to-face manner so that the memory is stacked over the peripheral circuits. The second substrate is thinned from a second side of the second substrate relative to the first side until the end of the insulating structure is reached and the doped regions of the second substrate are exposed.

In some embodiments, the insulating structure extends vertically into the doped region to a greater depth than the channel structure extends vertically into the doped region.

In some embodiments, after thinning the second substrate, then contacts are formed through the doped regions of the thinned second substrate, and over and over the doped regions of the thinned second substrate Interconnect layer in contact with contacts.

In some embodiments, before the first substrate and the second substrate are bonded, a source contact formed on the doped semiconductor layer and in contact with the doped semiconductor layer is further included, so that after bonding the first substrate and the second substrate, a source contact is further included. After the two substrates, the doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact.

In some embodiments, prior to forming the channel structure and the insulating structure, further comprising doping a portion of the second substrate from the first side of the second substrate to form a doped region, and forming a trench in the doped region.

In some embodiments, the steps of forming the channel structure and the insulating structure include forming a sacrificial layer over the doped regions and in the trench and a dielectric stack over the sacrificial layer, and then forming a stack extending vertically through The dielectric stack and the sacrificial layer extend into the channel structure in the doped region, then an opening is formed extending vertically through the dielectric stack to connect to the trench, and then the opening is formed in the doped region and the dielectric A doped semiconductor layer between the dielectric stacks replaces the sacrificial layer, followed by forming insulating structures in the openings and trenches.

In some embodiments, the openings are laterally aligned with the grooves, and the lateral dimensions of the grooves are greater than the lateral dimensions of the openings.

In some embodiments, the depth of the trench is no greater than the thickness of the doped region of the second substrate.

In some embodiments, the trenches extend laterally over stepped regions of the dielectric structure.

In some embodiments, the step of forming the insulating structure includes depositing one or more dielectric materials into the openings and trenches to fill the openings and trenches.

In some embodiments, the step of forming the channel structure includes forming a channel hole extending vertically through the dielectric stack and the sacrificial layer and into the doped region of the second substrate, and subsequently forming sidewalls along the channel hole storage membranes and semiconductor channels.

In some embodiments, forming the doped semiconductor layer to replace the sacrificial layer includes etching the sacrificial layer through the opening to form a cavity between the doped region and the dielectric stack, followed by removing a portion of the storage film through the opening etch to expose a portion of the semiconductor channel along the sidewall of the via hole, then deposit doped polysilicon into the cavity through the opening to form a doped semiconductor layer, and then remove a portion of the dopant deposited into the opening and the trench through an opening etch polysilicon.

The foregoing detailed description of specific embodiments can give insight into the general nature of the invention and enable those skilled in the art to readily modify and/or modify the invention without departing from the general concept of the invention. These specific embodiments are adapted for various applications without undue experimentation. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not limitation. The terms or expressions used in this specification will be interpreted by those skilled in the art in light of the teaching and guidance.

Embodiments of the present invention have been described above with the aid of functional blocks that illustrate the implementation of specific functions and relationships thereof. For the convenience of description, the boundaries of these functional blocks are arbitrarily defined in the foregoing embodiments, but as long as the specific functions and their relationships are appropriately performed, alternative boundaries may also be defined in other embodiments.

The Summary and Abstract sections are intended to describe one or more, but not all, exemplary embodiments of the invention proposed by the inventors, and are not intended to limit the scope of the invention and the appended claims in any way. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention. The above descriptions are only preferred embodiments of the present invention, and the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments. and modifications, all should fall within the scope of the present invention.

100: 3D Memory Components 101: Substrate 102: First semiconductor structure 104: Second Semiconductor Structure 106: Bonding interface 108: Peripheral circuit 110: Bonding layer 111: Bonded contacts 112: Bonding layer 113: Bonded Contacts 114: Memory Stack 116: Conductive layer 118: Dielectric layer 120: the first semiconductor layer 122: the second semiconductor layer 124: Channel Structure 126: Storage film 128: Semiconductor channel 129: Channel Plug 130: Insulation structure 133: Interconnect layer 134: Interlayer dielectric layer 138: Passivation layer 140: Contact pad 142: source contact 144: Memory Stack 146: source contact 148: Peripheral contacts 150: Channel local contact 152: Word line local contact X: direction Y: direction Z: direction 200: 3D Memory Components 206A: First Core Array Area 206B: Second Core Array Area 204: Central staircase area 201: 3D Memory Components 207A: Side Step Area 207B: Side Step Area 202: Block 205: Central Core Array Area 208: Insulation structure 210: Channel Structure 302: Silicon substrate 303: Groove 304: Doping region 305: oxide underlayer 306: Sacrificial Layer 308: Dielectric Stack 310: Stacked Dielectric Layers 312: Stacked sacrificial layers 312 314: Channel Structure 316: Storage Film 318: Semiconductor channel 320: Slit 322: cavity 324: isolation layer 326: Doping semiconductor layer 327: Lateral grooves 328: Stacked Conductive Layers 330: Memory Stack 332: gate dielectric layer 334: Dielectric Filler 336: Insulation structure 338: source contact 339: source contact 340: Peripheral Contacts 344: Channel local contact 346: Bonding Layer 348: Bonding Layer 350: Silicon substrate 352: Peripheral circuit 354: Bonding interface 356: Interlayer dielectric layer 368: Contacts 372: Passivation layer 374: Contact pad 376: Interconnect Layer 380: Step Area 382: Core array area 384: Bottom Surface 400: Method 402: Step 404: Step 406: Step 408: Step 410: Steps 412: Steps 414: Steps 416: Steps 418: Steps 420: Steps 422: Steps 424: Steps 426: Steps D-D: Tangent

The accompanying drawings provide a more in-depth understanding of the embodiments of the present invention, and are incorporated in and constitute a part of this specification. These drawings and descriptions serve to explain the principles of some embodiments and to enable those skilled in the relevant art to make and use the present disclosure. Figure 1 shows a schematic cross-sectional view of an exemplary 3D memory device in accordance with some embodiments of this disclosure. Figure 2A shows a schematic plan view of an exemplary 3D memory element in accordance with some embodiments of this disclosure. Figure 2B shows a schematic plan view of another exemplary 3D memory element in accordance with some embodiments of this disclosure. Figures 3A-3M show cross-sectional schematic diagrams of steps of a method for forming an exemplary 3D memory device in accordance with some embodiments of this disclosure. Figures 4A and 4B show a flow diagram of steps for a method for forming an exemplary 3D memory element in accordance with some embodiments of this disclosure. Embodiments of the present disclosure will be described with reference to the accompanying drawings.

100: 3D Memory Components

101: Substrate

102: First semiconductor structure

104: Second Semiconductor Structure

106: Bonding interface

108: Peripheral circuit

110: Bonding layer

111: Bonded contacts

112: Bonding layer

113: Bonded Contacts

114: Memory Stack

116: Conductive layer

118: Dielectric layer

120: the first semiconductor layer

122: the second semiconductor layer

124: Channel Structure

126: Storage film

128: Semiconductor channel

129: Channel Plug

130: Insulation structure

133: Interconnect layer

134: Interlayer dielectric layer

138: Passivation layer

140: Contact pad

142: source contact

144: Memory Stack

146: source contact

148: Peripheral contacts

150: Channel local contact

152: Word line local contact

X: direction

Y: direction

Z: direction

Claims (20)

A three-dimensional (3D) memory device comprising: a base; a peripheral circuit on the substrate; a memory stack including interleaved conductive layers and dielectric layers over the peripheral circuit; a first semiconductor layer on the memory stack; a second semiconductor layer on and in contact with the first semiconductor layer; a plurality of channel structures, wherein each of the channel structures extends vertically through the memory stack and the first semiconductor layer; and An insulating structure extending vertically through the memory stack, the first semiconductor layer and the second semiconductor layer. The 3D memory device according to claim 1, wherein an upper end of the insulating structure is flush with a top surface of the second semiconductor layer. The 3D memory device according to claim 2, wherein the upper end of the insulating structure is located above an upper end of each of the channel structures. The 3D memory device according to claim 1, wherein the insulating structure is filled with one or more dielectric materials. The 3D memory device according to claim 1, wherein the insulating structure extends laterally to divide the channel structures into a plurality of blocks. The 3D memory device according to claim 1, wherein each of the channel structures extends vertically into the second semiconductor layer. The 3D memory device according to claim 1, wherein the second semiconductor layer comprises monocrystalline silicon. The 3D memory device according to claim 1, wherein the first semiconductor layer comprises polysilicon. The 3D memory device according to claim 1, wherein the first semiconductor layer is an N-type doped semiconductor layer, and the second semiconductor layer is an N-type doped semiconductor layer. The 3D memory device according to claim 1, wherein the first semiconductor layer is an N-type doped semiconductor layer, and the second semiconductor layer is a P-type doped semiconductor layer. The 3D memory device according to claim 1, further comprising a source contact located under the first semiconductor layer and in contact with the first semiconductor layer, allowing the first semiconductor layer to pass through at least the first semiconductor layer. The source contact is electrically connected to the peripheral circuit. The 3D memory device according to claim 1, further comprising a bonding interface between the peripheral circuit and the memory stack. The 3D memory device according to item 1 of the claimed scope further includes: a contact through the second semiconductor layer; and An interconnect layer over the second semiconductor layer and including a contact pad, wherein the contact pad is electrically connected to the peripheral circuit through at least the contact. A three-dimensional (3D) memory device comprising: a first semiconductor structure including a peripheral circuit; A second semiconductor structure comprising: a memory stack including alternating conductive layers and dielectric layers; a doped semiconductor layer; a plurality of channel structures, each of the channel structures extending vertically through the memory stack and into the doped semiconductor layer and electrically connected to the peripheral circuit; and an insulating structure extending vertically through the memory stack and the doped semiconductor layer and extending laterally to divide the channel structures into blocks; and a bonding interface between the first semiconductor structure and the second semiconductor structure. The 3D memory device according to claim 14, wherein the doped semiconductor layer comprises: a first N-type doped semiconductor layer comprising polysilicon and a second N-type doped semiconductor layer comprising monocrystalline silicon . The 3D memory device according to claim 14, wherein the doped semiconductor layer comprises: a first N-type doped semiconductor layer comprising polysilicon and a P-type doped semiconductor layer comprising monocrystalline silicon. The 3D memory device of claim 15, wherein each of the channel structures vertically extends through the first N-type doped semiconductor layer. The 3D memory device according to claim 14, wherein an upper end of the insulating structure is flush with a top surface of the doped semiconductor layer. The 3D memory device of claim 14, wherein the insulating structure is filled with one or more dielectric materials. The 3D memory device of claim 14, wherein the second semiconductor structure further comprises: a source contact extending vertically between the bonding interface and the doped semiconductor layer, wherein the source A pole contact is in contact with the doped semiconductor layer such that the doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact.

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