TW202145232A - Semiconductor storing apparatus and pre-charge method - Google Patents

Abstract

A semiconductor storing apparatus capable of suppressing a peak current in a pre-charge operation and shortening a sense time is provided, includes: a pre-charge method of a bit line of a NAND type flash memory turning on a transistor (BLPRE) and supplying a pre-charge voltage to a sense node (SNS) in time (t1), turning on a transistor (BLCLAMP) connecting to the sense node (SNS) and generating a clamping voltage and turning on a transistor (BLCN) connecting to a node (BLS) in time (t2), turning on a transistor (BLSe/BLSo) connecting between the node (BLS) and a bit line (GBLe/GBLo) in time (t3), and performing the pre-charge operation on the bit line.

Description

Semiconductor memory device and precharging method

The present invention relates to a semiconductor storage device such as a flash memory, in particular to a method for precharging a bit line.

In the read operation of a NAND (Not AND) type flash memory, so-called shield read is performed, that is, by alternately reading pages of even bit lines or reading of odd bit lines page, thereby reducing noise caused by capacitive coupling between adjacent bit lines (for example, Patent Document 1). Furthermore, in order to suppress the peak current when precharging the bit line during the read operation, Patent Document 2 discloses a method in which the precharging of the read node is divided into a plurality of times, and the precharging of the selected bit line is performed. Charging is divided into multiple times. [Prior Art Literature] [Patent Literature]

Patent Document 1: Japanese Patent Laid-Open No. 11-176177 Patent Document 2: Japanese Patent No. 6164713

[Problems to be Solved by Invention]

FIG. 1(A) is a diagram showing the overall configuration of a page buffer/read circuit of a NAND-type flash memory. As shown in this figure, a page buffer/readout circuit is shared by an even bit line GBLe and an odd bit line GBLo, and the page buffer/readout circuit 10 includes n page buffers/ Readout circuits 10_1 , 10_2 , . . . , 10_n (for example, n is 32K).

(B) of FIG. 1 shows the configuration of a page buffer/readout circuit and a bit line selection circuit connected thereto. The page buffer/readout circuit 10_1 includes a readout circuit 20 that reads out the data read out to the bit line, or sets a voltage corresponding to "0" or "1" of the data that should be programmed to the bit line; and The latch circuit 30 holds the read data or the data to be programmed.

Here, for convenience, the signal applied to the gate is used for the identification of the transistor. Also, all transistors are N-channel Metal Oxide Semiconductor (NMOS) transistors. The readout circuit 20 includes a transistor BLPRE, which is connected between the voltage supply node V1 and the sense node SNS, and supplies a precharge voltage to the sense node SNS, and a transistor BLCLAMP, which generates a clamp at the node TOBL voltage; and a transistor BLCN, connected between the node TOBL and the node BLS of the bit line selection circuit 40 . The sense node SNS of the sense circuit 20 is connected to the latch circuit 30 via a transistor for charge transfer, and the transistor BLCN is connected to the node BLS of the bit line selection circuit 40 .

The bit line selection circuit 40 includes a transistor BLSe for selecting an even-numbered bit line GBLe, a transistor BLSo for selecting an odd-numbered bit line GBLo, a transistor YBLe for connecting a virtual power supply VIRPWR to the even-numbered bit line GBLe, It is formed by connecting the virtual power supply VIRPWR to the transistor YBLo of the odd-numbered bit line GBLo. A NAND string (not shown) is connected to the even-numbered bit line GBLe and the odd-numbered bit line GBLo, respectively.

The operations of the readout circuit 20 and the bit line selection circuit 40 are based on page buffer control signals (BLPRE, BLCLAMP, BLCN, BLSe/BLSo, YBLe/YBLo, etc. in FIG. 1(B) ) generated by the page buffer control 12 . signal) is controlled.

FIG. 2(A) and FIG. 2(B) are sequences showing a conventional bit line precharge operation (Patent Document 2), and show voltage waveforms of each part of the page buffer/read circuit. Here, it is assumed that even-numbered bit lines are selected by the bit line selection circuit 40 .

Time t1: The voltage supply node V1 transitions from GND to Vcc (eg, 1.8V). Time t2: Vcc is applied to the gate of the transistor BLPRE, and the sense node SNS is precharged to Vcc-Vth (Vth is the threshold value of the transistor BLPRE). Time t3: The transistor YBLe is turned off, and the even-numbered bit line GBLe is separated from the virtual power supply VIRPWR. Time t4: VCLAMP2+Vth is applied to the gate of the transistor BLCLAMP, and a voltage smaller than either VCLAMP2 or Vcc-Vth is generated at the node TOBL (Vth is the threshold value of the transistor BLCLAMP). Time t5 : A voltage higher than Vcc (eg, 5 V) is applied to the gate of the transistor BLCN, and the node TOBL is connected to the node BLS of the bit line selection circuit 40 . The transistor BLCN is strongly turned on, and the node BLS is precharged with a voltage smaller than either VCLAMP2 or Vcc-Vth, which is substantially equal to the node TOBL. Time t6: Apply a voltage higher than Vcc (for example, 5V) to the gate of the transistor BLSe, connect the node BLS to the selected bit line GBLe, and the selected bit line GBLe with a voltage lower than either VCLAMP2 or Vcc-Vth. Start precharging. Time t7: VCLAMP1+Vth is applied to the gate of the transistor BLCLAMP, and a voltage smaller than either VCLAMP1 or Vcc-Vth is generated at the node TOBL. There is a relationship of VCLAMP1>VCLAMP2. At this time, the precharge potential Vcc-Vth of the sense node SNS is supplied to the node TOBL, the node BLS, and the selected bit line GBL_e via the transistor BLCLAMP, and the whole is precharged to a voltage lower than either VCLAMP1 or Vcc-Vth . Time t8: A voltage higher than Vcc (eg, 4V) is applied to the gate of the transistor BLPRE, the transistor BLPRE is strongly turned on, and the voltage of the sense node SNS is boosted to Vcc. There is a relationship of Vcc>VCLAMP1. In this way, finally, the node TOBL to the selected bit line GBLe are precharged to VCLAMP1 as a target.

In this way, the conventional precharging method has the advantage that the peak current can be suppressed by turning on the transistors one by one, preventing a plurality of transistors from being turned on at the same time, but on the other hand, there is the following problem, that is, until the start of alignment The time until the line is precharged (time t6 ) becomes longer, and the read operation takes time. Furthermore, in a NAND-type flash memory equipped with a Serial Peripheral Interface (SPI) function, in order to perform continuous reading of pages at high speed in synchronization with an external serial clock signal, it is necessary to make the memory array The readout time is shortened to meet a fixed spec.

An object of the present invention is to solve such a conventional problem, and to provide a semiconductor memory device capable of suppressing a peak current during a precharge operation and reducing a read time. [Technical means to solve the problem]

The method for precharging the bit line of the NAND flash memory of the present invention is that at the first timing, the first transistor for applying the precharge voltage to the read node is turned on by the first control signal, and at the second timing , the second transistor connected to the readout node and used to generate the clamp voltage is turned on by the second control signal, and the node connected to the second transistor and the bit line side is made by the third control signal The third transistor between the nodes is turned on, and at the third timing, the fourth transistor connected between the node and the bit line is turned on by the fourth control signal.

In one embodiment, the precharge method further shifts the voltage supply node connected to the first transistor from the GND level to the supply voltage level at the first timing. In one embodiment, the precharging method further includes the step of: switching the drive capability of the supply voltage level from a low drive capability to a high drive capability at a fourth timing after the third timing. In one embodiment, at the first timing, the fifth transistor connected between the bit line and the virtual power supply is made non-conductive by the fifth control signal. In one embodiment, the bit line side transistors of the NAND strings are turned on at the first timing. In one embodiment, the first to fourth control signals are driven to the H level when the first to fourth transistors are turned on.

The semiconductor memory device of the present invention includes: a NAND-type memory cell array; a page buffer/readout circuit connected to the memory cell array; a bit line selection circuit connected to the page buffer/readout circuit; and a readout unit that reads out a selected page of the memory cell array, the page buffer/readout circuit includes a voltage supply node, a first transistor connected between the voltage supply node and the readout node, and a first transistor connected between the voltage supply node and the readout node. a second transistor that senses the read node and generates a clamp cell voltage, and a third transistor that is connected between the second transistor and a node of the bit line selection circuit, the bit line selection circuit including the connection The fourth transistor between the node and the bit line, the readout unit turns on the first transistor at the first timing via the first control signal, and at the second timing via the second control signal and the first transistor The second transistor and the third transistor are turned on by three control signals, and the fourth transistor is turned on by the fourth control signal at a third timing.

In one embodiment, the readout unit transitions the voltage supply node from a ground level to a supply voltage level at the first timing. In one embodiment, the readout unit switches the drive capability of the supply voltage level from a low drive capability to a high drive capability at a fourth timing after the third timing. In one embodiment, the bit line selection circuit includes a fifth transistor connected between the even-numbered bit lines and a virtual power supply, and a sixth transistor connected between the odd-numbered bit lines and the virtual power supply, the At the first timing, the readout unit turns off the fifth or sixth transistor via the fifth control signal or the sixth control signal to block the connection between the selected bit line and the virtual power supply. In one embodiment, the readout unit turns on the bit line side transistor of the NAND string via the selected gate line at the first timing. In one embodiment, the semiconductor memory device further includes an internal voltage generating unit including: an internal power supply voltage generating circuit that generates an internal power supply voltage based on the external power supply voltage; and a charge pump that generates an internal power supply voltage based on the external power supply voltage a high voltage; and a regulator to generate a regulated voltage based on the high voltage generated by the charge pump, the readout component using the voltage generated by the regulator to generate the first control signal, a third control signal, and a fourth control signal, and use the internal power supply voltage to generate a supply voltage for the voltage supply node. In one embodiment, the internal voltage generating component includes: another charge pump that generates a high voltage based on the external supply voltage; and another regulator that generates a regulated voltage based on the high voltage generated by the charge pump voltage, the second control signal is generated using the voltage generated by the other regulator. In one embodiment, the internal power supply voltage generation circuit selectively generates an internal power supply voltage with a high drive capability or an internal power supply voltage with a low drive capability based on control from the readout unit. In one embodiment, the readout component generates the select gate signal using a high voltage generated by the charge pump. [Effect of invention]

According to the present invention, from the first timing to the third timing, the first to fourth transistors are enabled to precharge the bit lines through the first to fourth control signals, so that the precharge operation can be suppressed. The peak current at the same time can be shortened until the precharge is started, and thus the readout time can be shortened. Furthermore, the first control signal, the third control signal, and the fourth control signal are not driven to the H level at the same time, and the voltages from the voltage supply nodes are not simultaneously precharged to the bit lines, so peak current caused by precharging can be suppressed.

Next, embodiments of the present invention will be described. The semiconductor storage device of the present invention includes a NAND-type flash memory. The form of the NAND-type flash memory is arbitrary, and the semiconductor storage device may also include other volatile memories (such as Dynamic Random Access Memory (DRAM), Static random access memory (Static Random Access Memory, SRAM, etc.), logic, digital signal processor (Digital Signal Processor, DSP), central processing unit (Central Processing Unit, CPU), etc. [Example]

FIG. 3 is a diagram showing a structure of a NAND-type flash memory according to an embodiment of the present invention. The flash memory 100 of the present embodiment is composed of the following parts: a memory array 110, a plurality of memory cells are arranged in a matrix; an input/output circuit 120, connected to the external input/output terminal I /O; ECC circuit 130, performs error detection/correction of data to be programmed into or read from memory cell array 110; address register 140, receives address data from input/output circuit 120; controller 150, control reading, programming, erasing, etc., based on commands or control signals from an external host device; word line selection circuit 160, decode the row address information Ax from the address register 140, and perform decoding based on the decoding result. Block selection or word line selection, etc.; page buffer/readout circuit 170, holding readout data of the page selected by wordline selection circuit 160, or holding data for programming the selected page; column selection circuit 180, decodes the column address information Ay from the address register 140, and selects a column in the page buffer/readout circuit 170 based on the decoding result; and the internal voltage generation circuit 190, generates a readout , various voltages required for programming and erasing (read voltage Vread, programming voltage Vpgm, internal power supply voltage Vdd, regulator voltage Vreg, etc.).

The memory cell array 110 includes m blocks BLK(0), BLK(1), . . . , BLK(m-1). In one block, as shown in FIG. 4 , a plurality of NAND strings NU are formed, and the NAND strings NU are formed by connecting memory cells in series. A NAND string NU includes a plurality of memory cells (64 in the illustration), bit line side selection transistors and source line side selection transistors. The bit line side select transistor connects the memory cell to the bit line based on the select gate signal SGD applied to the gate, and the source line side select transistor connects the memory cell based on the select gate signal SGS applied to the gate. element is connected to the source line SL. In the illustration, two pages of NAND strings NU are formed in one block, the even-numbered NAND strings NU are connected to the even-numbered bit lines GBLe, and the odd-numbered NAND strings NU are connected to the odd-numbered bit lines GBLo.

The memory cell array 110 may be formed two-dimensionally on the surface of the substrate, or three-dimensionally formed along the vertical direction from the surface of the substrate. Moreover, the storage cell may be either a single-level cell (SLC) type storing 1-bit (2-value data), or a multi-level cell (MLC) type storing multiple bits. )type.

The ECC circuit 130 can be activated or deactivated by commands, settings at the time of shipment, or the like. When the ECC circuit 130 operates, the ECC circuit 130 performs error detection/correction of data read out from the memory cell array 110 or performs error detection/correction of data to be programmed into the memory cell array 110 .

The controller 150 includes a state machine or a microcontroller, and controls various operations of the flash memory. In the read operation, a certain positive voltage is applied to the bit line, a certain voltage (eg, 0 V) is applied to the selected word line, a pass voltage is applied to the unselected word line, and a positive voltage is applied to the selection gate signal SGD and the selection gate signal SGS. voltage, apply 0V to the source line. In the programming operation, a high-voltage programming voltage Vpgm is applied to the selected word line, and an intermediate potential is applied to the non-selected word lines, so that the selection transistor on the bit line side is turned on, the selection transistor on the source line side is turned off, and the bit cell is turned off. The line supplies the potential corresponding to the data "0" or "1". In the erasing operation, 0V is applied to all the selected word lines in the block, and a high-voltage erase voltage is applied to the P-well, and electrons of the floating gate are extracted to the substrate, and data is erased on a block-by-block basis.

As shown in FIG. 1(A) and FIG. 1(B) , the page buffer/readout circuit 170 includes a readout circuit 20 and a latch circuit 30 . A page buffer/readout circuit 170 is shared by the even bit lines and odd bit lines via the bit line selection circuit 40, therefore, the page buffer/readout circuit 170 includes a number of pages (eg, 32K). The page buffer/readout circuit 170 or the bit line selection circuit 40 is controlled according to the page buffer control signal generated by the page buffer control 12 shown in FIG. 1(A) and FIG. 1(B) .

As described above, the internal voltage generation circuit 190 generates various voltages necessary for the read operation, the program operation, and the erase operation. As shown in FIG. 5 , the internal voltage generation circuit 190 includes a Vdd generation circuit 200 , a charge pump 210 , and a regulator 210 in relation to the voltage used in the readout operation.

The Vdd generation circuit 200 uses the external power supply voltage Vcc to generate the internal power supply voltage Vdd. The external power supply voltage Vcc is, for example, 3.3V, and the internal power supply voltage Vdd is, for example, 1.8V. The internal power supply voltage Vdd is used, for example, for the voltage supply of the page buffer/readout circuit 170 to the node V1 or the voltage of the virtual power supply VIRPWR.

The charge pump 210 uses the external power supply voltage Vcc to generate the high voltage Vxd. The high voltage is, for example, 5.4V. The high voltage Vxd is used for a regulator or level shifter to generate the select gate line SGD of the bit line side select transistor or the select gate line SGS of the source line side select transistor.

The regulator 220 uses the high voltage Vxd generated by the charge pump 210 to generate the voltage VYPASSB. The voltage VYPASSB is, for example, 4.4V. The voltage VYPSSB is used for page buffer control signals (BLPRE, BLCN, BLSe/BLSo, YBLe/YBLo) and the like to control the page buffer/readout circuit 170 .

FIG. 6 shows an example of the Vdd generation circuit 200 . The Vdd generation circuit 200 includes a PMOS transistor and a resistive divider connected in series to the current path between the external power supply voltage Vcc and GND, and further includes an operational amplifier for the nodes divided by the resistive divider The voltage of , is compared with the reference voltage Vref, and the PMOS transistor is controlled based on the comparison result. The output terminal outputs the internal power supply voltage Vdd which is obtained by stepping down the external power supply voltage Vcc. The internal power supply voltage Vdd is supplied to the V1 drive circuit, the drive circuit of the virtual power supply VIRPWR, or the like.

The structure of the V1 drive circuit is shown in FIG. 7 . The V1 drive circuit 300 is a circuit that drives the voltage supply node V1 of the page buffer/readout circuit 170 . The V1 driving circuit 300 operates with the internal power supply voltage Vdd, including: a P-type pull-up transistor PU1 and a pull-up transistor PU2, which are connected in parallel between the internal power supply voltage Vdd and the output node V1; an N-type pull-down transistor PD , connected between the output node V1 and GND; and the inverter 310 , the inverter 320 , and the inverter 330 , the outputs are connected to the gates of these transistors PU1 , PU2 , and PD. To the inverter 310 , the inverter 320 , and the inverter 330 , the control signal S1 , the control signal S2 , and the control signal S3 from the controller 150 are input.

The PMOS/NMOS transistors constituting the pull-up transistor PU1, the pull-up transistor PU2, the pull-down transistor PD, the inverter 310, the inverter 320, and the inverter 330 are the low voltage of the internal power supply voltage Vdd (for example, 1.8 V) is driven, the withstand voltage of the transistor should be small, and the gate length Lg is 0.3 μm.

Further, the drive capability of the pull-up transistor PU2 is configured to be stronger than the drive capability of the pull-up transistor PU1. That is, the W/L ratio of the pull-up transistor PU2 is greater than the W/L ratio of the pull-up transistor PU1, so the drain current that flows when the pull-up transistor PU2 is turned on is greater than the drain current that flows when the pull-up transistor PU1 is turned on current.

When the control signal S1 is at the H level, the control signal S2 is at the L level, and the control signal S3 is at the H level, the pull-up transistor PU1 is turned on, the pull-up transistor PU2 is turned off, the pull-down transistor PD is turned off, and at the output node V1 generates a voltage Vdd with a weak driving capability. Moreover, when the control signal S1 is at the L level, the control signal S2 is at the H level, and the control signal S3 is at the H level, the pull-up transistor PU1 is turned off, the pull-up transistor PU2 is turned on, and the pull-down transistor PD is turned off. The output node V1 generates a voltage Vdd with a strong driving capability. Or, when the control signal S1 is at the H level, the control signal S2 is at the H level, and the control signal S3 is at the H level, the pull-up transistor PU1 is turned on, the pull-up transistor PU2 is turned on, the pull-down transistor PD is turned off, and the output The node V1 generates a combined voltage of the voltage Vdd with weak driving capability and the voltage Vdd with strong driving capability. When the control signal S1, the control signal S2, and the control signal S3 are at L level, the pull-up transistor PU1 and the pull-up transistor PU2 are turned off, the pull-down transistor PD is turned on, and the GND level is generated at the output node V1.

Next, the precharge operation of the bit line at the time of the read operation/verify read of the present embodiment will be described. The number of page buffer/readout circuits 170 is very large (for example, a page is 32K), when the page buffer control signal (for example, BLPRE, BLCN, BLSe/BLSo, YBLe/YBLo) is changed from the L level to the H level. Usually, a large current is consumed in order to drive these control signals. Furthermore, since the capacity of the sense node SNS or the capacity of the bit line wired across and between blocks is large, the current consumption increases when the bit line is precharged via the sense node SNS.

When the page buffer control signal is simultaneously transitioned from L to H, the voltage VYPASSB used for the page buffer control signal temporarily drops. Since the voltage VYPASSB uses the high voltage Vxd, the high voltage Vxd also temporarily drops at the same time. The high voltage Vxd is used for the generation of the selection gate signal SGS/SGS or the level shifter. If the voltage drop of the high voltage Vxd is large, in the worst case, the level shifter may invert the output and cause Malfunction. Furthermore, if the precharge current flows from the voltage supply node V1 to the bit line together, the internal power supply voltage Vdd will temporarily drop, and the external power supply voltage Vcc will drop temporarily, causing stacking in the operation of the flash memory. or reset. Therefore, it is desirable to suppress the peak current when precharging the bit line as much as possible.

In this embodiment, based on this viewpoint, there is a limitation on the operation of switching (transition from L to H, or transition from H to L) multiple page buffer control signals at the same time. This limitation is that when the page buffer control signal is changed from L to H, the plurality of page buffer control signals generated by the voltage VYPASSB are not switched at the same time. That is, the three control signals, the control signal BLPRE, the control signal BLCN, and the control signals BLSe/BLSo, are not switched to the H level at the same time. If these three control signals are switched to the H level at the same time, a large voltage drop occurs in the voltage VYPASSB. The reason for this is that the gate capacitances of the transistors of the page buffer/readout circuit 170 are large, and if there are a number corresponding to one page, driving them to the H level consumes a large amount of current. In other words, when any one of these three control signals is switched to the H level, simultaneous switching of the other control signals is allowed. For example, it is permitted to switch the voltage supply node V1 to the H level, or to switch the control signals YBLe/YBLo to the L level, or to switch the control signal BLCLAMP to the H level.

Furthermore, when any one of the three control signals is switched to the H level, it is also allowed to switch the selection gate signals SGD/SGS at the same time. For example, the select gate signal SGD is driven to the H level. The select gate signal uses the high voltage Vxd generated by the charge pump 210, but the bit line side select transistors or source line side select transistors of the NAND string are as small as the memory cells, so the gates of these transistors are small. The pole capacitance is sufficiently smaller than the transistors of the page buffer readout circuit 170 or the bit line selection circuit 40 . Therefore, even at the same time as the switching of the page buffer control signal, the drop in the voltage Vxd due to the selection of the gate line can be ignored.

In order to generate VCLAMP1 or VCLAMP2 at the node TOBL, the control signal BLCLAMP applies the clamp voltage of VCLAMP1+Vth or VCLAMP2+Vth to the gate. VCLAMP1+Vth and VCLAMP2+Vth sometimes require a voltage level higher than Vcc. However, unlike the above-mentioned three control signals, since it is a clamp cell voltage, it is expected that a constant voltage level is always maintained. For example, when VCLAMP1+Vth and VCLAMP2+Vth that are stepped down from VYPASSB are generated by a regulator not shown, the control signal BLCLAMP may temporarily cause a voltage drop due to the switching of the three control signals. Therefore, ideally, it is generated by stepping down a regulation voltage higher than Vcc, which is different from VYPASSB. For example, the voltage generation circuit 190 shown in FIG. 5 further includes another charge pump different from the charge pump 210, and another regulator for adjusting the high voltage generated by the other charge pump, the control signal BLCLAMP The clamp cell voltages (VCLAMP1+Vth, VCLAMP2+Vth) are generated using the voltage of the other regulator.

Next, a specific bit line precharging method of the present embodiment will be described with reference to the sequence of FIGS. 8(A) and 8(B). Here, it is assumed that even-numbered bit lines are selected by the bit line selection circuit. Time t1: The voltage supply node V1 is switched from the GND level to the internal power supply voltage Vdd. The controller 150 causes the output node V1 of the V1 drive circuit 300 (see FIG. 7 ) to generate an internal power supply voltage Vdd (eg, 1.8V) with a weak drive capability via the control signal S1 , the control signal S2 , and the control signal S3 . That is, the pull-up transistor PU1 is turned on, and the pull-up transistor PU2 and the pull-down transistor PD are turned off. Furthermore, at time t1, the control signal BLPRE is driven from the L level to the H level (for example, 4.4V), the transistor BLPRE is turned on, the selection gate signal SGD is driven from the L level to the H level (for example, 4.5V), and the bit The line side select transistor is turned on. Then, the control signal YBLe transitions from the H level to the L level, the transistor YBLe is turned off, and the even-numbered bit line GBLe is cut off from the virtual power supply VIRPWR. In this way, the sense node SNS is charged with the internal power supply voltage Vdd. This charging utilizes the internal power supply voltage Vdd with weak driving capability, so the charging speed is relatively slow.

Time t2: The control signal BLCLAMP is driven from the L level to the H level (voltage VCLAMP1+Vth), the transistor BLCLAMP is turned on, and the control signal BLCN is driven from the L level to the H level (for example, 4.4V), the transistor BLCN is turned on . There is a relationship of Vcc>VCLAMP1. In this way, the node TOBL and the node BLS are charged with the voltage of VCLAMP1. Vth is the threshold of transistor BLCLAMP.

Time t3: The control signal BLSe is driven from the L level to the H level (for example, 4.4V), and the transistor BLSe is turned on. Thereby, the even-numbered bit line GBLe is connected to the node BLS, and precharging of the even-numbered bit line GBLe is started. This charging utilizes the internal power supply voltage Vdd with weak driving capability, so the charging speed is relatively slow.

Time t4: At time t4 after a fixed time has elapsed from time t3, the internal power supply voltage Vdd supplied from the voltage supply node V1 is switched to a strong driving capability. The controller 150 causes the output node V1 of the V1 driving circuit 300 to generate an internal power supply voltage Vdd (eg, 1.8V) with strong driving capability via the control signal S1 , the control signal S2 , and the control signal S3 . For example, the pull-up transistor PU1 and the pull-up transistor PU2 are turned on, and the pull-down transistor PD is turned off. Thereby, the even-numbered bit line GBLe is rapidly charged by the internal power supply voltage Vdd having a strong driving capability.

From time t1 to time t4, since the internal power supply voltage Vdd supplied from the voltage supply node V1 has a weak driving capability, at time t4, the node SNS may be initially charged only to a voltage lower than the target voltage Vdd . Likewise, it is possible that the node TOBL, the node BLS, and the even-numbered bit line GBLe are only initially charged to a voltage lower than the target voltage, ie, VCLAMP1. Since the internal power supply voltage Vdd supplied from the power supply node V1 is switched to a strong driving capability at time t4, the node SNS, the node TOBL, the node BLS, and the even-numbered bit line GBLe are charged to the target voltages, respectively. Therefore, it is possible to reduce the voltage caused by The peak current caused by the supply node V1 can also be precharged to the target voltage.

(B) of FIG. 8 shows the four steps of the precharge method of the present embodiment, and if it is compared with the six steps of the conventional precharge method of FIG. 2(B) , it can be seen that in the present embodiment , the time at which the precharge is started is t4, whereas the conventional time is t6, and the start time of the precharge in this embodiment is faster.

In the conventional precharging method, the voltage of the clamp cell is boosted from VCLAMP2 to VCLAMP1 in two stages, but in this embodiment, VCLAMP1 is generated at one time. There are two concerns about this. One is the peak current and the other is the precharge voltage level of the bit line.

Regarding the peak current, the largest peak current is generated after the precharging of the sense node SNS or the bit line with a large capacity is started. In the present embodiment, as described above, in the period from time t1 to time t4, the internal power supply voltage Vdd supplied from the voltage supply node V1 has a weak drive capability, that is, at time t1, the pair reading is performed using a weak drive capability The initial charging of the output node SNS is performed at the time t2 and the initial charging of the node BLS is performed at the time t2, and then the initial charging of the bit lines is sequentially started in stages at the time t3. Therefore, the peak current caused by the generation of VCLAMP1 does not occur. cause too much problem.

In addition, with regard to the precharge voltage level of the bit line, if the voltages of the node SNS and the node TOBL change abruptly, the transistor BLCLAMP becomes temporarily unstable due to the coupling effect. Although also affected by Process Voltage Temperature (PVT) conditions, the unstable transistor BLCLAMP has the potential to cause larger precharge voltage levels. However, in the present embodiment, when generating VCLAMP1, the internal power supply voltage Vdd having a weak driving capability is used in the period from time t1 to time t4, thereby suppressing abrupt voltage fluctuations of the node SNS and the node TOBL. Furthermore, after time t4, the internal power supply voltage Vdd with strong driving capability is used, but since the node SNS and the node TOBL are initially charged in advance, this phenomenon can be suppressed as long as the difference from the target voltage is charged.

In this way, according to the present embodiment, compared with the conventional precharge method, the time until the precharge is started can be shortened, the peak current can be suppressed, and the generation of an undesired precharge voltage level can be suppressed.

The precharge method of this embodiment is also applicable to a normal read operation or verify read during a program operation. Furthermore, the precharge method of this embodiment can also be applied to the operation of continuously reading out pages in synchronization with an external serial clock signal.

Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

10, 10_1~10_n: page buffer/readout circuit 12: Page Buffer Control 20: readout circuit 30: Latch circuit 40: Bit line selection circuit 100: flash memory 110: Memory cell array 120: Input/Output Buffer 130: ECC circuit 140: address register 150: Controller 160: word line selection circuit 170: Page Buffer/Readout Circuit 180: Column selection circuit 190: Internal voltage generation circuit 200: Vdd generation circuit 210: Charge Pump 220: Regulator 300:V1 drive circuit 310, 320, 330: Inverter Ax: row address information Ay: column address information BLK(0)~BLK(m-1): block BLCLAMP, BLCN, BLPRE, BLSe, BLSo, YBLe, YBLo: Page buffer control signals (control signals) BLS, SNS, T0BL: Node GBL: bit line GBLe: even bit line GBLo: Odd Bit Lines NU: NAND string PD:N type pull-down transistor PU1, PU2: P-type pull-up transistor S1, S2, S3: control signal SGD, SGS: select gate signal SL: source line t1~t7: time V1: Voltage supply node Vcc: External power supply voltage Vth: Threshold of BLCLAMP VCLAMP1: target voltage VCLAMP1+Vth, VCLAMP2+Vth: Clamping cell voltage Vdd/GND: Internal supply voltage/ground voltage VIRPWR: hypothetical power supply Vpgm: programming voltage Vread: read voltage Vref: Reference voltage Vreg: regulator voltage Vxd: high voltage VYPASSB: Voltage

FIG. 1(A) is a diagram showing the overall configuration of a page buffer/read circuit, and FIG. 1(B) is a diagram showing the configuration of one page buffer read circuit and a bit line selection circuit connected thereto. FIG. 2(A) is a sequence showing a conventional bit line precharge operation, and FIG. 2(B) is a diagram showing six steps of the conventional precharge operation. FIG. 3 is a diagram showing a structure of a NAND-type flash memory according to an embodiment of the present invention. FIG. 4 is a diagram showing a NAND string cell of a NAND-type flash memory. FIG. 5 is a diagram showing a configuration of an internal voltage generating circuit according to an embodiment of the present invention. 6 is a diagram showing a configuration of a Vdd generation circuit according to an embodiment of the present invention. FIG. 7 is a diagram showing a configuration of a V1 drive circuit according to an embodiment of the present invention. FIG. 8(A) is a diagram showing the sequence of the precharge operation of the bit line according to the embodiment of the present invention, and FIG. 8(B) is a diagram showing the four steps of the precharge operation in this embodiment.

BLCLAMP, BLCN, BLPRE, BLSe, YBLe: Page buffer control signals (control signals)

SGD: select gate signal

t1~t4: time

V1: Voltage supply node

BLS, SNS, T0BL: Node

GBL: bit line

GBLe: even bit line

VCLAMP1: target voltage

Vdd: Internal supply voltage

GND: ground voltage

Claims (15)

A precharging method is a precharging method for a bit line of an NAND type flash memory, and the precharging method is: At the first timing, the first transistor for applying the precharge voltage to the read node is turned on by the first control signal, At the second timing, the second transistor connected to the readout node and used for generating the clamp voltage is turned on by the second control signal, and the second transistor connected to the bit is turned on by the third control signal The third transistor between the nodes on the line side conducts, At the third timing, the fourth transistor connected between the node and the bit line is turned on by the fourth control signal. The precharging method of claim 1, wherein The precharge method further causes the voltage supply node connected to the first transistor to transition from the ground level to the supply voltage level at the first timing. The precharging method of claim 1 or 2, wherein The precharging method also includes the following steps: At a fourth timing after the third timing, the drive capability of the supply voltage level is switched from a low drive capability to a high drive capability. The precharging method of claim 1 or 2, wherein At the first timing, the fifth transistor connected between the bit line and the virtual power source is made non-conductive by the fifth control signal. The precharging method of claim 1 or 2, wherein At the first timing, the bit line side transistor of the NAND string is turned on. The precharging method of claim 1, wherein The first to fourth control signals are driven to the H level when the first to fourth transistors are turned on. A semiconductor storage device, comprising: NAND-type memory cell array; a page buffer/readout circuit, connected to the memory cell array; a bit line selection circuit connected to the page buffer/readout circuit; and a readout component that reads out the selected page of the memory cell array, The page buffer/readout circuit includes a voltage supply node, a first transistor connected between the voltage supply node and a sense node, a second transistor connected to the sense node and generating a clamp cell voltage a crystal, and a third transistor connected between the second transistor and the node of the bit line selection circuit, the bit line selection circuit includes a fourth transistor connected between the node and the bit line, The readout unit turns on the first transistor via the first control signal at the first timing, At the second timing, the second transistor and the third transistor are turned on through the second control signal and the third control signal, At the third timing, the fourth transistor is turned on via the fourth control signal. The semiconductor memory device of claim 7, wherein The readout unit transitions the voltage supply node from the ground level to the supply voltage level at the first timing. The semiconductor memory device as claimed in claim 7 or 8, wherein The readout unit switches the drive capability of the supply voltage level from a low drive capability to a high drive capability at a fourth timing after the third timing. The semiconductor memory device of claim 7, wherein The bit line selection circuit includes a fifth transistor connected between the even-numbered bit lines and a virtual power supply, and a sixth transistor connected between the odd-numbered bit lines and the virtual power supply, The readout unit turns off the fifth or sixth transistor via the fifth control signal or the sixth control signal at the first timing to block the connection between the selected bit line and the virtual power supply. The semiconductor memory device of claim 7, wherein The readout unit turns on the bit line side transistor of the NAND string via the selection gate line at the first timing. The semiconductor memory device of claim 7, wherein The semiconductor memory device further includes an internal voltage generating part, The internal voltage generating section includes: an internal power supply voltage generating circuit that generates an internal power supply voltage based on an external power supply voltage; a charge pump that generates a high voltage based on the external power supply voltage; and a regulator based on the voltage generated by the charge pump high voltage to generate a regulated voltage, The readout unit generates the first control signal, the third control signal, and the fourth control signal using the voltage generated by the regulator, and uses the internal power supply voltage to generate the supply of the voltage supply node Voltage. The semiconductor memory device of claim 7, wherein The internal voltage generating section includes: another charge pump that generates a high voltage based on the external power supply voltage; and another regulator that generates a regulated voltage based on the high voltage generated by the charge pump, the The second control signal is generated using the voltage generated by the further regulator. The semiconductor memory device of claim 12, wherein The internal power supply voltage generating circuit selectively generates an internal power supply voltage with a high driving capability or an internal power supply voltage with a low driving capability based on the control from the readout section. The semiconductor memory device of claim 11, wherein The readout component generates the select gate signal using a high voltage generated by the charge pump.

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